MP1039EY-LF [MPS]
Display Driver,;
| 型号： | MP1039EY-LF |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Display Driver, |
| 文件： | 总13页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP1039
Full Bridge
CCFL Controller
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP1039 is a fixed operating frequency
inverter controller that controls four external
N-Channel power MOSFETs in a full-bridge
configuration. The inverter is designed to power
one or more cold cathode fluorescent lamps
(CCFL) to backlight liquid crystal displays. Its
full-bridge architecture converts unregulated DC
input voltages to the nearly pure sine waves
required to ignite and operate CCFL.
•
Drives Four External, Low Cost, N-Channel
MOSFETs
Programmable Fixed Operating Frequency
Input Voltage Range of 10V to 28V
Lamp Current and Voltage Regulation
Full-Wave Sense Amp
Analog and Burst Mode Dimming Control
Integrated Burst Mode Oscillator and Modulator
Soft-On and Soft-Off Burst Envelope
Open Lamp Protection
Secondary Over-Current Protection
Dual-mode, Fault Timer
•
•
•
•
•
•
•
•
•
•
•
•
The switching frequency is set by an external
resistor, and can be synchronized to an external
clock to minimize the potential video display
interference. The built-in burst oscillator can be
synchronized with an external clock to minimize
display scan interference. Burst mode or analog
mode dimming is controlled with an external
analog signal. Built-in fault management features
include an open lamp regulator, a transformer
secondary peak current regulator, and a dual-
mode fault timer. The secondary over-current
timeout can be shortened with external
components. The MP1039 is available in
TSSOP28 and SOIC28 packages.
Drives up to 20 Lamps
Synchronization Ability for both Switching
Frequency and Burst Frequency
Available in TSSOP28 and SOIC28 Packages
•
APPLICATIONS
•
•
•
Desktop LCD Flat Panel Displays
Flat Panel Video Displays
LCD TVs and Monitors
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The MP1039 is covered by US Patents 6,683,422, 6,316,881, and 6,114,814.
Other Patents Pending.
TYPICAL APPLICATION
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SI
PGND2
GND
2
3
LI
BG2
VCC2
SW2
TG2
LV
4
COMP
AGND
FT
5
6
BT2
7
SWSET
SWPLL
BRPLL
BRS
VIN2
PGND1
BG1
8
9
10
11
12
13
14
VCC1
SW1
TG1
DBRT
ABRT
DBRT
ABRT
ENSYNC
LSYNC
ENSYNC
LSYNC
BT1
VIN1
V
PS
MP1039
MP1039 Rev. 1.1
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
1
MP1039 – FULL BRIDGE CCFL CONTROLLER
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
Input Voltage VIN2, VIN1 ................................. 30V
Logic Inputs ................................–0.3V to +6.5V
Inputs SI, LI, LV................................–3V to +3V
Junction Temperature...............................150°C
Power Dissipation...................................... 0.6W
Junction Temperature...............................150°C
Lead Temperature (Solder) ......................260°C
Operating Frequency............................. 150KHz
Storage Temperature ..............–55°C to +150°C
Recommended Operating Conditions (2)
Input Voltage VIN1, VIN2 ...................... 10V to 28V
Analog Brightness Voltage VABRT....... 0V to 1.2V
Digital Brightness Voltage VDBRT........ 0V to 1.2V
Enable Voltage VENSYNC ..................... 0V to 5.0V
Operating Frequency............. 20KHz to 100KHz
Operating Frequency (Typical)................ 47KHz
Operating Temperature .............–20°C to +85°C
TOP VIEW
SI
LI
1
2
3
4
5
6
7
8
9
28 PGND2
27 BG2
26 VCC2
25 SW2
24 TG2
23 BT2
LV
COMP
AGND
FT
SWSET
SWPLL
BRPLL
22 VIN2
21 PGND1
20 BG1
19 VCC1
18 SW1
17 TG1
16 BT1
BRS 10
DBRT 11
ABRT 12
ENSYNC 13
LSYNC 14
Thermal Resistance (3)
θJA
θJC
15 VIN1
TSSOP28 ...............................82...... 20... °C/W
SOIC28...................................60...... 30... °C/W
Part Number*
MP1039EM
MP1039EY
Package
TSSOP28
SOIC28
Temperature
–20°C to +85°C
–20°C to +85°C
Notes:
1) The device is not guaranteed to function outside of its
operating conditions.
2) Exceeding these ratings may damage the device.
3) Measured on approximately 1” square of 1 oz copper.
For Tape & Reel, add suffix –Z (eg. MP1039EM–Z)
For RoHS compliant packaging, add suffix –LF
(eg. MP1039EM–LF–Z)
*
ELECTRICAL CHARACTERISTICS
VIN1 = VIN2 = 17.5V, VBRPLL = VSWPLL = GND, TA = +25°C, unless otherwise noted.
Parameter
Output
Symbol Condition
Min
Typ
Max
Units
Gate Pull-Down
RGD
RGU
RON
2
9
Ω
Ω
Gate Pull-Up
Damper On Resistance
1.0
kΩ
ENSYNC
Threshold
VTH
1.35
0.3
2.0
V
V
Hysteresis
VTH_HYS
Sync Timing for Burst Oscillator
Sync Minimum Pulse Width
Sync Maximum Pulse Width
Sync Rate
tSYNC(MIN)
tSYNC(MAX)
fSYNC
1
µs
µs
Hz
V
10
200
2.1
0.4
DBRT Logic Input Threshold
DBRT Logic Input Hysteresis
VTH
VBRS = VCC
1.8
2.3
VTH_HYS VBRS = VCC
V
MP1039 Rev. 1.1
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9/24/2007
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© 2007 MPS. All Rights Reserved.
MP1039 – FULL BRIDGE CCFL CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VIN1 = VIN2 = 17.5V, VBRPLL = VSWPLL = GND, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
Lamp Frequency Sync
LSYNC Min Pulse Width
LSYNC Rate (4)
LSYNC Pulse Amplitude
Brightness Control Range
DBRT Full Brightness
DBRT 10% Brightness
ABRT Full Scale
tLSYNC(MIN)
fLSYNC
VLSYNC
20
60
ns
KHz
V
R3 = 100kΩ
120
2.5
VDBRT, FULL
VDBRT, 10%
VABRT
0.135
1.34
1.2
V
V
V
Burst Rate Generator
Source Current
ISRC(BRS) VBRS = 2V
VV(BRS)
VP(BRS)
120
2.2
3.3
150
2.35
3.5
180
2.5
3.7
µA
V
V
Lower Threshold
Upper Threshold
Supply Current
Supply Current (Enabled)
Supply Current (Disabled)
Operating Frequency
Accuracy of f0
IVIN
IVIN
f0
1.7
1
47
3
3
20
mA
µA
KHz
%
R3 = 100kΩ
Control Input Current
Frequency Set Voltage
Lamp Current Feedback
ISWPLL
VSWSET
µA
V
–8
1.2
1.10
1.18
1.30
1.32
VABRT > 1.2V
1.25
0.41
1.33
3
V
V
Vrms
%
Magnitude
|VLI|
VABRT = 0V
Sine Equivalent
Accuracy
VLI
VLI
VABRT > 1.2V
Input Resistance
VLI < 0V
62
kΩ
Open Lamp Voltage Feedback
Threshold (Peak)
Secondary Peak Current Threshold
Fault Timer
VTH(LV)
VTH(SI)
1.16
1.16
1.21
1.21
1.26
1.26
V
V
Threshold
Sink Current
Open Lamp Source Current
Secondary Over-Current Source
Current
Vt(FT)
ISINK(FT)
ISO(FT)+
1.16
1.21
–1
1
1.26
V
µA
µA
ISP(FT)+
70
µA
Comp
Clamp Voltage
Reference Current
Decay Current
VCOMP
ICOMP+
ICOMP-
0.56
20
60
V
µA
µA
End of Burst
Output (VCC1 and VCC2)
Voltage
VCC
ICC
5.5
6.0
5
6.5
V
mA
Current
Note:
4) Guaranteed by design, not tested.
MP1039 Rev. 1.1
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9/24/2007
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MP1039 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS
Pin #
Name
Description
1
SI
Secondary Current Feedback Input. Connect a current sense resistor from the cold end of
the secondary winding to ground. Connect this pin to the junction of the resistor and the
secondary winding. If the voltage at SI exceeds +1.2V, a pulse of current will pull down on
the COMP pin to attempt to regulate the secondary current and the Fault Timer will be
started.
2
3
LI
Lamp Current Feedback Input. Connect this pin to the cold end of the lamp and shunt a
sense resistor to ground. The sense amplifier will sink a current from the COMP pin
proportional to the absolute value of the voltage at this pin. (In regulation the average of the
absolute value of the voltage at this pin is determined by the voltage at the ABRT pin). A
470ꢀ resistor placed in series with this pin will improve ESD protection.
LV
Lamp Voltage Feedback Input. Connect a capacitive voltage divider from the hot end of the
lamp to ground. Connect this pin to the tap on the divider and shunt a bias resistor to
ground. If the voltage at LV exceeds +1.2 V, a pulse of current will pull down on the COMP
pin to attempt to regulate the lamp voltage and the Fault Timer will be started.
4
5
6
COMP
AGND
FT
Feed back Compensation Node. Connect a compensation capacitor from this pin to ground.
Analog Ground.
Fault Timing. Connect a timing capacitor from this pin to AGND to set the fault timeout
period.
7
8
SWSET Switching Frequency Set. Connect a resistor from this pin to AGND. This resistor sets the
operating frequency of the MP1039.
SWPLL Switching Frequency Phase Lock Loop. SWPLL provides compensation when the operating
clock is synchronized to an external clock. Connect a resistor in series with a capacitor from
SWPLL to AGND. Connect a smaller capacitor directly from SWPLL to AGND. Connect only
a single capacitor to AGND, if some sweeping of the operating clock can be tolerated during
open lamp conditions. Connect SWPLL to AGND to force the operating clock to the selected
value at all times.
9
BRPLL Burst Frequency Phase Lock Loop. BRPLL provides compensation when the burst
frequency is to be synchronized to an external clock. Connect a resistor in series with a
capacitor from BRPLL to AGND. Connect a smaller capacitor directly from BRPLL to AGND.
If the burst frequency is not to be synchronized to an external clock, connect BRPLL to
AGND.
10
11
BRS
Burst Frequency Setting. If the burst frequency is to be synchronized to an external clock,
connect a capacitor from BRS to AGND. If the burst rate generator is free-run and not be
synchronized with an external clock, connect a resistor in parallel with a capacitor from BRS
to AGND. If the burst is to be controlled by an external logic signal, connect BRS to VCC
and apply the logic signal to the DBRT pin.
DBRT
ABRT
Burst-Mode (Digital) Brightness Control Input. The voltage range of 0.12V to 1.34V at DBRT
linearly sets the burst-mode duty cycle from 100% to 10%. If burst dimming is not used tie
DBRT to GND. The MP1039 has negative dimming polarity on DBRT.
12
13
Analog Brightness Control Input. The voltage range of 0V to 1.2V at ABRT sets 3:1 dimming
range for the lamp current. If analog dimming is not used, tie ABRT to VCC.
ENSYNC Enable and Sync Composite Input. Pull ENSYNC high to turn on the MP1039, pull ENSYNC
low to turn it off. To synchronize the burst frequency to an external clock, apply the
synchronizing clock signal with low-going pulse width of 1-10µs to this pin. Once the
MP1039 has aligned the burst oscillator to the sync signal, each burst will start at the low-
going edge of the sync pulse.
14
LSYNC Lamp Frequency Synchronization Input. The synchronization clock must be greater than the
frequency fO set by the SWSET pin, but no greater than 1.4 times the value of fO.
MP1039 Rev. 1.1
9/24/2007
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© 2007 MPS. All Rights Reserved.
4
MP1039 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name
Description
15
VIN1
Input Power Rail, Side 1. Connect VIN1 directly to the drain of the side 1, top power
MOSFET.
16
BT1
Output Bootstrap, Side 1. BT1 provides gate bias for the side 1 top MOSFET. Connect a
capacitor from BT1 to SW1.
17
18
TG1
Top MOSFET Gate Output, Side 1.
SW1
Source of Top MOSFET, Side 1. Connect SW1 to the source of the side 1 top MOSFET and
the drain of the side 1 bottom MOSFET.
19
VCC1
Linear Regulator Output and Bias Supply of Bottom Gate Driver, Side 1. VCC1 allows
bypassing the bias supply for the control circuitry. Bypass VCC1 with a 1µF or larger
ceramic capacitor. Connect to VCC2.
20
21
22
BG1
Bottom MOSFET Gate Output, Side 1.
PGND1 Power Ground, Side 1. Connect PGND1 to the source of the bottom, side 1 MOSFET.
VIN2
Input Power Rail, Side 2. Connect VIN2 directly to the drain of the top, side 2, external
power MOSFET.
23
BT2
Output Bootstrap, Side 2. BT2 provides gate bias for the side 2 top MOSFET. Connect a
capacitor from BT2 to SW2.
24
25
TG2
Top MOSFET Gate Output, Side 2.
SW2
Source of Top MOSFET, Side 2. Connect SW2 to the source of the side 2, top MOSFET
and the drain of the side 2, bottom MOSFET.
26
VCC2
BG2
Voltage Rail Output, Side 2. VCC2 allows bypassing the bias supply for the control circuitry.
Bypass VCC2 with a 1µF or larger ceramic capacitor. Connect to VCC1. It is an input pin.
27
28
Bottom MOSFET Gate Output, Side 2.
PGND2 Power Ground, Side 2. Connect PGND2 to the source of the bottom, side 2 MOSFET.
MP1039 Rev. 1.1
9/24/2007
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MP1039 – FULL BRIDGE CCFL CONTROLLER
OPERATION
V
PS
R1
R8
1
3
SI
VIN2
22
1.2V
LV
TG2 24
BT2 23
SW2 25
BG2 27
FAULT
LEVEL
SHIFT
C10
C11
C8
MANAGEMENT
1.2V
C2
6
2
FT
R
LI
LI
LI
ERROR
AMP
12 ABRT
C1
R3
PGND2
28
26
4
COMP
LAMP
PWM
VCC2
7
8
SWSET
SWPLL
LAMP
CLOCK
R4
C4
V
PS
C12
R9
VIN1
15
C3
ABRT
LSYNC
EN
TG1 17
14 LSYNC
10 BRS
LEVEL
SHIFT
C13
C14
BT1
SW1
BG1
16
18
20
21
19
R6
C7
DBRT
C5
R5
C6
BURST
RATE
GENERATOR
9
BRPLL
PGND1
VCC1
C9
R2
13 ENSYNC
11 DBRT
SI LV
LI
BURST
PWM
5
AGND
Figure 1—MP1039 Block Diagram
The MP1039 implements burst mode dimming
of the lamp and features soft-on-soft-off control
of the lamp current envelope that is virtually
independent of supply voltage.
DESIGN INFORMATION
The MP1039 is a fixed operating frequency
inverter controller specifically designed to drive
a cold cathode fluorescent lamp (CCFL) used
as a backlight for liquid crystal displays.
Designed to run off 10V to 28V input supplies,
the MP1039 can drive up to 20 lamps (140W)
via four (4) external N-Channel MOSFETs. Its
full bridge architecture converts unregulated DC
input voltages to the nearly pure sine waves
required to ignite and operate CCFLs. The
Operating frequency is set by an external resistor
to minimize the possibility of interference with the
refresh rate of the display.
Burst frequency and duty cycle can either be
determined by driving the MP1039 with an
external logic signal or by choosing an external
resistor and capacitor to set the burst rate and
modulating the duty cycle with a DC control
voltage on DBRT.
Loop gain is compensated for variations in
supply voltage and the full-wave lamp current
sense amplifier provides superior output pulse
symmetry, loop response time, and phase
margin.
Regulated lamp current and maximum peak
transformer secondary current are set by
external resistors. Regulated open lamp voltage
is set by an external capacitive voltage divider.
The switching frequency of the MP1039 is set
by an external resistor. This frequency can be
synchronized to the input clock signal at the
LSYNC pin.
MP1039 Rev. 1.1
9/24/2007
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MP1039 – FULL BRIDGE CCFL CONTROLLER
Careful management of limit conditions
provides graceful reduction of lamp power at
low supply voltages but allows the loop to
recover quickly from an abrupt step in supply
voltage. System fault management facilities
include an on-chip open-lamp regulator, a
transformer secondary peak current regulator,
and a dual-mode fault timer.
The MP1039 does not utilize ZVS or ZCS. It
implements fast switching to reduce switching
loss and operates at the condition that IPRI and
VPRI are in phase to reduce primary RMS
current. Therefore, higher efficiency than ZVS
or ZCS is achieved.
V
V
PS
PS
A
B
C
D
By regulating the peak current in the
transformer secondary winding, UL60950 can
be met for most systems. When the MP1039 is
regulating open lamp voltage, it ignores the
burst control and runs continuously to ensure
either the lamp has a chance to re-ignite or the
fault timer can smoothly and accurately time
out. If the MP1039 detects an open lamp
condition for a time that exceeds the timer
interval, it will shut down until the part is turned
off and then turned on again. Similarly, the
MP1039 will shut down if it detects an over-
current condition in the secondary for about 2%
of the open lamp timer interval. If required, the
secondary over-current timeout can be
shortened with external components.
D1
V
PRI
-
+
I
PRI
A,D
B,C
V
I
:
:
PRI
ZVS
ZCS
0
0
0
PRI
MP1039
FEATURE DESCRIPTION
All reference designators refer to Figure 1,
unless otherwise designated.
Figure 2—VPRI vs. IPRI
Brightness Control
The MP1039 can operate in four modes:
Analog Mode, Burst Mode with a DC input,
Burst Mode with an external PWM or Analog
and Burst Mode. The four modes are
dependent on the pin connections defined
under Pin Functions.
High Efficiency Operation
There are two major power losses in a CCFL
inverter: switching loss of switches and copper
loss of the transformer winding. To reduce
switching loss, Zero Current Switching (ZCS as
described in US patent 6,114,814) or Zero Voltage
Switching (ZVS) are commonly implemented.
Choosing the required burst repetition
frequency can be achieved by an RC
combination, as defined in component
selection. The MP1039 has a soft-on and
soft-off feature to reduce noise, when using
burst mode dimming. Analog dimming and
Burst dimming are independent of each other
and may be used together to obtain a wider
dimming range.
As shown in Figure 2, ZCS and ZVS require
primary current IPRI lagging primary voltage VPRI
With ZVS, since D1 can only conduct at the
negative phase of IPRI, the beginning of A & D
conduction will only happen at the negative
phase of IPRI.
.
Higher phase delay will lead to higher primary
RMS current and therefore higher transformer
temperature. With ZCS, A & D conduction starts
at the zero crossing of IPRI.
MP1039 Rev. 1.1
9/24/2007
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MP1039 – FULL BRIDGE CCFL CONTROLLER
Table 1—Function Mode
Pin Connection
Excessive Secondary Current (Shorted Lamp):
The SI pin (#1) is used to detect whether
excessive secondary current has occurred. If a
fault condition occurs that increases the
secondary current, then the voltage at SI will be
greater than 1.2V. A pulse of current will pull
down on the COMP pin to regulate the
secondary current. The Fault Timer will be
started with a 55µA current source injecting into
C2 at the FT pin, while the fault condition
persists.
Function
ABRT
DBRT
BRS
Ratio
R6
C7
Analog Mode 0 – 1.2V
Burst Mode
GND
3:1
R6
C7
with DC
VCC
0 – 1.4V
PWM
10:1
Input Voltage
Burst Mode
with External
Source
Set by
Customer
VCC
VCC
If the voltage at the FT pin exceeds 1.2V, then
the chip will shut down and needs to be
re-enabled.
Analog and
Burst Mode
R6
C7
0 – 1.2V 0 – 1.4V
0 – 1.2V PWM
30:1
Analog and
Burst Mode
with External
Source
Set by
Customer
Fault Timer: The timing for the fault timer will
depend on the sourcing current, as described
above, and the capacitor C2 on the FT pin. The
user can program the time for the voltage to
rise after the chip detects a “real“ fault. When a
fault is triggered, then the internal voltage (VCC)
will collapse from 6V to 0V. If no fault is
detected a 1µA current sink will keep FT to 0V.
VCC
Brightness Polarity
Burst: 100% duty cycle is at 0V
Analog: 1.2V is maximum brightness
Fault Protection
Open Lamp: The LV pin (#3) is used to detect
whether an open lamp condition has occurred.
If the voltage at LV exceeds +1.2V, a pulse of
current will pull down on the COMP pin to
regulate the lamp voltage. The Fault Timer will
be started with a 1µA current source injecting
into C2 at the FT pin, while the fault condition
persists. If the voltage at the FT pin exceeds
1.2V, then the chip will shut down.
Chip Enable
The chip has an ON/OFF function, which is
controlled by the ENSYNC pin (#13). The
enable signal goes directly to a Schmitt trigger.
The chip will turn ON with an ENSYNC = High
and OFF with an ENSYNC = Low.
The Burst waveform can be synchronized to an
external reference clock. To do this, remove R6
and combine a low-going synchronization signal
with the enable signal at the ENSYNC pin. The
synchronizing pulses should be 1µs - 10µs wide
and should occur at the desired burst repetition
frequency.
MP1039 Rev. 1.1
9/24/2007
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MP1039 – FULL BRIDGE CCFL CONTROLLER
APPLICATION INFORMATION
Pin 1 (SI), R1:
FT
Secondary Short Protection: The R1 is used for
feedback to the SI pin to detect excessive
secondary current. The value for R1 is calculated
as 1.2V divided by the secondary peak current.
C2A
C2B
Pin 2 (LV): C13, C14 and R8:
Figure 3—Timeout Adjustment
Open Lamp protection: The regulated open
lamp voltage is proportional to the C14 and C13
ratio. C13 has to be rated at 3kV and is typically
between 5pF to 22pF. The value of C14 is set
by the customer to achieve the required open
lamp voltage detection value.
For C2B = 10nF, then the time out for
secondary short will be 0.2ms.
Note: The open lamp time out will remain the
same value as defined by C2A.
Pin 7 (SWSET), R3:
R3 is used to set the lamp operating clock. The
value for R3 is calculated by
C14 = C13×1.18× V(MAX)rms
The value of bias resistor R8 is typically 10kꢀ
to 100kꢀ (not critical).
5e9
R3 =
Pin 2 (LI), R2:
fο
Lamp Current Regulation: R2 is used for
feedback to the LI pin to regulate the lamp
current. The value for R2 is calculated as 1.33V
divided by the lamp rms current (assuming
ABRT is greater than 1.2V). For RMS 6mA lamp
current, R2 value is 220ꢀ.
For R3 = 100kꢀ, operating clock will be 47KHz.
Pin 8 (SWPLL):
This is the lamp clock control compensation pin
and needs a lag lead lag capacitor/resistor
network.
V
Pin 6 (FT), C2:
Pin 9 (BRPLL):
The C2 is used to set the fault timer. This
capacitor will determine when the chip will
reach the fault threshold value.
This is the burst rate control compensation pin
and needs a lag lead lag capacitor/resistor
network.
Open Lamp Time Out:
Pin 4 (COMP), C1:
C1 is the feedback compensation capacitor that
connects between COMP and AGND. A 1.5nF
or 2.2nF cap is recommended. This cap should
be X7R ceramic. The value of C1 affects the
soft-on rise time and soft-off fall time.
tOPENLAMP ×1µA
C2
(
nF =
)
1.2V
For a C2 = 820nF, then the time out for open
lamp will be 0.98 sec.
Secondary Overcurrent Timeout: When the
MP1039 is regulating secondary overcurrent (SI
feedback), the source current in the Fault Timer
(FT) cap is approximately 55µA. This causes
the SI timeout to be about 1/55 of the Open
Lamp (LV) timeout. To reduce the SI timeout
further, modify the network at the FT pin as
shown in Figure 3.
MP1039 Rev. 1.1
9/24/2007
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MP1039 – FULL BRIDGE CCFL CONTROLLER
Pin 18 (SW1), Pin 25 (SW2), C12, R9:
SW1 and SW2 pins are used to sense the
voltage at the output of the full bridge. They
also are the point of access for the output
dampers. SW1 and SW2 should make a Kelvin
connection to the sources of the top MOSFETs
and the drains of the bottom MOSFETs in the
output bridge.
Pin 11 (DBRT):
This pin is used for burst brightness control.
The DC voltage on this pin will control the burst
percentage on the output. The signal is filtered for
optimal operation. A voltage ranging from 0 to
1.4V on DBRT will correspond to a Burst Duty
Cycle of 100% to 10% respectively.
For direct Pulse Width Modulation of the burst
signal, connect BRS to VCC and connect DBRT
to a logic level PWM signal. Logic High is Burst
On and a logic Low is Burst Off.
The primary transformer current flows through
capacitor C12. Its value is typically 2.2µF. This
capacitor should be ceramic and has a ripple
current rating greater than the primary current.
It is more optimal to use two parallel 1µF
ceramic caps for minimal ESR losses. R9 is
used to ensure that the bridge outputs are at 0V
prior to startup. Typically R9 = 1kꢀ.
Pin 10 (BRS): C7, R6:
BRS is used to set the Burst frequency. C7 and
R6 will set the burst frequency and the
minimum burst time: tMIN. Set tMIN to achieve the
minimum required system
Pin 16 (BT1), Pin 23 (BT2), C8, C10:
BT1 and BT2 are the bias supplies for the level
shift of the upper MOSFETs. C8 and C10
should be 22nF and made of X7R ceramic
material.
brightness. Ensure that tMIN is long enough that
the lamp does not extinguish.
These values are determined as follows:
Select a Minimum Duty Cycle, DMIN, where:
Pin 19 (VCC1), Pin 26 (VCC2), C9, C11:
These capacitors bypass the 6V gate supply for
the bottom switches. They also supply power to
the MP1039. These pins should be bypassed
with a 0.47µF ceramic X7R capacitor.
DMIN = tMIN × fBurst
tFALL
DMIN
=
(
tFALL + tRISE
)
If operating in Free-Running mode:
Pin 13 (ENSYNC):
⎛
⎞
⎟
⎠
1
ENSYNC is a composite of the Enable and the
Burst Oscillator Synchronization function. This
pin will enable and disable the chip when the
enable function is used.
⎜
⎜
⎟
− 1 Vbg
DMIN
VP + VV
⎝
+
ξ
2
R6 =
Ib
To synchronize the Burst Oscillator to an
external signal, remove R6 from BRS pin and
apply a 1µs to 10µs pulse with a falling edge
trigger and a repetition rate of 200Hz. The Burst
Oscillator will then be synchronized with this
signal and start a burst on its falling edge.
⎛
⎞
1
⎜
⎜
⎟
R6 ~ 21.16k
− 1 + 21.43k
⎟
DMIN
⎝
⎠
For DMIN = 0.1 and R6 = 212k
1− DMIN
C7 =
Pin 14 (LSYNC):
The lamp frequency can be externally
synchronized by applying a signal to this pin.
fb × R6 × γ
The synchronization clock must be greater than
the frequency f0 set by the SWSET pin, but no
greater than 1.4x the value of f0.
MP1039 Rev. 1.1
9/24/2007
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10
MP1039 – FULL BRIDGE CCFL CONTROLLER
For DMIN = 0.1, R6 = 212k, fb = 200Hz, then C7 = 52nf
DMIN = Minimum Burst Duty Cycle
Vbg = VP - VV (~1.2V)
ESD Resistor
It is recommended that a resistor (RLI=470ꢀ) be
added in series with the lamp current feedback
as shown in Figure 4.
Vp = peak BRS voltage (~3.6V)
Vv = valley BRS voltage (~2.4V)
The addition of this resistor helps minimize the
possibility of ESD damage in case of
mishandling of the IC during board level
assembly and test.
3.6
2.4
⎛
⎞
⎟
γ = ln
≈ 0.405
⎜
⎝
⎠
Ib = BRS sink current (~150µA)
fb = burst frequency
If operating in Synchronous mode:
MP1039
lb × tMIN
C7 =
LI
Vbg
tMIN = Minimum Burst Time
Figure 4—ESD Resistor
MP1039 Rev. 1.1
9/24/2007
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11
MP1039 – FULL BRIDGE CCFL CONTROLLER
PACKAGE INFORMATION
TSSOP28
9.60
9.80
0.65 BSC
0.40 TYP
28
15
1.60
TYP
5.80
TYP
4.30
4.50
6.20
6.60
PIN 1 ID
14
1
TOP VIEW
RECOMMENDED LAND PATTERN
0.80
1.05
1.20 MAX
SEATING PLANE
0.09
0.20
0.19
0.05
0.15
0.65 BSC
0.30
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
NOTE:
GAUGE PLANE
0.25 BSC
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
0.45
0.75
0o-8o
5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AE.
6) DRAWING IS NOT TO SCALE.
DETAIL ꢀ
MP1039 Rev. 1.1
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9/24/2007
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
MP1039 – FULL BRIDGE CCFL CONTROLLER
PACKAGE INFORMATION
SOIC28
0.024
(0.61)
0.050
(1.27)
0.697(17.70)
0.713(18.10)
28
15
0.079
(2.00)
0.394
(10.00)
0.418
0.291
(7.40)
0.299
(7.60)
0.370
(9.40)
(10.60)
PIN 1 ID
1
14
TOP VIEW
RECOMMENDED LAND PATTERN
0.093(2.35)
0.104(2.65)
SEATING PLANE
0.009(0.23)
0.013(0.33)
0.013(0.33)
0.020(0.51)
0.050(1.27)
BSC
0.004(0.10)
0.012(0.30)
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
0.010(0.25)
0.030(0.75)
x 45o
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
GAUGE PLANE
0.010(0.25) BSC
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
0.016(0.41)
0.050(1.27)
0o-8o
5) DRAWING CONFORMS TO JEDEC MS-013, VARIATION AE.
6) DRAWING IS NOT TO SCALE.
DETAIL "A"
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP1039 Rev. 1.1
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
13
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