MP1048EY-LF-Z [MPS]
Liquid Crystal Driver, 1-Segment, PDSO28, LEAD FREE, MO-013AE, SOIC-28;
| 型号： | MP1048EY-LF-Z |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Liquid Crystal Driver, 1-Segment, PDSO28, LEAD FREE, MO-013AE, SOIC-28 光电二极管 |
| 文件： | 总12页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP1048
Full Bridge
CCFL Controller
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP1048 is a fixed operating frequency
inverter controller that controls four external
N-Channel power MOSFETs in a full-bridge
configuration. The inverter is designed to power
up to 6 cold cathode fluorescent lamps (CCFLs)
to backlight liquid crystal displays. Its full-bridge
architecture converts unregulated DC input
voltages to the nearly pure sine waves required
to ignite and operate CCFLs.
•
•
Capable of Driving up to 6 Lamps
Controls Four External, Low Cost, N-Channel
MOSFETs
•
•
•
•
•
•
•
•
•
•
•
Fixed Operating Frequency
Input Voltage Range of 10V to 22V
Lamp Current and Voltage Regulation
Full-Wave Sense Amp
Analog and Burst Mode Dimming Control
Integrated Burst Mode Oscillator and Modulator
Soft-On and Soft-Off Burst Envelope
Open Lamp Protection
Secondary Over-Current Protection
Dual-Mode Fault Timer
Available in TSSOP28 and SOIC28 Packages
For reliable lamp ignition, the operating
frequency is set by an external resistor and
during startup is temporarily swept toward the
unloaded resonant frequency of the tank. Burst
mode or analog mode dimming are controlled
with an external analog signal. Built-in fault
management features include an open lamp
regulator, a transformer secondary peak current
regulator and a dual-mode fault timer. The
secondary over-current timeout can be
shortened with external components. The
MP1048 is available in TSSOP28 and SOIC28
packages.
APPLICATIONS
•
•
Desktop LCD Flat Panel Displays
Monitors
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The MP1048 is covered by US Patents 6,683,422, 6,316,881, and 6,114,814.
Other Patents Pending.
TYPICAL APPLICATION
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SI
PGL
LGL
GND
2
3
LI
LV
VCCL
OUTL
UGL
4
COMP
AG
5
6
FT
BTL
7
LCS
LCC
BRC
BRS
DBRT
ABRT
EN
PRL
8
PGR
LGR
9
10
11
12
13
14
VCCR
OUTR
UGR
BTR
DBRT
ABRT
EN
NC
PRR
V
PS
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
1
MP1048 – FULL BRIDGE CCFL CONTROLLER
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
Input Voltage VPRR, VPRL ............................... 24V
Logic Inputs ................................–0.3V to +6.5V
Inputs SI, LI, LV................................–5V to +5V
Junction Temperature...............................150°C
Power Dissipation...................................... 0.6W
Junction Temperature...............................150°C
Lead Temperature (Solder) ......................260°C
Operating Frequency............................. 150KHz
Storage Temperature ..............–55°C to +150°C
Recommended Operating Conditions (2)
Input Voltage VPRR, VPRL .................... 10V to 22V
Analog Brightness Voltage VABRT....... 0V to 1.2V
Digital Brightness Voltage VDBRT........ 0V to 1.2V
Enable Voltage VEN............................ 0V to 5.0V
Operating Frequency............. 20KHz to 100KHz
Operating Frequency (Typical)................ 60KHz
Operating Temperature .............–20°C to +85°C
TOP VIEW
SI
LI
1
2
3
4
5
6
7
8
9
28 PGL
27 LGL
26 VCCL
25 OUTL
24 UGL
23 BTL
22 PRL
21 PGR
20 LGR
19 VCCR
18 OUTR
17 UGR
16 BTR
15 PRR
LV
COMP
AG
FT
LCS
LCC
BRC
BRS 10
DBRT 11
ABRT 12
EN 13
Thermal Resistance (3)
θJA
θJC
N/C 14
TSSOP28 ...............................82...... 20... °C/W
SOIC28...................................60...... 30... °C/W
Part Number*
MP1048EM
MP1048EY
Package
TSSOP28
SOIC28
Temperature
–20°C to +85°C
–20°C to +85°C
Notes:
1) The device is not guaranteed to function outside of its
operating conditions.
2) Exceeding these ratings may damage the device.
3) Measured on approximately 1” square of 1 oz copper.
For Tape & Reel, add suffix –Z (eg. MP1048EM–Z)
For RoHS Compliant Packaging, add suffix –LF
(eg. MP1048EM–LF–Z)
*
ELECTRICAL CHARACTERISTICS
VPRR = VPRL = 17.5V, VBRC = VLCC = GND, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
Output
Gate Pull-Down
Gate Pull-Up
RGD
RGU
RON
2.0
20
Ω
Ω
Damper On Resistance
EN
1.2
kΩ
Threshold
VTH
1.2
0.3
2.0
2.3
V
V
Hysteresis
VTH_HYS
Sync Timing
DBRT Logic Input Threshold
DBRT Logic Input Hysteresis
Burst Rate Generator
Source Current
Lower Threshold
Upper Threshold
VTH
VBRS = VCC
1.8
2.0
0.2
V
V
VTH_HYS VBRS = VCC
ISRC(BRS) VBRS = 2V
VV(BRS)
125
2.2
3.2
150
2.35
3.4
175
2.5
3.6
µA
V
VP(BRS)
V
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
2
MP1048 – FULL BRIDGE CCFL CONTROLLER
ELECTRICAL CHARACTERISTICS (continued)
VPRR = VPRL = 17.5V, VBRC = VLCC = GND, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max
Units
Supply Current
Supply Current (Enabled)
Supply Current (Disabled)
Operating Frequency
Accuracy of f0
IPR
IPR
2.2
3
3
25
53
8
mA
µA
KHz
%
f0
R3 = 100kΩ
45
49
3
Frequency Set Voltage
Lamp Current Feedback
VLCS
1.13
1.18
1.23
V
VABRT > 1.2V
VABRT = 0V
1.134
0.35
1.20
0.40
3
1.266
0.45
Magnitude
|VLI|
V
Accuracy
VLI
RLI
%
Input Resistance
VLI < 0V
60
kΩ
Open Lamp Voltage Feedback
Threshold (Peak)
VTH(LV)
VTH(SI)
1.15
1.15
1.20
1.20
1.25
1.25
V
V
Secondary Peak Current
Threshold
Fault Timer
Threshold
Vt(FT)
ISINK(FT)
ISO(FT)+
1.15
1.20
–1
1
1.25
V
Sink Current
µA
µA
Open Lamp Source Current
Secondary Over-Current Source
Current
ISP(FT)+
65
µA
Comp
Clamp Voltage
Reference Current
Decay Current
Output (VCCR and VCCL)
Voltage
VCOMP
ICOMP+
ICOMP-
0.62
20
V
µA
µA
End of Burst
20
VCC
ICC
5.7
6.0
5
6.3
V
Current
mA
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
3
MP1048 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS
Pin #
Name
Description
1
SI
Secondary Current Feedback Input. Connect a current sense resistor from the cold end of the
secondary winding to ground. Connect this pin to the junction of the resistor and the secondary
winding. If the voltage at SI exceeds +1.2V, a pulse of current will pull down on the COMP pin in
an attempt to regulate the secondary current and the Fault Timer will be started.
2
3
LI
Lamp Current Feedback Input. Connect this pin to the cold end of the lamp and shunt a sense
resistor to ground. The sense amplifier will sink a current from the COMP pin that is proportional
to the absolute value of the voltage at this pin. (In regulation the average of the absolute value of
the voltage at this pin is determined by the voltage at the ABRT pin).
LV
Lamp Voltage Feedback Input. Connect a capacitive voltage divider from the hot end of the lamp
to ground. Connect this pin to the tap on the divider and shunt a bias resistor to ground. If the
voltage at LV exceeds +1.2V, a pulse of current will pull down on the COMP pin to attempt to
regulate the lamp voltage and the Fault Timer will be started.
4
5
6
7
COMP Feedback Compensation Node. Connect a compensation capacitor from this pin to ground.
AG
FT
Analog Ground.
Fault Timing. Connect a timing capacitor from this pin to AG to set the fault timeout period.
LCS
Lamp Operating Clock Set. Connect a resistor from this pin to AG. This resistor sets the
operating frequency of the MP1048.
8
LCC
Lamp Clock Control. LCC provides compensation when the operating clock is swept in order to
strike the lamp. Connect a resistor in series with a capacitor from LCC to AG. Connect a smaller
capacitor directly from LCC to AG. Connect only a single capacitor to AG, if some sweeping of
the operating clock can be tolerated during open lamp conditions. Connect LCC to AG to force
the operating clock to the selected value at all times.
9
BRC
BRS
Burst Repetition Rate Control. Connect BRC to AG.
10
Burst Repetition Rate Setting. If the burst repetition rate is to be synchronized to an external
clock, connect a capacitor from BRS to AG. If the burst rate generator is free-run and will not be
synchronized with an external clock, connect a resistor in parallel with a capacitor from BRS to
AG. If the burst is to be controlled by an external logic signal, connect BRS to VCC and apply the
logic signal to the DBRT pin.
11
12
DBRT
ABRT
Burst-Mode (Digital) Brightness Control Input. The voltage range of 0V to 1.2V at DBRT linearly
sets the burst-mode duty cycle from minimum 10% to 100%. If burst dimming is not used, tie
DBRT to VCC.
Analog Brightness Control Input. The voltage range of 0V to 1.2V at ABRT sets the 3:1 dimming
range for the lamp current. If analog dimming is not used, tie ABRT to VCC.
13
14
15
EN
NC
Enable Input. Pull EN high to turn on the MP1048; low to turn it off.
No Connect.
PRR
Input Power Rail, Right-Side. Connect PRR directly to the drain of the high-side, right-side,
external power MOSFET.
16
17
18
19
BTR
UGR
Output Bootstrap, Right-Side. BTR provides gate bias for the right-side high-side MOSFET.
Connect a capacitor from BTR to OUTR.
High-Side MOSFET Gate Output, Right-Side. Connect UGR to the gate of the high-side,
right-side, external power MOSFET.
OUTR
VCCR
Bridge Output, Right-Side. Connect OUTR to the source of the right-side, high-side
MOSFET and the drain of the low-side, right-side MOSFET.
Voltage Rail Output, Right-Side. VCCR allows bypassing the bias supply for the control
circuitry. Bypass VCCR with a 0.47µF capacitor. Connect to VCCL.
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
4
MP1048 – FULL BRIDGE CCFL CONTROLLER
PIN FUNCTIONS (continued)
Pin #
Name
Description
20
LGR
Low-Side MOSFET Gate Output, Right-Side. Connect LGR to the gate of the low-side, right
side MOSFET.
21
22
PGR
PRL
Power Ground, Right-Side. Connect PGR to the source of the low-side, right-side MOSFET.
Input Power Rail, Left-Side. Connect PRL directly to the drain of the high-side, left-side,
external power MOSFET.
23
24
25
26
27
28
BTL
UGL
OUTL
VCCL
LGL
Output Bootstrap, Left-Side. BTL provides gate bias for the left-side high-side MOSFET.
Connect a capacitor from BTL to OUTL.
High-Side MOSFET Gate Output, Left-Side. Connect UGL to the gate of the high-side, left
side, external power MOSFET.
Bridge Output, Left-Side. Connect OUTL to the source of the left-side, high-side MOSFET
and the drain of the left-side, low-side MOSFET.
Voltage Rail Output, Left-Side. VCCL allows bypassing the bias supply for the control
circuitry. Bypass VCCL with a 0.47µF capacitor. Connect to VCCR.
Low-Side MOSFET Gate Output, Left-Side. Connect LGL to the gate of the low-side, left
side MOSFET.
PGL
Power Ground, Left-Side. Connect PGL to the source of the low-side, left-side MOSFET.
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
5
MP1048 – FULL BRIDGE CCFL CONTROLLER
OPERATION
V
PS
R1
R8
1
3
SI
PRL
22
1.2V
1.2V
UGL 24
BTL 23
OUTL 25
LGL 27
PGL 28
LV
FAULT
LEVEL
SHIFT
C10
C11
C8
MANAGEMENT
C2
6
2
FT
LI
R
LI
LI
ERROR
AMP
12 ABRT
C1
R3
4
COMP
VCCL
26
7
8
LCS
LCC
V
PS
LAMP
CLOCK
R4
C4
V
PS
C12
R9
PRR
15
C3
UGR 17
R6
C7
10 BRS
LEVEL
C13
C14
SHIFT BTR 16
OUTR 18
LGR 20
BURST
RATE
GENERATOR
9
BRC
PGR 21
C9
19
VCCR
R2
13 EN
SI LV
LI
11 DBRT
BURST
PWM
5
AG
R7
V
CCR
Figure 1—Functional Block Diagram
external capacitive voltage divider. Soft startup
of the lamp minimizes the peak transformer
secondary voltage. The MP1048 implements
burst mode dimming of the lamp and features
soft-on/soft-off control of the lamp current
envelope that is virtually independent of supply
voltage.
DESIGN INFORMATION
The MP1048 is a fixed operating frequency
inverter controller specifically designed to drive
up to 6 cold cathode fluorescent lamps (CCFLs)
used as a backlight for liquid crystal displays.
Designed to run off 10V to 22V input supplies,
the MP1048 can drive up to 6 lamps via four (4)
external N-Channel MOSFETs. Its full bridge
architecture converts unregulated DC input
voltages to the nearly pure sine waves required
to ignite and operate CCFLs. The operating
frequency is set by an external resistor to
minimize the possibility of interference with the
refresh rate of the display.
Burst repetition rate and duty cycle can either
be determined by driving the MP1048 with an
external logic signal or by choosing an external
resistor and capacitor to set the burst rate and
modulating the duty cycle with a DC control
voltage on DBRT
.
Loop gain is compensated for variations in
supply voltage and the full-wave lamp current
sense amplifier provides superior output pulse
symmetry, loop response time and phase
margin.
To ensure ignition of the lamp, the operating
frequency is swept temporarily to the unloaded
resonant frequency of the tank. Regulated lamp
current and maximum peak transformer
secondary current are set by external resistors.
Regulated open lamp voltage is set by an
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
6
MP1048 – FULL BRIDGE CCFL CONTROLLER
Careful management of limit conditions
provides graceful reduction of lamp power at
low supply voltages but allows the loop to
recover quickly from an abrupt step in supply
voltage. System fault management facilities
include an on-chip open-lamp regulator, a
transformer secondary peak current regulator
and a dual-mode fault timer.
Higher phase delay will lead to higher primary
RMS current and therefore higher transformer
temperature. With ZCS, A & D conduction starts
at the zero crossing of IPRI.
The MP1048 does not utilize ZVS or ZCS. It
implements fast switching to reduce switching
loss and operates at the condition that IPRI and
VPRI are in phase to reduce primary RMS
current. Therefore, higher efficiency than ZVS
or ZCS is achieved.
By regulating the peak current in the
transformer secondary winding, UL1950 can be
met for most systems. When the MP1048 is
regulating open lamp voltage, it ignores the
burst control and runs continuously to ensure
either the lamp has a chance to re-ignite or the
fault timer can smoothly and accurately time
out. If the MP1048 detects an open lamp
condition for a time that exceeds the timer
interval, it will shutdown until the part is turned
off and then turned on again. Similarly, the
MP1048 will shutdown if it detects an
over-current condition in the secondary for
about 2% of the open lamp timer interval. If
required, the secondary over-current timeout
can be shortened with external components.
On-chip current limit protects the MP1048 in
case of output fault conditions.
V
V
PS
PS
A
B
C
D
D1
V
PRI
-
+
I
PRI
A,D
B,C
V
I
:
:
PRI
PRI
ZVS
ZCS
0
0
0
FEATURE DESCRIPTION
All reference designators refer to the MP1048
Block Diagram, unless otherwise designated.
MP1048
Figure 2—VPRI vs. IPRI
Brightness Control
The MP1048 can operate in four modes:
Analog Mode, Burst Mode with a DC input,
Burst Mode with an external PWM or Analog
and Burst Mode. The four modes are
dependent on the pin connections defined
under Pin Functions.
High Efficiency Operation
There are two major power losses in a CCFL
inverter: switching loss of switches and copper
loss of the transformer winding. To reduce
switching loss, Zero Current Switching (ZCS as
described in US patent 6,114,814) or Zero Voltage
Switching (ZVS) are commonly implemented.
As shown in Figure 2, ZCS and ZVS require
Choosing the required burst repetition
frequency can be achieved by an RC
combination as defined in component selection.
The MP1048 has a soft-on and soft-off feature
to reduce noise when using burst mode
dimming. Analog dimming and Burst dimming
are independent of each other and may be
used together to obtain a wider dimming range.
primary current IPRI lagging primary voltage VPRI
.
With ZVS, since D1 can only conduct at the
negative phase of IPRI, the beginning of A & D
conduction will only happen at the negative
phase of IPRI.
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
7
MP1048 – FULL BRIDGE CCFL CONTROLLER
Table 1—Function Modes
Pin Connection
Fault Timer: The timing for the fault timer will
depend on the sourcing current as described
above and the capacitor C2 on the FT pin. The
user can program the time for the voltage to
rise after the chip detects a “real” fault. When a
fault is triggered, the internal voltage (VCC) will
collapse from 6V to 0V. If no fault is detected a
1µA current sink will keep FT to 0V.
Function
ABRT
DBRT BRS
Ratio
Analog Mode 0 – 1.2V
Burst Mode
VCC
VCC
3:1
R6
C7
with DC
VCC
0 – 1.2V
10:1
Input Voltage
Burst Mode
with External
Source
Startup
Set by
Customer
VCC
PWM
VCC
For reliable ignition of the lamp, the operating
frequency is swept temporarily toward the
unloaded resonant frequency of the tank during
startup. This guarantees the strike voltage of
the lamp at any temperature due to a resonant
topology for switching the outputs and
eliminates the need for external ramp timing
circuits to ensure startup. Once the strike
voltage is achieved, the switching frequency is
gradually adjusted to the preset fixed value.
The operating frequency before the lamp strikes
can be swept as much as 160% of the preset
frequency value.
Analog and
Burst Mode
R6
C7
0 – 1.2V 0 – 1.2V
0 – 1.2V PWM
30:1
Analog and
Burst Mode
with External
Source
Set by
Customer
VCC
Brightness Polarity
Burst: 100% duty cycle is at 1.2V
Analog: 1.2V is for maximum brightness
Fault Protection
Open Lamp: The LV pin (#3) is used to detect
whether an open lamp condition has occurred.
If the voltage at LV exceeds +1.2V, a pulse of
current will pull down on the COMP pin to
regulate the lamp voltage. The Fault Timer will
be started with a 1µA current source injecting
into C2 at the FT pin, while the fault condition
persists. If the voltage at the FT pin exceeds
1.2V, then the chip will shutdown.
Chip Enable
The chip has an ON/OFF function, which is
controlled by the EN pin (#13). The enable
signal goes directly to a Schmitt trigger. The
chip will turn ON with an EN = High and OFF
with an EN = Low.
Excessive Secondary Current (Shorted Lamp):
The SI pin (#1) is used to detect whether
excessive secondary current has occurred. If a
fault condition occurs that increases the
secondary current, then the voltage at SI will be
greater than 1.2V. A pulse of current will pull
down on the COMP pin to regulate the
secondary current. The Fault Timer will be
started with a 65µA current source injecting into
C2 at the FT pin while the fault condition
persists.
If the voltage at the FT pin exceeds 1.2V, then
the chip will shutdown and need to be enabled
again.
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
8
MP1048 – FULL BRIDGE CCFL CONTROLLER
Figure 3—Timeout Adjustment
APPLICATION INFORMATION
Pin 1 (SI), R1:
Secondary Short Protection: R1 is used for
feedback to the SI pin to detect excessive
secondary current. The value for R1 is calculated
as 1.2V divided by the secondary peak current.
For a C2B = 10nF, then the time out for
secondary short will be 0.2ms.
Note: The open lamp time out will remain the
same value as defined by C2A.
Pin 2 (LV): C13, C14 and R8:
Open Lamp protection: The regulated open
lamp voltage is proportional to the C14 and C13
ratio. C13 has to be rated at 3kV and is typically
between 5pF to 22pF. The value of C14 is set
by the customer to achieve the required open
lamp voltage detection value.
Pin 7 (LCS), R3:
R3 is used to set the lamp operating clock. The
value for R3 is calculated by
5e9
R3 =
fο
For R3 = 100kΩ, operating clock will be 50KHz.
C14 = C13×1.18× V(MAX)rms
Pin 8 (LCC):
The value of bias resistor R8 is typically 100kΩ
This is the lamp clock control compensation pin
and needs a lag lead lag capacitor/resistor
network.
(not critical).
Pin 2 (LI), R2:
Lamp Current Regulation: R2 is used for
feedback to the LI pin to regulate the lamp
current. The value for R2 is calculated as 1.33V
divided by the lamp rms current (assuming
VABRT is greater than 1.2V). For a RMS 6mA
lamp current, the R2 value is 220Ω.
Pin 4 (COMP), C1:
C1 is the feedback compensation capacitor that
connects between COMP and AG. A 1.5nF or
2.2nF cap is recommended. This cap should be
X7R ceramic. The value of C1 affects the
soft-on rise time and soft-off fall time.
Pin 6 (FT), C2:
Pin 18 (OUTR), Pin 25 (OUTL), C12, R9:
C2 is used to set the fault timer. This capacitor
will determine when the chip will reach the fault
threshold value.
The OUTR and OUTL pins are used to sense
the voltage at the output of the full bridge. They
are also the point of access for the output
dampers. OUTR and OUTL should make a
Kelvin connection to the sources of the
high-side MOSFETs and the drains of the
low-side MOSFETs in the output bridge.
Open Lamp Time Out:
tOPENLAMP ×1µA
C2
(
nF =
)
1.2V
For C2 = 820nF, then the timeout for open lamp
will be 0.98 sec.
The primary transformer current flows through
capacitor C12. Its value is typically 2.2µF. This
capacitor should be ceramic and has a ripple
current rating greater than the primary current.
It is more optimal to use two parallel 1µF
ceramic caps for minimal ESR losses. R9 is
used to ensure that the bridge outputs are at 0V
prior to startup. Typically R9 = 300Ω to 3kΩ.
Secondary Over Current Timeout: When the
MP1048 is regulating secondary over current
(SI feedback), the source current in the Fault
Timer (FT) cap is approximately 65µA. This
causes the SI timeout to be about 1/65 of the
Open Lamp (LV) timeout. To reduce the SI
timeout further, modify the network at the FT
pin as shown in Figure 3.
FT
C2A
C2B
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
9
MP1048 – FULL BRIDGE CCFL CONTROLLER
Pin 16 (BTR), Pin 23 (BTL), C8, C10:
BTR and BTL are the bias supplies for the level
shift of the upper MOSFETs. C8 and C10
should be 22nF and made of X7R ceramic
material.
For DMIN=0.1 and R6=212kꢀ
1− DMIN
C7 =
fb × R6 × γ
For DMIN=0.1, R6=212k, fb=200Hz, then
C7=52nf:
Pin 19 (VCCR), Pin 26 (VCCL), C9, C11:
These capacitors bypass the gate supply for the
low-side switches. They also supply power to
the MP1048. These pins should be bypassed
with a 0.47µF ceramic X7R capacitor.
Where DMIN=Minimum Burst Duty Cycle,
Vbg=VP - VV (~1.2V), VP=peak BRS voltage
(~3.6V), VV = valley BRS voltage (~2.4V) and
fb=burst repetition rate.
IMPORTANT–For all applications, VCCR and
VCCL must be connected together.
3.6
2.4
⎛
⎞
⎟
γ = ln
≈ 0.405
⎜
⎝
⎠
Pin 11 (DBRT):
ESD Resistor
This pin is used for burst brightness control.
The DC voltage on this pin will control the burst
percentage on the output. The signal is filtered
for optimal operation. A voltage ranging from 0V
to 1.2V on DBRT will correspond to a Burst
Duty Cycle of the minimum to 100%
respectively.
It is recommended that a resistor (RLI = 1kꢀ) be
added in series with the lamp current feedback
as shown in Figure 4.
The addition of this resistor helps minimize the
possibility of ESD damage in case of
mishandling of the IC during board level
assembly and test.
For direct Pulse Width Modulation of the burst
signal, connect BRS to VCC and connect DBRT
with a logic level PWM signal. A logic High is
Burst On and a logic Low is Burst Off.
Pin 10 (BRS): C7, R6:
MP1048
LI
BRS is used to set the Burst Repetition Rate.
C7 and R6 will set the burst repetition rate and
the minimum burst time: tMIN. Set tMIN to achieve
the minimum required system brightness.
Ensure that tMIN is long enough that the lamp
does not extinguish.
Figure 4—ESD Resistor
These values are determined as follows:
Select a Minimum Duty Cycle, DMIN, where:
DMIN = tMIN × fBurst
tFALL
DMIN
=
(
tFALL + tRISE
)
If operating in Free-Running mode:
⎛
⎞
⎟
⎠
1
⎜
⎜
⎟
− 1 Vbg
DMIN
VP + VV
⎝
+
ξ
2
R6 =
Ib
⎛
⎞
1
⎜
⎜
⎟
R6 ~ 21.16k
− 1 + 21.43k
⎟
DMIN
⎝
⎠
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
10
MP1048 – FULL BRIDGE CCFL CONTROLLER
PACKAGE INFORMATION
TSSOP28
9.60
9.80
0.65 BSC
0.40 TYP
28
15
1.60
TYP
4.30
4.50
5.80
TYP
6.20
6.60
PIN 1 ID
14
1
TOP VIEW
RECOMMENDED LAND PATTERN
0.80
1.05
1.20 MAX
SEATING PLANE
0.09
0.20
0.19
0.05
0.15
0.65 BSC
0.30
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
NOTE:
GAUGE PLANE
0.25 BSC
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSION OR GATE BURR.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
0.45
0.75
0o-8o
5) DRAWING CONFORMS TO JEDEC MO-153, VARIATION AE.
6) DRAWING IS NOT TO SCALE.
DETAIL
A
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
11
MP1048 – FULL BRIDGE CCFL CONTROLLER
SOIC28
0.024
(0.61)
0.050
(1.27)
0.697(17.70)
0.713(18.10)
28
15
0.079
(2.00)
0.291
(7.40)
0.299
(7.60)
0.394
(10.00)
0.418
0.370
(9.40)
(10.60)
PIN 1 ID
14
1
TOP VIEW
RECOMMENDED LAND PATTERN
0.093(2.35)
0.104(2.65)
SEATING PLANE
0.009(0.23)
0.013(0.33)
0.013(0.33)
0.020(0.51)
0.050(1.27)
BSC
0.004(0.10)
0.012(0.30)
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
0.010(0.25)
0.030(0.75)
x 45o
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
GAUGE PLANE
0.010(0.25) BSC
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.10 MILLIMETERS MAX.
0.016(0.41)
0.050(1.27)
0o-8o
5) DRAWING CONFORMS TO JEDEC MS-013, VARIATION AE.
6) DRAWING IS NOT TO SCALE.
DETAIL "A"
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP1048 Rev. 0.9
9/24/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
12
相关型号：
MP107-1
Parallel - Fundamental Quartz Crystal, 10.738635MHz Nom, ROHS COMPLIANT, RESISTANCE WELD, METAL, HC-49/U, 2 PIN
CTS
©2020 ICPDF网 联系我们和版权申明