MP1484EN [MPS]
Switching Regulator, Current-mode, 5.3A, 380kHz Switching Freq-Max, PDSO8, MS-012BA, SOIC-8;
| 型号： | MP1484EN |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Regulator, Current-mode, 5.3A, 380kHz Switching Freq-Max, PDSO8, MS-012BA, SOIC-8 光电二极管 |
| 文件： | 总10页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP1484
3A, 18V, 340KHz Synchronous Rectified
Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP1484 is a monolithic synchronous buck
regulator. The device integrates top and bottom
85mΩ MOSFETS that provide 3A of continuous
load current over a wide operating input voltage
of 4.75V to 18V. Current mode control provides
fast transient response and cycle-by-cycle
current limit.
•
•
•
•
•
•
•
•
•
•
•
3A Continuous Output Current
Wide 4.75V to 18V Operating Input Range
Integrated 85mΩ Power MOSFET Switches
Output Adjustable from 0.925V to 15V
Up to 95% Efficiency
Soft-Start
Stable with Low ESR Ceramic Output Capacitors
Fixed 340KHz Frequency
Cycle-by-Cycle Over Current Protection
Input Under Voltage Lockout
An adjustable soft-start prevents inrush current
at turn-on and in shutdown mode, the supply
current drops below 1µA.
Thermally Enhanced 8-Pin SOIC Package
The MP1484 is PIN compatible to the MP1482
2A/18V/Synchronous Step-Down Converter.
APPLICATIONS
EVALUATION BOARD REFERENCE
•
•
•
LCD TV
Green Electronics/Appliances
Notebook Computers
Board Number
Dimensions
EV1484EN-00A
2.0”X x 1.5”Y x 0.5”Z
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
C5
10nF
Efficiency vs
INPUT
4.75V to 18V
Load Current
100
V
= 5V
IN
95
90
85
80
75
70
65
60
55
50
V
= 12V
IN
2
1
IN
BS
OUTPUT
3.3V
3A
7
3
EN
SW
MP1484
8
5
SS
GND
FB
COMP
4
6
C3
3.9nF
0.1
1.0
LOAD CURRENT (A)
10
MP1484 Rev. 0.1
12/14/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
1
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
PACKAGE REFERENCE
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN.......................–0.3V to +20V
Switch Voltage VSW................. –1V to VIN + 0.3V
Boost Voltage VBS..........VSW – 0.3V to VSW + 6V
All Other Pins.................................–0.3V to +6V
Junction Temperature...............................150°C
Lead Temperature....................................260°C
Storage Temperature .............–65°C to +150°C
Recommended Operating Conditions (2)
Input Voltage VIN............................ 4.75V to 18V
Output Voltage VOUT .................... 0.925V to 15V
Ambient Operating Temp .............. –20°C to +85°C
TOP VIEW
BS
IN
1
2
3
4
8
7
6
5
SS
EN
SW
GND
COMP
FB
EXPOSED PAD
ON BACKSIDE
CONNECT
TO GND PIN
Thermal Resistance (3)
θJA
θJC
SOIC8N(Exposed Pad) ..........50...... 10... °C/W
Part Number*
Package
Temperature
Notes:
SOIC8N
(Exposed Pad)
MP1484EN
–20°C to +85°C
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
For Tape & Reel, add suffix –Z
For Lead Free, add suffix –LF
*
3) Measured on approximately 1” square of 1 oz copper.
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
0.3
Max
3.0
Units
μA
Shutdown Supply Current
Supply Current
VEN = 0V
VEN = 2.0V, VFB = 1.0V
4.75V ≤ VIN ≤ 23V
1.3
1.5
mA
V
Feedback Voltage
VFB
0.900
0.925
1.1
0.950
Feedback Overvoltage Threshold
Error Amplifier Voltage Gain (4)
Error Amplifier Transconductance
V
AEA
GEA
400
820
V/V
μA/V
ΔIC = ±10μA
High-Side/Low-Side Switch On-
Resistance (4)
85
mΩ
High-Side Switch Leakage Current
Upper Switch Current Limit
Lower Switch Current Limit
VEN = 0V, VSW = 0V
Minimum Duty Cycle
From Drain to Source
0
10
μA
A
3.8
5.3
0.9
A
COMP to Current Sense
Transconductance
GCS
5.2
A/V
Oscillation Frequency
Fosc1
Fosc2
300
340
110
90
380
2.0
KHz
KHz
%
Short Circuit Oscillation Frequency
VFB = 0V
Maximum Duty Cycle
Minimum On Time (4)
DMAX VFB = 1.0V
TON
220
1.5
ns
EN Shutdown Threshold Voltage
VEN Rising
1.1
V
EN Shutdown Threshold Voltage
Hysterisis
220
mV
MP1484 Rev. 0.1
12/14/2007
www.MonolithicPower.com
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© 2007 MPS. All Rights Reserved.
2
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS (continued)
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
2.5
Max
Units
V
EN Lockout Threshold Voltage
EN Lockout Hysterisis
2.2
2.7
210
mV
Input Under Voltage Lockout
Threshold
VIN Rising
3.80
4.05
210
4.40
V
Input Under Voltage Lockout
Threshold Hysteresis
mV
Soft-Start Current
VSS = 0V
6
μA
ms
°C
Soft-Start Period
Thermal Shutdown (4)
CSS = 0.1μF
15
160
Note:
4) Guaranteed by design, not tested.
MP1484 Rev. 0.1
12/14/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
3
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin # Name Description
High-Side Gate Drive Boost Input. BS supplies the drive for the high-side N-Channel MOSFET
switch. Connect a 0.01μF or greater capacitor from SW to BS to power the high side switch.
1
2
BS
IN
Power Input. IN supplies the power to the IC, as well as the step-down converter switches.
Drive IN with a 4.75V to 18V power source. See Input Capacitor.
Power Switching Output. SW is the switching node that supplies power to the output. Connect
the output LC filter from SW to the output load. Note that a capacitor is required from SW to
BS to power the high-side switch.
3
4
5
SW
GND Ground (Connect the exposed pad to Pin 4).
Feedback Input. FB senses the output voltage and regulates it. Drive FB with a resistive
voltage divider connected to it from the output voltage. The feedback threshold is 0.925V. See
FB
Setting the Output Voltage.
Compensation Node. COMP is used to compensate the regulation control loop. Connect a
6
7
8
COMP series RC network from COMP to GND. In some cases, an additional capacitor from COMP to
GND is required. See Compensation Components.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn on
the regulator; low to turn it off. Attach to IN with a 100kΩ pull up resistor for automatic startup.
EN
Soft-Start Control Input. SS controls the soft-start period. Connect a capacitor from SS to GND
SS
to set the soft-start period. A 0.1μF capacitor sets the soft-start period to 15ms. To disable the
soft-start feature, leave SS unconnected.
MP1484 Rev. 0.1
12/14/2007
www.MonolithicPower.com
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© 2007 MPS. All Rights Reserved.
4
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
OPERATION
The converter uses internal N-Channel
MOSFET switches to step-down the input
voltage to the regulated output voltage. Since
the high side MOSFET requires a gate voltage
greater than the input voltage, a boost capacitor
connected between SW and BS is needed to
drive the high side gate. The boost capacitor is
charged from the internal 5V rail when SW is low.
FUNCTIONAL DESCRIPTION
The MP1484 regulates input voltages from
4.75V to 18V down to an output voltage as low
as 0.925V, and supplies up to 3A of load
current.
The MP1484 uses current-mode control to
regulate the output voltage. The output voltage
is measured at FB through a resistive voltage
divider and amplified through the internal
transconductance error amplifier. The voltage at
the COMP pin is compared to the switch current
(measured internally) to control the output
voltage.
When the FB pin voltage exceeds 20% of the
nominal regulation value of 0.925V, the over
voltage comparator is tripped and the COMP
pin and the SS pin are discharged to GND,
forcing the high-side switch off.
+
CURRENT
2
IN
OVP
SENSE
AMPLIFIER
+
--
--
+
1.1V
0.3V
5V
RAMP
CLK
OSCILLATOR
110/340KHz
5
8
FB
SS
1
3
BS
--
S
Q
Q
--
+
--
+
+
SW
R
CURRENT
COMPARATOR
ERROR
AMPLIFIER
0.925V
6
7
COMP
EN
4
GND
--
EN OK
OVP
IN < 4.10V
1.2V
LOCKOUT
COMPARATOR
2.5V
1.5V
+
+
IN
7V
Zener
INTERNAL
REGULATORS
--
SHUTDOWN
COMPARATOR
Figure 1—Functional Block Diagram
MP1484 Rev. 0.1
12/14/2007
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5
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
APPLICATIONS INFORMATION
The inductance value can be calculated by:
COMPONENT SELECTION
Setting the Output Voltage
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
VOUT
VIN
⎜
L =
× 1−
The output voltage is set using a resistive
voltage divider connected from the output
voltage to FB. The voltage divider divides the
output voltage down to the feedback voltage by
the ratio:
fS × ΔIL
Where VOUT is the output voltage, VIN is the
input voltage, fS is the switching frequency, and
ΔIL is the peak-to-peak inductor ripple current.
R2
Choose an inductor that will not saturate under
the maximum inductor peak current, calculated
by:
VFB = VOUT
R1+ R2
Thus the output voltage is:
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
VOUT
VIN
R1+ R2
⎜
ILP = ILOAD
+
× 1−
VOUT = 0.925 ×
2× fS ×L
R2
R2 can be as high as 100kΩ, but a typical value
is 10kΩ. Using the typical value for R2, R1 is
determined by:
Where ILOAD is the load current.
The choice of which style inductor to use mainly
depends on the price vs. size requirements and
any EMI constraints.
R1 = 10.81× (VOUT − 0.925) (kꢀ)
Optional Schottky Diode
For example, for a 3.3V output voltage, R2 is
10kꢀ, and R1 is 26.1kꢀ. Table 1 lists
recommended resistance values of R1 and R2
for standard output voltages.
During the transition between the high-side
switch and low-side switch, the body diode of
the low-side power MOSFET conducts the
inductor current. The forward voltage of this
body diode is high. An optional Schottky diode
may be paralleled between the SW pin and
GND pin to improve overall efficiency. Table 2
lists example Schottky diodes and their
Manufacturers.
Table 1—Recommended Resistance Values
VOUT
1.8V
2.5V
3.3V
5V
R1
R2
9.53kꢀ
16.9kꢀ
26.1kꢀ
44.2kꢀ
121kꢀ
10kꢀ
10kꢀ
10kꢀ
10kꢀ
10kꢀ
Table 2—Diode Selection Guide
Voltage/Current
12V
Part Number
Vendor
Rating
30V, 1A
30V, 1A
Inductor
B130
SK13
Diodes, Inc.
Diodes, Inc.
The inductor is required to supply constant
current to the load while being driven by the
switched input voltage. A larger value inductor
will result in less ripple current that will in turn
result in lower output ripple voltage. However,
the larger value inductor will have a larger
physical size, higher series resistance, and/or
lower saturation current. A good rule for
determining inductance is to allow the peak-to-
peak ripple current to be approximately 30% of
the maximum switch current limit. Also, make
sure that the peak inductor current is below the
maximum switch current limit.
International
Rectifier
MBRS130
30V, 1A
Input Capacitor
The input current to the step-down converter is
discontinuous, therefore a capacitor is required
to supply the AC current while maintaining the
DC input voltage. Use low ESR capacitors for
the best performance. Ceramic capacitors are
preferred, but tantalum or low-ESR electrolytic
capacitors will also suffice. Choose X5R or
X7R dielectrics when using ceramic capacitors.
MP1484 Rev. 0.1
12/14/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
6
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
Since the input capacitor (C1) absorbs the input
When using tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated to:
switching current, it requires an adequate ripple
current rating. The RMS current in the input
capacitor can be estimated by:
VOUT
VOUT
VIN
⎛
⎞
⎛
⎞
⎟
VOUT
VOUT
⎜
ΔVOUT
=
× ⎜1−
⎟ ×RESR
IC1 = ILOAD
×
× 1−
⎜
⎟
⎜
⎝
⎟
⎠
fS ×L
V
V
⎝
⎠
IN
IN
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP1484 can be optimized for a wide range of
capacitance and ESR values.
The worst-case condition occurs at VIN = 2VOUT
,
where IC1 = ILOAD/2. For simplification, use an
input capacitor with a RMS current rating
greater than half of the maximum load current.
Compensation Components
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, a small, high quality ceramic
capacitor, i.e. 0.1μF, should be placed as close
to the IC as possible. When using ceramic
capacitors, make sure that they have enough
capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The
input voltage ripple for low ESR capacitors can
be estimated by:
MP1484 employs current mode control for easy
compensation and fast transient response. The
system stability and transient response are
controlled through the COMP pin. COMP is the
output of the internal transconductance error
amplifier.
A
series
capacitor-resistor
combination sets a pole-zero combination to
govern the characteristics of the control system.
The DC gain of the voltage feedback loop is
given by:
⎛
⎜
⎝
⎞
⎟
⎟
⎠
ILOAD
VOUT
VIN
VOUT
⎜
ΔV
=
×
× 1−
IN
C1× fS
V
VFB
IN
AVDC = RLOAD × GCS × AEA
×
VOUT
Where C1 is the input capacitance value.
Where VFB is the feedback voltage (0.925V),
AVEA is the error amplifier voltage gain, GCS is
the current sense transconductance and RLOAD
is the load resistor value.
Output Capacitor
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic,
tantalum, or low ESR electrolytic capacitors are
recommended. Low ESR capacitors are
preferred to keep the output voltage ripple low.
The output voltage ripple can be estimated by:
The system has two poles of importance. One
is due to the compensation capacitor (C3) and
the output resistor of the error amplifier, and the
other is due to the output capacitor and the load
resistor. These poles are located at:
⎛
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
VOUT
VIN
1
⎜
⎜
ΔVOUT
=
× 1−
× RESR
+
fS × L
8 × fS × C2
GEA
fP1
=
Where C2 is the output capacitance value and
RESR is the equivalent series resistance (ESR)
value of the output capacitor.
2π× C3× AVEA
1
fP2
=
2π × C2× RLOAD
When using ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance which is the main cause for the
output voltage ripple. For simplification, the
output voltage ripple can be estimated by:
Where GEA is the error amplifier transconductance.
⎛
⎜
⎝
⎞
VOUT
VOUT
VIN
⎜
⎟
⎟
⎠
ΔVOUT
=
× 1−
2
8 × fS × L × C2
MP1484 Rev. 0.1
12/14/2007
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7
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
2. Choose the compensation capacitor (C3) to
achieve the desired phase margin. For
applications with typical inductor values, setting
the compensation zero (fZ1) below one-forth of
the crossover frequency provides sufficient
phase margin.
The system has one zero of importance, due to the
compensation capacitor (C3) and the compensation
resistor (R3). This zero is located at:
1
fZ1
=
2π × C3×R3
The system may have another zero of
importance, if the output capacitor has a large
capacitance and/or a high ESR value. The zero,
due to the ESR and capacitance of the output
capacitor, is located at:
Determine C3 by the following equation:
4
C3 >
2π × R3 × fC
Where R3 is the compensation resistor.
1
3. Determine if the second compensation
capacitor (C6) is required. It is required if the
ESR zero of the output capacitor is located at
less than half of the switching frequency, or the
following relationship is valid:
fESR
=
2π × C2× RESR
In this case, a third pole set by the
compensation capacitor (C6) and the
compensation resistor (R3) is used to
compensate the effect of the ESR zero on the
loop gain. This pole is located at:
fS
2
1
<
2π × C2× RESR
1
If this is the case, then add the second
compensation capacitor (C6) to set the pole fP3
at the location of the ESR zero. Determine C6
by the equation:
fP3
=
2π× C6×R3
The goal of compensation design is to shape
the converter transfer function to get a desired
loop gain. The system crossover frequency
where the feedback loop has the unity gain is
important. Lower crossover frequencies result
in slower line and load transient responses,
while higher crossover frequencies could cause
system instability. A good standard is to set the
crossover frequency below one-tenth of the
switching frequency.
C2 × RESR
C6 =
R3
External Bootstrap Diode
An external bootstrap diode may enhance the
efficiency of the regulator, the applicable
conditions of external BS diode are:
z VOUT is 5V or 3.3V; and
VOUT
To optimize the compensation components, the
following procedure can be used.
z Duty cycle is high: D=
>65%
VIN
In these cases, an external BS diode is
recommended from the output of the voltage
regulator to BS pin, as shown in Fig.2
1. Choose the compensation resistor (R3) to set
the desired crossover frequency.
Determine R3 by the following equation:
External BST Diode
IN4148
2π × C2 × fC VOUT 2π × C2 × 0.1× fS VOUT
R3 =
×
<
×
BS
GEA × GCS
VFB
GEA × GCS
VFB
CBST
MP1484
Where fC is the desired crossover frequency
which is typically below one tenth of the
switching frequency.
5V or 3.3V
SW
L
COUT
Figure 2—Add Optional External Bootstrap
Diode to Enhance Efficiency
The recommended external BS diode is IN4148,
and the BS cap is 0.1~1µF.
MP1484 Rev. 0.1
12/14/2007
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© 2007 MPS. All Rights Reserved.
8
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUIT
C5
10nF
INPUT
4.75V to 18V
2
1
IN
BS
OUTPUT
3.3V
3A
7
8
3
5
EN
SS
SW
MP1484
FB
GND
COMP
4
6
D1
C3
3.9nF
B130
C6
(optional)
(optional)
Figure 3—MP1484 with 3.3V Output, 22uF/6.3V Ceramic Output Capacitor
MP1484 Rev. 0.1
12/14/2007
www.MonolithicPower.com
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© 2007 MPS. All Rights Reserved.
9
MP1484 – 3A, 18V, 340KHz SYNCHRONOUS RECTIFIED STEP-DOWN CONVERTER
PACKAGE INFORMATION
SOIC8N (EXPOSED PAD)
0.189(4.80)
0.197(5.00)
0.124(3.15)
0.136(3.45)
8
5
0.150(3.80)
0.157(4.00)
0.228(5.80)
0.244(6.20)
0.089(2.26)
0.101(2.56)
PIN 1 ID
1
4
TOP VIEW
BOTTOM VIEW
SEE DETAIL "A"
0.051(1.30)
0.067(1.70)
SEATING PLANE
0.000(0.00)
0.006(0.15)
0.0075(0.19)
0.0098(0.25)
0.013(0.33)
0.020(0.51)
SIDE VIEW
0.050(1.27)
BSC
FRONT VIEW
0.010(0.25)
0.020(0.50)
x 45o
GAUGE PLANE
0.010(0.25) BSC
0.050(1.27)
0.024(0.61)
0.063(1.60)
0.016(0.41)
0.050(1.27)
0o-8o
DETAIL "A"
0.103(2.62)
0.213(5.40)
NOTE:
1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN
BRACKET IS IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH,
PROTRUSIONS OR GATE BURRS.
3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH
OR PROTRUSIONS.
0.138(3.51)
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING)
SHALL BE 0.004" INCHES MAX.
5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION BA.
6) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP1484 Rev. 0.1
12/14/2007
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2007 MPS. All Rights Reserved.
10
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