MP2396ES-LF [MPS]
Switching Regulator, Current-mode, 650kHz Switching Freq-Max, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8;
| 型号： | MP2396ES-LF |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Regulator, Current-mode, 650kHz Switching Freq-Max, PDSO8, ROHS COMPLIANT, MS-012AA, SOIC-8 开关 光电二极管 |
| 文件： | 总14页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2396
2A, 18V, 500kHz
Non-Synchronous Step-down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP2396 is a 500kHz non-synchronous
step-down switch mode converter with a built in
internal power high side MOSFET. It offers a
very compact solution to achieve 2A continuous
output current over a wide input supply range
with excellent load and line regulation.
•
•
•
•
•
•
•
•
•
•
•
•
Wide 4.5V to 18V Operating Input Range
2A Output Current
90mΩ Internal Power MOSFET
Fixed 500kHz switching frequency
Sync from 300kHz to 2MHz External Clock
Internal Compensation
Power Good Output
Integrated Bootstrap Diode
Over-Current Latch-off
Current mode operation provides fast transient
response and eases loop stabilization.
Full protection features include OCP and thermal
shut down.
Thermal Shutdown
Output Adjustable from 0.8V
Available in SOIC8 package.
The MP2396 requires a minimum number of
readily available standard external components
and is available in a space saving SOIC8
package.
APPLICATIONS
•
•
•
•
•
•
Notebook Systems and I/O Power
Networking Systems
Digital Set Top Boxes
Personal Video Recorders
Flat Panel Television and Monitors
Distributed Power Systems
“MPS” and “The Future of Analog IC Technology” are Registered Trademarks of
Monolithic Power Systems, Inc.
The information in this datasheet about the product and its associated
technologies are proprietary and intellectual property of Monolithic Power
Systems and are protected by copyright and pending patent applications
TYPICAL APPLICATION
Efficiency vs.Output Current
VOUT=3.3V
8
3
2
IN
BST
SW
V
100
90
IN
C1
22uF
C4
0.1uF
L1
4.7uH
80
7
V
V
=5V
OUT
3.3V
IN
VCC
V
=12V
70
60
50
40
30
20
10
0
IN
V
=18V
R3
100K
IN
MP2396
R1
D1
40.2K
6
4
PG
C2
47uF
5
FB
EN/SYNC
OFF ON
R2
13K
GND
1
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
MP2396 Rev. 0.9
9/17/2009
www.MonolithicPower.com
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1
MP2396 – 2A, 18V, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marketing
Temperature
MP2396ES
SOIC8
MP2396ES
–20°C to +85°C
For Tape & Reel, add suffix –Z (e.g. MP2396ES–Z); For RoHS compliant packaging, add suffix –LF;
(e.g. MP2396ES–LF–Z)
PACKAGE REFERENCE
TOP VIEW
GND
SW
1
2
3
4
8
7
6
5
IN
VCC
PG
FB
BST
EN/SYNC
Operating Temperature............. –20°C to +85°C
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage VIN ....................................... 20V
Thermal Resistance (4)
θJA
θJC
SOIC8 .....................................90 ...... 45...°C/W
VSW....................–0.3V （-5V for <10ns）to 21V
VBS .......................................................VSW + 6V
All Other Pins.................................–0.3V to +6V
Operating Temperature.............. -20°C to +85°C
Notes:
1) Exceeding these ratings may damage the device.
2) The device is not guaranteed to function outside of its
operating conditions.
(2)
3) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
Continuous Power Dissipation (TA = +25°C)
……………………………………………....1.4W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature.............. –65°C to +150°C
Recommended Operating Conditions (3)
Supply Voltage VIN ...........................4.5V to 18V
Output Voltage VOUT.........................0.8V to 15V
4) Measured on JESD51-7 4-layer board.
MP2396 Rev. 0.9
9/17/2009
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2
MP2396 – 2A, 18V, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA = +25°C, unless otherwise noted.
Parameters
Symbol
IIN
Condition
Min
Typ
Max
Units
μA
Supply Current (Shutdown)
Supply Current (Quiescent)
Switch On Resistance
Switch Leakage
VEN = 0V
10
IIN
VEN = 2V, VFB = 1V
650
90
μA
RDSON
SWLKG
ILIMIT
mΩ
μA
VEN = 0V, VSW =0V
0.1
3
10
Current Limit (5)
A
Oscillator Frequency
Fold-back Frequency
Maximum Duty Cycle
Sync Frequency Range
Feedback Voltage
FSW
VFB = 700mV
VFB = 300mV
VFB = 700mV
350
500
140
90
650
KHz
KHz
%
FFB
DMAX
FSYNC
VFB
85
0.3
794
2
MHz
mV
nA
810
10
826
50
Feedback Current
IFB
VFB = 800mV
VEN = 2V
EN Rising Threshold
EN Threshold Hysteresis
VEN_RISING
VEN_HYS
1.05
1.3
0.35
2
1.55
V
V
EN Input Current
IEN
μA
VEN = 0V
0.1
5
EN Turn Off Delay
ENTd-Off
μsec
ms
Soft-Start Period
1
3.5
0.9
0.7
15
5
Power Good High Threshold
Power Good Low Threshold
Power Good Delay
VTHPG
VTLPG
PGTd
VFB
VFB
μs
Power Good Sink Current
Capability
VPG
Sink 4mA
0.4
25
V
nA
V
Power Good Leakage Current
IPG_LEAK
INUVVth
VPG = 3.3V
VIN Under Voltage Lockout
Threshold Rising
3.75
4.0
4.25
VIN Under Voltage Lockout
Threshold Hysteresis
INUVHYS
VCC
880
mV
VCC Regulator
5.1
3
V
%
°C
VCC Load Regulation
Thermal Shutdown
Icc=1mA
TSD
150
Note:
5) Guaranteed by design.
MP2396 Rev. 0.9
9/17/2009
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name
GND
SW
Description
System Ground. This pin is the reference ground of the regulated output voltage.
For this reason care must be taken in PCB layout.
1
2
3
Switch Output. Use wide PCB traces and multiple vias to make the connection.
Bootstrap. A capacitor connected between SW and BS pins is required to form a
floating supply across the high-side switch driver.
BST
EN=1 to enable the chip. External clock can be applied to EN pin for changing
4
5
EN/SYNC switching frequency. For automatic start-up, connect EN pin to VIN by proper EN
resistor divider as Figure 2 shows.
Feedback. An external resistor divider from the output to GND, tapped to the FB
pin, sets the output voltage. To prevent current limit run away during a short circuit
fault condition the frequency fold-back comparator lowers the oscillator frequency
FB
when the FB voltage is below 500mV.
Power Good Output, the output of this pin is open drain. Power good threshold is
90% low to high and 70% high to low of regulation value.
6
7
PG
Bias Supply. Decouple with 0.1uF~0.22uF cap. And the capacitance should be no
more than 0.22uF.
VCC
Supply Voltage. The MP2396 operates from a +4.5V to +18V input rail. C1 is
8
IN
needed to decouple the input rail. Use wide PCB traces and multiple vias to make
the connection.
MP2396 Rev. 0.9
9/17/2009
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CURVES
VIN=12V, VOUT=3.3V, L=4.7uH, TA = +25°C, unless otherwise noted.
Enable Supply Current
vs. Input Voltage
Disable Supply Current
vs. Input Voltage
V
Regulator Line Regulation
CC
V
=1V
V
=0V
FB
EN
800
790
780
770
760
750
740
730
720
710
700
0.2
0.15
0.1
5
4.5
4
0.05
0
-0.05
-0.1
-0.15
-0.2
3.5
3
0
5
10
15
20
0
5
10
15
20
0
5
10
15
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Peak Current vs. Duty Cycle
Operating Range
Load Regulation
7
6
5
4
3
2
1
0
100
10
1
0.5
0.4
0.3
0.2
0.1
Dmax Limit
V
=12V
IN
0
Minimum on time
-0.1
V
=18V
IN
-0.2
-0.3
-0.4
-0.5
0.1
0 10 20 30 40 50 60 70 80 90100
DUTY CYCLE (%)
0
5
10
15
20
0
0.5
1
1.5
2.5
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Line Regulation
14
12
10
8
0.5
0.4
0.3
0.2
0.1
0
IO=0A
IO=1A
6
-0.1
-0.2
-0.3
-0.4
-0.5
IO=2A
4
2
0
0
5
10
15
20
0
0.5
1
1.5
2
INPUT VOLTAGE (V)
OUTPUT CURRENT (A)
MP2396 Rev. 0.9
9/17/2009
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CURVES (continued)
VIN=12V, VOUT=3.3V, L=4.7uH, TA = +25°C, unless otherwise noted.
Efficiency vs.Output Current
VOUT=1.2V
Efficiency vs.Output Current
VOUT=1.8V
Efficiency vs.Output Current
VOUT=2.5V
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
V
=5V
IN
V
=5V
V
=12V
IN
IN
V
=12V
V
=18V
IN
IN
V
=5V
IN
V
=18V
V
=12V
IN
IN
V
=18V
IN
0
0.5
1
1.5
2
0
0.5
1
1.5
2
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Efficiency vs.Output Current
VOUT=3.3V
100
90
80
70
60
50
40
30
20
10
0
V
=5V
IN
V
=12V
IN
V
=18V
IN
0
0.5
1
1.5
2
OUTPUT CURRENT (A)
MP2396 Rev. 0.9
9/17/2009
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CURVES (continued)
VIN=12V, VOUT=3.3V, L=4.7uH, TA = +25°C, unless otherwise noted.
Short Entry
I0=2A
Power up without Load
Power up with 2A Load
V
V
OUT
2V/div
OUT
2V/div
V
OUT
2V/div
V
V
SW
SW
10V/div
10V/div
V
SW
10V/div
V
V
IN
IN
10V/div
10V/div
I
I
INDUCTOR
2A/div
I
INDUCTOR
2A/div
INDUCTOR
2A/div
200us/div
4ms/div
4ms/div
Enable Startup without Load
Enable Startup with 2A Load
Load Transient Response
I0=1A~2A
V
OUT/AC
V
V
OUT
2V/div
OUT
2V/div
100mV/div
V
SW
V
SW
10V/div
10V/div
V
V
EN
EN
5V/div
5V/div
I
LOAD
2A/div
I
INDUCTOR
2A/div
I
INDUCTOR
2A/div
4ms/div
4ms/div
200us/div
Input Ripple Voltage
IOUT=2A
Output Ripple Voltage
IOUT=2A
V
OUT/AC
V
IN/AC
10mV/div
100mV/div
V
SW
10V/div
V
SW
5V/div
I
INDUCTOR
2A/div
1us/div
MP2396 Rev. 0.9
9/17/2009
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER
BLOCK DIAGRAM
IN
+
- -
VCC
VCC
REGULATOR
CURRENT SENSE
RSEN
AMPLIFIER
BOOST
REGULATOR
PG
BST
PG
COMPARATOR
+
- -
HS
DRIVER
OSCILLATOR
Q
S
0
+
--
R
R
SW
CURRENT
LIMIT
1pF
COMPARATOR
EN/SYNC
FB
REFERENCE
1MEG
50pF
+
+
--
+
0
--
PWM
ERROR
AMPLIFIER
COMPARATOR
GND
0
Figure 1—Functional Block Diagram
MP2396 Rev. 0.9
9/17/2009
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER
1) Enabled by external logic H/L signal
OPERATION
The chip starts up once the enable signal goes
higher than EN/SYNC input high voltage (2V),
and is shut down when the signal is lower than
EN/SYNC input low voltage (0.4V). To disable
the chip, EN must be pulled low for at least 5µs.
The input is compatible with both CMOS and TTL.
2) Enabled by Vin through voltage divider.
Connect EN with VIN through a resistive voltage
divider for automatic startup as the figure 2
shows.
The MP2396 is
a
high frequency non-
synchronous step-down switch mode converter
with built in internal power MOSFETs. It offers a
very compact solution to achieve 2A continuous
output current over a wide input supply range
with excellent load and line regulation.
The MP2396 operates in a fixed frequency, peak
current control mode to regulate the output
voltage. A PWM cycle is initiated by the internal
clock. The integrated high-side power MOSFET
is turned on and remains on until its current
reaches the value set by the COMP voltage.
When the power switch is off, it remains off until
the next clock cycle starts. If, in 90% of one PWM
period, the current in the power MOSFET does
not reach the COMP set current value, the power
MOSFET will be forced to turn off
V
IN
R
EN1
EN
R
EN2
Figure 2—Enable Divider Circuit
Power Good Indicator
Choose the value of the pull-up resistor REN1 and
pull-down resistor REN2 to reset the automatic
start-up voltage:
When the FB is below 0.70VFB, the PG pin will be
internally pulled low. When the FB is above
0.9VFB, the PG becomes an open-drain output.
Internal Regulator
(REN1 + REN2 ||1MΩ)
V
= VEN_RISING ⋅
IN_START
REN2 ||1MΩ
Most of the internal circuitries are powered from
the 5V internal regulator. This regulator takes the
VIN input and operates in the full VIN range.
When VIN is greater than 5.0V, the output of the
regulator is in full regulation. When VIN is lower
than 5.0V, the output decreases, a 0.1uF ceramic
capacitor for decoupling purpose is required.
(REN1 + REN2 ||1MΩ)
REN2 ||1MΩ
V
=
VEN-FALLING ⋅
IN_STOP
Error Amplifier
The error amplifier compares the FB pin voltage
with the internal 0.810V reference (REF) and
outputs a current proportional to the difference
between the two. This output current is then used
to charge or discharge the internal compensation
network to form the COMP voltage, which is used
to control the power MOSFET current. The
Figure 3—Startup Sequence Using EN Divider
optimized
internal
compensation
network
3) Synchronized by External Sync Clock Signal
The chip can be synchronized to external clock
range from 300kHz up to 2MHz through this pin
2ms right after output voltage is set, with the
internal clock rising edge synchronized to the
external clock rising edge.
minimizes the external component counts and
simplifies the control loop design.
Enable/Sync Control
EN/Sync is a digital control pin that turns the
regulator on and off. Drive EN high to turn on the
regulator, drive it low to turn it off. There is an
internal 1MEG resistor from EN/Sync to GND
thus EN/Sync can be floated to shut down the
chip.
MP2396 Rev. 0.9
9/17/2009
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9
MP2396 – 2A, 18V, STEP-DOWN CONVERTER
lower threshold, typically 140°C, the chip is
enabled again.
Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection. This UVLO’s
rising threshold is 2.2V with a hysteresis of
150mV. The bootstrap capacitor voltage is
regulated internally by VIN through D1, M3, C4,
L1 and C2 (Figure 5). If (VIN-VSW) is more than
5V, U2 will regulate M3 to maintain a 5V BST
voltage across C4.
Figure 4—Startup Sequence Using External
Sync Clock Signal
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) is implemented to
protect the chip from operating at insufficient
supply voltage. The MP2396 UVLO comparator
monitors the output voltage of the internal
regulator, VCC. The UVLO rising threshold is
about 4.0V while its falling threshold is a
consistent 3.2V.
SW
Internal Soft-Start
The soft-start is implemented to prevent the
converter output voltage from overshooting
during startup. When the chip starts, the internal
circuitry generates a soft-start voltage (SS)
ramping up from 0V to 1.2V. When it is lower
than the internal reference (REF), SS overrides
REF so the error amplifier uses SS as the
reference. When SS is higher than REF, REF
regains control. The SS time is internally fixed to
4ms.
Figure 5—Internal Bootstrap Charging Circuit
Startup and Shutdown
If both VIN and EN are higher than their
appropriate thresholds, the chip starts. The
reference block starts first, generating stable
reference voltage and currents, and then the
internal regulator is enabled. The regulator
provides stable supply for the remaining
circuitries.
Three events can shut down the chip: EN low,
VIN low and thermal shutdown. In the shutdown
procedure, the signaling path is first blocked to
avoid any fault triggering. The COMP voltage and
the internal supply rail are then pulled down. The
floating driver is not subject to this shutdown
command.
Over-Current-Protection and Latch Off
The MP2396 has cycle-by-cycle over current limit
when the inductor current peak value exceeds
the set current limit threshold. Meanwhile, output
voltage starts to drop until FB is below the Under-
Voltage (UV) threshold, typically 30% below the
reference. Once a UV is triggered, the MP2396 is
latched off until En or IN is recycled. This
protection mode is especially useful when the
output is dead-short to ground.
Thermal Shutdown
Thermal shutdown is implemented to prevent the
chip from operating at exceedingly high
temperatures. When the silicon die temperature
is higher than 150°C, it shuts down the whole
chip. When the temperature is lower than its
MP2396 Rev. 0.9
9/17/2009
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER
Choose inductor ripple current to be
approximately 30% if the maximum load current,
2A. The maximum inductor peak current is:
APPLICATION INFORMATION
Setting the Output Voltage
The external resistor divider is used to set the
output voltage (see Typical Application on page
1). The feedback resistor R1 also sets the
feedback loop bandwidth with the internal
ΔIL
IL(MAX) = ILOAD
+
2
Under light load conditions below 100mA, larger
inductance is recommended for improved
efficiency.
compensation
capacitor
(see
Typical
Application on page 1). Choose R1 to be
around 40.2kꢀ for optimal transient response.
R2 is then given by:
Output Rectifier Diode
The output rectifier diode supplies the current to
the indicator when the high-side switch is off.
To reduce losses due to the diode forward
voltage and recovery times, use a Schottky
diode.
R1
R2 =
VOUT
−1
VFB
The T-type network is highly recommended when
Vo is low, as Figure 6 shows.
Choose a diode whose maximum reverse
voltage rating is greater than the maximum
input voltage and whose current rating is
greater than the maximum load current. Table 2
R1
Rt
1
FB
VOUT
lists
example
Schottky
diodes
and
R2
manufacturers.
Table 2—Diode Selection Guide
Voltage/Current
Figure 6— T-type Network
Table 1 lists the recommended T-type resistors
value for common output voltages.
Part No.
Raging
Manufacture
B330A
30V, 3A
Diodes Inc.
Table 1—Resistor Selection for Common
Output Voltages
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous, therefore a capacitor is required to
supply the AC current to the step-down converter
while maintaining the DC input voltage. Use low
ESR capacitors for the best performance. Ceramic
capacitors with X5R or X7R dielectrics are
highly recommended because of their low ESR
and small temperature coefficients. For most
applications, a 22µF capacitor is sufficient.
VOUT (V)
1.05
1.2
R1 (kΩ)
4.99(1%)
4.99(1%)
4.99(1%)
4.99(1%)
40.2 (1%)
40.2(1%)
40.2(1%)
R2 (kΩ)
Rt (kΩ)
16.5(1%) 24.9(1%)
10.2(1%) 24.9(1%)
5.76(1%) 24.9(1%)
4.02(1%) 24.9(1%)
1.5
1.8
2.5
19.1(1%)
13(1%)
0
0
0
3.3
5
7.68(1%)
Since the input capacitor (C1) absorbs the input
switching current it requires an adequate ripple
current rating. The RMS current in the input
capacitor can be estimated by:
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
of at least 25% percent higher than the
maximum load current is recommended for
most applications. For highest efficiency, the
inductor DC resistance should be less than
15mꢀ. For most designs, the inductance value
can be derived from the following equation.
⎛
⎞
⎟
VOUT
VIN
VOUT
VIN
⎜
IC1 = ILOAD
×
× 1−
⎜
⎝
⎟
⎠
The worse case condition occurs at VIN = 2VOUT,
where:
VOUT × (VIN − VOUT
VIN × ΔIL × fOSC
)
ILOAD
L =
IC1
=
2
Where ΔIL is the inductor ripple current.
MP2396 Rev. 0.9
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MP2396 – 2A, 18V, STEP-DOWN CONVERTER WITH INTERNAL MOSFETS
For simplification, choose the input capacitor
whose RMS current rating greater than half of
the maximum load current.
PCB Layout
PCB layout is very important to achieve stable
operation. Please follow these guidelines and
take Figure 7 for references.
The input capacitor can be electrolytic, tantalum
or ceramic. When using electrolytic or tantalum
capacitors, a small, high quality ceramic
capacitor, i.e. 0.1μF, should be placed as close
to the IC as possible. When using ceramic
capacitors, make sure that they have enough
capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The
input voltage ripple caused by capacitance can
be estimated by:
1) Keep the power loop of input capacitor, HS
switch, LS switch as small as possible.
2) Keep the connection of input capacitor and
IN pin as short and wide as possible.
3) Ensure all feedback connections are short
and direct. Place the feedback resistors
and compensation components as close to
the chip as possible.
4) Route SW away from sensitive analog
areas such as FB.
5) Connect IN, SW, and especially GND
respectively to a large copper area to cool
the chip to improve thermal performance
and long-term reliability.
⎛
⎜
⎝
⎞
⎟
⎟
⎠
ILOAD
VOUT
VIN
VOUT
⎜
ΔV
=
×
× 1−
IN
fS × C1
V
IN
Selecting the Output Capacitor
The output capacitor (C2) is required to
maintain the DC output voltage. Ceramic,
tantalum, or low ESR electrolytic capacitors are
recommended. Low ESR capacitors are
preferred to keep the output voltage ripple low.
The output voltage ripple can be estimated by:
6) Adding RC snubber circuit from IN pin to
SW pin can reduce SW spikes.
⎛
⎜
⎝
⎞
⎟
⎟
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
VOUT
VIN
1
⎜
⎜
ΔVOUT
=
× 1−
× RESR
+
fS × L
8 × fS × C2
⎠
Where L is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
In the case of ceramic capacitors, the
impedance at the switching frequency is
dominated by the capacitance. The output
voltage ripple is mainly caused by the
capacitance. For simplification, the output
voltage ripple can be estimated by:
Top Layer
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
8 × fS2 × L × C2
VOUT
⎜
ΔVOUT
=
× 1−
V
IN
In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the
output ripple can be approximated to:
VOUT
VOUT
⎛
⎞
ΔVOUT
=
× ⎜1−
⎟ ×RESR
⎜
⎟
fS ×L
VIN
⎝
⎠
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP2396 can be optimized for a wide range of
capacitance and ESR values.
Bottom Layer
Figure 7—PCB Layout
MP2396 Rev. 0.9
9/17/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
12
MP2396 – 2A, 18V, STEP-DOWN CONVERTER
External Bootstrap Diode
An external bootstrap diode may enhance the
efficiency of the regulator, the applicable
conditions of external BST diode is:
VOUT
z Duty cycle is high: D=
>65%
VIN
In this case, an external BST diode is
recommended from the VCC pin to BST pin, as
shown in Figure 8
External BST Diode
IN4148
BST
VCC
CBST
MP2396
SW
L
COUT
Figure 8—Add Optional External Bootstrap
Diode to Enhance Efficiency
The recommended external BST diode is IN4148,
and the BST cap is 0.1~1µF
MP2396 Rev. 0.9
9/17/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
13
MP2396 – 2A, 18V, STEP-DOWN CONVERTER
PACKAGE INFORMATION
SOIC8
MP2396 Rev. 0.9
9/17/2009
www.MonolithicPower.com
MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited.
© 2009 MPS. All Rights Reserved.
14
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CTS
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