MP2420 [MPS]
75V, 0.3A Synchronous Step-Down Converter with Watchdog;
| 型号： | MP2420 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | 75V, 0.3A Synchronous Step-Down Converter with Watchdog |
| 文件： | 总22页 (文件大小：728K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2420
75V, 0.3A Synchronous
Step-Down Converter with Watchdog
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP2420 is a step-down switching regulator
with integrated high- and low-side, high-voltage
power MOSFETs. It achieves a highly efficient
output of up to 0.3A, and the integrated
watchdog adds additional security redundancy
to the system.
•
•
20μA Quiescent Current for Buck Only
Wide 4.5V to 75V Operating Input Range
(80V ABS MAX)
1.2Ω/0.45Ω Internal Power MOSFETs
Programmable Soft Start
FB Tolerance: 1% at Room Temperature,
2% at Full Temperature
Adjustable Output Voltage
•
•
•
The wide 4.5V to 75V input range accommodates
a variety of step-down applications in an
automotive environment. A 5μA shutdown
mode quiescent current in a full temperature
range is ideal for battery-powered applications.
•
•
•
Integrated Window Watchdog
Power-On Reset during Power Up and
Under-Voltage Lockout (UVLO)
Programmable Short Window Mode or Long
Window Mode
Low Shutdown Mode Current of 5μA
Available in a TSSOP-16 EP Package
•
The MP2420 allows for high-power conversion
efficiency over a wide load range by scaling
down the switching frequency under light-load
conditions to reduce switching and gate driver
losses. The start-up switching frequency and
short circuit can also be scaled down to prevent
an inductor current runaway.
•
•
APPLICATIONS
•
•
•
•
Automotive Systems
Industrial Power Systems
Distributed Power Systems
Battery-Powered Systems
Full protection features include under-voltage
lockout (UVLO) and thermal shutdown. Thermal
shutdown provides reliable, fault-tolerant
operation.
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive.
For MPS green status, please visit the MPS website under Quality
Assurance. “MPS” and “The Future of Analog IC Technology” are registered
trademarks of Monolithic Power Systems, Inc.
The MP2420 is available in a TSSOP-16 EP
package.
TYPICAL APPLICATION
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
1
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP2420GF
TSSOP-16 EP
See Below
* For Tape & Reel, add suffix –Z (e.g. MP2420GF–Z)
TOP MARKING
MPS: MPS prefix
YY: Year code
WW: Week code
MP2420: Part code of MP2420GF
LLLLLL: Lot number
PACKAGE REFERENCE
TOP VIEW
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
TSSOP-16 EP
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
2
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ………….......-0.3V to +80V
Switch voltage (VSW) …… …….-0.3V to VIN + 1V
BST to SW…………………… .……-0.3 to +6.0V
All other pins………………... ……-0.3V to +6.0V
EN sink current………………............……150µA
Thermal Resistance (4)
TSSOP-16 EP ……..……..……45……10…°C/W
θJA
θJC
NOTES:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ (MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD (MAX) = (TJ
(MAX)-TA)/θJA. Exceeding the maximum allowable power
dissipation produces an excessive die temperature, causing
the regulator to go into thermal shutdown. Internal thermal
shutdown circuitry protects the device from permanent
damage.
(2)
Continuous power dissipation (TA = +25°C)
TSSOP-16 EP………………………..…..….2.7W
Junction temperature…………... …………150°C
Lead temperature …………...... …………260°C
Storage temperature………….. -65°C to +150°C
Recommended Operating Conditions (3)
Supply voltage (VIN)…………...........4.5V to 75V
Output voltage (VOUT)………………1V to 0.9xVIN
Operating junction temp. (TJ)..... -40°C to 125°C
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
3
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ELECTRICAL CHARACTERISTICS
VIN = 24V, VEN = 2V, VCC = 5V, TJ = +25°C, unless otherwise noted.
Parameter
Condition
Min
Typ
Max
Units
DC/DC Converter
Supply quiescent current
Shutdown supply current
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN UVLO hysteresis
No load, VFB = 1.2V
VEN < 0.3V
20
2.2
25
3.5
μA
μA
V
3.9
4.2
4.4
3.45
3.75
0.45
1.0
3.95
V
V
VIN = 4.5V to 75V, TJ = 25°C
0.99
0.98
1.01
1.02
Feedback voltage
VIN = 4.5V to 75V,
-40°C < TJ < 125°C
1.0
V
Feedback current
VREF voltage
VFB = 1.2V
-50
0.965
0.9
2
1
50
1.035
1.5
nA
V
VIN = 4.5V to 75V, IREF = 100μA
Upper switch-on resistance VBST - VSW = 5V
Lower switch-on resistance VBIAS = 5V
1.2
0.45
Ω
0.275
0.625
1
Ω
Lower switch leakage
VEN = 0V, VSW = 75V
μA
mA
ns
V
Peak current limit
670
730
120
1.55
1.2
0.35
0.8
5.5
90
790
Minimum switch-on time(5)
Enable rising threshold
Enable falling threshold
Enable threshold hysteresis
Enable current
1.25
1.85
1.152
1.248
V
V
VEN = 2.4V
μA
μA
%
%
%
μs
V
Soft-start current
4
7
POK upper trip threshold
POK lower trip threshold
POK threshold hysteresis
POK deglitch timer
FB respect to the nominal value
FB respect to the nominal value
FB respect to the nominal value
86
81
94
89
85
5
40
POK output voltage low
FB OVP rising threshold
FB OVP hysteresis
ISINK = 1mA
0.4
1.1
1.05
50
V
mV
°C
Thermal shutdown(5)
175
Thermal shutdown
hysteresis(5)
20
°C
NOTE:
5) Derived from bench characterization. Not tested in production.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
4
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
ELECTRICAL CHARACTERISTICS (continued)
VIN = 24V, VEN = 2V, VCC = 5V, TJ = 25°C, unless otherwise noted.
Parameter
Symbol Condition
Min
Typ
Max Units
Watchdog Power Supply
Timer voltage
RTIMER = 51k
0.3
16
25
V
RTIMER = 100k
IQ
19
32
μA
μA
Quiescent current
RTIMER = 51k
VPOR-HIGH WDO goes high with rising VCC
VPOR-LOW WDO goes low with falling VCC
4.4
4.3
4.6
4.5
4.8
4.7
V
V
Power-on reset
threshold
Watchdog Timing
Single period
Power-on delay(6)
T
t0
RTIMER = 51k
RTIMER = 51k
-10%
880
10
+10%
µs
cycle
Sync signal monitoring
time(6)
t1
t2
t3
t4
t5
t6
RTIMER = 51k
450
15
cycle
cycle
cycle
cycle
cycle
Watchdog window close
time (short mode) (6)
RTIMER = 51k, mode = low
RTIMER = 51k, mode = low
RTIMER = 51k, mode = high
RTIMER = 51k, mode = high
RTIMER = 51k
Watchdog window open
time (short mode) (6)
10
Watchdog window close
time (long mode) (6)
1500
1000
4
Watchdog window open
time (long mode) (6)
WDO reset pulse
width(6)
cycle
WDI_OK pulse width
Watchdog Input and Output
WDI logic high
10
3.2
3.2
5000
0.8
μs
V
V
WDI logic low
MODE logic high
MODE logic low
V
0.8
1
V
MODE = 5V
MODE = 0V
0.1
5
μA
μA
V
MODE input current
8
/WD_DIS logic high
/WD_DIS logic low
3.2
0.8
1
V
WD_DIS = 5V
0.1
5
μA
μA
V
/WD_DIS input current
WDO high
WD_DIS = 0V
8
VCC = 5V, IWDO = 1mA
VCC = 5V, IWDO = 1mA
VCC = 1V, IWDO = 300μA
VCC-0.2
0.2
0.1
V
WDO low
V
NOTE:
6) Guaranteed by design.
MP2420 Rev. 1.0
www.MonolithicPower.com
5
9/6/2015
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL CHARACTERISTICS
DC/DC CONVERTER
VIN = 12V, unless otherwise noted.
Feedback Voltage vs.
Quiescent Current vs.
Junction Temperature
Shutdown Current vs.
Junction Temperature
Junction Temperature
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.010
30
27
24
21
18
15
1.008
1.006
1.004
1.002
1.000
0.998
0.996
0.994
0.992
0.990
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
Current Limit vs.
Switch On Resistance vs.
Junction Temperature
EN Threshold vs.
Junction Temperature
Junction Temperature
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
750
740
730
720
710
700
690
680
670
660
650
Upper
Rising
Falling
Lower
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
V
IN
UVLO vs.
V
REF
vs.
I
SS
vs.
Junction Temperature
Junction Temperature
Junction Temperature
4.5
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
1.02
1.01
1.00
0.99
0.98
0.97
5.5
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
Rising
Falling
-50 -25
0
25 50 75 100 125
JUNCTION TEMPERATURE (°C)
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
JUNCTION TEMPERATURE (°C)
JUNCTION TEMPERATURE (°C)
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
6
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL CHARACTERISTICS (continued)
WATCHDOG
Quiescent Current vs.
Junction Temerature
Quiescent Current vs.
Junction Temerature
RTIMER=100k
Single Period vs.
Junction Temerature
RTIMER=51k
RTIMER=51k
28.5
28.0
27.5
27.0
26.5
26.0
25.5
25.0
910
900
890
880
870
860
850
17.0
16.8
16.6
16.4
16.2
16.0
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
8000
7000
6000
5000
4000
3000
2000
1000
0
0
100 200 300 400 500
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
7
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL PERFORMANCE CHARACTERISTICS
DC-DC CONVERTER
VIN = 12V, VOUT = 3.3V, L = 33µH, COUT = 2x22µF, TA = 25°C, unless otherwise noted.
Load Current
0.5
0.0
90
80
70
60
50
40
30
20
10
0
0.20
0.15
0.10
0.05
0.00
-0.05
-0.10
-0.15
-0.20
-0.5
-1.0
-1.5
-2.0
-2.5
0.1
1
10
100
1000
0
30 60 90 120150180210240270300
0
20
40
60
80
V
/AC
OUT
V
/AC
OUT
50mV/div.
50mV/div.
V
IN
5V/div.
V
OUT
I
2V/div.
L
500mA/div.
SW
5V/div.
V
SW
5V/div.
SW
5V/div.
I
I
L
L
500mA/div.
500mA/div.
V
IN
10V/div.
V
V
IN
IN
5V/div.
5V/div.
V
V
OUT
OUT
V
2V/div.
2V/div.
OUT
2V/div.
V
SW
I
I
L
L
10V/div.
500mA/div.
500mA/div.
I
V
V
L
SW
SW
500mA/div.
10V/div.
10V/div.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
8
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 33µH, COUT = 2x22µF, TA = 25°C, unless otherwise noted.
EN
2V/div.
EN
2V/div.
EN
2V/div.
V
V
OUT
OUT
2V/div.
2V/div.
V
OUT
I
I
2V/div.
L
L
I
500mA/div.
500mA/div.
L
500mA/div.
SW
SW
SW
5V/div.
10V/div.
2V/div.
V
V
OUT
OUT
EN
2V/div.
2V/div.
2V/div.
V
I
OUT
L
I
2V/div.
500mA/div.
L
500mA/div.
I
L
500mA/div.
SW
10V/div.
SW
5V/div.
SW
5V/div.
V
OUT
500mV/div.
V
V
OUT
OUT
2V/div.
2V/div.
I
I
L
L
500mA/div.
200mA/div.
I
L
500mA/div.
SW
5V/div.
SW
5V/div.
SW
5V/div.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
9
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
PIN FUNCTIONS
Pin #
Name
Description
Watchdog
1
2
WDO
WDI
Watchdog output. WDO outputs the reset signal to the MCU.
Watchdog input. WDI receives the trigger signal from the MCU.
Mode switching. Pull MODE high to make the watchdog work in long window
3
MODE
mode; pull MODE low to make the watchdog work in short window mode. MODE
has a weak internal pull-up.
Ground. Connect GND as close the output capacitor as possible to avoid high-
current switch paths.
4
GND
14
15
VCC
Power input.
TIMER
Watchdog timer. Set the time-out with an external resistor.
Watchdog disable. Pull /WD_DIS low to disable the watchdog; pull /WD_DIS high
to enable the watchdog. /WD_DIS has a weak internal pull-up.
16
/WD_DIS
DC/DC
4
GND
IN
Ground. Same as GND in Watchdog.
Input supply. IN requires a decoupling capacitor connected to ground to reduce
switching spikes.
5
Enable input. Pull EN below the low threshold to shut the chip down; pull EN
above the high threshold to enable the chip. Float EN to shut the chip down.
6
7
EN
VREF
Reference voltage output.
Feedback input to the error amplifier (for QFN-10 (3mmx3mm) package only).
Connect FB to the tap of an external resistive divider between output and GND. FB
sets the regulation voltage when compared to the internal 1V reference.
8
FB
Soft-start control input. Connect a capacitor from SS to GND to set the soft-start
period.
9
SS
Open-drain power good output. A high output indicates that VOUT is higher than
90% of the reference. POK is pulled down during shutdown.
10
POK
Controller bias input. BIAS supplies a current to the internal circuit when VBIAS
>
11
BIAS
2.9V. BIAS is the feedback input for the SOIC-8 E package, which has a fixed
output only.
Bootstrap. BST is the positive power supply for the internal floating high-side
MOSFET driver. Connect a bypass capacitor between BST and SW.
12
13
BST
SW
Switch node.
Exposed Pad Connect the exposed pad to the GND plane for optimal thermal performance.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
10
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
FUNCTIONAL BLOCK DIAGRAM
VIN
BIAS
BST
REGULATOR
REF
VREF
EN
EN Control
+
-
SW
3M
ILIMIT
POK
SS
POK
S
RS
+
+
R
SS
-
FB
ZCD
FB
VCC
Power On
Reset
Oscillator,
State Machine
WDGND
GND
/WD_DIS
MODE WDI
WDO
TIMER
Figure 1: Functional Block Diagram
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
11
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Internal Regulator and BIAS
OPERATION
DC/DC SECTION:
The 2.6V internal regulator powers most of the
internal circuitry. This regulator takes VIN and
The MP2420 is a 75V, 0.3A, synchronous step-
down, switching regulator with integrated high-
side and low-side, high-voltage power MOSFETs
(HS-FET and LS-FET, respectively). It provides a
highly efficient 0.3A output and features a wide
input voltage range, external soft-start control,
and precision current limit. It has a very low
operational quiescent current, making it suitable
for battery-powered applications.
operates in the full VIN range. When VIN is greater
than 3.0V, the output of the regulator is in full
regulation. Lower values of VIN result in lower
output voltages. When VBIAS > 2.9V, the BIAS
supply overrides the input voltage and supplies
power to the internal regulator. When VBIAS
4.5V, BIAS powers the LS-FET driver.
>
Using BIAS to power the internal regulator
improves efficiency. It is recommended to
connect BIAS to the regulated output voltage
when it is in the 2.9V to 5.5V range. When the
output voltage is out of this range, an external
supply of >2.9V to >4.5V can be used to power
BIAS.
Control Scheme
The ILIM comparator, FB comparator, and zero
current detector (ZCD) block control the PWM
(see Figure 2). If VFB is below the 1V reference
and the inductor current drops to zero, the HS-
FET turns on, and the ILIM comparator begins
sensing the HS-FET current. When the HS-FET
current reaches its limit, the HS-FET turns off,
and the LS-FET and ZCD block turn on. The ILIM
comparator turns off to reduce the quiescent
current. The LS-FET and ZCD block turn off after
the inductor current drops to zero. If VFB is below
the 1V reference at this time, the HS-FET turns
on and begins another cycle. If VFB is still higher
than the 1V reference, the HS-FET remains off
until VFB drops below 1V.
Enable (EN) Control
The MP2420 has a dedicated enable control
(EN). When VIN goes high, EN enables and
disables the chip (high logic). Its falling threshold
is a consistent 1.2V, and the rising threshold is
about 350mV higher. When floating, EN is pulled
down internally to GND to disable the chip.
When EN = 0V, the chip enters the lowest
shutdown current mode. When EN is higher than
zero but lower than its rising threshold, the chip
remains in shutdown mode with a slightly larger
shutdown current.
VFB
VREF
VSW
A Zener diode is connected internally from EN to
GND. The typical clamping voltage of the Zener
diode is 6.5V. VIN can be connected to EN
through a high ohm (ꢀ) resistor if the system
does not have another logic input acting as the
EN signal. The resistor must be designed to limit
the EN sink current to less than 150μA. Note that
there is an internal 3Mꢀ resistor from EN to GND,
so the external pull up resistor should be smaller
[VIN(MIN) -1.55V]×3M
Ipeak
Io
IL
Io increase
than
to ensure that EN can
1.55V
turn on at the lowest operation (VIN).
Under-Voltage Lockout (UVLO)
Figure 2: Control Scheme
VIN under-voltage lockout (UVLO) protects the
chip from operating below its operational supply
voltage range. The UVLO rising threshold is
about 4.2V while its trailing threshold is about
3.75V.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
12
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Soft Start (SS)
As long as VIN is sufficiently higher than SW, the
bootstrap capacitor can charge. When the HS-
FET is on, VIN is about equal to SW, and the
bootstrap capacitor cannot charge. The optimal
charging period occurs when the LS-FET is on,
and VIN - VSW is at its largest. VSW is equal to VOUT
when there is no current in the inductor. The
difference between VIN and VOUT charges the
bootstrap capacitor.
The reference-type soft start prevents the
converter output voltage from overshooting
during start-up. When the chip starts, the internal
circuitry generates a constant current to charge
the external soft-start capacitor. The SS voltage
ramps up slowly from 0V at a pace set by the SS
time. When VSS is less than VREF, VSS overrides
VREF, and the FB comparator uses VSS as the
reference instead of VREF. When VSS is higher
than VREF, VREF resumes control.
If the internal circuit does not have sufficient
voltage and time to charge the bootstrap
capacitor, extra external circuitry can be used to
ensure that the bootstrap voltage operates in its
normal region.
VSS can be much smaller than VFB, but it can only
barely exceed VFB. If VFB drops, VSS tracks VFB.
This function prevents an output voltage
overshoot during short-circuit recovery. When the
short circuit is removed, a new SS process
ramps up.
Start-Up and Shutdown
If both VIN and VEN are higher than their
appropriate thresholds, the chip starts up. The
reference block starts first, generating stable
reference voltages and currents, and then it
enables the internal regulator. The regulator
provides a stable supply for the rest of the device.
Thermal Shutdown
Thermal shutdown prevents a thermal runaway
on the chip. When the silicon die reaches
temperatures exceeding its upper threshold, the
entire chip shuts down. When the temperature
falls below its lower threshold, the chip is enabled
again.
If the internal supply rail is high, an internal timer
holds the power MOSFET off for about 50µs to
clear up any start-up glitches. When the soft-start
block is enabled, the SS output voltage is first
held low and then slowly ramps up.
Floating Driver and Bootstrap Charging
The external bootstrap capacitor powers the
floating HS-FET driver. This floating driver has
its own UVLO protection. This UVLO’s rising
threshold is about 2.4V with a hysteresis of about
300mV. During the UVLO, the SS voltage resets
to zero. When the UVLO is disabled, the
regulator follows the soft-start process.
Three events can shut down the chip: VEN low,
VIN low, and thermal shutdown. During the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. The
internal supply rails are then pulled down. The
floating driver is not subject to this shutdown
command, but its charging path is disabled.
The dedicated internal bootstrap regulator
charges and regulates the bootstrap capacitor to
about 5V. When the voltage difference between
BST and SW falls below its working parameters,
a PMOS pass transistor connected from VIN to
BST turns on to charge the bootstrap capacitor.
The current path runs from VIN to BST to SW.
The external circuit must have sufficient voltage
headroom to accommodate charging.
Power OK (POK)
POK is an open-drain power good output. A high
output indicates that VOUT is higher than 90% of
its nominal value. POK is pulled down in
shutdown mode.
Reference Voltage Output (VREF
)
VREF has an output reference voltage of 1V. It has
up to 500µA of source current capability.
MP2420 Rev. 1.0
9/6/2015
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13
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
WATCHDOG SECTION:
Supply Voltage
Long Window Mode
A supply voltage of VCC = 5V +/-10% is
recommended for normal operation. WDO is
pulled low when VCC rises to 1V or above. After
If the MCU and watchdog are synchronized
correctly and MODE is high, the watchdog
works in long window mode if WDI_OK is
received in a window close state (t4). The
watchdog outputs a reset signal and enters a
sync signal monitoring state.
VCC rises to 4.65V, WDO remains at a low level
for t0 to reset the MCU.
Timer
Calculate the period T (µs) with Equation (1):
If WDI_OK is received in a window open state
(t5), the watchdog enters a window close state.
The MCU is in normal operation in this situation.
T μs = 15.75×R
kΩ + 73.5 (1)
(
)
(
)
TIMER
Calculate the RTIMER (kΩ) with Equation (2):
If WDI_OK is not received in t4+t5, the watchdog
then outputs a reset signal and enters the sync
signal monitoring state.
RTIMER kΩ = 0.063× T μs − 4.67 (2)
(
)
(
)
For example, if RTIMER = 51kꢀ, then T ≈ 0.88ms.
MODE is pulled low during the long window
mode, and the watchdog enters a short window
mode.
Monitoring the MCU Synchronization Signal
When the watchdog is in a sync signal
monitoring state, the watchdog IC receives a
WDI_OK signal from the MCU within t1. The
timer resets, and the watchdog enters normal
operation (WDI remains low for 10µs to 5ms). If
the watchdog does not receive the WDI_OK
signal from the MCU during t1, it generates a
reset signal and enters a sync signal monitor
state again.
Watchdog Disable
Pull /WD_DIS low to disable the watchdog, and
pull /WD_DIS high to enable the watchdog. It
has a weak internal pull-up, so leaving
/WD_DIS open enables the watchdog.
WDI Error
The WDI signal remaining at a low level for
longer than the max WDI_OK pulse width is
regarded as an error. When this error occurs,
WDO is pulled down until WDI rises to its high
level again.
Short Window Mode
If the MCU and watchdog are synchronized
correctly and MODE is low, the watchdog works
in a short window mode if WDI_OK is received
in a window close state (t2). The watchdog
outputs a reset signal and enters the sync
signal monitoring state.
If WDI_OK is received in a window open state
(t3), the watchdog enters a window close state.
The MCU is in normal operation in this situation.
If WDI_OK is not received in t2+t3, the watchdog
outputs a reset signal and enters the sync
signal monitoring state.
MODE is pulled to high during the short window
mode, and the watchdog then enters long
window mode.
MP2420 Rev. 1.0
9/6/2015
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14
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TIMING DIAGRAM
Power-On Reset and No Sync Signal
Synchronized by WDI and Triggered in Open Window (MODE = 0, Short Window Mode)
Synchronized by WDI and No Trigger Signal (MODE = 0, Short Window Mode)
MP2420 Rev. 1.0
9/6/2015
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MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Synchronized by WDI and Triggered in Closed Window (MODE = 0, Short Window Mode)
t6
t0
VCC
WDO
t2
t1
t1
WDI_OK
WDI_OK
1
0
WDI
0
MODE
NOTE: When the WDI_OK rising edge approaches WDO when it is low, the t6 timer is reset. In the situation above, the WDO
reset signal keeps t6+WDI_OK time.
Synchronized by WDI and Triggered in Open Window (MODE = 1, Long Window Mode)
t0
VCC
WDO
t4
t5
t1
t4
WDI_OK
WDI_OK
1
0
WDI
1
0
MODE
Synchronized by WDI and No Trigger Signal (MODE = 1, Long Window Mode)
MP2420 Rev. 1.0
9/6/2015
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16
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Synchronized by WDI and Triggered in Closed Window (MODE = 1, Long Window Mode)
NOTE: When the WDI_OK rising edge approaches WDO when it is low, the t6 timer is reset. In the situation above, the WDO
reset signal keeps t6+WDI_OK time.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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17
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
STATE DIAGRAM
NOTE: The state diagram above does not show a WDI error situation.
MP2420 Rev. 1.0
9/6/2015
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18
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
Setting the Output Voltage
APPLICATION INFORMATION
The output voltage is set using a resistive voltage
divider from the output voltage to FB. To achieve
the desired output voltage, select the resistor
divider with Equation (7):
Selecting the Inductor
Ipeak is fixed, and the inductor value can be
determined with Equation (3):
(
)
VOUT × V - VOUT
VOUT
IN
R1
(3)
L =
(7)
=
-1
V ×Ipeak ×fs
R2 VREF
Where VREF is the FB reference voltage (1V).
IN
Where fs is the switching frequency at the
maximum output current.
The current flowing into the resistor divider
increases the supply current, especially at no-
load and light-load conditions. The VIN supply
current caused by the feedback resistors can be
calculated with Equation (8):
A larger inductor value results in a lower
switching frequency and higher efficiency.
However, the larger value inductor has a larger
physical size, a higher series resistance, a lower
saturation current, and slow load transient
dynamic performance. The inductor value has a
lower limit, which is determined by the minimum
on time. To keep the inductor functioning
properly, the inductor value should be higher
than LMIN and can be derived from Equation (4):
VOUT
VOUT
1
(8)
IIN_FB
=
×
×
R1+ R2 VIN
η
Where is the efficiency of the regulator.
To reduce this current, it is recommended to use
resistors in the Mꢀ range. The recommended
values of the feedback resistors are shown in
Table 1.
V
(MAX) ×tON(MIN)
IN
(4)
LMIN
=
Ipeak
Where VIN(MAX) is the maximum value of the input
voltage, and tON(MIN) is the 115ns minimum
switch-on time.
Table 1: Resistor Selection for Common Output
Voltages
VOUT (V)
R1 (kΩ)
1200
R2 (kΩ)
523
Switching Frequency
3.3
5
1200
300
The switching frequency can be estimated with
Equation (5):
Under-Voltage Lockout (UVLO) Point Setting
(
)
2×Io× VOUT × V - VOUT
IN
(5)
fs =
The MP2420 has an internal, fixed, under-voltage
lockout (UVLO) threshold. The rising threshold is
about 4.2V while its trailing threshold is about
3.75V. External resistor dividers placed between
EN and VIN can be used to achieve a higher
equivalent UVLO threshold (see Figure 3).
Ip2eak × V ×L
IN
A larger inductor can achieve a lower fs. fs
increases as Io increases. When Io increases to
its maximum value (Ipeak/2), fs reaches its highest
value. The maximum fs value can be estimated
with Equation (6):
(
)
VOUT × V - VOUT
IN
(6)
fs(max)
=
Ipeak × V ×L
IN
Figure 3: Adjustable UVLO Using EN
MP2420 Rev. 1.0
9/6/2015
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MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
The UVLO threshold can be calculated with
Equation (9) and Equation (10):
R4
UVLOTH_Rising = (1+
3M//R5
(9)
)×ENTH_Rising
R4
UVLOTH_Falling = (1+
3M//R5
(10)
)×ENTH_Falling
Soft-Start Capacitor
The soft-start time is the duration of an internal
5µA current source charging the SS capacitor
form 0 to the FB reference voltage (1V). The SS
capacitor can be determined with Equation (11):
(11)
CSS = 5× tSS (μF)
Feed-Forward Capacitor
The HS-FET turns on when FB drops below the
reference voltage, producing ideal load transient
performance. However, this also causes the HS-
FET to be very sensitive to the FB voltage during
turn-on. The HS-FET is affected easily at turn-on,
which can trigger a Fsw jitter. Fsw jitter occurs
most often when the Vo ripple is very small. To
improve jitter performance, it is recommended to
use a small feed-forward capacitor of about 39pF
between Vo and FB.
MP2420 Rev. 1.0
9/6/2015
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20
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
TYPICAL APPLICATION CIRCUITS
Figure 4: 3.3V Output Typical Application Circuit
MP2420 Rev. 1.0
9/6/2015
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21
MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG
PACKAGE INFORMATION
TSSOP-16 EP
PIN 1 ID
TOP VIEW
RECOMMENDED LAND PATTERN
SEE DETAIL "A"
FRONT VIEW
SIDE VIEW
DETAIL "A"
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) PACKAGE LENGTH DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
3) PACKAGE WITDH DOES NOT INCLUDE INTERLEAD
FLASH OR PROTRUSION.
4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER
FORMING) SHALL BE 0.10 MILLIMETERS MAX.
5) DRAWING CONFORMS TO JEDEC MO-153,
VARIATION ABT.
BOTTOM VIEW
6) DRAWING IS NOT TO SCALE.
NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications.
Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS
products into any application. MPS will not assume any legal responsibility for any said applications.
MP2420 Rev. 1.0
9/6/2015
www.MonolithicPower.com
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© 2015 MPS. All Rights Reserved.
22
相关型号：
MP245-2
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CTS
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