MP2454 [MPS]
36V, 0.6A Step-Down Converter;
| 型号： | MP2454 |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | 36V, 0.6A Step-Down Converter |
| 文件： | 总19页 (文件大小：677K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2454
36V, 0.6A
Step-Down Converter
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP2454 is a frequency-programmable
(350kHz to 2.3MHz), step-down switching
regulator with an integrated internal high-side,
high-voltage power MOSFET. It outputs
efficiently up to 0.6A and has current-mode
control for fast loop response.
60μA Operating Quiescent Current
Wide 3.3V to 36V Operating Input Range
200mΩ Internal Power MOSFET
Up to 2.3MHz Programmable Switching
Frequency
Stable with Ceramic Output Capacitors
Internal Compensation
The wide 3.3V to 36V input range accommodates a
variety of step-down applications in automotive-
input environments. A 3.5μA shutdown mode
quiescent current allows for use in battery-
powered applications. Also, the device has a high
duty cycle and low drop-out mode for automotive
cold-crank conditions.
External Soft Start
> 90% Efficiency
Low Dropout Operation for Cold Crank
3.5μA Low Shutdown Supply Current
Synchronization to External Clock
Power Good Output
Programmable Power Good Delay Time
MSOP-10 EP and QFN-10 (3mm x 3mm)
Packages
The MP2454 achieves high-power conversion
efficiency over a wide load range by scaling
down the switching frequency at light-load
conditions to reduce both switching and gate
driving losses.
APPLICATIONS
High-Voltage Power Conversion
Automotive Systems
Industrial Power Systems
Distributed Power Systems
Battery Powered Systems
Frequency foldback prevents inductor current
runaway during start-up and short circuit.
Thermal shutdown provides reliable, fault-tolerant
operation. An open-drain power good (PG) signal
indicates when the output is within its nominal
voltage.
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
The MP2454 is available in MSOP-10 EP and
QFN-10 (3mm x 3mm) packages.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
Efficiency vs.
100
95
90
85
80
75
70
65
60
55
50
45
40
10
100
1000
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
1
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP2454GH
MSOP-10 EP
See Below
MP2454GQ
QFN-10 (3mm x 3mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP2454GH–Z)
TOP MARKING (MP2454GH)
Y: Year code
W: Week code
LLL: Lot number
M: Product code of MP2454GH
2454: Four digits of the part number
TOP MARKING (MP2454GQ)
AEF: Product code of MP2454GQ
Y: Year code
LLL: Lot number
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
2
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
PACKAGE REFERENCE
TOP VIEW
1
2
3
4
5
10
9
8
7
6
EXPOSED PAD
ON BACKSIDE
MSOP-10 EP
QFN-10 (3mm x 3mm)
Thermal Resistance (3)
MSOP-10 EP..........................55...... 12... °C/W
QFN-10 (3mm x 3mm)............50...... 12... °C/W
θJA
θJC
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN) ........................-0.3V to 40V
Switch voltage (VSW) .......–0.3V to VIN (MAX)+0.3V
BST to SW.......................................-0.3 to 6.0V
All other pins..................................-0.3V to 5.0V
EN sink current ........................................ 150µA
NOTES:
1) Absolute maximum ratings are rated under room temperature
unless otherwise noted. Exceeding these ratings may
damage the device.
(2)
Continuous power dissipation.... (TA = +25°C)
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance (θJA), and the ambient
temperature (TA). The maximum allowable continuous power
dissipation at any ambient temperature is calculated by
PD(MAX)=(TJ(MAX)-TA)/ θJA. Exceeding the maximum
allowable power dissipation will produce an excessive die
temperature, causing the regulator to go into thermal
shutdown. Internal thermal shutdown circuitry protects the
device from permanent damage.
MSOP-10 EP ........................................... 2.27W
QFN-10 (3mm x 3mm)............................. 2.50W
Junction temperature................................150°C
Lead temperature .....................................260°C
Storage temperature.................. -65°C to 150°C
Recommended Operating Conditions
Supply voltage (VIN) .........................3.3V to 36V
Operating junction temp (TJ).... -40°C to +125°C
3) Measured on JESD51-7, 4-layer PCB.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
3
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TA= +25°C, unless otherwise noted.
Parameter
Condition
Min
Typ
Max
Units
Feedback voltage
VIN = 3.3V to 36V
0.784
0.8
0.816
V
Switch on resistance
Switch leakage
VBST - VSW = 5V
200
0.1
350
1
mΩ
μA
A
VEN = 0V, VSW = 0V
Duty Cycle = 30%
Current limit
1
1.8
2.7
3.2
2.95
VIN UVLO rising threshold
VIN UVLO falling threshold
VIN UVLO hysteresis
Soft-start current
2.6
2.35
2.9
V
2.65
0.25
1.8
V
V
VSS = 1.2V
0.9
300
800
1840
350
2.7
µA
kHz
kHz
kHz
kHz
ns
RFREQ = 130kꢀ
RFREQ = 49.9kꢀ
400
1000
2300
500
Oscillator frequency
1200
2760
2300
R
FREQ = 17.4kꢀ
Sync. frequency range
Minimum switch-on time(4)
Shutdown supply current
60
VEN = 0V
3.5
10
85
1
μA
No load, VFB = 0.83V,
Quiescent supply current
60
μA
VBST - VSW = 5.5V
EN input logic-low voltage
EN input logic-high voltage
V
V
1.8
FB in respect to the nominal
value, VOUT rising
90
107
4.5
%
%
%
POK threshold
FB in respect to the nominal
value, VOUT falling
FB in respect to the nominal
value
POK hysteresis
POK output voltage low
POK delay current source
Thermal shutdown(4)
Thermal shutdown hysteresis(4)
NOTE:
ISINK = 5mA
0.4
2.7
V
0.9
1.8
170
25
µA
°C
°C
4) Derived from bench characterization. Not tested in production.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
4
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name
Description
Switch node. The output from the high-side switch. SW requires a low VF Schottky
diode to ground (close to SW) to reduce switching spikes.
1
SW
Input supply. VIN provides power to all the internal control circuitry (both the BST
regulators and the high-side switch). VIN requires a decoupling capacitor to ground
(close to VIN) to minimize the switching spikes.
2
3
VIN
Ground. Place the output capacitor as close to GND as possible to shorten the
high-current switching paths.
GND
Soft start. Place a capacitor from SS to SGND to set the soft-start period. The
MP2454 sources 1.8µA from SS to the soft-start capacitor at start-up. As the SS
voltage rises, the feedback threshold voltage increases to limit the inrush current
during start-up.
4
5
SS
FB
Feedback. Connect FB to the tap of the external resistor divider. The feedback
threshold voltage is 0.8V.
POK signal delay. Connect a capacitor from POKDL to GND to program the POK
signal delay time.
6
7
8
POKDL
POK
Open-drain power good output. POK goes high when VO is within the ±10%
window of the nominal voltage. POK is pulled down during shutdown.
Switching frequency program. Connect a resistor from FREQ to ground to set the
switching frequency.
FREQ
Enable and SYNC input. Pull EN/SYNC below the specified threshold to shut the
chip down. Pull EN/SYNC above the specified threshold to enable the chip. Floating
EN/SYNC shuts the chip down. Apply a clock signal (350kHz to 2.3MHz) to
synchronize the internal oscillator frequency to the external clock.
9
EN/SYNC
Bootstrap. The positive power supply for the internal floating high-side MOSFET
driver. Connect a bypass capacitor between BST and SW.
10
BST
Exposed Pad Connect the exposed pad to the GND plane to optimize thermal performance.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
5
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 10µH, COUT = 2 x 10μF, fS = 1MHz, TA = +25°C, unless otherwise noted.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
0.806
0.804
0.802
0.800
0.798
0.796
0.794
0.792
66
64
62
60
58
56
54
52
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
3.00
2.95
2.90
2.85
2.80
2.75
2.70
2.65
2.60
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
300
275
250
225
200
175
150
125
100
Rising
Falling
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1040
1030
1020
1010
1000
990
Rising
Falling
980
-50 -25
0
25 50 75 100 125
-50 -25
0
25 50 75 100 125
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
6
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 10µH, COUT = 2 x 10μF, fS = 1MHz, TA = +25°C, unless otherwise noted.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
7
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10µH, COUT = 2 x 10μF, fS = 1MHz, TA = +25°C, unless otherwise noted.
Steady State Steady State
I
=0.1A
OUT
I
=0.6A
OUT
V
/AC
V
/AC
OUT
OUT
V
/AC
OUT
10mV/div.
10mV/div.
50mV/div.
I
L
I
L
200mA/div.
500mA/div.
V
V
SW
SW
I
OUT
5V/div.
5V/div.
200mA/div.
Start-Up through V
Start-Up through V
Shutdown through V
IN
IN
IN
I
= 0A
I
= 0.6A
I
= 0A
OUT
OUT
OUT
V
V
IN
IN
10V/div.
10V/div.
V
IN
10V/div.
V
V
OUT
OUT
2V/div.
2V/div.
V
OUT
2V/div.
V
SW
V
V
SW
SW
10V/div.
10V/div.
10V/div.
I
L
50mA/div.
I
I
L
L
200mA/div.
500mA/div.
Shutdown through V
Start-Up through EN
Start-Up through EN
IN
I
= 0.6A
I
= 0A
I
= 0.6A
OUT
OUT
OUT
V
V
EN
EN
2V/div.
2V/div.
V
IN
V
5V/div.
OUT
V
2V/div.
OUT
V
2V/div.
OUT
2V/div.
V
V
SW
SW
V
SW
10V/div.
10V/div.
10V/div.
I
I
I
L
L
L
500mA/div.
200mA/div.
500mA/div.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
8
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10µH, COUT = 2 x 10μF, fS = 1MHz, TA = +25°C, unless otherwise noted.
V
V
V
EN
EN
OUT
2V/div.
2V/div.
2V/div.
V
OUT
V
V
SW
OUT
2V/div.
V
5V/div.
2V/div.
10V/div.
V
SW
SW
10V/div.
I
L
I
L
500mA/div.
I
L
50mA/div.
500mA/div.
V
OUT
2V/div.
V
V
OUT
OUT
2V/div.
2V/div.
V
SW
V
SW
10V/div.
V
SW
10V/div.
10V/div.
I
I
I
L
L
L
200mA/div.
500mA/div.
500mA/div.
V
OUT
2V/div.
V
V
IN
IN
5V/div.
5V/div.
V
OUT
2V/div.
V
SW
V
10V/div.
V
POKDL
2V/div.
OUT
2V/div.
I
L
200mA/div.
V
POK
V
2V/div.
I
SW
L
5V/div.
500mA/div.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
9
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
FUNCTIONAL BLOCK DIAGRAM
VIN
EN
EN/SYNC
Logic
Internal
Regulator
EN/SYNC
3.5V
5V
EXCLK
SW
Oscillator
FREQ
POK
BST
CLK
M1
Logic
Slope
ISW
Slope
Compensation
and Peak Current
SW
FB
Limit
2.5V
0.8V
M2
Soft Start
POK
Delay
BST
POKDL
SS
GND
Figure 1: MP2454 Block Diagram
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
10
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
OPERATION
internal op amp with an RC feedback network
connected between its output node (internal
COMP node) and GND. When the FB voltage
(VFB) is less than its internal reference voltage
(VREF), the op amp drives the COMP output
higher, increasing the switch peak current output
and hence increases the energy delivered to the
The MP2454 is a non-synchronous, step-down,
switching regulator with an internal high-side,
high-voltage power MOSFET. It provides an
internally compensated, highly-efficient output of
0.6A with current-mode control.
It features a wide input voltage range, a switching
frequency programmable up to 2.3MHz, an
external soft start, and a precise current limit. Its
very low operational quiescent current makes it
suitable for battery-powered applications.
output. Conversely, when VFB rises above VREF
,
the output energy drops.
When connecting to FB, connect FB to the tap of
a resistor divider between VO and GND.
PWM Control
Internal Regulator
At moderate to high output currents, the MP2454
operates in a fixed frequency, peak-current-
control mode to regulate the output voltage.
Once the internal clock initiates a PWM cycle, the
power MOSFET turns on and remains on until its
current reaches the value set by the COMP
voltage. When the power switch is off, it remains
off for at least 100ns before the next cycle starts.
If the current in the power MOSFET does not
reach the COMP set current value (within one
PWM cycle), the power MOSFET remains on,
skipping a turn-off period.
The 3.5V internal regulator powers most of the
internal circuitry. This regulator takes the VIN
input and operates in the full VIN range. When
VIN exceeds 3.5V, the output of the regulator is in
full regulation; conversely, when VIN is lower than
3.5V, the output degrades.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor powers the
floating power MOSFET driver. A dedicated
internal bootstrap regulator charges and
regulates the bootstrap capacitor to about 5V.
When the voltage between the BST and SW
nodes falls below the regulation voltage, a PMOS
pass transistor connected from VIN to BST turns
on. The charging current path is from VIN to BST
and then to SW. The external circuit must provide
enough voltage headroom to facilitate charging.
Pulse-Skipping Mode
In light-load conditions, the MP2454 enters
pulse-skipping mode to improve light-load
efficiency. Pulse skipping occurs when the
internal COMP voltage falls below the internal
sleep threshold, which generates a pause
command to block the turn-on clock pulse that
controls the power MOSFET. The power
MOSFET therefore does not turn on,
subsequently reducing gate drive and switching
losses. This pause command puts the chip
largely into sleep mode, which consumes very
low quiescent current and further improves the
light-load efficiency.
As long as VIN is sufficiently higher than SW, the
bootstrap capacitor will charge. When the power
MOSFET is on, VIN is about equal to SW and
prevents the bootstrap capacitor from charging.
When the external free-wheeling diode is on, the
difference between VIN to SW is at its largest,
making this period the best time to charge. When
there is no current in the inductor, SW equals VO,
so the difference between VIN and VO charges the
bootstrap capacitor.
When the COMP voltage exceeds the sleep
threshold, the pause signal resets, so the chip
enters normal PWM operation. Every time the
pause signal goes from low to high, a signal turns
on the power MOSFET.
At higher duty cycles, the time period available
for bootstrap charging is smaller, so the
bootstrap capacitor may not fully charge. In case
the external circuit does not have sufficient
voltage and time to charge the bootstrap
Error Amplifier (EA)
The error amplifier circuit is composed of an
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
11
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
capacitor, add external circuitry to ensure that the
bootstrap voltage is in the normal operation
region.
An external clock with a frequency range of
350kHz to 2.3MHz can be used to synchronize
the device through EN/SYNC. The internal
clock’s rising edge is synchronized to the
external clock’s rising edge.
Low Dropout Operation (LDO)
The MP2454 is designed to operate at a 100%
duty cycle as long as the voltage difference
across BST to SW is greater than 2.5V; this
improves dropout. When the voltage from BST to
SW drops below 2.5V, an under-voltage lockout
(UVLO) circuit turns off the high-side MOSFET
(HS-FET), and an internal low-current switch
pulls the SW node low to refresh the charge on
the BST capacitor. After the BST capacitor
voltage is re-charged, the HS-FET turns on again
to regulate the output. Since the supply current
sourced from the BST capacitor is low, the HS-
FET can remain on for more switching cycles
than are required to refresh the capacitor, thus
increasing the effective duty cycle of the
switching regulator. The low-dropout operation
makes the MP2454 suitable for the automotive
cold crank.
If a clock on period exceeds 4µs or an off period
exceeds 2µs, the device interprets the signal as
an enable input and disables synchronization.
Frequency Programmable
An external resistor (RFREQ) from FREQ to GND
sets the MP2454’s oscillating frequency. For
additional details on the relationship between
RFREQ and fS, refer to the “Application Information”
section.
The oscillating frequency is related to the FB
voltage. When the FB voltage decreases, the
oscillating frequency decreases accordingly and
becomes one fifth of the nominal value (when FB
is 0). This frequency foldback scheme prevents
inductor current runaway during start-up or an
output short circuit.
Under-Voltage Lockout (UVLO)
The voltage drop across the power MOSFET, the
inductor resistance, the low-side diode, and the
printed circuit board resistance influence heavily
the effective duty cycle during regulator dropout.
VIN UVLO protects the chip from operating at an
insufficient supply voltage. The UVLO rising
threshold is 2.9V while its falling threshold is
2.65V.
Enable Control and Frequency
Synchronization
Soft Start (SS)
Soft start (SS) prevents the converter output
voltage from overshooting during start-up. When
the soft-start period begins, an internal current
source charges the external soft-start capacitor.
When the SS voltage falls below the internal
reference (REF), the SS overrides REF as the
error amplifier reference. When SS exceeds REF,
REF acts as the reference.
EN/SYNC is a digital control pin that turns the
regulator on and off. When EN is pulled below 1V
for longer than 2µs, the chip enters the lowest
shutdown current mode. Forcing EN/SYNC
above 1.8V for longer than 200ns turns on the
device. Internally, a 1.2Mꢀ resistor is connected
from EN to GND. So when left floating, the
device pulls EN down to GND, and the chip is
disabled.
The SS time is calculated with Equation (1):
tSS (ms)ISS (A)
A Zener diode is connected from EN to GND
internally. The typical clamping voltage of the
Zener diode is 7.5V, so VIN can be connected to
EN through a high value resistor if the system
does not have another logic input acting as an
enable signal. The resistor needs to be designed
to limit the EN sink current to less than 150μA.
(1)
CSS (nF)
VREF (V)
Where ISS is the soft-start current, and VREF is the
0.8V reference voltage. It can be used for
tracking and sequencing.
Thermal Shutdown (TSD)
Thermal shutdown prevents the chip from
thermal runaway. When the die temperature
exceeds the upper threshold (170oC), the entire
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
12
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
chip shuts down. When the temperature falls
below the lower threshold (145oC), the chip is
enabled again.
programmed by adding a capacitor on POKDL.
To select a capacitor for POKDL, use Equation
(2):
tPOKDL (ms)IPOKDL (A)
Current Comparator and Current Limit
(2)
CDL (nF)
Vth_POKDL (V)
A current sense MOSFET senses accurately the
power MOSFET current. The sensed current
goes to the high-speed current comparator for
current-mode control. When the power MOSFET
turns on, the comparator is blanked first (until the
end of the turn-on transition) to reduce noise.
Then, the comparator compares the power-
switch current against the reference current set
by the COMP voltage. When the power-switch
current exceeds the reference current, the
comparator outputs low to turn off the power
MOSFET.
Where IPOKDL is the POKD source current, and
V
.
th_POKDL is 1.2V.
The maximum current of the internal power
MOSFET is limited internally cycle-by-cycle. The
current limit is related to the FB voltage and
deceases as Vo decreases, which prevents
inductor current runaway during start-up or an
output short circuit.
Start-Up and Shutdown
If both VIN and VEN exceed their respective
thresholds, the chip starts up. The reference
block starts first, generating a stable reference
voltage and stable currents, and then the internal
regulator is enabled. The regulator provides a
stable supply for the rest of the circuit. After this
occurs, the soft-start block starts working and
output ramps up slowly.
Three events shut down the chip: VEN low, VIN
low, and thermal shutdown. During shutdown, the
signaling path is blocked initially to avoid
triggering any faults. Then the COMP voltage
and the internal supply rail are pulled down.
Power Good Output
The MP2454 includes an open-drain power good
output that indicates whether the regulator’s
output is within ±10% of its nominal value. When
the output voltage falls outside this range, the
POK output is pulled to ground. It should be
connected to a voltage source of no more than
5V through a resistor (e.g. 100kꢀ). There is a
20µs de-glitch time when POK asserts high (if
POKDL is left floating). The de-glitch time can be
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
13
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
APPLICATION INFORMATION
Setting the Output Voltage
Output Rectifier Diode
The output voltage is set using a resistive voltage
divider from the output voltage to FB. The voltage
divider divides the output voltage down to the
feedback voltage by the ratio from Equation (3):
An inductor is required to supply constant current
to the output load while being driven by the
switched input voltage. A larger value inductor
results in less ripple current, which results in
lower output ripple voltage. However, the larger
value inductor will be larger physically, have a
higher series resistance, and/or lower saturation
current.
R2
VFB =VOUT
(3)
R1+R2
The output voltage is calculated by Equation (4):
R1+R2
A good rule for determining the inductance is to
allow the peak-to-peak ripple current in the
inductor to be approximately 30% of the
maximum switch current limit. Also, make sure
that the peak inductor current is below the
maximum switch current limit. The inductance
value can be calculated using Equation (6):
VOUT =VFB
(4)
R2
Choose R2 around 100kꢀ, then R1 can be
calculated by Equation (5):
VOUT
R1 R2(
1)
(5)
VFB
VOUT
VOUT
L1=
(1-
)
(6)
For example, for a 3.3V output voltage, choose
R2 as 95.3kꢀ, then R1 is 300kꢀ.
fs ΔIL
V
IN
Where VOUT is the output voltage, VIN is the input
voltage; fS is the switching frequency, and ∆IL is
the peak-to-peak inductor ripple current.
Setting the Switching Frequency
The switching frequency (fS) is set using a
resistor (RFREQ) between FREQ and GND. Table
1 shows the recommended RFREQ values for a
typical fS.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current is calculated using Equation (7):
Table 1: fS vs. RFREQ
VOUT
V
OUT
(7)
RFREQ (kꢀ)
fS (kHz)
ILP ILOAD
1
2 fS L1
V
IN
150
105
49.9
30
350
500
1000
1500
2000
2300
Where ILOAD is the load current.
Output Rectifier Diode
The output rectifier diode supplies the current to
the inductor when the high-side switch is off. To
reduce losses due to the diode forward voltage
and recovery times, use a Schottky diode.
21
17.4
For detailed RFREQ values for various fs values,
refer to the fS vs. RFREQ curve in the “Typical
Performance Characteristics” section.
Choose a diode with a maximum reverse voltage
rating greater than the maximum input voltage,
and a current rating that is greater than the
maximum load current.
For high fS applications (especially when VIN is
high and VOUT is low), avoid kicking the minimum
switch-on time. Once the minimum switch-on
time is kicked, pulse skipping occurs, resulting in
a large output ripple. The typical minimum
switch-on time is 60ns. For VOUT = 3.3V, the
recommended operating input is 24V (or lower)
at a 2MHz fS and 20V (or lower) at a 2.3MHz fS.
Input Capacitor
The input current to the step-down converter is
discontinuous, therefore, a capacitor is required
to supply the AC current to the step-down
converter while maintaining the DC input voltage.
Use low ESR capacitors for best performance.
Ceramic capacitors are preferred, but tantalum or
low ESR electrolytic capacitors will suffice.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
14
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
For simplification, choose an input capacitor with
a RMS current rating greater than half of the
maximum load current. The input capacitor (CIN)
can be electrolytic, tantalum, or ceramic.
External Bootstrap Diode
An external bootstrap diode is recommended to
reduce the quiescent current at no load and light
load and enhance efficiency, especially for a high
duty cycle (>65%) or high switching frequency
applications (e.g. >2MHz).
When using electrolytic or tantalum capacitors, a
small, high-quality ceramic capacitor (i.e. 0.1μF)
should be placed as close to the IC as possible.
When using ceramic capacitors, make sure they
have enough capacitance to provide sufficient
charge in order to prevent an excessive voltage
ripple at the input. The input voltage ripple
caused by capacitance can be estimated with
Equation (8):
At no load or light load, the part enters sleep
mode, and the internal BST regulator turns off to
save power. This makes the BST capacitor
voltage drop easily to its UVLO and the internal
low-side switch turn on frequently to refresh the
BST capacitor. The high frequency switching
brings in a relative high quiescent current. Adding
an external BST diode reduces greatly the BST
refresh frequency, thus producing a lower
quiescent current.
ILOAD
VOUT
VOUT
VIN
(8)
ΔVIN
1
fS CIN
V
IN
Output Capacitor
A power supply between 3V and 5V can be used
to power the external bootstrap diode. VOUT is a
good choice for this power supply (see Figure 2).
The output capacitor (COUT) is required to
maintain the DC output voltage. Ceramic,
tantalum, or low ESR electrolytic capacitors are
recommended. Low ESR capacitors are
preferred to keep the output voltage ripple low.
The output voltage ripple can be estimated with
Equation (9):
VOUT
V
VOUT
1
(9)
RESR
ΔVOUT
1
IN
fS L
8fS COUT
Where L is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
When using ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is caused
mainly by the capacitance. For simplification, the
output voltage ripple can be estimated with
Equation (10):
Figure 2: External Bootstrap Diode
The bootstrap diode can be low cost (i.e., a
IN4148 or a BAT54).
VOUT
8 fS2 LCOUT
VOUT
(10)
ΔVOUT
1
V
IN
When using tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
switching frequency. For simplification, the output
ripple can be approximated with Equation (11):
VOUT
VOUT
VIN
ΔVOUT
1
RESR
fS L
(11)
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
15
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
Minimum Input Voltage
3) Keep the connection from the power
ground→Schottky diode→SW as short and
wide as possible.
The low dropout and active BST refresh
operations allow the MP2454 to start up and
regulate the output at a very low input voltage.
Figure 3 shows the minimum input voltage
necessary to regulate the output voltage within
5% of the nominal value (at different loads). Note
that the minimum input voltage curve is the same
when VIN ramps up or down.
4) Ensure all feedback connections are short
and direct. Place the feedback resistors as
close to the chip as possible.
5) Route SW away from sensitive analog areas
such as FB.
3.50
fS=1MHz
3.45
6) Connect IN, SW, the exposed pad, and
especially GND to large copper areas to cool
the chip for improved thermal performance
and long-term reliability.
3.40
3.35
3.30
3.25
3.20
3.15
3.10
3.05
3.00
Below is the recommended PCB layout for the
MSOP10 package. The recommended layout for
the QFN10 package is similar.
0
100
200
300
400
500
600
LOAD CURRENT (mA)
(a) VOUT=3.3V
5.10
5.05
5.00
4.95
4.90
4.85
4.80
4.75
4.70
fS=1MHz
Top Layer
0
100
200
300
400
500
600
LOAD CURRENT (mA)
(b) VOUT=5V
Figure 3 : Minimum Input Voltage vs. Load Current
PCB Layout Guidelines
Efficient PCB layout is critical for stable operation.
For best results, refer to Figure 4 and follow the
guidelines below:
1) Keep the path of the switching current short
and minimize the loop area formed by the
input capacitor, high-side MOSFET, and
Schottky diode.
Bottom Layer
2) Place the input capacitor as close to VIN as
possible.
Figure 4: Recommended PCB Layout
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
16
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS
Figure 5: 3.3V Output Typical Application Circuit
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
17
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-10 (3mm x 3mm)
2.90
3.10
0.30
0.50
1.45
1.75
PIN 1 ID
SEE DETAIL A
PIN 1 ID
MARKING
0.18
0.30
10
1
5
2.25
2.55
2.90
3.10
PIN 1 ID
INDEX AREA
0.50
BSC
6
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
R0.20 TYP.
PIN 1 ID OPTION B
R0.20 TYP.
0.80
1.00
0.20 REF
0.00
0.05
SIDE VIEW
DETAIL A
NOTE:
2.90
1) ALL DIMENSIONS ARE IN MILLIMETERS.
0.70
1.70
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) DRAWING CONFORMS TO JEDEC MO-229, VARIATION VEED-5.
5) DRAWING IS NOT TO SCALE.
0.25
0.50
2.50
RECOMMENDED LAND PATTERN
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
18
MP2454―36V, 0.6A, STEP-DOWN CONVERTER
PACKAGE INFORMATION
MSOP-10 EP
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP2454 Rev. 1.01
9/18/2015
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2015 MPS. All Rights Reserved.
19
相关型号：
MP2459GJ-Z
Switching Regulator, Current-mode, 1.5A, 580kHz Switching Freq-Max, PDSO6, TSOT-23, 6 PIN
MPS
©2020 ICPDF网 联系我们和版权申明