MP2498DV-LF-Z [MPS]
Switching Regulator, Current-mode, 4.7A, 1300kHz Switching Freq-Max, 4 X 5 MM, ROHS COMPLIANT, MO-220VHGD-3, QFN-28;
| 型号： | MP2498DV-LF-Z |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | Switching Regulator, Current-mode, 4.7A, 1300kHz Switching Freq-Max, 4 X 5 MM, ROHS COMPLIANT, MO-220VHGD-3, QFN-28 开关 |
| 文件： | 总16页 (文件大小：482K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP2498
Integrated 100V Load Dump Protection,
2A Step-Down Regulator
The Future of Analog IC Technology
DESCRIPTION
FEATURES
The MP2498 is a high frequency monolithic
step-down switch mode converter with
integrated buck internal high side high voltage
power MOSFET and an integrated input
overvoltage protection. It provides 2A output
with current mode control for fast loop response
and easy compensation.
•
•
•
•
100V Switch for load dump protection
Eliminate External Transorb and Fuse
250mΩ Internal MOSFET in Buck Regulator
150kHz to 2MHz Programmable Switching
Frequency to Reduce Radio Interference
120μA Quiescent Current
Ceramic Capacitor Stable
Up to 95% Efficiency
Output Adjustable from 0.8V to 15V
Available in a 4x5mm 28-Pin QFN Package
•
•
•
•
•
The wide 6.5V to 30V input range of the buck
regulator accommodates a variety of step-down
applications, including those in automotive input
environment.
APPLICATIONS
High power conversion efficiency over a wide
load range is achieved by scaling down the
switching frequency at light load condition to
reduce the switching and gate driving losses.
•
•
•
•
Automotive Electronics
Industrial Power Systems
Distributed Power Systems
Power Supply for Linear Charger
Fault condition protection includes cycle-by-
cycle current limiting and thermal shutdown.
All MPS parts are lead-free and adhere to the RoHS directive. For MPS green
status, please visit MPS website under Quality Assurance. “MPS” and “The
Future of Analog IC Technology” are Registered Trademarks of Monolithic
Power Systems, Inc.
The MP2498 can survive high-voltage
transients such as those found in automotive
and industrial applications.
The MP2498 requires a minimum number of
readily available standard external components.
The MP2498 is available in a 28-pin QFN
package.
TYPICAL APPLICATION
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
1
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP2498DV
QFN28 (4mm x 5mm)
2498DV
* For Tape & Reel, add suffix –Z (e.g. MP2498DV–Z).
For RoHS compliant packaging, add suffix –LF (e.g. MP2498DV–LF–Z)
PACKAGE REFERENCE
TOP VIEW
FB COMP EN
N/C
N/C
N/C
28
27 26
25
24 23
AGND
SW
SW
1
2
3
4
5
6
7
8
22
21
20
19
18
17
16
15
N/C
FREQ
BST
GND
N/C
IN
N/C
N/C
N/C
VDD
VDD
N/C
N/C
9
10 11 12 13 14
N/C CTR
N/C
N/C
N/C
N/C
Recommended Operating Conditions (3)
Input Voltage .....................................6.5V - 30V
Surge Voltage VIN ...............90V/100ms duration
VDD......................................................5V - 55V
Output Voltage VOUT (VIN>16.5)........ 0.8V to 15V
Output Voltage VOUT (V <16.5V)....0.8V to (V -1.5V)
ABSOLUTE MAXIMUM RATINGS (1)
Supply Voltage (VIN)................................... 100V
IN to CTR......................................-0.3V to 100V
VDD to CTR....................................-0.3V to 45V
VDD ............................................................. 60V
VSW.............................................. -0.3V to VDD
VBST ..............................................VSW + 6.5V
All Other Pins....................................-0.3V to 5V
Continuous Power Dissipation (TA = +25°C) (2)
............................................................. 2.5W
Junction Temperature...............................150°C
Lead Temperature ....................................260°C
Storage Temperature.............. –65°C to +150°C
IN
IN
Operating Junct. Temp (TJ) .....–40°C to +125°C
Thermal Resistance (4)
θJA
θJC
QFN28 (4mm x5mm)..............50...... 11... °C/W
Notes:
1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/ θJA. Exceeding the maximum allowable power dissipation
will cause excessive die temperature, and the regulator will go
into thermal shutdown. Internal thermal shutdown circuitry
protects the device from permanent damage.
3) The device is not guaranteed to function outside of its
operating conditions.
4) Measured on JESD51-7 4-layer board.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
2
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
ELECTRICAL CHARACTERISTICS
VIN = 12V, TA= +25°C, unless otherwise noted.
Specifications over temperature are guaranteed by design and characterization.
Parameter
Symbol Condition
Min
Typ
Max Units
4.5V < VDD < 50V
0.780 0.800 0.820
Feedback Voltage
VFB
V
0.772
0.829
0.5
330
400
–40°C to +85°C
VDD=VCTR
VBST – VSW = 5V
–40°C to +85°C
VEN = 0V, VSW = 0V
Over Voltage Protector Resistance
Buck Switch On Resistance (5)
Buck Switch Leakage
0.25
250
ꢀ
mꢀ
μA
A
175
160
RDS(ON)
1
2.6
2.2
3.2
4.5
4.7
Buck Regulator Current Limit
–40°C to +85°C
COMP to Current Sense
Transconductance
GCS
5.7
A/V
Error Amp Voltage Gain
400
120
10
-10
3.0
V/V
µA/V
µA
Error Amp Transconductance
Error Amp Min Source current
Error Amp Min Sink current
ICOMP = ±3µA
VFB = 0.7V
VFB = 0.9V
µA
2.7
2.4
3.3
3.6
VIN UVLO Threshold
V
–40°C to +85°C
VIN UVLO Hysteresis
Soft-Start Time (5)
0.35
0.5
1
V
ms
0V < VFB < 0.8V
RFREQ = 95kꢀ
0.8
0.7
1.2
1.3
Oscillator Frequency
MHz
–40°C to +85°C
Minimum Switch On Time
Shutdown Supply Current
Quiescent Supply Current
Thermal Shutdown
100
12
ns
µA
µA
°C
ns
ns
VEN < 0.3V
No load, VFB = 0.9V
Hysteresis = 20°C
20
120
150
100
100
1.55
Minimum Off Time
Minimum On Time (5)
1.4
1.3
1.7
1.8
EN Up Threshold
V
–40°C to +85°C
EN Threshold Hysteresis
320
mV
Note:
5) Guaranteed by design.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
3
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
PIN FUNCTIONS
QFN
Pin #
Name
AGND
FREQ
Description
1
Analog Ground, connect to COMP, FREQ, FB, and EN circuits ground.
Switching Frequency Program Input. Connect a resistor from this pin to ground to set
the switching frequency.
3
Ground. It should be connected as close as possible to the output capacitor avoiding
the high current switch paths. Connect exposed pad to GND plane for optimal thermal
performance.
GND,
Exposed pad
4
Input Supply of Buck regulator. This supplies power to all the internal control circuitry,
both BS regulators and the high-side switch. A decoupling capacitor to ground must
be placed close to this pin to minimize switching spikes.
7, 8
VDD
Tie a Zener diode from CTR to ground. The zener voltage should equal to normal VDD
voltage.
10
18
20
CTR
IN
Connect input power supply, which may have surge voltage to IN pin. Also connect
Exposed Pad exposed pad to VIN plane for optimal thermal performance.
Bootstrap. This is the positive power supply for the internal floating high-side
MOSFET driver. Connect a bypass capacitor between this pin and SW pin.
BST
Switch Node. This is the output from the high-side switch. A low VF Schottky rectifier
21, 22
SW
to ground is required. The rectifier must be close to the SW pins to reduce switching
spikes.
Enable Input. Pulling this pin below the specified threshold shuts the chip down.
Pulling it up above the specified threshold or leaving it floating enables the chip.
26
27
EN
Compensation. This node is the output of the GM error amplifier. Control loop
frequency compensation is applied to this pin.
COMP
Feedback. This is the input to the error amplifier. An external resistive divider
connected between the output and GND is compared to the internal +0.8V reference
to set the regulation voltage.
28
FB
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
4
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT =5V, C1=4.7μF, C2= 33μF, L=10μH, TA = +25°C, unless otherwise noted.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
5
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT =3.3V, C1=4.7μF, C2= 33μF, L=10μH, TA = +25°C, unless otherwise noted.
Shut down
IOUT=0.1A
Strart up
IOUT=2A
Strart up
IOUT=0.1A
VEN
2V/div
VEN
2V/div
VEN
2V/div
VOUT
2V/div
VOUT
2V/div
VOUT
2V/div
V
sw
V
sw
V
sw
10V/div
10V/div
10V/div
I
L
I
L
1A/div
1A/div
I
L
2A/div
4ms/div
10ms/div
1ms/div
Output Voltage Ripple
IOUT=2A
Shut down
IOUT=2A
Output Voltage Ripple
IOUT=0.1A
VOUT
AC Coupled
VOUT
AC Coupled
VEN
2V/div
10mV/div
10mV/div
VOUT
2V/div
V
V
sw
sw
10V/div
10V/div
V
sw
10V/div
I
L
500mA/div
I
L
I
L
2A/div
2A/div
Short Circuit Entry
IOUT=0.1A to Short
Short Circuit Steady State
Short Circuit Recovery
IOUT=Short to 0A
VOUT
2V/div
VOUT
2V/div
VOUT
2V/div
V
V
V
sw
sw
sw
10V/div
10V/div
10V/div
I
I
I
L
L
L
1A/div
1A/div
2A/div
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
6
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
BLOCK DIAGRAM
VDD
VIN
OVP
CTR
EN
REFERENCE
UVLO
INTERNAL
REGULATORS
BST
SW
--
+
ISW
LOGIC
1.5ms SS
SS
--
+
FB
COMP
SS
0V8
OSCILLATOR
FREQ
COMP
AGND
GND
Figure 1—Functional Block Diagram
OPERATION
The MP2498 is a programmable frequency,
non-synchronous, step-down buck switching
regulator with an integrated high-side high
voltage power MOSFET. A normally on 100V/350
mꢀ over-voltage protection device is also
intergrated to protect the buck regulator input
from load dump surge (up to 100V). It provides a
single highly efficient solution with current mode
control for fast loop response and easy
compensation. It features a wide input voltage
range, internal soft-start control and precision
current limiting. Its very low operational quiescent
current makes it suitable for battery powered
applications.
until its current reaches the value set by the
COMP voltage. When the power switch is off, it
remains off for at least 100ns before the next
cycle starts. If, in one PWM period, the current in
the power MOSFET does not reach the COMP
set current value, the power MOSFET remains
on, saving a turn-off operation.
Pulse Skipping Mode
Under light load condition the switching
frequency stretches down zero to reduce the
switching loss and driving loss.
Error Amplifier
The error amplifier compares the FB pin voltage
with the internal reference (REF) and outputs a
current proportional to the difference between the
two. This output current is then used to charge
the external compensation network to form the
COMP voltage, which is used to control the
power MOSFET current.
PWM Control Mode
At moderate to high output current, the MP2498
operates in a fixed frequency, peak current
control mode to regulate the output voltage. A
PWM cycle is initiated by the internal clock. The
power MOSFET is turned on and remains on
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
7
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
During operation, the minimum COMP voltage is
Thermal Shutdown
clamped to 0.9V and its maximum is clamped to
2.0V. COMP is internally pulled down to GND in
shutdown mode. COMP should not be pulled up
beyond 2.6V.
Thermal shutdown is implemented to prevent the
chip from operating at exceedingly high
temperatures. When the silicon die temperature
is higher than its upper threshold, it shuts down
the whole chip. When the temperature is lower
than its lower threshold, the chip is enabled again.
Internal Regulator
Most of the internal circuitries are powered from
the 2.6V internal regulator. This regulator takes
the VIN input and operates in the full VIN range.
When VIN is greater than 3.0V, the output of the
regulator is in full regulation. When VIN is lower
than 3.0V, the output decreases.
Floating Driver and Bootstrap Charging
The floating power MOSFET driver is powered by
an external bootstrap capacitor. This floating
driver has its own UVLO protection. This UVLO’s
rising threshold is 2.2V with a hysteresis of
150mV. The driver’s UVLO is soft-start related. In
case the bootstrap voltage hits its UVLO, the
soft-start circuit is reset. To prevent noise, there
is 20µs delay before the reset action. When
bootstrap UVLO is gone, the reset is off and then
soft-start process resumes.
Enable Control
The MP2498 has a dedicated enable control pin
(EN). With high enough input voltage, the chip
can be enabled and disabled by EN which has
positive logic. Its falling threshold is a precision
1.2V, and its rising threshold is 1.5V (300mV
higher).
The bootstrap capacitor is charged and regulated
to about 5V by the dedicated internal bootstrap
regulator. When the voltage between the BST
and SW nodes is lower than its regulation, a
PMOS pass transistor connected from VIN to
BST is turned on. The charging current path is
from VIN, BST and then to SW. External circuit
should provide enough voltage headroom to
facilitate the charging.
When floating, EN is pulled up to about 3.0V by
an internal 1µA current source so it is enabled.
To pull it down, 1µA current capability is needed.
When EN is pulled down below 1.2V, the chip is
put into the lowest shutdown current mode.
When EN is higher than zero but lower than its
rising threshold, the chip is still in shutdown
mode but the shutdown current increases slightly.
As long as VIN is sufficiently higher than SW, the
bootstrap capacitor can be charged. When the
power MOSFET is ON, VIN is about equal to SW
so the bootstrap capacitor cannot be charged.
When the external diode is on, the difference
between VIN and SW is largest, thus making it
the best period to charge. When there is no
current in the inductor, SW equals the output
voltage VOUT so the difference between VIN and
VOUT can be used to charge the bootstrap
capacitor.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) is implemented to
protect the chip from operating at insufficient
supply voltage. The UVLO rising threshold is
about 3.0V while its falling threshold is a
consistent 2.6V.
Internal Soft-Start
The soft-start is implemented to prevent the
converter output voltage from overshooting
during startup and short circuit recovery. When
the chip starts, the internal circuitry generates a
soft-start voltage (SS) ramping up from 0V to
2.6V. When it is lower than the internal reference
(REF), SS overrides REF so the error amplifier
uses SS as the reference. When SS is higher
than REF, REF regains control.
At higher duty cycle operation condition, the time
period available to the bootstrap charging is less
so the bootstrap capacitor may not be sufficiently
charged.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
8
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
In case the internal circuit does not have
Startup and Shutdown
sufficient voltage and the bootstrap capacitor is
not charged, extra external circuitry can be used
to ensure the bootstrap voltage is in the normal
operational region. Refer to External Bootstrap
Diode in Application section.
If both VIN and EN are higher than their
appropriate thresholds, the chip starts. The
reference block starts first, generating stable
reference voltage and currents, and then the
internal regulator is enabled. The regulator
provides stable supply for the remaining
circuitries.
The DC quiescent current of the floating driver is
about 20µA. Make sure the bleeding current at
the SW node is higher than this value, such that:
While the internal supply rail is up, an internal
timer holds the power MOSFET OFF for about
50µs to blank the startup glitches. When the
internal soft-start block is enabled, it first holds its
SS output low to ensure the remaining circuitries
are ready and then slowly ramps up.
VO
IO
+
> 20μA
(R1+ R2)
Current Comparator and Current Limit
The power MOSFET current is accurately sensed
via a current sense MOSFET. It is then fed to the
high speed current comparator for the current
mode control purpose. The current comparator
takes this sensed current as one of its inputs.
When the power MOSFET is turned on, the
comparator is first blanked till the end of the turn-
on transition to avoid noise issues. The
comparator then compares the power switch
current with the COMP voltage. When the
sensed current is higher than the COMP voltage,
the comparator output is low, turning off the
power MOSFET. The cycle-by-cycle maximum
current of the internal power MOSFET is
internally limited.
Three events can shut down the chip: EN low,
VIN low and thermal shutdown. In the shutdown
procedure, power MOSFET is turned off first to
avoid any fault triggering. The COMP voltage and
the internal supply rail are then pulled down.
Programmable Oscillator
The MP2498 oscillating frequency is set by an
external resistor, RFREQ from the FREQ pin to
ground. The value of RFREQ can be calculated
from:
100000
RFREQ(kꢀ) =
-5kꢀ
fS(kHz)
To get fSW=1.2MHz, RFREQ=78.7kꢀ.
Short Circuit Protection
When the output is shorted to the ground, the
switching frequency is folded back and the
current limit is reduced to lower the short circuit
current. When the voltage of FB is at zero, the
current limit is reduced to about 50% of its full
current limit. When FB voltage is higher than
0.4V, current limit reaches 100%.
In short circuit FB voltage is low, the SS is pulled
down by FB and SS is about 100mV above FB.
In case the short circuit is removed, the output
voltage will recover at the SS pace. When FB is
high enough, the frequency and current limit
return to normal values.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
9
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
APPLICATION INFORMATION
Inductor
COMPONENT SELECTION
The inductor is required to supply constant
current to the output load while being driven by
the switched input voltage. A larger value
inductor will result in less ripple current that will
result in lower output ripple voltage. However, the
larger value inductor will have a larger physical
size, higher series resistance, and/or lower
saturation current.
Setting the Output Voltage
The output voltage is set using a resistive voltage
divider from the output voltage to FB pin. The
voltage divider divides the output voltage down to
the feedback voltage by the ratio:
R2
VFB =VOUT
×
R1+R2
A good rule for determining the inductance to use
is to allow the peak-to-peak ripple current in the
inductor to be approximately 30% of the
maximum switch current limit. Also, make sure
that the peak inductor current is below the
maximum switch current limit. The inductance
value can be calculated by:
Thus the output voltage is:
R1+R2
R2
VOUT =VFB
×
For example, the value for R2 can be 10kꢀ. With
this value, R1 can be determined by:
R1=12.5×(VOUT -0.8)(kꢀ)
VOUT
VOUT
L1=
×(1-
)
fs × ΔIL
V
IN
For example, for a 3.3V output voltage, R2 is
10kꢀ, and R1 is 31.6kꢀ.
Where VOUT is the output voltage, VIN is the input
voltage, fS is the switching frequency, and ∆IL is
the peak-to-peak inductor ripple current.
Choose an inductor that will not saturate under
the maximum inductor peak current. The peak
inductor current can be calculated by:
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
VOUT
⎜
ILP = ILOAD
+
× 1−
2 × fS × L1
V
IN
Where ILOAD is the load current.
Table 1 lists a number of suitable inductors from
various manufacturers. The choice of which style
inductor to use mainly depends on the price vs.
size requirements and any EMI requirement.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
Table 1—Inductor Selection Guide
Inductance
(µH)
Max DCR
Current Rating
(A)
Dimensions
Part Number
(Ω)
L x W x H (mm3)
Wurth Electronics
7447789004
744066100
744771115
744771122
TDK
4.7
10
15
22
0.033
0.035
0.025
0.031
2.9
3.6
7.3x7.3x3.2
10x10x3.8
12x12x6
3.75
3.37
12x12x6
RLF7030T-4R7
SLF10145T-100
SLF12565T-150M4R2
SLF12565T-220M3R5
Toko
4.7
10
15
22
0.031
0.0364
0.0237
0.0316
3.4
3
7.3x6.8x3.2
10.1x10.1x4.5
12.5x12.5x6.5
12.5x12.5x6.5
4.2
3.5
FDV0630-4R7M
919AS-100M
919AS-160M
919AS-220M
4.7
10
16
22
0.049
0.0265
0.0492
0.0776
3.3
4.3
3.3
3
7.7x7x3
10.3x10.3x4.5
10.3x10.3x4.5
10.3x10.3x4.5
Output Rectifier Diode
Choose a diode whose maximum reverse voltage
rating is greater than the maximum input voltage,
and whose current rating is greater than the
maximum load current. Table 2 lists example
Schottky diodes and manufacturers.
The output rectifier diode supplies the current to
the inductor when the high-side switch is off. To
reduce losses due to the diode forward voltage
and recovery times, use a Schottky diode.
Table 2—Diode Selection Guide
Voltage/
Current
Rating
Diodes
Manufacturer
B290-13-F
B380-13-F
90V, 2A
80V, 3A
100V, 2A
100V, 3A
Diodes Inc.
Diodes Inc.
Central Semi
Central Semi
CMSH2-100M
CMSH3-100MA
MP2498 Rev. 1.0
8/7/2012
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11
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
Input Capacitor
switching frequency. For simplification, the output
ripple can be approximated to:
The input current to the step-down converter is
discontinuous, therefore a capacitor is required to
supply the AC current to the step-down converter
while maintaining the DC input voltage. Use low
ESR capacitors for the best performance.
Ceramic capacitors are preferred, but tantalum or
low-ESR electrolytic capacitors may also suffice.
VOUT
VOUT
⎛
⎞
ΔVOUT
=
× ⎜1−
⎟ ×RESR
⎜
⎟
fS ×L
VIN
⎝
⎠
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP2498 can be optimized for a wide range of
capacitance and ESR values.
For simplification, choose the input capacitor with
RMS current rating greater than half of the
maximum load current. The input capacitor (C1)
can be electrolytic, tantalum or ceramic.
Compensation Components
MP2498 employs current mode control for easy
compensation and fast transient response. The
system stability and transient response are
controlled through the COMP pin. COMP pin is
the output of the internal error amplifier. A series
capacitor-resistor combination sets a pole-zero
combination to control the characteristics of the
control system. The DC gain of the voltage
feedback loop is given by:
When using electrolytic or tantalum capacitors, a
small, high quality ceramic capacitor, i.e. 0.1μF,
should be placed as close to the IC as possible.
When using ceramic capacitors, make sure that
they have enough capacitance to provide
sufficient charge to prevent excessive voltage
ripple at input. The input voltage ripple caused by
capacitance can be estimated by:
VFB
AVDC = RLOAD × GCS × AVEA
×
VOUT
⎛
⎜
⎝
⎞
⎟
⎟
⎠
ILOAD
VOUT
VIN
VOUT
⎜
ΔV
=
×
× 1−
IN
fS × C1
V
IN
Where AVEA is the error amplifier voltage gain,
400V/V; GCS is the current sense
transconductance, 5.6A/V; RLOAD is the load
resistor value.
Output Capacitor
The output capacitor (C2) is required to maintain
the DC output voltage. Ceramic, tantalum, or low
ESR electrolytic capacitors are recommended.
Low ESR capacitors are preferred to keep the
output voltage ripple low. The output voltage
ripple can be estimated by:
The system has two poles of importance. One is
due to the compensation capacitor (C3), the
output resistor of error amplifier. The other is due
to the output capacitor and the load resistor.
These poles are located at:
⎛
⎜
⎝
⎞
⎟
⎟
⎛
⎞
⎟
⎟
⎠
VOUT
VOUT
VIN
1
⎜
⎜
ΔVOUT
=
× 1−
× RESR
+
⎜
⎝
GEA
fS × L
8 × fS × C2
⎠
fP1
=
=
2π× C3× AVEA
Where L is the inductor value and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
1
fP2
2π× C2×RLOAD
In the case of ceramic capacitors, the impedance
at the switching frequency is dominated by the
capacitance. The output voltage ripple is mainly
caused by the capacitance. For simplification, the
output voltage ripple can be estimated by:
Where,
transconductance, 120μA/V.
GEA
is
the
error
amplifier
The system has one zero of importance, due to
the compensation capacitor (C3) and the
compensation resistor (R3). This zero is located
at:
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
8 × fS2 × L × C2
VOUT
⎜
ΔVOUT
=
× 1−
V
IN
1
fZ1
=
In the case of tantalum or electrolytic capacitors,
the ESR dominates the impedance at the
2π× C3×R3
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
12
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
The system may have another zero of
2π× C2× fC VOUT
R3 =
×
importance, if the output capacitor has a large
capacitance and/or a high ESR value. The zero,
due to the ESR and capacitance of the output
capacitor, is located at:
GEA × GCS
VFB
Where fC is the desired crossover frequency.
2. Choose the compensation capacitor (C3) to
achieve the desired phase margin. For
applications with typical inductor values, setting
the compensation zero, fZ1, below one forth of the
crossover frequency provides sufficient phase
margin. Determine the C3 value by the following
equation:
1
fESR
=
2π × C2×RESR
In this case, a third pole set by the compensation
capacitor (C5) and the compensation resistor (R3)
is used to compensate the effect of the ESR zero
on the loop gain. This pole is located at:
4
C3 >
1
2π× C2× fC
fP3
=
2π× C5×R3
3. Determine if the second compensation
capacitor (C6) is required. It is required if the
ESR zero of the output capacitor is located at
less than half of the switching frequency, or the
following relationship is valid:
The goal of compensation design is to shape the
converter transfer function to get a desired loop
gain. The system crossover frequency where the
feedback loop has the unity gain is important.
Lower crossover frequencies result in slower line
and load transient responses, while higher
crossover frequencies could cause system
unstable. A good rule of thumb is to set the
crossover frequency to approximately one-tenth
of the switching frequency.
fS
2
1
<
2π × C2×RESR
If this is the case, then add the second
compensation capacitor (C5) to set the pole fP3 at
the location of the ESR zero. Determine the C5
value by the equation:
Table 3—Compensation Values for Typical
Output Voltage/Capacitor Combinations
C2×RESR
C5 =
VOUT
(V)
C2
(µF)
R3
(kꢀ)
C3
(pF)
C6
(pF)
L (µH)
R3
High Frequency Operation
1.8
2.5
3.3
5
4.7
33
22
22
33
22
32.4
26.1
68.1
47.5
16
680
680
220
330
470
None
None
None
None
2
The switching frequency of MP2498 can be
programmed up to 1.2MHz by an external
resistor.
4.7 - 6.8
6.8 -10
15 - 22
10
The minimum on time of MP2498 is about 100ns
(typ). Pulse skipping operation can be seen more
easily at higher switching frequency due to the
minimum on time.
12
Since the internal bootstrap circuitry has higher
impedance, which may not be adequate to
charge the bootstrap capacitor during each
(1-D)×Ts charging period, an external bootstrap
charging diode is strongly recommended if the
switching frequency is about 1.2MHz (see
External Bootstrap Diode section for detailed
implementation information).
To optimize the compensation components for
conditions not listed in Table 3, the following
procedure can be used.
1. Choose the compensation resistor (R3) to set
the desired crossover frequency. Determine the
R3 value by the following equation:
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
13
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
With higher switching frequencies, the inductive
External Bootstrap Diode
reactance (XL) of capacitor comes to dominate,
so that the ESL of input/output capacitor
determines the input/output ripple voltage at
higher switching frequency. As a result of that,
high frequency ceramic capacitor is strongly
recommended as input decoupling capacitor and
output filtering capacitor for such high frequency
operation.
An external bootstrap diode may enhance the
efficiency of the regulator. In below cases, an
external BST diode is recommended from the 5V
to BST pin:
z
z
z
There is a 5V rail available in the system;
VIN is no greater than 5V;
VOUT is between 3.3V and 5V;
Layout becomes more important when the device
switches at higher frequency. It is essential to
place the input decoupling capacitor, catch diode
and the MP2498 (VIN pin, SW pin and PGND) as
close as possible, with traces that are very short
and fairly wide. This can help to greatly reduce
the voltage spike on SW node, and lower the EMI
noise level as well.
This diode is also recommended for high duty
cycle operation (when VOUT/VIN
applications.
>
65%)
The bootstrap diode can be a low cost one such
as IN4148 or BAT54.
Try to run the feedback trace as far from the
inductor and noisy power traces as possible. It is
often a good idea to run the feedback trace on
the side of the PCB opposite of the inductor with
a ground plane separating the two. The
compensation components should be placed
closed to the MP2498. Do not place the
compensation components close to or under high
dv/dt SW node, or inside the high di/dt power
loop. If you have to do so, the proper ground
plane must be in place to isolate those. Switching
loss is expected to be increased at high switching
frequency. To help to improve the thermal
conduction, a grid of thermal vias can be created
right under the exposed pad. It is recommended
that they be small (15mil barrel diameter) so that
the hole is essentially filled up during the plating
process, thus aiding conduction to the other side.
Too large a hole can cause ‘solder wicking’
problems during the reflow soldering process.
The pitch (distance between the centers) of
several such thermal vias in an area is typically
40mil.
MP2498
Figure 2—External Bootstrap Diode
At no load or light load, the converter may
operate in pulse skipping mode in order to
maintain the output voltage in regulation. Thus
there is less time to refresh the BS voltage. In
order to have enough gate voltage under such
operating conditions, the difference of (VIN –VOUT
should be greater than 3V. For example, if the
VOUT is set to 3.3V, the VIN needs to be higher
than 3.3V+3V=6.3V to maintain enough BST
voltage at no load or light load. To meet this
requirement, EN pin can be used to program the
input UVLO voltage to VOUT+3V.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
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© 2012 MPS. All Rights Reserved.
14
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
2) Bypass ceramic capacitors are suggested
PCB LAYOUT GUIDE
to be put close to the VDD Pin.
PCB layout is very important to achieve stable
operation. It is highly recommended to duplicate
EVB layout for optimum performance.
3) Ensure all feedback connections are short
and direct. Place the feedback resistors
and compensation components as close to
the chip as possible.
If change is necessary, please follow these
guidelines and take Figure 5 for reference.
4) Route SW away from sensitive analog
areas such as FB.
1) Keep the path of switching current short
and minimize the loop area formed by Input
cap, high-side MOSFET and external
switching diode.
5) Connect IN, SW, and especially GND
respectively to a large copper area to cool
the chip to improve thermal performance
and long-term reliability.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
15
MP2498 –INTEGRATED 100V LOAD DUMP PROTECTION, 2A STEP-DOWN REGULATOR
PACKAGE INFORMATION
QFN28 (4mmx5mm)
2.50
2.70
3.90
4.10
23
28
PIN 1 ID
PIN 1 ID
MARKING
SEE DETAIL A
22
1
1.50
1.70
0.50
BSC
PIN 1 ID
INDEX AREA
4.90
5.10
0.18
0.30
0.40
REF
1.50
1.70
8
15
14
9
0.35
0.45
TOP VIEW
BOTTOM VIEW
PIN 1 ID OPTION A
0.30x45º TYP.
PIN 1 ID OPTION B
R0.25 TYP.
0.80
1.00
0.20 REF
0.00
0.05
DETAIL A
SIDE VIEW
3.90
2.70
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) EXPOSED PADDLE SIZE DOES NOT INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10 MILLIMETER MAX.
4) JEDEC REFERENCE IS JEDEC MO-220, VARIATION VHGD-3.
5) DRAWING IS NOT TO SCALE.
0.70
0.25
1.60
4.90
0.50
0.40
1.60
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP2498 Rev. 1.0
8/7/2012
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2012 MPS. All Rights Reserved.
16
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