MP38900DL-LF-Z_技术文档

MP38900/MP38900-B

High Efficiency, Fast Transient, 10A, 16V

Synchronous Step-down Converter

In a Tiny QFN20 (3x4mm) Package

The Future of Analog IC Technology

DESCRIPTION

FEATURES

The MP38900/MP38900-B is a fully integrated,

high frequency synchronous rectified step-down

switch mode converter. It offers a very compact

solution to achieve 10A continuous output current

over a wide input supply range with excellent



Wide 4.5V to 16V Operating Input Range

10A Output Current

Internal 27mΩ High-Side, 10mΩ Low-Side

Power MOSFETs

Proprietary Switching Loss Reduction

Technique

1% Reference Voltage

Programmable Soft Start Time

Soft Shutdown (MP38900,)

High-Z Shutdown (MP38900-B)

Programmable Switching Frequency

SCP, OCP, OVP, UVP Protection and

Thermal Shutdown



load and line regulation. The

MP38900/

MP38900-B operates at high efficiency over a

wide output current load range.



The table below summarizes the variations

among the MP38900 and the MP38900-B.

External

V_CC

OCP

Latch Off

OCP

MP38900

Soft SHDN

Hi-Z SHDN

MP38900-B Built-in V_CC

Hiccup



Output Adjustable from 0.8V to 13V

Available in a QFN20 (3x4mm) Package

To futher optimize efficiency at light load, the V_CC

supply of MP38900 is designed to be biased

externally.

APPLICATIONS



Notebook Systems and I/O Power

Networking Systems

Optical Communication Systems

Distributed Power POL Systems

Constant-On-Time (COT) control mode provides

fast transient response and eases loop

stabilization.

Full protection features include SCP, OCP, OVP,

UVP and thermal shutdown.

All MPS parts are lead-free and adhere to the RoHS directive. For MPS green

status, please visit MPS website under Quality Assurance. “MPS” and “The

Future of Analog IC Technology” are Registered Trademarks of Monolithic

Power Systems, Inc.

The MP38900/MP38900-B requires a minimum

number of readily available standard external

components and is available in a space-saving

QFN20 (3x4mm) package.

MP38900/MP38900-B Rev. 1.1

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL APPLICATION

U1

R3

4.7

8,19

7

BST

SW

IN

VIN

R7

174k

R5

100k

9,10,17,18

MP38900

VOUT

1.05V

2

FREQ

VCC

20

R4

360k

R1

12.1k

C4

220pF

GND

6

5

PGOOD

3

FB

EN

SS

R2

43.2k

AGND PGND

11-16

4

1

C6

33nF

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

ORDERING INFORMATION

Part Number

MP38900DL*

Package

Top Marking

38900

QFN20 (3x4mm)

MP38900DL-B***

38900B

* For Tape & Reel, add suffix –Z (e.g. MP38900DL–Z)

For RoHS compliant packaging, add suffix –LF (e.g. MP38900DL–LF–Z)

***For Tape & Reel, add suffix –Z (e.g. MP38900DL-B–Z)

For RoHS compliant packaging, add suffix –LF (e.g. MP38900DL-B–LF–Z)

PACKAGE REFERENCE

TOP VIEW

VCC IN SW

SW

20

19

18

17

16

15

14

13

12

PGND

AGND

FREQ

FB

1

2

3

4

5

6

IN

SW

SS

SW

EN

IN

11 PGND

PGOOD

7

8

9

10

BST IN SW SW

EXPOSED PAD

ON BACKSIDE

Thermal Resistance ⁽⁴⁾

QFN20 (3x4mm)......................48 ...... 10...C/W

θ_JA

θ_JC

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

Supply Voltage V_IN....................................... 18V

Supply Voltage V_CC........................................ 6V

Notes:

1) Exceeding these ratings may damage the device.

2) The maximum allowable power dissipation is a function of the

maximum junction temperature T_J(MAX), the junction-to-

ambient thermal resistance θ_JA, and the ambient temperature

T_A. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by P_D(MAX)=(T_J(MAX)-

T_A)/θ_JA. Exceeding the maximum allowable power dissipation

will cause excessive die temperature, and the regulator will go

into thermal shutdown. Internal thermal shutdown circuitry

protects the device from permanent damage.

V

_SW........................................-0.3V to V_IN+ 0.3V

_BST......................................................V_SW+ 6V

I

V

_{VIN (RMS)}........................................................ 3.5A

_PGOOD...................................-0.3V to V_CC+0.6V

All Other Pins..................................-0.3V to +6V

(2)

Continuous Power Dissipation (T_A= +25°C)

………………………………………………….2.6W

Junction Temperature...............................150C

Lead Temperature ....................................260C

Storage Temperature............... -65C to +150C

3) The device is not guaranteed to function outside of its

operating conditions.

4) Measured on JESD51-7, 4-layer PCB.

Recommended Operating Conditions ⁽³⁾

Supply Voltage V_IN...........................4.5V to 16V

Supply Voltage V_CC........................................ 5V

Output Voltage V_OUT.........................0.8V to 13V

Operating Junction Temp. (T_J). -40°C to +125°C

MP38900/MP38900-B Rev. 1.1

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

ELECTRICAL CHARACTERISTICS

V_IN= 12V, V_CC=5V, T_A= +25C, unless otherwise noted.

Parameters

Symbol

Condition

Min

Typ

0

Max

1

Units

Input Supply Current

(Shutdown)

I_IN

V_EN= 0V

μA

Input Supply Current

(Quiescent)

V

_EN= 2V, V_FB= 0.95V,

I_IN

420

40

μA

MP38900-B ⁽⁶⁾

Input Supply Current

(Quiescent)

V_EN= 2V, V_FB= 0.95V

MP38900 ⁽⁶⁾

V_CCSupply Current

(Quiescent)

V_EN= 2V, V_FB= 1V

MP38900

Ivcc

350

HS Switch On Resistance ⁽⁵⁾

LS Switch On Resistance ⁽⁵⁾

HS_RDS-ON

LS_RDS-ON

27

10

mΩ

V_EN= 0V, V_SW= 0V or

12V

Switch Leakage

Current Limit

SW_LKG

I_LIMIT

0

1

μA

A

16.5

300

R7=250kΩ,

One-Shot On Time

T_ON

ns

V_OUT=1.05V

Minimum Off Time⁽⁵⁾

T_OFF

T_FB

100

7.5

50

ns

μs

Fold-back Off Time⁽⁵⁾

I_LIM=1 (HIGH)

OCP hold-off time⁽⁵⁾

T_OC

μs

Feedback Voltage

V_FB

807

815

10

823

50

mV

nA

μA

V_FB

ms

V

Feedback Current

I_FB

V_FB= 815mV

V_SS=0V

Soft Start Charging Current

Soft Stop Discharging Current

Power Good Rising Threshold

Power Good Falling Threshold

Power Good Rising Delay

EN Rising Threshold

+I_SS

8.5

0.9

0.85

1.5

1.35

420

1.5

-I_SS

V_SS=0.815V

PGOOD_Vth-_Hi

PGOOD_Vth-_Lo

T_PGOOD

EN_Vth-Hi

EN_Vth-Hys

I_EN

Tss = 2ms, MP38900

MP38900-B

1.05

3.8

1.60

4.2

EN Threshold Hysteresis

EN Input Current

mV

μA

V_EN= 2V

MP38900

V_CCUnder-Voltage Lockout

Threshold Rising

V_CCUV_Vth

V_CCUV_HYS

VINUV_Vth

4.0

880

4.0

V

mV

V

V_CCUnder-Voltage Lockout

Threshold Hysteresis

MP38900

VIN Under-Voltage Lockout

Threshold Rising

MP38900-B

3.8

4.2

5

VIN Under-Voltage Lockout

Threshold Hysteresis

VINUV_HYS

V_CC

880

5

mV

V_CCRegulator Output Voltage

V_CCRegulator Load Regulation

MP38900-B

V

MP38900-B, I_CC=5mA

%

V_OUTOver-Voltage Protection

Threshold

V_OVP

1.25

V_FB

MP38900/MP38900-B Rev. 1.1

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

ELECTRICAL CHARACTERISTICS (continued)

V_IN= 12V, V_CC=5V, T_A= +25C, unless otherwise noted.

Parameters

Symbol

Condition

Min

Typ

0.7

Max

Units

V_FB

V_OUTUnder-Voltage Detection

Threshold

V_UVP

Thermal Shutdown

T_SD

150

25

°C

Thermal Shutdown Hysteresis

T_SD-HYS

Notes:

5) Guaranteed by design.

6) If the test condition is marked with MP38900 or MP38900-B, the characteristic applies to MP38900 or MP38900-B respectively.

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

PIN FUNCTIONS

Pin #

Name

Description

1

AGND

Analog Ground.

Frequency Set during CCM operation. The ON period is determined by the input

voltage and the frequency-set resistor connected to FREQ pin. Connect a resistor

to IN for line feed-forward. Decouple with a 1nF capacitor.

2

3

FREQ

FB

Feedback. An external resistor divider from the output to GND, tapped to the FB

pin, sets the output voltage.

Soft Start. Connect an external SS capacitor to program the soft start time for the

switch mode regulator. When the EN pin becomes high, an internal current source

(8.5μA) charges up the SS capacitor and the SS voltage slowly ramps up from 0 to

4

SS

V_FBsmoothly. For MP38900, when the EN pin becomes low, an internal current

source (8.5μA) discharges the SS capacitor and the SS voltage slowly ramps

down. For MP38900-B, SS will pull low as soon as EN goes low.

EN=1 to enable the MP38900/MP38900-B. For automatic start-up, connect EN pin

to IN with a 100kΩ resistor. It includes an internal 1MΩ pull-down resistor.

5

6

EN

Power Good Output. The output of this pin is an open drain and is high if the

output voltage is higher than 90% of the nominal voltage. There is delay from FB ≥

90% to PGOOD high, which is 50% of SS time plus 0.5ms. For MP38900-B, the

delay is fixed as 1.5ms.

PGOOD

Bootstrap. A capacitor connected between SW and BS pins is required to form a

floating supply across the high-side switch driver.

7

BST

IN

Supply Voltage. The MP38900/MP38900-B operates from a +4.5V to +16V input

rail. C1 is needed to decouple the input rail. Use wide PCB traces and multiple vias

to make the connection.

8, 19

9, 10, 17, 18

11-16

SW

Switch Output. Use wide PCB traces and multiple vias to make the connection.

System Ground. This pin is the reference ground of the regulated output voltage.

For this reason care must be taken in PCB layout.

PGND

MP38900: External 5V Supply. This 5V supply has to be applied in order to bias

the device. Decouple with a 1µF capacitor as close to this pin as possible.

MP38900-B: Internal 5V supply. Decouple with a 1μF capacitor as close to this pin

as possible.

20

VCC

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS

V_IN=12V, V_OUT=1.2V, L=1.0µH, T_A=+25°C, unless otherwise noted.

100

90

100

90

V

=5V

IN

F

=300kHz

F

SW

90

80

V

=12V

80

=600kHz

SW

IN

70

60

70

60

70

60

50

0.01

50

0.1

1

10

0.01

0.1

I_OUT(A)

1

10

0.01

0.1

I_OUT(A)

1

10

I_OUT(A)

Line Regulation

Load Regulation

Case Temperature Rise vs.

Output Current

50

45

40

35

30

25

20

0.6

0.4

0.2

0.3

0.2

0.1

0

I

=10A

OUT

V

=5V

IN

I

=0A

OUT

0

-0.1

-0.2

-0.3

-0.4

V

=12V

IN

I

=5A

OUT

-0.2

-0.4

-0.6

5

7

9

11

0

2

4

6

8

10

0

2

4

6

8

10

V

_IN(V)

I

_OUT(A)

I_OUT(A)

Frequency vs. Temperature

Frequency vs. V

Frequency vs. Load Current

IN

I

= 10A

I

= 10A

OUT

1000

100

730

710

690

670

650

800

700

600

10

1

500

-50 -25

0

25 50 75 100 125

4

6

8

10

12

0.01

0.1

I_OUT(A)

1

10

V_IN(V)

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_IN=12V, V_OUT=1.2V, L=1.0µH, T_A=+25°C, unless otherwise noted.

Input & Output Voltage Ripple Input & Output Voltage Ripple Input & Output Voltage Ripple

I

= 0A

I

= 0.5A

I

= 10A

OUT

V

OUT

V

50mV/div.

OUT

50mV/div.

V

IN

50mV/div.

200mV/div.

50mV/div.

I

L

5A/div.

V

SW

5V/div.

10V/div.

I

L

V

L

SW

5A/div.

10V/div.

Power Good Through

Vin Start-up

Power Good Through

Vin Shut-down

Start-up Through Vin

I

= 0A

OUT

I

= 10A

I

= 10A

OUT

V

OUT

1V/div.

V

IN

5V/div.

V

5V/div.

PG

SW

PG

5V/div.

I

L

I

L

5A/div.

Start-up Through Vin

Shut-down Through Vin

I

= 10A

I

= 0A

I

= 10A

OUT

V

OUT

1V/div.

V

IN

5V/div.

V

SW

5V/div.

V

SW

5V/div.

I

L

5A/div.

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_IN=12V, V_OUT=1.2V, L=1.0µH, T_A=+25°C, unless otherwise noted.

MP38900/MP38900-B Rev. 1.1

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL PERFORMANCE CHARACTERISTICS (continued)

V_IN=12V, V_OUT=1.2V, L=1.0µH, T_A=+25°C, unless otherwise noted.

MP38900/MP38900-B Rev. 1.1

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

BLOCK DIAGRAM

IN

Current Sense

Amplifer

FREQ

VCC

+

-

RSEN

OC

Over-Current

Timer

D2

Refresh

Timer

BST

I

LIM

+

OFF

Timer

REFERENCE

EN

-

HS-FET

HS Ilimit

HS

Comparator

Driver

PWM

xS

xR

Q

0.4V

1.0V

0.8V

1MEG

LOGIC

SW

SOFT

START/STOP

SS

VCC

ON

Timer

START

Loop

+

-

LS-FET

FB

LS

Driver

Comparator

Current

Modulator

PGOOD

+

-

UV

+

-

PGND

AGND

PGOOD

Comparator

UV Detect

Comparator

OV

+

-

OV Detect

Comparator

Figure 2: Functional Block Diagram

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

OPERATION

PWM Operation

As Figure 3 shows, when the output current is

high, the HS-FET and LS-FET repeat on/off as

The MP38900/MP38900-B is a fully integrated

synchronous rectified step-down switch mode

converter. Constant-on-time (COT) control is

employed to provide fast transient response and

easy loop stabilization. At the beginning of each

cycle, the high-side MOSFET (HS-FET) is turned

on when the feedback voltage (V_FB) is below the

described above. In this operation, the inductor

current will never go to zero. It’s called

continuous-conduction-mode (CCM) operation. In

CCM operation, the switching frequency (f_SW) is

fairly constant.

Light-Load Operation

reference voltage (V_REF

)

which indicates

When the load current decreases, The

MP38900/MP38900-B reduces the switching

frequency automatically to maintain high

efficiency. The light load operation is shown in

Figure 4. The V_FBdoes not reach V_REFwhen the

inductor current is approaching zero. As the

output current reduces from heavy-load condition,

the inductor current also decreases, and

eventually comes close to zero. The LS-FET

driver turns into tri-state (high Z) whenever the

inductor current reaches zero level. A current

modulator takes over the control of LS-FET and

limits the inductor current to less than 600μA.

Hence, the output capacitors discharge slowly to

GND through LS-FET as well as R1 and R2. As a

result, the efficiency at light load condition is

greatly improved. At light load condition, the HS-

FET is not turned ON as frequently as at heavy

load condition. This is called skip mode.

insufficient output voltage. The ON period is

determined by the input voltage and the

frequency-set resistor as follows:

12R7



k



(1)

t_on(ns) 

 t_DELAY1(ns)

V (V)0.45

IN

Where R7 is the resistor to set switching

frequency, t_DELAY1is the 20ns delay of a

comparator in the t_ONmodule.

After the ON period elapses, the HS-FET is

turned off, or becomes OFF state. It is turned ON

again when V_FBdrops below V_REF. By repeating

operation this way, the converter regulates the

output voltage. The integrated low-side MOSFET

(LS-FET) is turned on when the HS-FET is in its

OFF state to minimize the conduction loss. There

will be a dead short between input and GND if

both HS-FET and LS-FET are turned on at the

same time. It’s called shoot-through. In order to

avoid shoot-through,

a

dead-time (DT) is

internally generated between HS-FET off and LS-

FET on, or LS-FET off and HS-FET on.

Heavy-Load Operation

Figure 4: Light Load Operation

As the output current increases from the light

load condition, the time period within which the

current modulator regulates becomes shorter.

The HS-FET is turned on more frequently. Hence,

the switching frequency increases correspondingly.

The output current reaches the critical level when

the current modulator time is zero. The critical

level of the output current is determined as

follows:

Figure 3: Heavy Load Operation

MP38900/MP38900-B Rev. 1.1

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

the V_FBripple dominates in noise immunity. The

magnitude of the V_FBripple doesn’t affect the

noise immunity directly.

(VIN  VOUT) VOUT

2LF^SW V^IN

I_OUT



(2)

It turns into PWM mode once the output current

exceeds the critical level. After that, the switching

frequency stays fairly constant over the output

current range.

V_{S L OPE1}

V_NOISE

V_{F B}

V_{R E F}

Switching Frequency

HS Driver

Constant-on-time (COT) control is used in the

MP38900/MP38900-B and there is no dedicated

oscillator in the IC. The input voltage is feed-

forwarded to the on-time one-shot timer through

the resistor R7. The duty ratio is kept as V_OUT/V_IN.

Hence, the switching frequency is fairly constant

over the input voltage range. The switching

frequency can be set as follows:

J itter

Figure 5: Jitter in PWM Mode

V_{S L OP E 2}

V_NOISE

V_FB

V_REF

10⁶

V (V)

(3)

f_SW(kHz) 

12R7(k)

IN



 t_DELAY2(ns)

HS Driver

V (V)0.45 V_OUT(V)

IN

Jitter

Where t_DELAY2is the comparator delay. It’s about

40ns.

Figure 6: Jitter in Skip Mode

Ramp with Large ESR Cap

In the case of POSCAP or other types of

capacitor with larger ESR is applied as output

capacitor. The ESR ripple dominates the output

ripple, and the slope on the FB is quite ESR

related. Figure 7 shows an equivalent circuit in

PWM mode with the HS-FET off and without an

external ramp circuit. Turn to application

information section for design steps with large

ESR caps.

MP38900/MP38900-B is optimized to operate at

high switching frequency with high efficiency.

High switching frequency makes it possible to

utilize small sized LC filter components to save

system PCB space.

Jitter and FB Ramp Slope

Figure 7: Simplified Circuit in PWM Mode

without External Ramp Compensation

Figure 5 and Figure 6 show jitter occurring in

both PWM mode and skip mode. When there is

noise in the V_FBdownward slope, the ON time of

the HS-FET driver deviates from its intended

location and produces jitter. It is necessary to

understand that there is a relationship between a

system’s stability and the steepness of the V_FB

ripple’s downward slope. The slope steepness of

To realize the stability when no external ramp is

used, usually the ESR value should be chosen

as follow:

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

As can be seen from equation 8, if there is

instability in PWM mode, we can reduce either

R4 or C4. If C4 can not be reduced further due to

limitation from equation 5, then we can only

reduce R4. For a stable PWM operation, the

t_SW

t_ON

2



0.7 

(4)

R_ESR



C_OUT

t

_SWis the switching period.

V

_slope1should be design follow equation 9.

When using a large-ESR capacitor on the output,

add a ceramic capacitor with a value of 10uF or

less to in parallel to minimize the effect of ESL.

t_SW

t

+

^ON-R_ESRC_OUT

2

Io10^-3

t_SW-t_on

0.7π

(9)

-V_slope1



V_OUT+

Ramp with Small ESR Cap

2LC_OUT

When the output capacitors are ceramic ones,

the ESR ripple is not high enough to stabilize the

system, and external ramp compensation is

needed. Skip to application information section

for design steps with small ESR caps.

Where Io is the load current.

In skip mode, the downward slope of the V_FB

ripple is the same whether the external ramp is

used or not. Figure 9 shows the simplified circuit

of the skip mode when both the HS-FET and LS-

FET are off.

L

Vout

SW

C4

R4

R1

R2

I_R4

I_C4

R9

I_FB

Ceramic

FB

.

Figure 9: Simplified Circuit in skip Mode

Figure 8: Simplified Circuit in PWM Mode with

External Ramp Compensation

The downward slope of the V_FBripple in skip

mode can be determined as follow:

Figure 8 shows a simplified external ramp

compensation (R4 and C4) for PWM mode, with

HS-FET off. Chose R1, R2, R9 and C4 of the

external ramp to meet the following condition:

V_REF

( R R //Ro)C

₂

(10)

V_SLOPE2





1

OUT

Where Ro is the equivalent load resistor.









₉



R₁R₂

R₁ R₂

1

5

As described in Figure 6, V_SLOPE2in the skip

mode is lower than that is in the PWM mode, so

it is reasonable that the jitter in the skip mode is

larger. If one wants a system with less jitter

during ultra light load condition, the values of the





 R

(5)

2F_SW C₄

Where:

I_R4 I_C4I_FB I_C4

(6)

V

_FBresistors should not be too big, however, that

will decrease the light load efficiency.

And the Vramp on the V_FBcan then be estimated

as:

V  V_OUT

R₄C₄

R₁//R₂

IN

(7)

V_RAMP



 t_ON

R₁//R₂R₉

The downward slope of the V_FBripple then

follows

V_RAMP

t_off

V_OUT

R₄C₄

(8)

V_SLOPE1



MP38900/MP38900-B Rev. 1.1

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14

MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

The PGOOD delay time is determined as follows:

Bootstrap Charging

The floating power MOSFET driver is powered by

an external V_CCthrough D2 as shown in Figure 2.

This floating driver has its own UVLO protection.

This UVLO’s rising threshold is 2.2V with a

hysteresis of 150mV. The recommended BST

cap C4 is 1μF.

MP38900:

t_PGOOD(ms)  0.5 t_SS(ms)  0.5

MP38900-B:

(12)

t_PGOOD(ms)  1.5ms

When the FB voltage drops to 85% of the REF

voltage, the PGOOD pin will be pulled low.

Soft Start/Stop

The MP38900 employ soft start/stop (SS)

mechanism to ensure smooth output during

power-up and power shutdown. When the EN pin

becomes high, an internal current source (8.5μA)

charges up the SS CAP. The SS CAP voltage

takes over the V_REFvoltage to the PWM

comparator. The output voltage smoothly ramps

up with the SS voltage. Once the SS voltage

reaches the same level as the REF voltage, it

keeps ramping up while REF takes over the

PWM comparator. At this point, the soft start

finishes and it enters into steady state operation.

Over-Current Protection (OCP) and Short-

Circuit Protection (SCP)

The MP38900/MP38900-B has cycle-by-cycle

over-current limit control. The inductor current is

monitored during the ON state. Once it detects

that the inductor current is higher than the current

limit, the HS-FET is turned off. At the same time,

the OCP timer is started. The OCP timer is set as

40μs. If in the following 40μs, the current limit is

hit for every cycle, then it’ll trigger OCP.

When the current limit is hit and the FB voltage is

lower than 50% of the REF voltage, the device

considers this as a dead short on the output and

triggers OCP immediately. This is short circuit

protection (SCP).

When the EN pin becomes low, the SS CAP

voltage is discharged through an 8.5μA internal

current source. Once the SS voltage reaches

REF voltage, it takes over the PWM comparator.

The output voltage will decrease smoothly with

SS voltage until zero level. The SS CAP value

can be determined as follows:

Under OCP/SCP condition, MP38900 will latch

off. The converter needs power cycle to restart.

MP38900-B will enter hiccup mode, and restart

by itself once the OCP/SCP condition is removed.

t_SS(ms)I_SS(A)

C_SS(nF) 

(11)

V_REF(V)

Over/Under-voltage Protection (OVP/UVP)

The MP38900/MP38900-B monitors the output

voltage through a resistor divider feedback (FB)

voltage to detect overvoltage and undervoltage

on the output. When the FB voltage is higher

than 125% of the REF voltage, it’ll trigger OVP.

Once it triggers OVP, the LS-FET is always on

while the HS-FET is always off. It needs power

cycle to power up again. When the FB voltage is

below 70% of the REF voltage (0.815V), UVP will

be triggered. Usually, UVP accompanies a hit in

current limit and this results in SCP.

If the output capacitors have large capacitance

value, it’s not recommended to set the SS time

too small. A minimal value of 4.7nF should be

used if the output capacitance value is larger

than 330μF.

MP38900-B has the same soft start mechanism,

however, the soft shut-down feature is disabled

to support output prebias applications.

Power Good (PGOOD)

The

MP38900/MP38900-B has power-good

(PGOOD) output. The PGOOD pin is the open

drain of a MOSFET. It should be connected to

V_CCor other voltage source through a resistor

(e.g. 100k). After the input voltage is applied, the

MOSFET is turned on, so that the PGOOD pin is

pulled to GND before SS ready. After FB voltage

reaches 90% of REF voltage, the PGOOD pin is

pulled high after a delay.

UVLO protection

The MP38900/MP38900-B has under-voltage

lock-out protection (UVLO). When V_CCis higher

than the UVLO rising threshold voltage, the

MP38900/MP38900-B will be powered up. It

shuts off when V_CCis lower than the UVLO falling

threshold voltage. This is non-latch protection.

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

Thermal Shutdown

Thermal shutdown is employed in the MP38900/

MP38900-B. The junction temperature of the IC

is internally monitored. If the junction temperature

exceeds the threshold value (typically 150ºC), the

converter shuts off. This is non-latch protection.

There is about 25ºC hysteresis. Once the

junction temperature drops to around 125ºC, it

initiates a soft start.

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16

MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

C4.The output voltage is influenced by ramp

APPLICATION INFORMATION

voltage V_RAMPbesides R divider as shown in

Figure 11. The V_RAMPcan be calculated as shown

in equation 7. R2 should be chosen reasonably,

a small R2 will lead to considerable quiescent

current loss while too large R2 makes the FB

noise sensitive. It is recommended to choose a

Setting the Output Voltage-Large ESR Caps

For applications that electrolytic capacitor or POS

capacitor with a controlled output of ESR is set

as output capacitors. The output voltage is set by

feedback resistors R1 and R2. As Figure 10

shows.

value within 5kꢀ-50kꢀ for R2, using

a

comparatively larger R2 when Vo is low,

etc.,1.05V, and a smaller R2 when Vo is high.

And the value of R1 then is determined as follow:

R₂

(14)

R₁=

V

R₂

FB(AVG)

-

(V_OUT-V_FB(AVG)) R₄+R₉

The V_FB(AVG)is the average value on the FB,

V_FB(AVG)varies with the Vin, Vo, and load

condition, etc., its value on the skip mode would

be lower than that of the PWM mode, which

means the load regulation is strictly related to the

Figure10: Simplified Circuit of POS Capacitor

First, choose a value for R2. R2 should be

chosen reasonably, a small R2 will lead to

considerable quiescent current loss while too

large R2 makes the FB noise sensitive. It is

recommended to choose a value within 5kꢀ-

50kꢀ for R2, using a comparatively larger R2

when Vout is low, etc.,1.05V, and a smaller R2

when Vout is high. Then R1 is determined as

follow with the output ripple considered:

V

_FB(AVG). Also the line regulation is related to the

_FB(AVG). If one wants to gets a better load or line

regulation, a lower Vramp is suggested, as long

as the criterion shown in equation 8 can be met.

For PWM operation, V_FB(AVG)value can be

deduced from the equation below.

R₁//R₂

1

V

 V_REF V_RAMP



(15)

FB(AVG)

2

R₁//R₂R₉

1

Usually, R9 is set to 0ꢀ, and it can also be set

following equation 16 for a better noise immunity.

It should also set to be 5 timers smaller than

R1//R2 to minimize its influence on Vramp.

V_OUT



V_OUT V_REF

2

(13)

R₁

R₂

V_REF

V_OUTis the output ripple determined by equation

1

21.

R₉

(16)

2C₄2F

Setting the Output Voltage-Small ESR Caps

SW

Using equation 14 to calculate the R1 can be

complicated. To simplify the calculation, a DC-

blocking capacitor Cdc can be added to filter the

DC influence from R4 and R9. Figure 12 shows

a

simplified circuit with external ramp

compensation and a DC-blocking capacitor. With

this capacitor, R1 can easily be obtained by

using the simplified equation for PWM mode

operation:

1

(V_OUT V_REF V_RAMP

)

2

Figure11: Simplified Circuit of Ceramic

Capacitor

R₁

R₂

(17)

1

V_REF V_RAMP

2

When low ESR ceramic capacitor is used in the

output, an external voltage ramp should be

added to FB through resistor R4 and capacitor

Cdc is suggested to be at least 10 times larger

than C4 for better DC blocking performance, and

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17

MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

should also not larger than 0.47uF considering

The input capacitance value determines the input

voltage ripple of the converter. If there is input

voltage ripple requirement in the system design,

choose the input capacitor that meets the

specification.

start up performance. In case one wants to use

larger Cdc for a better FB noise immunity,

combined with reduced R1 and R2 to limit the

Cdc in a reasonable value without affecting the

system start up. Be noted that even when the

Cdc is applied, the load and line regulation are

still Vramp related.

The input voltage ripple can be estimated as

follows:

I_OUT

V_OUT

V 



(1

)

(20)

IN

F_SW C_IN

V

IN

The worst-case condition occurs at V_IN= 2V_OUT

,

where:

I_OUT

4 F  C_IN

1

V 



(21)

IN

SW

Output Capacitor

The output capacitor is required to maintain the

DC output voltage. Ceramic or POSCAP

capacitors are recommended. The output voltage

ripple can be estimated as:

Figure12: Simplified Circuit of Ceramic

Capacitor with DC blocking capacitor

V_OUT

V

1

Input Capacitor

V_OUT



(1 ^OUT)(R_ESR



(22)

)

F

L

V

8F  C_OUT

SW

The input current to the step-down converter is

discontinuous. Therefore, a capacitor is required

to supply the AC current to the step-down

converter while maintaining the DC input voltage.

Ceramic capacitors are recommended for best

performance. In the layout, it’s recommended to

put the input capacitors as close to the IN pin as

possible.

SW

IN

Where R_ESRis the equivalent series resistance

(ESR) of the output capacitor.

In the case of ceramic capacitors, the impedance

at the switching frequency is dominated by the

capacitance. The output voltage ripple is mainly

caused by the capacitance. For simplification, the

output voltage ripple can be estimated as:

The capacitance varies significantly over

temperature. Capacitors with X5R and X7R

ceramic dielectrics are recommended because

they are fairly stable over temperature.

V_OUT

V_OUT



(1

)

(23)

8F ²LC_OUT

V

SW

IN

The output voltage ripple caused by ESR is very

small. Therefore, an external ramp is needed to

stabilize the system. The external ramp can be

generated through resistor R4 and capacitor C4

using the following equation 5, 8 and 9.

The capacitors must also have a ripple current

rating greater than the maximum input ripple

current of the converter. The input ripple current

can be estimated as follows:

In the case of POSCAP capacitors, the ESR

dominates the impedance at the switching

frequency. The ramp voltage generated from the

ESR is high enough to stabilize the system.

Therefore, an external ramp is not needed. A

minimum ESR value of 12mꢀ is required to

ensure stable operation of the converter. For

simplification, the output ripple can be

approximated as:

V_OUT

I_CIN I_OUT



(1

)

(18)

V

IN

The worst-case condition occurs at:

I_OUT

I_CIN



(19)

2

For simplification, choose the input capacitor

whose RMS current rating is greater than half of

the maximum load current.

V_OUT

V

V_OUT



(1 ^OUT)R_ESR

(24)

F

L

V

SW

IN

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18

MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

Inductor

V_OUT

 I_L

V_OUT

L 

(1

)

(25)

The inductor is required to supply constant

current to the output load while being driven by

the switching input voltage. A larger value

inductor will result in less ripple current that will

result in lower output ripple voltage. However, a

larger value inductor will have a larger physical

size, higher series resistance, and/or lower

saturation current. A good rule for determining

the inductor value is to allow the peak-to-peak

ripple current in the inductor to be approximately

30~40% of the maximum switch current limit.

Also, make sure that the peak inductor current is

below the maximum switch current limit. The

inductance value can be calculated as:

F

V

SW

IN

Where ΔI_Lis the peak-to-peak inductor ripple

current.

Choose an inductor that will not saturate under

the maximum inductor peak current. The peak

inductor current can be calculated as:

V_OUT

I_LP I_OUT



(1

)

(26)

2F L

V

SW

IN

The inductors listed in Table 1 are highly

recommended for the high efficiency they can

provide.

Table 1: Inductor Selection Guide

Switching

Frequency

(kHz)

Inductance DCR

Current

Dimensions

Part Number

Manufacturer

(µH)

(mΩ) Rating (A) L x W x H (mm³)

PCMC-135T-R68MF

Cyntec

0.68

1.7

34

13.5 x 12.6 x 4.8

600

FDA1254-1R0M

FDA1254-1R2M

TOKO

1

2

25.2

20.2

13.5 x 12.6 x 5.4

300~600

1.2

2.05

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

Typical Design Parameter Tables

Table 3: 600kHz, 12V_IN, w/o External Ramp,

C_OUT=220μF, 15mꢀ

The following tables include recommended

component values for typical output voltages

(1.05V, 1.2V, 1.8V, 2.5V, 3.3V) and switching

frequencies (300kHz, and 600kHz). Refer to

Tables 2-3 for design cases without external

ramp compensation and Tables 4-5 for design

cases with external ramp compensation.

External ramp is not needed when high-ESR

capacitors, such as electrolytic or POSCAPs are

used. External ramp is needed when low-ESR

capacitors, such as ceramic capacitors are used.

For cases not listed in this datasheet, a calculator

in excel spreadsheet can also be requested

through a local sales representative to assist with

the calculation.

V_OUT

(V)

L

(μH)

R1

(kꢀ)

R2

(kꢀ)

R7

(kꢀ)

1.05

1.2

1.8

2.5

3.3

0.68

1.2

5.6

9.1

20

10

147

165

240

330

442

12.1

21

1.2

30.9

Table 4: 300kHz, 12V_IN, with External Ramp

V_OUT

(V)

L

R1

(kꢀ)

R2

(kꢀ)

R4

C4

R7

(μH)

(kꢀ) (pF)

(kꢀ)

1.05

1.2

1.8

2.5

3.3

1

5.11

8.87

12

20

10

300

590

220

324

357

475

680

866

1

Table 2: 300kHz, 12V_IN, w/o External Ramp,

2.0

C_OUT=220μF, 15mꢀ

20.5

30.9

590 220

V_OUT

(V)

L

(μH)

R1

(kꢀ)

R2

(kꢀ)

R7

(kꢀ)

Table 5: 600kHz, 12V_IN, with External Ramp

1.05

1.2

1.8

2.5

3.3

1

5.49

9.1

20

10

324

357

475

680

866

V_OUT

(V)

L

R1

(kꢀ)

R2

(kꢀ)

R4

C4

R7

1

(μH)

(kꢀ) (pF)

(kꢀ)

2.0

12

1.05 0.68

5.6

9.1

20

10

205

300

180

154

169

240

330

453

20.5

30.1

1.2

1.8

2.5

3.3

0.68

1.2

12.1

21.5

33

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

TYPICAL APPLICATION

U1

R3

4.7

8,19

7

BST

SW

IN

VIN

R_FREQ

169k

GND

MP38900

C7

1nF

R5

100k

9,10,17,18

VOUT

1.2V

2

FREQ

VCC

C4

R4

20

GND

VCC

205k

180pF

R6

100k

R1

9.1k

R9

1k

6

5

PGOOD

EN

PGOOD

EN

3

FB

R2

20k

SS AGND PGND

4

11-16

1

C6

33nF

Figure 13 : Typical Application Circuit with Low ESR Ceramic Capacitor

U1

R3

4.7

8,19

7

BST

IN

VIN

R_FREQ

357k

GND

MP38900

C7

R5

9,10,17,18

1nF

100k

SW

VOUT

1.2V

2

FREQ

VCC

20

VCC

R6

100k

R1

9.1k

GND

6

5

PGOOD

EN

PGOOD

EN

3

FB

R2

20k

SS AGND PGND

4

11-16

1

C6

33nF

Figure 14 : Typical Application Circuit with No External Ramp

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21

MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

LAYOUT RECOMMENDATION

1. The high current paths (GND, IN, and SW)

should be placed very close to the device

with short, direct and wide traces.

2. Put the input capacitors as close to the IN

and GND pins as possible.(<2mm)

3. Put the decoupling capacitor as close to the

V_CCand GND pins as possible.

4. Keep the switching node SW short and away

from the feedback network.

5. The external feedback resistors should be

placed next to the FB pin. Make sure that

there is no via on the FB trace.

Inner1 Layer

6. Keep the BST voltage path (BST, C_BST,and

SW) as short as possible.

7. Keep the bottom IN and SW pads connected

with large copper to achieve better thermal

performance.

8. Four-layer layout is strongly recommended to

achieve better thermal performance.

Inner2 Layer

Top Layer

Bottom Layer

Figure 15: PCB Layout

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MP38900/MP38900-B – HIGH EFFICIENCY, FAST TRANSIENT SYNCHRONOUS STEP-DOWN CONVERTER

PACKAGE INFORMATION

QFN20(3x4mm)

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third

party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not

assume any legal responsibility for any said applications.

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23


型号：	MP38900DL-LF-Z
厂家：	MONOLITHIC POWER SYSTEMS
描述：	Switching Regulator, 3 X 4 MM, ROHS COMPLIANT, MO-220, QFN-20 开关
文件：	总23页 (文件大小：858K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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