MP4430GL [MPS]
36V, 3.5A, Low Quiescent Current, Synchronous, Step-Down Converter;
| 型号： | MP4430GL |
| 厂家： | 
MONOLITHIC POWER SYSTEMS |
| 描述： | 36V, 3.5A, Low Quiescent Current, Synchronous, Step-Down Converter |
| 文件： | 总29页 (文件大小：2180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MP4430
36V, 3.5A, Low Quiescent Current,
Synchronous, Step-Down Converter
DESCRIPTION
FEATURES
The MP4430 is a frequency-programmable
(350kHz to 2.5MHz), synchronous, step-down,
switching regulator with integrated internal high-
side and low-side power MOSFETs. It provides
up to 3.5A of highly efficient output current with
current mode control for fast loop response.
Wide 3.3V to 36V Operating Input Range
3.5A Continuous Output Current
1μA Low Shutdown Mode Current
10μA Sleep Mode Quiescent Current
Internal 90mΩ High-Side and 40mΩ Low-
Side MOSFETs
350kHz
Switching Frequency
to
2.5MHz
Programmable
The wide 3.3V to 36V input range accommodates
a variety of step-down applications in automotive
input environments and is ideal for battery-
powered applications due to its extremely low
quiescent current.
Fixed Output Options: 3.3V, 3.8V, 5V
Synchronize to External Clock
Selectable In-Phase or 180° Out-of-Phase
Power Good (PG) Indicator
Programmable Soft-Start (SS) Time
80ns Minimum On Time
Selectable Forced CCM or AAM
Low Dropout Mode
Over-Current Protection (OCP) with Valley-
Current Detection and Hiccup
The MP4430 employs advanced asynchronous
mode (AAM), which helps achieve high
efficiency in light-load condition by scaling down
the switching frequency to reduce switching and
gate driving losses.
Standard features include soft start (SS),
external clock synchronization, enable (EN)
control, and a power good (PG) indicator. High-
duty cycle and low dropout mode are provided
for automotive cold-crank condition.
Available in
Package
a
QFN-16 (3mmx4mm)
APPLICATIONS
Over-current protection (OCP) with valley-
current detection is employed to prevent the
inductor current from running away. Hiccup
mode reduces the average current in short-
circuit condition greatly. Thermal shutdown
provides reliable and fault-tolerant operation.
Automotive Systems
Industrial Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS
directive. For MPS green status, please visit the MPS website under
Quality Assurance. “MPS” and “The Future of Analog IC Technology” are
registered trademarks of Monolithic Power Systems, Inc.
The MP4430 is available in a QFN-16
(3mmx4mm) package.
TYPICAL APPLICATION
VIN
3.3 to 36V
VIN
BST
EN
SYNC
VOUT
SW
MP4430
PHASE
GND
FREQ
FB
PG
SS
VCC
BIAS
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
1
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
ORDERING INFORMATION
Part Number*
Package
Top Marking
MP4430GL
QFN-16 (3mmx4mm)
See Below
* For Tape & Reel, add suffix –Z (e.g. MP4430GL–Z)
TOP MARKING
MP: MPS prefix
Y: Year code
W: Week code
4430: First four digits of the part number
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
FREQ
FB
SS
AGND
PHASE
VIN
VCC
BST
SW
SW
PGND
PGND
EN
SYNC
PG
BIAS
QFN-16 (3mmx4mm)
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
2
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
ABSOLUTE MAXIMUM RATINGS (1)
Supply voltage (VIN)...................... -0.3V to 40V
Switch voltage (VSW) ............ -0.3V to VIN +0.3V
BST voltage (VBST)............................VSW + 6.5V
EN voltage (VEN) ............................ -0.3V to 40V
BIAS voltage (VBIAS)....................... -0.3V to 20V
All other pins.................................... -0.3V to 6V
Thermal Resistance (3) θJA
QFN-16 (3mmx4mm) ............ 48.......11 ... °C/W
θJC
NOTES:
1) Absolute maximum ratings are rated under room temperature
unless otherwise noted. Exceeding these ratings may
damage the device.
2) The maximum allowable power dissipation is a function of the
maximum junction temperature TJ(MAX), the junction-to-
ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
TA)/ θJA. Exceeding the maximum allowable power dissipation
produces an excessive die temperature, causing the regulator
to go into thermal shutdown. Internal thermal shutdown
circuitry protects the device from permanent damage.
3) Measured on JESD51-7, 4-layer PCB.
(2)
Continuous power dissipation (TA = +25°C)
QFN-16 (3mmx4mm).................................2.6W
Junction temperature...............................150°C
Lead temperature ....................................260°C
Storage temperature..................-65°C to 150°C
Recommended Operating Conditions
Supply voltage (VIN)....................... 3.3V to 36V
Operating junction temp. (TJ) ..-40°C to +125°C
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
3
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
ELECTRICAL CHARACTERISTICS
VIN = 12V, VEN = 2V, TJ = -40°C to +125°C (4), unless otherwise noted. Typical values at TJ = +25°C.
Parameter
Symbol
Condition
Min
Typ
Max Units
VFB = 0.85V, no load, no
switching, TJ = +25°C
10
18
VIN quiescent current
VIN shutdown current
IQ
µA
VFB = 0.85V, no load, no switching
VEN = 0V
10
1
25
ISHDN
5
µA
V
VIN under-voltage lockout
threshold rising
INUVRISING
2.4
2.8
3.2
VIN under-voltage lockout
threshold hysteresis
INUVHYS
VREF
150
mV
784
792
800
800
475
816
808
550
mV
mV
kHz
kHz
kHz
ns
Feedback reference voltage
TJ = 25°C
RFREQ = 180kΩ or from sync clock 400
Switching frequency
FSW
RFREQ = 82kΩ or from sync clock
RFREQ = 27kΩ or from sync clock
850
1000 1150
2250 2500 2750
Minimum on time (5)
SYNC input low voltage
SYNC input high voltage
Current limit
TON_MIN
VSYNC_LOW
VSYNC_HIGH
ILIMIT_HS
ILIMIT_LS
IZCD
80
0.4
V
1.8
V
Duty cycle = 40%
4.7
3.1
5.8
4.4
0.1
3
7.3
5.7
A
Low-side valley current limit
ZCD current
VOUT = 3.3V, L = 4.7µH
A
A
Reverse current limit
Switch leakage current
HS switch on resistance
LS switch on resistance
Soft-start current
ILIMIT_REVERSE
ISW_LKG
A
0.01
90
1
µA
mΩ
mΩ
µA
V
RON_HS
VBST - VSW = 5V
VSS = 0.8V
155
75
RON_LS
40
ISS
5
10
15
EN rising threshold
EN threshold hysteresis
VEN_RISING
VEN_HYS
0.9
1.05
120
90
1.2
mV
%
VFB rising
85
105
79
95
115
89
PG rising threshold (VFB/VREF
)
PGRISING
VFB falling
110
84
VFB falling
%
%
µs
µs
V
PG falling threshold (VFB/VREF
PG deglitch timer
)
PGFALLING
VFB rising
113.5 118.5 123.5
PG from low to high
PG from high to low
ISINK = 2mA
30
50
TPG_DEGLITCH
PG output voltage low
VCC regulator
VPG_LOW
VCC
0.2
5
0.4
3
V
VCC load regulation
Thermal shutdown (5)
ICC = 5mA
%
C
°C
TSD
170
20
Thermal shutdown hysteresis
TSD_HYS
NOTE:
4) Not tested in production and guaranteed by over-temperature correlation.
5) Not tested in production and guaranteed by design and characterization.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
4
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
5
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL CHARACTERISTICS (continued)
VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
6
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
7
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
8
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
9
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
10
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
11
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
12
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
13
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VIN = 12V, VOUT = 3.3V, L = 10μH, FSW = 500kHz, AAM, TA = +25°C, unless otherwise noted.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
14
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
PIN FUNCTIONS
Pin #
Name Description
Selectable in-phase or 180° out-of-phase of SYNC input. Drive PHASE high to be
in-phase. Drive PHASE low to be 180° out-of-phase.
1
PHASE
Input supply. VIN supplies power to all of the internal control circuitries and the
power switch connected to SW. A decoupling capacitor to ground must be placed
close to VIN to minimize switching spikes.
2
VIN
SW
3, 10
4, 9
Switch node. SW is the output of the internal power switch.
Power ground. PGND is the reference ground of the power device and requires
PGND careful consideration during PCB layout. For best results, connect PGND with copper
pours and vias.
Enable. Pull EN below the specified threshold to shut the chip down. Pull EN above
the specified threshold to enable the chip.
5
6
EN
Synchronize. Apply a 350kHz to 2.5MHz clock signal to SYNC to synchronize the
internal oscillator frequency to the external clock. The external clock should be at
least 250kHz larger than the RFREQ set frequency. SYNC can also be used to select
forced continuous conduction mode (CCM) or advanced asynchronous mode (AAM).
SYNC
Drive SYNC high before the chip starts up to choose forced CCM. Drive SYNC low or
leave SYNC floating to choose AAM.
Power good indicator. The output of PG is an open drain and goes high if the output
voltage is within ±10% of the nominal voltage.
7
8
PG
External power supply for the internal regulator. Connect BIAS to an external
power supply (5V ≤ VBIAS ≤ 18V) to reduce power dissipation and increase efficiency.
BIAS
Float BIAS or connect BIAS to ground if not used.
Bootstrap. BST is the positive power supply of the high-side MOSFET driver
connected to SW. Connect a bypass capacitor between BST and SW.
11
BST
VCC
Internal bias supply. VCC supplies power to the internal control circuit and gate
drivers. A ≥1µF decoupling capacitor to ground is required close to VCC.
12
13
AGND Analog ground. AGND is the reference ground of the logic circuit.
Soft-start input. Place an external capacitor from SS to AGND to set the soft-start
period. The MP4430 sources 10µA from SS to the soft-start capacitor during start-up.
As the SS voltage rises, the feedback threshold voltage increases to limit inrush
14
SS
current during start-up.
Feedback input. Connect FB to the tap of an external resistor divider from the output
15
16
FB
to AGND to set the output voltage. The feedback threshold voltage is 0.8V. Place the
resistor divider as close to FB as possible. Avoid placing vias on the FB traces.
Switching frequency program. Connect a resistor from FREQ to ground to set the
switching frequency.
FREQ
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
15
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
BLOCK DIAGRAM
BIAS
VCC
VCC
Regulator
VCC
EN
VIN
VCC
Vref
Reference
FREQ
SYNC
BST
Oscillator
PLL
ISW
PHASE
+
-
VFB
PG
110%xVREF
Control Logic,
OCP,
OTP,
BST Refresh
Logic
90%xVREF
VFB
+
-
SW
VCC
Error Amplifier
VREF
VFB
+
+
-
VC
R1
460kΩ
C1
SS
FB
C2
0.2pF
52pF
Ireverse
PGND
AGND
Figure 1: Functional Block Diagram
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
16
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TIMING SEQUENCE
VIN
0
SW
0
EN
Threshold
E
N
0
VCC
VCC
Threshold
0
118.5% Vref
90% Vref
SS
84% Vref
110% Vref
50% REF
IL=ILimit
Vo
0
IL
0
s
30µ
P
G
30µs
50µs
30µs
50µs
0
Start-Up
Nor mal
Nor mal
Nor mal
OV
EN Shutdown
OCP
OC
Release
Figure 2: Time Sequence
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
17
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
Once the device is in CCM, SYNC can be
pulled low again, or with an external clock if
needed. The advantage of CCM is the
controllable frequency and smaller output ripple,
but it also has low efficiency at light load.
OPERATION
The MP4430 is a high-frequency, synchronous,
rectified, step-down, switch-mode converter
with integrated internal high-side and low-side
power MOSFETs. The MP4430 offers a very
compact solution that achieves 3.5A of
continuous output current with excellent load
and line regulation over a wide 3.3V to 36V
input supply range.
Driving SYNC below its specified threshold or
leaving SYNC floating before the chip starts up
enables AAM power-save mode. The MP4430
first enters non-synchronous operation for as
long as the inductor current approaches zero at
light load. If the load is further decreased or is
at no load, then VCOMP is below the internally set
AAM value (VAAM). The MP4430 then enters
sleep mode, which consumes very low
quiescent current to further improve light-load
efficiency.
The MP4430 features a switching frequency
programmable from 350kHz to 2.5MHz,
external soft start, power good indication, and
precision current limit. Its very low operational
quiescent current makes it suitable for battery-
powered applications.
Pulse-Width Modulation (PWM) Control
In sleep mode, the internal clock is blocked first,
so the MP4430 skips some pulses. Since the
FB voltage (VFB) is lower than the internal 0.8V
reference (VREF) at this time, VCOMP ramps up
until it crosses over VAAM. Then the internal
clock is reset, and the crossover time is taken
as the benchmark of the next clock. This control
scheme helps achieve high efficiency by scaling
down the frequency to reduce switching and
gate driver losses during light-load or no-load
conditions.
At moderate to high output current, the MP4430
operates in a fixed-frequency, peak-current-
control mode to regulate the output voltage. An
internal clock initiates a pulse-width modulation
(PWM) cycle. At the rising edge of the clock,
the high-side power MOSFET (HS-FET) is
turned on, and the inductor current rises linearly
to provide energy to the load. The HS-FET
remains on until its current reaches the value
set by the COMP voltage (VCOMP), which is the
output of the internal error amplifier. If in one
PWM period, the current in the HS-FET does
not reach VCOMP, the HS-FET remains on,
saving a turn-off operation.
When the output current increases from light-
load condition, VCOMP becomes larger, and the
switching frequency increases. If the DC value
of VCOMP exceeds VAAM, the operation mode
resumes DCM or CCM, which have a constant
switching frequency.
When the HS-FET is off, it remains off until the
next clock cycle begins. The low-side MOSFET
(LS-FET) is turned on immediately while the
inductor current flows through it.
Inductor
Current
Inductor
Current
AAM Mode
Forced CCM Mode
To prevent shoot-through, a dead time is
inserted to prevent the HS-FET and LS-FET
from being on at the same time. For each turn-
on and -off in a switching cycle, the HS-FET
turns on or off with minimum on and off time
limit.
t
t
t
Load
Decreased
Load
Decreased
t
t
t
Forced CCM and AAM
Figure 3: Forced CCM and AAM
The MP4430 has selectable forced continuous
conduction mode (CCM) and advanced
asynchronous mode (AAM) (see Figure 3).
Driving SYNC higher than its specified
threshold before the chip starts up forces the
device into CCM with a fixed frequency
regardless of the output load current.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
18
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
Error Amplifier (EA)
±10% of its nominal output, the PG output is
pulled high after a delay, typically 30μs. When
the output voltage moves outside of this range
with a hysteresis, the PG output is pulled low
with a 50μs delay to indicate a failure output
status.
The error amplifier compares VFB with VREF and
outputs a current proportional to the difference
between the two. This output current then
charges
or
discharges
the
internal
compensation network to form VCOMP, which
controls the power MOSFET current. The
optimized internal compensation network
minimizes the external component count and
simplifies the control loop design.
Programmable Frequency
The oscillating frequency of the MP4430 can be
programmed either by an external frequency
resistor (RFREQ) or by a logic level synchronous
clock. The frequency resistor should be located
between FREQ and ground as close as to the
device as possible.
Internal Regulator and BIAS
Most of the internal circuitry is powered on by
the 5V internal regulator. This regulator takes
the VIN input and operates in the full VIN range.
When VIN exceeds 5V, the output of the
regulator is in full regulation. When VIN falls
below 5V, the output decreases following VIN.
A decoupling ceramic capacitor is needed close
to VCC.
The value of RFREQ can be estimated with
Equation (1):
170000
fSW1.11(kHz)
RFREQ(kΩ)
(1)
The calculated resistance may need fine-tuning
during the bench test.
For better thermal performance, connect BIAS
to an external power supply between 5V and
18V. The BIAS supply overrides VIN to power
the internal regulator. Using the BIAS supply
allows VCC to be derived from a high-efficiency
external source, such as VOUT. Float BIAS or
connect BIAS to ground if not used.
FREQ is not allowed to be floated even if an
external SYNC clock is added.
SYNC and PHASE
The internal oscillator frequency can be
synchronized to an external clock ranging from
350kHz up to 2.5MHz through SYNC. The
external clock should be at least 250kHz larger
than the RFREQ set frequency. Ensure that the
high amplitude of the SYNC clock is higher than
1.8V, and the low amplitude is lower than 0.4V.
There is no pulse width requirement, but there
is always parasitic capacitance of the pad, so if
the pulse width is too short, a clear rising and
falling edge may not be seen due to the
parasitic capacitance. A pulse longer than
100ns is recommended in application.
Under-Voltage Lockout (UVLO)
Under-voltage lockout (UVLO) protects the chip
from operating at an insufficient supply voltage.
The UVLO comparator monitors the output
voltage of the internal regulator (VCC). The
UVLO rising threshold is about 2.8V with a
150mV hysteresis.
Enable Control (EN)
EN is a digital control pin that turns the
regulator on and off. When EN is pulled below
its threshold voltage, the chip is put into the
lowest shutdown current mode. Pulling EN
above its threshold voltage turns on the part.
Do not float EN.
PHASE is used when two or more MP4430
devices are in parallel with the same SYNC
clock. Pulling PHASE high forces the device to
operate in-phase of the SYNC clock. Pulling it
low forces the device to be 180° out-of-phase of
the SYNC clock. By setting different voltages
for PHASE, two devices can operate 180° out-
of-phase to reduce the total input current ripple
so a smaller input bypass capacitor can be
used (see Figure 4). The PHASE rising
threshold is about 2.5V with a 400mV
hysteresis.
Power Good Indicator (PG)
The MP4430 has a power good (PG) indicator.
PG is the open drain of a MOSFET and should
be connected to VCC or another voltage source
through a resistor (e.g.: 100kΩ). In the
presence of an input voltage, the MOSFET
turns on so that PG is pulled low before SS is
ready. When the regulator output is within
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
19
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
immediately. Then the LS-FET turns on to
discharge the energy, and the inductor current
SW1: Phase high
decreases. The HS-FET remains off unless the
inductor valley current is lower than a certain
current threshold (the valley current limit), even
though the internal clock pulses high. If the
inductor current does not drop below the valley
current limit when the internal clock pulses high,
the HS-FET misses the clock, and the switching
frequency decreases to half the nominal value.
Both the peak and valley current limits assist in
keeping the inductor current from running away
during an overload or short-circuit condition.
SW2: Phase low
SW1, 2 has a 180o phase shift
SYNC
CLK
SW1
SW2
t
Figure 4: In-Phase and 180° Out-of-Phase
Soft Start (SS)
Soft start (SS) is implemented to prevent the
converter output voltage from overshooting
during start-up. When the chip starts up, an
internal current source begins charging the
external soft-start capacitor. When the soft-start
voltage (VSS) is lower than the internal
reference (VREF), VSS overrides VREF, so the
error amplifier uses VSS as the reference. When
VSS is higher than VREF, the error amplifier uses
VREF as the reference.
When the output is shorted to ground, causing
the output voltage to drop below 55% of its
nominal output, the peak current limit is kicked,
and the device considers this to be an output
dead short and triggers hiccup mode
immediately to restart the part periodically.
In hiccup mode, the MP4430 disables its output
power stage and discharges the soft-start
capacitor slowly. The MP4430 restarts with a
full soft-start when the soft-start capacitor is
fully discharged. If the short-circuit condition still
remains after the soft start ends, the device
repeats this operation until the fault is removed
and output returns to the regulation level. This
protection mode reduces the average short
circuit current greatly to alleviate thermal issues
and protect the regulator.
The soft-start time (tSS) set by the external SS
capacitor can be calculated with Equation (2):
CSS(nF) VREF(V)
tSS(ms)
(2)
ISS(A)
Where CSS is the external SS capacitor, VREF is
0.8V, and ISS is the internal 10μA SS charge
current.
Floating Driver and Bootstrap Charging
SS can be used for tracking and sequencing.
A 0.1μF to 1μF external bootstrap capacitor
powers the floating power MOSFET driver. The
floating driver has its own UVLO protection with
a rising threshold of 2.5V and hysteresis of
200mV.
Pre-Bias Start-Up
At start-up, if VFB is higher than VSS, which
means the output has a pre-bias voltage,
neither the HS-FET nor the LS-FET are turned
on until VSS is higher than VFB.
The bootstrap capacitor voltage is charged to
~5V from VCC through a PMOS pass transistor
when the LS-FET is on.
Over-Current Protection (OCP) and Hiccup
The MP4430 has cycle-by-cycle peak current-
limit protection with valley-current detection and
hiccup mode.
At a high duty cycle operation or sleep mode
condition, the time period available to the
bootstrap charging is less, so the bootstrap
capacitor may not be charged sufficiently. In
case the external circuit does not have
sufficient voltage or time to charge the
bootstrap capacitor, extra external circuitry can
be used to ensure that the bootstrap voltage is
in the normal operation region.
The power MOSFET current is accurately
sensed via a current sense MOSFET. It is then
fed to the high-speed current comparator for
current-mode control purposes. During the HS-
FET on state, if the sensed current exceeds the
peak-current limit value set by the COMP high-
clamp voltage, the HS-FET turns off
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
20
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
BST Refresh
Start-Up and Shutdown
To improve dropout, the MP4430 is designed to
operate at close to 100% duty cycle for as long
as the BST to SW voltage is greater than 2.5V.
When the voltage from BST to SW drops below
2.5V, the HS-FET is turned off using a UVLO
circuit, which forces the LS-FET on to refresh
the charge on the BST capacitor.
If both VIN and EN exceed their appropriate
thresholds, the chip starts up. The reference
block starts first, generating a stable reference
voltage and current, and then the internal
regulator is enabled. The regulator provides a
stable supply for the rest of the circuitries.
While the internal supply rail is up, an internal
timer holds the power MOSFET off for about
50µs to blank start-up glitches. When the soft-
start block is enabled, it first holds its SS output
low to ensure that the rest of the circuitries are
ready and slowly ramps up.
Since the supply current sourced from the BST
capacitor is low, the HS-FET can remain on for
more switching cycles than are required to
refresh the capacitor, making the effective duty
cycle of the switching regulator high.
The effective duty cycle during the dropout of
the regulator is mainly influenced by the voltage
drops across the HS-FET, LS-FET, inductor
resistance, and printed circuit board resistance.
Three events can shut down the chip: VIN low,
EN low, and thermal shutdown. During the
shutdown procedure, the signaling path is
blocked first to avoid any fault triggering. VCOMP
and the internal supply rail are then pulled down.
The floating driver is not subject to this
shutdown command, but its charging path is
disabled.
Thermal Shutdown
Thermal shutdown is implemented to prevent
the chip from running away thermally. When the
silicon die temperature exceeds its upper
threshold, the power MOSFETs shut down.
When the temperature drops below its lower
threshold, the chip is enabled again.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
21
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
Since CIN absorbs the input switching current, it
APPLICATION INFORMATION
Setting the Output Voltage
requires an adequate ripple current rating. The
RMS current in the input capacitor can be
estimated with Equation (4):
The external resistor divider connected to FB
sets the output voltage (see Figure 5).
VOUT
VOUT
ICIN ILOAD
(1
)
(4)
V
V
IN
IN
MP4430
FB
The worst-case condition occurs at VIN = 2VOUT
shown in Equation (5):
,
RFB1
Vout
ILOAD
RFB2
ICIN
(5)
2
For simplification, choose an input capacitor
with an RMS current rating greater than half of
the maximum load current.
Figure 5: Feedback Network
Choose RFB1 to be around 40kΩ. Then calculate
RFB2 with Equation (3):
The input capacitor can be electrolytic, tantalum,
or ceramic. When using electrolytic or tantalum
capacitors, add a small, high-quality ceramic
capacitor (e.g.: 0.1μF) as close to the IC as
possible. When using ceramic capacitors,
ensure that they have enough capacitance to
provide a sufficient charge to prevent excessive
voltage ripple at the input. The input voltage
ripple caused by the capacitance can be
estimated with Equation (6):
RFB1
RFB2
(3)
VOUT
1
0.8V
Table 1 lists the recommended feedback
resistor values for common output voltages.
Table 1: Resistor Selection for Common Output
Voltages
ILOAD
VOUT
VOUT
(6)
V
(1
)
VOUT (V)
RFB1 (kΩ)
RFB2 (kΩ)
IN
fSW CIN
V
V
IN
IN
3.3
5
41.2 (1%)
68.1 (1%)
13 (1%)
13 (1%)
Selecting the Output Capacitor
The output capacitor maintains the DC output
voltage. Use ceramic, tantalum, or low-ESR
electrolytic capacitors. For best results, use low
ESR capacitors to keep the output voltage
ripple low. The output voltage ripple can be
estimated with Equation (7):
Selecting the Input Capacitor
The input current to the step-down converter is
discontinuous and therefore requires
capacitor to supply AC current to the converter
while maintaining the DC input voltage. For the
best performance, use low ESR capacitors.
Ceramic capacitors with X5R or X7R dielectrics
are highly recommended because of their low
ESR and small temperature coefficients.
a
VOUT
V
1
(7)
)
VOUT
(1 OUT )(RESR
fSW L
V
8fSW COUT
IN
Where L is the inductor value, and RESR is the
equivalent series resistance (ESR) value of the
output capacitor.
For most applications, use a 4.7µF to 10µF
capacitor. It is strongly recommended to use
another lower-value capacitor (e.g.: 0.1µF) with
a small package size (0603) to absorb high-
frequency switching noise. Place the smaller
capacitor as close to VIN and GND as possible.
For ceramic capacitors, the capacitance
dominates the impedance at the switching
frequency and causes the majority of the output
voltage ripple.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
22
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
For simplification, the output voltage ripple can
be estimated with Equation (8):
higher UVLO point, an external resistor divider
between VIN and EN can be used to achieve a
higher equivalent UVLO threshold (see Figure
6).
VOUT
8fSW2 LCOUT
VOUT
(8)
)
VOUT
(1
V
IN
VIN
VIN
For tantalum or electrolytic capacitors, the ESR
dominates the impedance at the switching
frequency. For simplification, the output ripple
can be approximated with Equation (9):
RUP
EN
RDOWN
VOUT
V
VOUT
(1 OUT )RESR
(9)
fSW L
V
IN
Figure 6: Adjustable UVLO Using EN Divider
The characteristics of the output capacitor also
affect the stability of the regulation system. The
MP4430 can be optimized for a wide range of
capacitance and ESR values.
The UVLO threshold can be calculated with
Equation (12) and Equation (13):
RUP
(12)
(13)
INUVRISING (1
INUVFALLING (1
) VEN_RISING
RDOWN
RUP
Selecting the Inductor
A 1µH to 10µH inductor with a DC current rating
at least 25% higher than the maximum load
current is recommended for most applications.
For higher efficiency, choose an inductor with a
lower DC resistance. A larger-value inductor
results in less ripple current and a lower output
ripple voltage, but also has a larger physical
size, higher series resistance, and lower
saturation current. A good rule for determining
the inductor value is to allow the inductor ripple
current to be approximately 30% of the
maximum load current. The inductance value
can then be calculated with Equation (10):
) VEN_FALLING
RDOWN
Where VEN_RISING is 1.05V, and VEN_FALLING is
0.93V.
External BST Diode and Resistor
An external BST diode can enhance the
efficiency of the regulator when the duty cycle is
high. A power supply between 2.5V and 5V can
be used to power the external bootstrap diode.
VCC or VOUT is recommended to be this power
supply in the circuit (see Figure 7).
VCC
VOUT
VOUT
External BST diode
IN4148
L
(1
)
(10)
RBST
fSW IL
V
BST
SW
IN
VCC/VOUT
CBST
Where ∆IL is the peak-to-peak inductor ripple
L
VOUT
current.
COUT
Choose the inductor ripple current to be
approximately 30% of the maximum load
current. The maximum inductor peak current
can be calculated with Equation (11):
Figure 7: Optional External Bootstrap Diode to
Enhance Efficiency
The recommended external BST diode is
IN4148, and the recommended BST capacitor
value is 0.1µF to 1μF. A resistor in series with
the BST capacitor (RBST) can reduce the SW
rising rate and voltage spikes. This helps
enhance EMI performance and reduce voltage
stress at a high VIN. A higher resistance is
better for SW spike reduction but compromises
efficiency. To make a tradeoff between EMI and
efficiency, a ≤20Ω RBST is recommended.
VOUT
VOUT
ILP ILOAD
(1
)
(11)
2fSW L
V
IN
VIN UVLO Setting
The MP4430 has an internal fixed under-
voltage lockout (UVLO) threshold. The rising
threshold is 2.8V, while the falling threshold is
about 2.65V. For the applications that need a
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
23
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
PCB Layout Guidelines (6)
Efficient PCB layout, especially for input
capacitor placement, is critical for stable
operation.
A
four-layer layout is strongly
recommended to achieve better thermal
performance. For best results, refer to Figure 8
and follow the guidelines below.
1. Place symmetric input capacitors as close to
VIN and GND as possible.
2. Use a large ground plane to connect to
PGND directly.
Top Layer
3. Add vias near PGND if the bottom layer is a
ground plane.
4. Ensure that the high-current paths at GND
and VIN have short, direct, and wide traces.
5. Place the ceramic input capacitor, especially
the small package size (0603) input bypass
capacitor, as close to VIN and PGND as
possible to minimize high-frequency noise.
6. Keep the connection of the input capacitor
and VIN as short and wide as possible.
Inner Layer 1
7. Place the VCC capacitor as close to VCC
and GND as possible.
8. Route SW and BST away from sensitive
analog areas, such as FB.
9. Place the feedback resistors close to the
chip to ensure that the trace which connects
to FB is as short as possible.
10. Use multiple vias to connect the power
planes to the internal layers.
Inner Layer 2
NOTE:
6) The recommended PCB layout is based on Figure 9.
Bottom Layer
Figure 8: Recommended PCB Layout
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
24
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS
U1
3.3V-36V
11
2
VIN
VIN
BST
C1A C1B
C1C C1D
10μF
10μF 0.1μF 0.1μF
C5
0.1μF
L1
R1
100kΩ
MP4430
GND
EN
5
3.3V/3.5A
C2A
3, 10
15
EN
VOUT
GND
SW
FB
10μH
C2B
22μF 22μF
C6
R3
1MΩ
5pF
12
VCC
PG
C4
1μF
R4
R5
100kΩ
316kΩ
7
6
R6
NS
14
16
PG
SYNC
SS
FREQ
BIAS
C3
4.7nF
SYNC
PHASE
R2
169kΩ
1
8
PHASE
C7
NS
PGND AGND
Figure 9: VOUT = 3.3V, FSW = 500kHz
U1
3.3V-36V
11
2
VIN
VIN
EN
BST
C1A C1B
10μF
C1C C1D
10μF 0.1μF 0.1μF
C5
0.1μF
R1
100kΩ
MP4430
GND
EN
L1
5
3.3V/3.5A
3, 10
15
VOUT
SW
FB
10μH
C2A
C2B
22μF 22μF
C6
R3
41.2kΩ
10pF
GND
12
VCC
PG
C4
1μF
R4
13kΩ
R5
100kΩ
7
6
R6
NS
14
16
PG
SYNC
SS
FREQ
BIAS
C3
4.7nF
SYNC
R2
169kΩ
1
8
PHASE
PHASE
C7
NS
PGND AGND
Figure 10: VOUT = 3.3V, FSW = 500kHz for <100kΩ FB Divider Application
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
25
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
U1
3.3V-36V
11
2
VIN
VIN
BST
C1A C1B
C1C C1D
10μF
10μF 0.1μF 0.1μF
C5
0.1μF
L1
R1
100kΩ
MP4430
GND
EN
5
5V/3.5A
3, 10
15
EN
VOUT
GND
SW
FB
10μH
C2A C2B
22μF 22μF
C6
R3
1MΩ
5pF
12
VCC
PG
C4
1μF
R4
R5
100kΩ
191kΩ
7
6
R6
10Ω
14
16
PG
SYNC
SS
FREQ
BIAS
C3
4.7nF
SYNC
PHASE
R2
169kΩ
1
8
PHASE
C7
0.1μF
PGND AGND
Figure 11: VOUT = 5V, FSW = 500kHz
U1
3.3V-36V
11
2
VIN
VIN
EN
BST
C1A C1B
10μF
C1C C1D
10μF 0.1μF 0.1μF
C5
0.1μF
L1
R1
100kΩ
MP4430
GND
EN
5
5V/3.5A
3, 10
15
VOUT
SW
FB
10μH
C2A
C2B
22μF 22μF
C6
R3
68.1kΩ
10pF
GND
12
VCC
PG
C4
1μF
R4
13kΩ
R5
100kΩ
7
6
R6
14
16
PG
SYNC
SS
FREQ
BIAS
10Ω
C3
4.7nF
SYNC
R2
169kΩ
1
8
PHASE
PHASE
C7
0.1µF
PGND AGND
Figure 12: VOUT = 5V, FSW = 500kHz for <100kΩ FB Divider Application
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
26
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
U1
3.3V-36V
11
2
VIN
VIN
BST
C1A C1B
C1C C1D
10μF
10μF 0.1μF 0.1μF
C5
0.1μF
L1
R1
100kΩ
MP4430
GND
EN
5
3.3V/3.5A
3, 10
15
EN
VOUT
GND
SW
FB
2.2μH
C2A
C2B
22μF
22μF
C6
R3
1MΩ
10pF
12
VCC
PG
C4
1μF
R4
R5
100kΩ
316kΩ
7
6
R6
NS
14
16
PG
SYNC
SS
FREQ
BIAS
C3
4.7nF
SYNC
PHASE
R2
33kΩ
1
8
PHASE
C7
NS
PGND AGND
Figure 13: VOUT = 3.3V, FSW = 2.2MHz
U1
3.3V-36V
11
2
VIN
VIN
EN
BST
C1A C1B
10μF
C1C C1D
10μF 0.1μF 0.1μF
C5
0.1μF
L1
R1
100kΩ
MP4430
GND
EN
5
3.3V/3.5A
3, 10
15
VOUT
SW
FB
2.2μH
C2A
C2B
22μF 22μF
C6
R3
41.2kΩ
10pF
GND
12
VCC
PG
C4
1μF
R4
13kΩ
R5
100kΩ
7
6
R6
NS
14
16
PG
SYNC
SS
FREQ
BIAS
C3
4.7nF
SYNC
R2
33kΩ
1
8
PHASE
PHASE
C7
NS
PGND AGND
Figure 14: VOUT = 3.3V, FSW = 2.2MHz for <100kΩ FB Divider Application
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
27
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
TYPICAL APPLICATION CIRCUITS (continued)
U1
3.3V-36V
11
2
VIN
VIN
BST
C1A C1B
C1C C1D
10μF
10μF 0.1μF 0.1μF
C5
0.1μF
L1
R1
MP4430
GND
EN
100kΩ
5
5V/3.5A
C2A
3, 10
15
EN
VOUT
GND
SW
FB
2.2μH
C2B
22μF 22μF
C6
R3
1MΩ
10pF
12
VCC
PG
C4
1μF
R4
R5
100kΩ
191kΩ
7
6
R6
10Ω
14
16
PG
SYNC
SS
FREQ
BIAS
C3
4.7nF
SYNC
PHASE
R2
33kΩ
1
8
PHASE
C7
0.1µF
PGND AGND
Figure 15: VOUT = 5V, FSW = 2.2MHz
U1
3.3V-36V
11
2
VIN
VIN
EN
BST
C1A C1B
10μF
C1C C1D
10μF 0.1μF 0.1μF
C5
0.1μF
L1
R1
100kΩ
MP4430
GND
EN
5
5V/3.5A
3, 10
15
VOUT
GND
SW
FB
2.2μH
C2A
22μF
C2B
22μF
C6
R3
68.1kΩ
10pF
12
VCC
PG
C4
1μF
R4
13kΩ
R5
100kΩ
7
6
R6
14
16
PG
SYNC
SS
FREQ
BIAS
10Ω
C3
4.7nF
SYNC
R2
33kΩ
1
8
PHASE
PHASE
C7
0.1µF
PGND AGND
Figure 16: VOUT = 5V, FSW = 2.2MHz for <100kΩ FB Divider Application
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
28
MP4430 – 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER
PACKAGE INFORMATION
QFN-16 (3mmx4mm)
PIN 1 ID
MARKING
PIN 1 ID
0.15x45°TYP.
PIN 1 ID
INDEX AREA
TOP VIEW
BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.
2) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
0.15x45°
3) JEDEC REFERENCE IS MO-220.
4) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.
MP4430 Rev. 1.01
1/12/2018
www.MonolithicPower.com
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2018 MPS. All Rights Reserved.
29
相关型号：
MP4458DQT-LF
Switching Regulator, Current-mode, 2.2A, 4800kHz Switching Freq-Max, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229VEED-5, TQFN-10
MPS
MP4458DQT-LF-Z
Switching Regulator, Current-mode, 2.2A, 4800kHz Switching Freq-Max, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-229VEED-5, TQFN-10
MPS
MP4458DQT-Z
Switching Regulator, Current-mode, 2.2A, 4800kHz Switching Freq-Max, PDSO10, 3 X 3 MM, MO-229VEED-5, TQFN-10
MPS
©2020 ICPDF网 联系我们和版权申明