AD3V-Z1C-R3/Q [MSYSTEM]
Plug-in Signal Conditioners M-UNIT;
| 型号： | AD3V-Z1C-R3/Q |
| 厂家： | 
M-SYSTEM |
| 描述： | Plug-in Signal Conditioners M-UNIT |
| 文件： | 总9页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MODEL: AD3V
Plug-in Signal Conditioners M-UNIT
[2] OUTPUT LEVEL
A: Open collector (NPN)
B: Open collector (PNP)
C: CMOS level
A/D CONVERTER
(16-bit resolution)
Functions & Features
• Converts a DC input into parallel digital signals with parity
check
[3] POWER INPUT
AC Power
• BCD, binary, reflected binary, two’s complement outputs
selectable
M2: 100 – 240 V AC (Operational voltage range 85 – 264 V,
47 – 66 Hz)
• Open collector or CMOS for output levels
• Output can be scaled and displayed in convenient
engineering unit
DC Power
R3: 12 – 24 V DC
(Operational voltage range 10.8 - 26.4 V, ripple 10 %p-p max.)
P: 110 V DC
• Loop test output
• Response time adjustable within 0.15 and 60 sec.
(Operational voltage range 85 – 150 V, ripple 10 %p-p max.)
Typical Applications
[4] OPTIONS
blank: none
• Interface of analog signal to computers and PLC
• Input to a digital panel meter
/Q: With options (specify the specification)
50
(1.97)
SPECIFICATIONS OF OPTION: Q (multiple selections)
COATING (For the detail, refer to M-System's web site.)
/C01: Silicone coating
80
(3.15)
/C02: Polyurethane coating
/C03: Rubber coating
TERMINAL SCREW MATERIAL
/S01: Stainless steel
139
(5.47)
mm (inch)
RELATED PRODUCTS
• Connector terminal block (model: CNT)
MODEL: AD3V–[1][2]–[3][4]
• Special cable (model: MCN26)
ORDERING INFORMATION
• Code number: AD3V-[1][2]-[3][4]
Specify a code from below for each of [1] through [4].
(e.g. AD3V-S1C-M2/Q)
GENERAL SPECIFICATIONS
Construction: Plug-in
Connection
Input & power: M3.5 screw terminals
Output: 26-pin connector (OMRON XG4A-2634)
Paired connector: OMRON XG4M-2630-T, XG5M-263x-N
Cover: OMRON XG5S-2612
• Specify the specification for option code /Q
(e.g. /C01/S01)
• Use Ordering Information Sheet (No. ESU-1389) for
settings.
Screw terminal: Chromated steel (standard) or stainless
steel
Default setting will be used if not otherwise specified.
Housing material: Flame-resistant resin (black)
Isolation: Input to output to power
Zero adjustment: -99.99 – 99.99 % (front)
Span adjustment-99.99 – 99.99 % (front)
Setting: (Front key pad)
[1] INPUT
Current
Z1: Range 0 – 50 mA DC (Input resistance 100 Ω)
Voltage
S1: Range -1 – + 1 V DC (Input resistance 100 kΩ min.)
S2: Range -10 – +10 V DC (Input resistance 1 MΩ min.)
S3: Range -30 – +30 V DC (Input resistance 1 MΩ min.)
• Scaled range
• Moving average
• Output code
• Available number of bits
• POL/OVF output logic
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 1/9
https://www.m-system.co.jp/
MODEL: AD3V
• Data output logic
OUTPUT SPECIFICATIONS
• HOLD input logic
■ Output Code: Code, logic and scaling are user-selectable.
BCD with polarity (Settable range: -9999 - 9999)
Binary with polarity (Settable range: -7FFF - 7FFF)
Offset binary (Settable range: 0000 - FFFF)
Two’s complement (Settable range: 8000 - 7FFF)
Reflected binary (Settable range: 0000 - FFFF)
Output code, logic, scaling are settable.
■ Available number of bits
• DAV output logic
• DAV output time
• Output rate ‘n’ ratio
• Parity check
• etc.
For detailed information, refer to the instruction manual.
■DISPLAY
LED: 7 mm (.28") 7 segment, red
Number of display digits: 4 digits for DATA display; 2 digits
for ITEM display
Selectable from 8, 10, 12, 14, 16 bits
■ Output Level
• Open Collector
PV indication: Output signal in engineering unit
Overrange indication: LEDs blinking
Power saving mode: Displays turn off if the keys are
untouched for a preset time period
PL1 (POL) LED: Red LED turns on at negative polarity.
PL2 (HOLD) LED: Red LED turns on at HOLD.
Max. collector-emitter voltage: 30 V DC
Max. collector current: 30 mA
Saturation voltage:
NPN ≤ 1.1 V negative common
PNP ≤ 2.0 V positive common
• CMOS Level
H output: ≥ 4.5 V DC
L output: ≤ 0.5 V DC
INPUT SPECIFICATIONS
■ DC Current: 0 – 50 mA DC; shunt resistor attached to
input terminals (0.5 W)
Common: Negative
■ POL output (Polarity): Same logic and level as for the
output code; logic user-selectable
■ OVF output (Overflow): Same logic and level as for the
output code; logic user-selectable
■ DAV output (Data available): Same level as for the output
code; logic user-selectable
Operational range: 0 – 70 mA DC (with 100 Ω/0.5 W)
Usable range:
• Max. range: 0 - 50 mA DC
• Min. step: 0.1 mA DC
• Input setting must: 100 % setting ≥ 0 % setting
• Input value is operational range or 15 to +115 %.
■ DC Voltage
■ Odd or even parity: Same level as for the output code;
logic user-selectable
Operation range:
S1: -1.15 to +1.15 V DC
INSTALLATION
Power consumption
S2: -11.5 to +11.5 V DC
S3: -34.5 to +34.5 V DC
•AC: Approx. 10 VA
Usable range:
•DC: Approx. 4 W (160 mA at 24 V)
Operating temperature: -5 to +55°C (23 to 131°F)
Operating humidity: 30 to 90 %RH (non-condensing)
Mounting: Surface or DIN rail
Weight: 260 g (0.57 lb)
• Max. range:
S1: -1 to +1 V DC
S2: -10 to +10 V DC
S3: -30 to +30 V DC
• Min. step:
S1: 10m V DC
PERFORMANCE in percentage of max. span
Accuracy: ±0.1 %
S2: 100m V DC
S3: 100m V DC
Min. span required to ensure the accuracy: 20 % of the
nominal output range
• Input setting must: 100 % setting ≥ 0 % setting
• Input value is operational range or 15 to +115 %.
■ Hold Input: TTL level (5 V - CMOS level)
Commands to stop data renewal;
Choose from below:
Temp. coefficient: ±0.015 %/°C (±0.008 %/°F)
Resolution: 16 bits
Response time: 0.15 – 60 sec. (0 – 90 %) programmable at
front key pad.
Hold with low or short
Line voltage effect: ±0.1 % over voltage range
Insulation resistance: ≥ 100 MΩ with 500 V DC
Dielectric strength: 2000 V AC @1 minute (input to output
to power to ground)
Hold with high or open
(detecting voltage: approx. 5 V, saturation voltage: ≤ 1 V,
sink current: 0.5 mA)
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 2/9
https://www.m-system.co.jp/
MODEL: AD3V
STANDARDS & APPROVALS
EU conformity:
EMC Directive
EMI EN 61000-6-4
EMS EN 61000-6-2
Low Voltage Directive
EN 61010-1
Installation Category II
Pollution Degree 2
Input or output to power: Reinforced insulation (300 V)
Input to output: Basic insulation (300 V)
RoHS Directive
EXTERNAL VIEW
(Pin Assignments)
DATA Display
DATA
ITEM Display
1
2
26-pin Connector
ITEM
PL1 (POL) LED
PL2 (HOLD) LED
ITEM
DATA
ITEM
UP-DOWN Keys
DATA
UP-DOWN Keys
25
26
PARAMETER LIST
It is available to configure or confirm settings shown below by using front key pad.
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 3/9
https://www.m-system.co.jp/
MODEL: AD3V
MDF.
CODE
ITEM
P/L
DATA
CONTENTS
DEFAULT
----
N/A
-9999 – 9999 Output display in engineering unit with ITEM 01 DATA 1 (as set in ITEM 06/07)
(-FFFF – FFFF) Loop test output with ITEM 01 DATA 2 (‘L’ is indicated as ITEM No.)
BCD or binary (with polarity), offset binary, two’s complement, reected binary
01
1, 2, 3
Modication code
1 : Data indication only.
2 : All parameters are modiable.
3 : Only ITEM 24 is modiable.
1
02
03
N/A
N/A
0 – 99
Status indication (“0” is normally indicated.)
0: Normal 1: Memory error 10: Out of input range -15 – +115%
0
-15.0 – 115.0 Input indicated in % (of the range set in ITEM 22/23)
----
04
05
06
07
06
07
06
07
06
07
06
07
08
2
2
2
2
2
2
2
2
2
2
2
2
2
-99.99 – 99.99 Zero adjustment (%) (ne adj. of the value set in ITEM 22)
-99.99 – 99.99 Span adjustment (%) (ne adj. of the value set in ITEM 23)
0.00
0.00
-9999 – 9999 BCD
-9999 – 9999
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
Display range scaling 0% *1
Display range scaling 100% *1
-1000
1000
-7FFF
7FFF
0000
FFFF
8000
7FFF
0000
FFFF
5
-7FFF – 7FFF Binary
-7FFF – 7FFF
0000 – FFFF Offset binary
0000 – FFFF
8000 – 7FFF Two’s complement
8000 – 7FFF
0000 – FFFF Reected binary
0000 – FFFF
0 – 99
Power ON-delay time (seconds)
09
2
0, 1, 2, 3, 4
Display code 0 : BCD with polarity (decimal)
1 : Binary with polarity 2 : Offset binary
0
3 : Two’s complement
4 : Reected binary
10
11
12
2
2
2
0, 1, 2, 3, 4
0, 1, 2
Available number of bits
0: 16 bits 1: 14 bits 2: 12 bits 3: 10 bits 4: 8 bits
Parity check
0
0
0
0: Disable 1: Enable Parity per each digit 2: Enable Parity for all digits
Odd or even parity (Checking the number of High in the output)
0 : Odd (CMOS level, open collector (PNP) ),
Even (open collector (NPN) )
0, 1
1 : Even (CMOS level, open collector (PNP) ),
Odd (open collector (NPN) )
13
14
2
2
0, 1
0, 1
POL, OVF output logic 0 : Data available at High (CMOS level) or ON (open collector)
1 : Data available at Low (CMOS level) or OFF (open collector)
0
0
Data output logic *2
0 : Positive (CMOS level, open collector (PNP) ),
Negative (open collector (NPN) )
1 : Negative (CMOS level, open collector (PNP) ),
Positive (open collector (NPN) )
15
16
2
2
0, 1
0, 1
HOLD input logic
DAV output logic
0 : HOLD at Low or shortcircuit
1 : HOLD at High or open circuit
0
0
0 : Data available at High (CMOS level) or ON (open collector)
1 : Data available at Low (CMOS level) or OFF (open collector)
17
18
2
2
1 – 50
DAV output time (msec.) selectable up to 50% of the Output Rate (ITEM 20)
1
1
0, 1, 2, 3, 4, 5 Moving average (10 msec./sampling)
0: No 1: 5 samples 2: 8 samples 3: 12 samples 4: 20 samples 5: 36 samples
Delay buffer (seconds, 0 – 90%)
19
2
0.0 – 60.0
0.5
* When setting to less than or equal to 0.1, response time is 0.15 seconds.
20
21
2
2
1 – 20
Output rate ‘n’ ratio (n : 1 – 20 times)
1
0, 1 – 60
Power-saving mode
Input code S1
Input code S2
Input code S3
Input code Z1
0 : Continuous display
1 – 60 : Time before display turned off (minutes)
0% input voltage (V) *3
100% input voltage (V) *3
0% input voltage (V) *3
100% input voltage (V) *3
0% input voltage (V) *3
100% input voltage (V) *3
0% input current (mA) *3
100% input current (mA) *3
10
22
23
22
23
22
23
22
23
24
2
2
2
2
2
2
2
2
3
-1.00 – 1.00
-1.00 – 1.00
-10.0 – 10.0
-10.0 – 10.0
-30.0 – 30.0
-30.0 – 30.0
0.0 – 50.0
0.0 – 50.0
0, 1
-1.00
1.00
-10.0
10.0
-30.0
30.0
4.0
20.0
0
Reset all settings
ROM version
25
N/A
----
----
*1. Of the range set in ITEM 04/05. ITEM 06 < ITEM 07.
*2. ITEM 13, 15 or 16 is independent from ITEM 14.
*3. ITEM 22 < ITEM 23.
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 4/9
https://www.m-system.co.jp/
MODEL: AD3V
EXTERNAL DIMENSIONS unit: mm [inch]
CLAMP
(top & bottom)
7.8 (.31)
DIN RAIL
35mm wide
6
5
4
3
2–4.5 (.18) dia.
MTG HOLE
15 (.59) deep
7
8
1
2
8–M3.5
SCREW
16
(.63)
50 (1.97)
103 (4.06)
123 (4.84)
40 (1.57)
50 (1.97)
55 (2.17) min.
[3.3 (.13)]
•When mounting, no extra space is needed between units.
TERMINAL ASSIGNMENTS unit: mm (inch)
INPUT RESISTOR
(model: REM)
6
5
4
3
7
8
1
2
Input shunt resistor attached
for current input.
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 5/9
https://www.m-system.co.jp/
MODEL: AD3V
SCHEMATIC CIRCUITRY & CONNECTION DIAGRAM
PL1 PL2
(POL) (HOLD)
Isolation
Low Drift
Amplifier
A/D
Converter
+
–
3
4
1
2
5
6
OUTPUT
*
INPUT
R
Digital
Computation
Circuit
DATA
ITEM
7
8
U(+)
V(–)
POWER
Base Socket
*Input shunt resistor attached for current input.
■ Connection Examples
• OPEN COLLECTOR (NPN)
• OPEN COLLECTOR (PNP)
• CMOS LEVEL (5V-CMOS)
AD3V
AD3V
AD3V
OUTPUT
OUTPUT
COM (+)
OUTPUT
LOAD
COM (
-
)
COM (-)
LOAD
H : 4.5V or more
L : 0.5V or less
For inductive load, connect
a spark quenching diode at
load side.
COM (-)
26-pin
CONNECTOR
26-pin
CONNECTOR
For inductive load, connect
a spark quenching diode at
load side.
26-pin
CONNECTOR
Max. collector-emitter voltage : 30V DC
Max. collector current : 30mA
Saturation voltage : ≤ 1.1V DC
Max. collector-emitter voltage : 30V DC
Max. collector current : 30mA
Saturation voltage : ≤ 2.0V DC
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 6/9
https://www.m-system.co.jp/
MODEL: AD3V
OUTPUT CONNECTOR (26-pin)
■ BCD OUTPUT
■ BINARY,TWO’S COMPLEMENT OUTPUTS
PIN NO.
ASSIGNMENT
PIN NO.
17
ASSIGNMENT
PIN NO.
ASSIGNMENT
PIN NO.
17
ASSIGNMENT
COM *1
COM (–)
OVF
1
2
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
100
100
100
100
101
101
101
101
102
102
102
102
103
103
103
103
COM
1
2
B0
B1
1
*
18
COM (–)
OVF
18
3
B2
19
3
19
4
B3
20
POL
4
20
POL
5
B4
21
DAV
5
21
DAV
2
*
2
*
6
B5
22
HOLD
6
22
HOLD
4
P0
7
B6
23
P0
3
*
*
7
23
P1
P2
P3
P1
P2
P3
8
B7
24
8
24
9
B8
25
9
25
10
11
12
13
14
15
16
B9
26
10
11
12
13
14
15
16
26
B10
B11
B12
B13
B14
B15
*1. For open collector (NPN) and CMOS level, COM (–). For open collector(PNP), COM (+).
*2. HOLD signal is for input, the others are for output.
*3. P0 corresponds to n × 100, P1 to n × 101, P2 to n × 102, P3 to n × 103. P0 – P3 are in sync when the parity for all digits
are valid.
*4. P0 corresponds to B0 – B3, P1 to B4 – B7, P2 to B8 – B11, P3 to B12 – B15. P0 – P3 are in sync when the parity for all
digits are valid.
Note: With the number of bits set to 14 (or 12, 10, 8) with ITEM 10, Pin No. 1 – 14 (or 1 – 12, 1 – 10, 1 – 8) are valid.
TIMING CHART
output rate approx. 10 ms*
DAV
OUTPUT
approx. 1 ms**
DATA
OUTPUT
HOLD
INPUT
Data output is halt during HOLD input.
DAV is output during DATA output.
* Varies by individual module. Set to ‘n’ times with ITEM 20.
**Selectable with ITEM 17.
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 7/9
https://www.m-system.co.jp/
MODEL: AD3V
INPUT-OUTPUT RELATION EXAMPLES
• FS
-FS stands for -15 % of the input range, which is configured by ITEM 22, 0 % input voltage/current and ITEM 23, 100 % input
voltage/current. +FS stands for +115 % of the input range.
• OVF
When one of the following conditions is true, the digital output overflows (OVF).
1) When the input signal is out of the range between -FS and +FS.
2) When the display value (= output signal) exceeds the display range.
The display range differs according to output code. For example, in case of BCD with polarity, it is -9999 to 9999. Please refer
to the instruction manual for detail.
■ BCD, BINARY (WITH POLARITY)
DATA
DIGITAL OUTPUT
POLARITY
OVF
POL
MSB
LSB
■ OFFSET BINARY & TWO’S COMPLEMENT
–FS
ANALOG INPUT
DATA
+FS
0%
UNUSED
OVF
POL
MSB
LSB
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 8/9
https://www.m-system.co.jp/
MODEL: AD3V
OUTPUT DATA & PARITY BIT RELATIONSHIP
Hi and Lo indicate the voltage level. Parity logic is unchanged. (ITEM 12 = I12; ITEM 14 = I14)
■ OPEN COLLECTOR (NPN)
■ CMOS LEVEL, OPEN COLLECTOR (PNP)
• Positive Logic I14 : 0, Lo : False, Hi: True
PARITY
• Positive Logic I14 : 1, Lo : False, Hi: True
PARITY
DATA
8
4
2
1
DATA
8
4
2
1
Even I12 : 0 Odd I12 : 1
Odd I12 : 0
Even I12 : 1
0
1
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
0
1
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
10
11
12
13
14
15
• Negative Logic I14 : 0, Lo : True, Hi: False
PARITY
Even I12 : 0 Odd I12 : 1
• Negative Logic I14 : 1, Lo : True, Hi: False
PARITY
DATA
8
4
2
1
DATA
8
4
2
1
Odd I12 : 0
Hi
Even I12 : 1
0
1
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
0
1
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Hi
Hi
Lo
Lo
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
Hi
Lo
Lo
Hi
Hi
Lo
Lo
Hi
Lo
Hi
Hi
Lo
Lo
2
2
Lo
3
3
Hi
4
4
Lo
5
5
Hi
6
6
Hi
7
7
Lo
8
8
Lo
9
9
Hi
10
11
12
13
14
15
10
11
12
13
14
15
Hi
Lo
Hi
Lo
Lo
Hi
Specifications are subject to change without notice.
AD3V SPECIFICATIONS
ES-1389 Rev.24 Page 9/9
https://www.m-system.co.jp/
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