ADS-935MC-C [MURATA]
A/D Converter, 16-Bit, 1 Func, Hybrid, CDIP40;
| 型号： | ADS-935MC-C |
| 厂家： | 
muRata |
| 描述： | A/D Converter, 16-Bit, 1 Func, Hybrid, CDIP40 CD 转换器 |
| 文件： | 总8页 (文件大小：440K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
PRODUCT OVERVIEW
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION
PIN FUNCTION
The ADS-935 is a 16-bit, 5MHz sampling A/D converter.
This device accurately samples full-scale input signals
up to Nyquist frequencies with no missing codes.
The dynamic performance of the ADS-935 has been
optimized to achieve a signal-to-noise ratio (SNR) of
83dB and a total harmonic distortion (THD) of –86dB.
1
±
3
4
5
6
ꢁ
8
9
+3.±ꢀ REF. OUT 40 +1±ꢀ/+15ꢀ
UNIPOLAR
39 –1±ꢀ/–15ꢀ
ANALOG INPUT
38 +5ꢀ ANALOG SUPPLY
ANALOG GROUND 3ꢁ –5ꢀ SUPPLY
OFFSET ADJUST 36 ANALOG GROUND
GAIN ADJUST
35 COMP. BITS
Packaged in a 40-pin TDIP, the functionally complete
ADS-935 contains a fast-settling sample-hold amplifier,
a subranging (two-pass) A/D converter, an internal
reference, timing/control logic, and error-correction
circuitry. Digital input and output levels are TTL. The
ADS-935 only requires the rising edge of the start
convert pulse to operate.
DIGITAL GROUND 34 OUTPUT ENABLE
FIFO/DIR
33 OꢀERFLOW
FEATURES
FIFO READ
3± EOC
■
16-bit resolution
10 FSTAT1
11 FSTAT±
31 +5ꢀ DIGITAL SUPPLY
30 DIGITAL GROUND
■
5MHz sampling rate
■
1± START CONꢀERT ±9 BIT 1 (MSB)
Functionally complete
13 BIT 16 (LSB)
14 BIT 15
15 BIT 14
16 BIT 13
1ꢁ BIT 1±
18 BIT 11
19 BIT 10
±0 BIT 9
±8 BIT 1 (MSB)
±ꢁ BIT ±
±6 BIT 3
±5 BIT 4
±4 BIT 5
±3 BIT 6
±± BIT ꢁ
±1 BIT 8
■
Requiring ±5ꢀ supplies and either ±1±v or ±15ꢀ
supplies, the ADS-935 dissipates 3.3 Watts. The device
is offered with a bipolar (±±.ꢁ5ꢀ) or a unipolar (0 to
–5.5ꢀ) analog input range. Models are available for use
in either commercial (0 to +ꢁ0°C) or HI-REL (–55 to
+1±5°C) operating temperature ranges. A proprietary,
auto-calibrating, error-correcting circuit enables the
device to achieve specified performance over the full
military temperature range. Typical applications include
medical imaging, radar, sonar, communications and
instrumentation.
No missing codes over full HI-REL temperature
range
■
■
■
■
■
Edge-triggered
±5ꢀ, ±1±ꢀ or ±15ꢀ supplies, 3.0 Watts
Small, 40-pin, ceramic TDIP
83dB SNR, –86dB THD
Ideal for both time and frequency-domain
applications
BLOCK DIAGRAM
POWER AND GROUNDING
+5V ANALOG SUPPLY
+5V DIGITAL SUPPLY
–5V SUPPLY
38
31
37
ANALOG GROUND
DIGITAL GROUND
4, 36
7, 30
–12/–15V ANALOG SUPPLY 39
+12/+15V ANALOG SUPPLY 40
UNIPOLAR
2
Figure 1. ADS-935 Functional Block Diagram
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
01 Apr 2011 MDA_ADS-935.B02 Page 1 of 8
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
ABSOLUTE MAXIMUM RATINGS
PHYSICAL/ENꢀIRONMENTAL
PARAMETERS
+5ꢀ Supply (Pins 31, 38)
–5ꢀ Supply (Pin 3ꢁ)
+1±ꢀ/+15ꢀ Supply (pin 40)
–1±ꢀ/–15ꢀ Supply (pin 39)
Digital Inputs (Pin 8, 9, 1±, 34, 35)
Analog Input (Pin 3)
LIMITS
0 to +6
0 to –6
UNITS
ꢀolts
ꢀolts
ꢀolts
ꢀolts
ꢀolts
ꢀolts
°C
PARAMETERS
MIN.
TYP.
MAX.
UNITS
Operating Temp. Range, Case
ADS-935MC
ADS-935MM
0
–55
—
—
+70
+125
°C
°C
0 to +16ꢀ
0 to -16ꢀ
–0.3 to +ꢀdd +0.3
Thermal Impedance
θjc
θca
Storage Temperature Range
—
—
4
18
—
—
°C/Watt
°C/Watt
±5
+300
Lead Temperature (10 seconds)
–65
—
+150
°C
Package Type
40-pin, metal-sealed, ceramic TDIP
0.56 ounces (16 grams)
Weight
FUNCTIONAL SPECIFICATIONS
(TA = +±5°C, ±ꢀCC = ±1±/15ꢀ ±ꢀDD = ±5ꢀ, 5MHz sampling rate, and a minimum 3 minute warmup ➀ unless otherwise specified.)
+±5°C
TYP.
0 TO +ꢁ0°C
TYP.
–55 TO +1±5°C
ANALOG INPUT
MIN.
MAX.
MIN.
MAX.
MIN.
TYP.
MAX.
UNITS
Input ꢀoltage Range
Unipolar
Bipolar
Input Resistance (pin 3)
Input Resistance (pin ±)
Input Capacitance
—
—
—
—
—
0 to –5.5
±±.ꢁ5
400
480
10
—
—
—
—
15
—
—
—
—
—
0 to –5.5
±±.ꢁ5
400
480
10
—
—
—
—
15
—
—
—
—
—
0 to –5.5
±±.ꢁ5
400
480
10
—
—
—
—
15
ꢀolts
ꢀolts
Ω
Ω
pF
DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0" ➁
Start Convert Positive Pulse Width ➂
+±.0
—
—
—
±0
—
—
—
—
50
—
+0.8
+±0
–±0
—
+±.0
—
—
—
±0
—
—
—
—
50
—
+0.8
+±0
–±0
—
+±.0
—
—
—
±0
—
—
—
—
50
—
+0.8
+±0
–±0
—
ꢀolts
ꢀolts
μA
μA
ns
STATIC PERFORMANCE
Resolution
—
—
–0.95
—
—
—
16
—
—
—
—
–0.95
—
—
—
16
—
—
—
—
–0.95
—
—
—
16
—
—
Bits
LSB
LSB
%FSR
%FSR
%FSR
%FSR
Bits
Integral Nonlinearity (fin = 10kHz)
Differential Nonlinearity (fin = 10kHz)
Full Scale Absolute Accuracy
Bipolar Zero Error (Tech Note ±)
Bipolar Offset Error (Tech Note ±)
Gain Error (Tech Note ±)
±1.0
±0.5
±0.15
±0.1
±0.1
±0.15
—
±1.5
±0.5
±0.3
±0.±
±0.±
±0.3
—
±±.0
±0.5
±0.5
±0.4
±0.4
±0.5
—
+1.0
±0.3
±0.±
±0.±
±0.3
—
+1.0
±0.5
±0.4
±0.4
±0.5
—
+1.5
±0.8
±0.6
±0.6
±0.8
—
—
16
—
16
—
16
No Missing Codes (fin = 10kHz)
DYNAMIC PERFORMANCE
Peak Harmonics (–0.5dB)
dc to 500kHz
500kHz to ±.45MHz
Total Harmonic Distortion (–0.5dB)
dc to 500kHz
—
—
–8ꢁ
–8±
–8±
–80
—
—
–8ꢁ
–8±
–8±
–80
—
—
–8±
–ꢁ8
–ꢁ8
–ꢁ8
dB
dB
—
—
–86
–81
–81
–80
—
—
–86
–81
–81
–80
—
—
–81
–ꢁꢁ
–ꢁ6
–ꢁ6
dB
dB
500kHz to 1MHz
Signal–to–Noise Ratio
(w/o distortion, –0.5dB)
dc to 500kHz
500kHz to ±.45MHz
Signal-to-Noise Ratio ➃
(& distortion, –0.5dB)
dc to 500kHz
500kHz to ±.45MHz
Two-tone Intermodulation
Distortion (fin = ±00kHz,
fs = 5MHz, –0.5dB)
84
8±
86
85
—
—
84
8±
86
85
—
—
ꢁꢁ
ꢁꢁ
80
80
—
—
dB
dB
80
ꢁ9
8±
81
—
—
80
ꢁ9
8±
81
—
—
ꢁ6
ꢁ6
ꢁ8
ꢁ5
—
—
dB
dB
—
—
–86
80
–85
—
—
—
–86
80
–85
—
—
—
–86
80
–8±
—
dB
μꢀrms
Noise
Input Bandwidth (–3dB)
Small Signal (–±0dB input)
Large Signal (–0.5dB input)
Feedthrough Rejection (fin = 1MHz)
Slew Rate
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time
(to ±0.001%FSR, 5.5ꢀ step)
Overvoltage Recovery Time ➄
A/D Conversion Rate
—
—
—
—
—
—
±5
15
90
±400
4
±
—
—
—
—
—
—
—
—
—
—
—
—
±5
±5
90
±400
4
±
—
—
—
—
—
—
—
—
—
—
—
—
±5
15
90
±400
4
±
—
—
—
—
—
—
MHz
MHz
dB
ꢀ/μs
ns
ps rms
—
—
5
80
±00
—
—
—
—
—
—
5
80
±00
—
—
—
—
—
—
5
90
±00
—
—
—
—
ns
ns
MHz
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
01 Apr 2011 MDA_ADS-935.B02 Page ± of 8
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
+±5°C
TYP.
0 to +ꢁ0°C
TYP.
–55 to +1±5°C
ANALOG OUTPUT
MIN.
MAX.
MIN.
MAX.
MIN.
TYP.
MAX.
UNITS
Internal Reference
ꢀoltage
Drift
—
—
—
+3.±
±30
5
—
—
—
—
—
—
+3.±
±30
5
—
—
—
—
—
—
+3.±
±30
5
—
—
—
ꢀolts
ppm/°C
mA
External Current
DIGITAL OUTPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
Output Coding ➅
+±.4
—
—
—
—
—
—
—
+0.4
–4
+±.4
—
—
—
—
—
—
—
+0.4
–4
+±.4
—
—
—
—
—
—
—
+0.4
–4
ꢀolts
ꢀolts
mA
—
+4
—
+4
—
+4
mA
(Offset) Binary / Complementary (Offset) Binary / Two's Complement / Complementary Two's Complement
POWER REQUIREMENTS
Power Supply Ranges ➆
+5ꢀ Supply
–5ꢀ Supply
+1±ꢀ Supply ➇
–1±ꢀ Supply ➇
+15ꢀ Supply ➇
–15ꢀ Supply ➇
Power Supply Currents
+5ꢀ Supply
+4.ꢁ5
–4.ꢁ5
+11.5
–11.5
+14.5
–14.5
+5.0
–5.0
+1±.0
–1±.0
+15.0
–15.0
+5.±5
–5.±5
+1±.5
–1±.5
+15.5
–15.5
+4.ꢁ5
–4.ꢁ5
+11.5
–11.5
+14.5
–14.5
+5.0
–5.0
+1±.0
–1±.0
+15.0
–15.0
+5.±5
–5.±5
+1±.5
–1±.5
+15.5
–15.5
+4.9
–4.9
+11.5
–11.5
+14.5
–14.5
+5.0
–5.0
+1±.0
–1±.0
+15.0
–15.0
+5.±5
–5.±5
+1±.5
–1±.5
+15.5
–15.5
ꢀolts
ꢀolts
ꢀolts
ꢀolts
ꢀolts
ꢀolts
—
—
—
—
—
—
+±40
–150
–50
+65
3.3
—
—
—
—
—
—
—
—
—
+±40
–150
–50
+65
3.3
—
—
—
—
—
—
—
—
—
—
—
+±40
–150
–50
+65
3.3
—
—
—
—
—
mA
mA
mA
–5ꢀ Supply
–1±/15ꢀ Supply ➇
+1±/15ꢀ Supply ➇
Power Dissipation
Power Supply Rejection
mA
Watts
%FSR/%ꢀ
—
±0.0ꢁ
—
—
±0.0ꢁ
—
±0.0ꢁ
Footnotes:
➀ All power supplies must be on before applying a start convert pulse. All supplies and
the clock (START CONVERT) must be present during warmup periods. The device
must be continuously converting during this time.
➄ This is the time required before the A/D output data is valid once the analog input is
back within the specified range.
➅ The minimum supply voltages of +4.9V and –4.9V for VDD are required for –55°C
operation only. The minimum limits are +4.75V and –4.75V when operating at
+125°C.
➁ When COMP. BITS (pin 35) is low, logic loading "0" will be –350μA.
➂ A 5MHz clock with a 50nsec positive pulse width is used for all production testing.
See Timing Diagram for more details.
➆ The minimum supply voltages of +4.9V and –4.9V for VDD are required for –55°C
operation only. The minimum limits are +4.75V and –4.75V when operating at
+125°C.
➃ Effective bits is equal to:
Full Scale Amplitude
(SNR + Distortion) – 1.76 +
20 log
6.02
Actual Input Amplitude
➇ 12V only or 15V only required.
TECHNICAL NOTES
1. Obtaining fully specified performance from the ADS-935 requires care-
ful attention to pc-card layout and power supply decoupling. The device's
analog and digital ground systems are connected to each other internally.
For optimal performance, tie all ground pins ((4, ꢁ, 30 and 36) directly to a
large analog ground plane beneath the package.
binary. Using the MSB output (pin ±9) instead of the MSB output (pin ±8)
changes the respective output codings to complementary two's comple-
ment and two's complement.
Pin 35 is TTL compatible and can be directly driven with digital logic in
applications requiring dynamic control over its function. There is an internal
pull-up resistor on pin 35 allowing it to be either connected to +5ꢀ or left
open when a logic "1" is required.
For the best performance it is recommended to use a single power source
for both the +5ꢀ analog and +5ꢀ digital supplies. Bypass all power supplies
and the +3.±ꢀ reference output to ground with 4.ꢁꢂF tantalum capacitors
in parallel with 0.1ꢂF ceramic capacitors. Locate the bypass capacitors as
close to the unit as possible.
4. To enable the three-state outputs, connect OUTPUT ENABLE (pin 34) to a
logic "0" (low). To disable, connect pin 34 to a logic "1" (high).
5. Applying a start convert pulse while a conversion is in progress (EOC =
logic "1") will initiate a new and probably inaccurate conversion cycle. Data
from both the interrupted and subsequent conversions will be invalid.
±. The ADS-935 achieves its specified accuracies without the need for exter-
nal calibration. If required, the device's small initial offset and gain errors
can be reduced to zero using the adjustment circuitry shown in Figure ±.
When using this circuitry, or any similar offset and gain calibration hard-
ware, make adjustments following warmup. To avoid interaction, always
adjust offset before gain. Tie pins 5 and 6 to ANALOG GROUND (pin 4) if not
using offset and gain adjust circuits.
6. Do not enable/disable or complement the output bits or read from the FIFO
during the conversion process (from the rising edge of EOC to the falling
edge of EOC).
ꢁ. The OꢀERFLOW bit (pin 33) switches from 0 to 1 when the input voltage
exceeds that which produces an output of all 1’s or when the input equals
or exceeds the voltage that produces all 0’s. When COMP BITS is activated,
the above conditions are reversed.
3. Pin 35 (COMP. BITS) is used to select the digital output coding format of the
ADS-935 (see Tables ±a and ±b). When this pin has a TTL logic "0" applied,
it complements all of the ADS-935's digital outputs.
When pin 35 has a logic "1" applied, the output coding is complementary
offset binary. Applying a logic "0" to pin 35 changes the coding to offset
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
01 Apr 2011 MDA_ADS-935.B02 Page 3 of 8
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
Once the FIFO is full (indicated by FSTAT1 and FSTAT± both equal to "1"), it
can be read by dropping the FIFO READ line (pin 9) to a logic "0" and then
applying a series of 15 rising edges to the read line. Since the first data word
is already present at the FIFO output, the first read command (the first rising
edge applied to FIFO READ) will bring data from the second conversion to the
output. Each subsequent read command/rising edge brings the next word
to the output lines. After the 15th rising edge brings the 16th data word to
the FIFO output, the subsequent falling edge on READ will update the status
outputs (after a ±0ns maximum delay) to FSTAT1 = 0, FSTAT± = 1 indicating
that the FIFO is empty.
INTERNAL FIFO OPERATION
The ADS-935 contains an internal, user-initiated, 18-bit, 16-word FIFO
memory. Each word in the FIFO contains the 16 data bits as well as the MSB
and OꢀERFLOW bits. Pins 8 (FIFO/DIR) and 9 (FIFO READ) control the FIFO's
operation. The FIFO's status can be monitored by reading pins 10 (FSTAT1)
and 11 (FSTAT±).
When pin 8 (FIFO/DIR) has a logic "1" applied, the FIFO is inserted into the
digital data path. When pin 8 has a logic "0" applied, the FIFO is transpar-
ent and the output data goes directly to the output three-state register (whose
operation is controlled by pin 34 (ENABLE)).Read and write commands to the
FIFO are ignored when the ADS-935 is operated in the "direct" mode.It takes a
maximum of ±0ns to switch the FIFO in or out of the ADS-935's digital data path.
If a read command is issued after the FIFO empties, the last word (the 16th
conversion) will remain present at the outputs.
FIFO Reset Feature
FIFO WRITE and READ Modes
At any time, the FIFO can be reset to an empty state by putting the ADS-935
into its "direct" mode (logic "0" applied to pin 8, FIFO/DIR) and also applying
a logic "0" to the FIFO READ line (pin 9). The empty status of the FIFO will be
indicated by FSTAT1 going to a "0" and FSTAT± going to a "1". The status
outputs change 40ns after applying the control signals.
Once the FIFO has been enabled (pin 8 high), digital data is automatically
written to it, regardless of the status of FIFO READ (pin 9). Assuming the FIFO
is initially empty, it will accept data (18-bit words) from the next 16 consecu-
tive A/D conversions. As a precaution, pin 9 (which controls the FIFO's READ
function) should not be low when data is first written to an empty FIFO.
When the FIFO is initially empty, digital data from the first conversion (the
"oldest" data) appears at the output of the FIFO immediately after the first
conversion has been completed and remains there until the FIFO is read.
FIFO Status, FSTAT1 and FSTAT2
Monitor the status of the data in the FIFO by reading the two status pins,
FSTAT1 (pin 10) and FSTAT± (pin 11).
If the output three-state register has been enabled (logic "0" applied to pin
34), data from the first conversion will appear at the output of the ADS-935.
Attempting to write a 1ꢁth word to a full FIFO will result in that data, and any
subsequent conversion data, being lost.
CONTENTS
Empty (0 words)
<half full (≤8 words)
half-full or more (≥8 words)
Full (16 words)
FSTAT1
FSTAT±
0
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
1
0
0
Table 1. FIFO Delays
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
01 Apr 2011 MDA_ADS-935.B02 Page 4 of 8
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
Zero/Offset Adjust Procedure
CALIBRATION PROCEDURE
1. Apply a train of pulses to the START CONꢀERT input (pin 1±) so that the
converter is continuously converting.
Connect the converter per Figure ±. Any offset/gain calibration procedures
should not be implemented until the device is fully warmed up. To avoid
interaction, adjust offset before gain. The ranges of adjustment for the
circuits in Figure ± are guaranteed to compensate for the ADS-935’s initial
accuracy errors and may not be able to compensate for additional system
errors.
±. For zero/offset adjust, apply –4±ꢂꢀ to the ANALOG INPUT (pin 3).
3. Adjust the offset potentiometer until the code flickers between 1000 0000
0000 0000 and 0111 1111 1111 1111 with pin 35 tied high (comple-
mentary offset binary) or between 0111 1111 1111 1111 and 1000 0000
0000 0000 with pin 35 tied low (offset binary).
A/D converters are calibrated by positioning their digital outputs exactly
on the transition point between two adjacent digital output codes. This is
accomplished by connecting LED's to the digital outputs and performing
adjustments until certain LED's "flicker" equally between on and off. Other
approaches employ digital comparators or microcontrollers to detect when
the outputs change from one code to the next.
4. Two's complement coding requires using BIT 1 (MSB) (pin ±9). With pin 35
tied low, adjust the trimpot until the output code flickers between all 0’s
and all 1’s.
Gain Adjust Procedure
For the ADS-935, offset adjusting is normally accomplished when the ana-
log input is 0 minus ½ LSB (–4±ꢂꢀ). See Table ±b for the proper bipolar
output coding.
1. For gain adjust, apply +±.ꢁ498ꢁ4ꢀ to the ANALOG INPUT (pin 3).
±. Adjust the gain potentiometer until all output bits are 0’s and the LSB flick-
ers between a 1 and 0 with pin 35 tied high (complementary offset binary)
or until all output bits are 1’s and the LSB flickers between a 1 and 0 with
pin 35 tied low (offset binary).
Gain adjusting is accomplished when the analog input is at nominal full
scale minus 1½ LSB's (+±.ꢁ498ꢁ4ꢀ).
Note: Connect pin 5 to ANALOG GROUND (pin 4) for operation without
zero/offset adjustment. Connect pin 6 to pin 4 for operation without gain
adjustment.
3. Two's complement coding requires using BIT 1 (MSB) (pin ±9). With pin
35 tied low, adjust the gain trimpot until the output code flickers equally
between 0111 1111 1111 1111 and 0111 1111 1111 1110.
OUTPUT FORMAT
Complementary (Offset) Binary
PIN 35 LOGIC LEVEL
4. To confirm proper operation of the device, vary the applied input voltage to
obtain the output coding listed in Table ±b.
1
0
1
0
(Offset) Binary
Complementary Two’s Complement (Using MSB, pin ±9)
Two’s Complement (Using MSB, pin ±9)
Table 2a. Setting Output Coding Selection (Pin 35)
Figure 2. Bipolar Connection Diagram
DATEL
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Tel: (508) 339-3000
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01 Apr 2011 MDA_ADS-935.B02 Page 5 of 8
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
COMP. BINARY
BINARY
COMP. TWO'S COMP.
TWO'S COMP.
UNIPOLAR
SCALE
0 –1 LSB
INPUT RANGE
0 to –5.5ꢀ
–0.000084
–0.0001±6
–0.68ꢁ500
–1.3ꢁ5000
–±.ꢁ49958
–±.ꢁ50000
–4.1±5000
–4.81±500
–5.499916
–5.499958
–5.500000
INPUT RANGE
±±.ꢁ5ꢀ
BIPOLAR
SCALE
+FS –1 LSB
+FS –1 1/± LSB
+3/4 FS
+1/± FS
0
–1/± LSB
–1/± FS
–3/4 FS
MSB
1111 1111 1111 1111 0000 0000 0000 0000 0111 1111 1111 1111 1000 0000 0000 0000
LSB "1" to "0" LSB "0" to "1" LSB "1" to "0" LSB "0" to "1"
1110 0000 0000 0000 0001 1111 1111 1111 0110 0000 0000 0000 1001 1111 1111 1111
1100 0000 0000 0000 0011 1111 1111 1111 0100 0000 0000 0000 1011 1111 1111 1111
1000 0000 0000 0000 0111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111
0111 1111 1111 1111 1000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000
0100 0000 0000 0000 1011 1111 1111 1111 1100 0000 0000 0000 0011 1111 1111 1111
0010 0000 0000 0000 1101 1111 1111 1111 1010 0000 0000 0000 0101 1111 1111 1111
0000 0000 0000 0001 1111 1111 1111 1110 1000 0000 0000 0001 0111 1111 1111 1110
LSB MSB
LSB MSB
LSB MSB
LSB
+±.ꢁ49916
+±.ꢁ498ꢁ4
+±.06±500
+1.3ꢁ5000
0.000000
–0.000084
–1.3ꢁ5000
–±.06±500
–±.ꢁ49916
–±.ꢁ49958
–±.ꢁ50000
0 –1 1/± LSB
0 – 1/8 FS
0 – 1/4 FS
–1/± FS – 1/±LSB
–1/± LSB
–3/4 FS
–ꢁ/8 FS
–FS +1 LSB
–FS + 1/± LSB
–FS
–FS +1 LSB
–FS + 1/± LSB
–FS
LSB "0" to "1"
0000 0000 0000 0000 1111 1111 1111 1111 1000 0000 0000 0000 0111 1111 1111 1111
OFFSET BINARY COMP. OFF. BIN. TWO'S COMP. COMP. TWO'S COMP.
LSB "1" to "0"
LSB "0" to "1"
LSB "1" to "0"
Table 2b. Output Coding
THERMAL REQUIREMENTS
not overheat. The ground and power planes beneath the package, as well as
all pcb signal runs to and from the device, should be as heavy as possible to
help conduct heat away from the package. Electrically insulating, thermally-
conductive "pads" may be installed underneath the package. Devices should
be soldered to boards rather than "socketed", and of course, minimal air flow
over the surface can greatly help reduce the package temperature.
All DATEL sampling A/D converters are fully characterized and specified over
operating temperature (case) ranges of 0 to +ꢁ0°C and –55 to +1±5°C. All
room-temperature (TA = +±5°C) production testing is performed without the
use of heat sinks or forced-air cooling. Thermal impedance figures for each
device are listed in their respective specification tables.
These devices do not normally require heat sinks, however, standard precau-
tionary design and layout procedures should be used to ensure devices do
Acquisition Time
75ns typ.
20ns typ.
INTERNAL S/H
125ns typ.
20ns typ.
50ns typ.
EOC
110ns typ.
150ns typ.
20ns typ.
50ns typ.
NOTES:
1. Scale is approximately 20ns per didsion.fs = 5MHz
2. This device has three pipeline delays. Four start convert pulses (clock cycles) must be applied for valid data from the
first conversion to appear at the output of the A/D.
Figure 3. ADS-935 Timing Diagram
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
01 Apr 2011 MDA_ADS-935.B02 Page 6 of 8
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
Preliminary Evaluation Board - Modified ADS-B933 to include 12V or 15V Supplies to U6
DATEL
•
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
•
Tel: (508) 339-3000
•
www.datel.com
•
e-mail: help@datel.com
01 Apr 2011 MDA_ADS-935.B02 Page ꢁ of 8
®
®
ADS-935
16-Bit, 5MHz Sampling A/D Converters
MECHANICAL DIMENSIONS - INCHES (mm)
ORDERING INFORMATION
MODEL
NUMBER
OPERATING
TEMP. RANGE
ACCESSORIES
ADS-935MC
ADS-935MM
0 to +ꢁ0°C
ADS-B935
HS-40
Evaluation Board (without ADS-935)
Heat Sink for all ADS-935 models
–55 to +1±5°C
Receptacles for PC board mounting can be ordered through AMP, Inc., Part # 3-331±ꢁ±-8 (Component
Lead Socket), 40 required. For MIL-STD-883 product, or surface mount packaging, contact DATEL.
DATEL
. makes no representation that the use of its products in the circuits described herein, or the use of other
technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not
imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change
without notice.
11 Cabot Boulevard, Mansfield, MA 02048-1151 USA
ITAR and ISO 9001/14001 REGISTERED
www.datel.com • e-mail: help@datel.com
01 Apr 2011 MDA_ADS-935.B02 Page 8 of 8
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