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MU9C2480BF-90TBC [MUSIC]

Content Addressable SRAM, 2KX64, 90ns, CMOS, PQFP64;
MU9C2480BF-90TBC
型号： MU9C2480BF-90TBC
厂家： MUSIC SEMICONDUCTORS    MUSIC SEMICONDUCTORS
描述：

Content Addressable SRAM, 2KX64, 90ns, CMOS, PQFP64

双倍数据速率 静态存储器 内存集成电路
文件： 总32页 (文件大小：236K)
中文：  中文翻译
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Data Sheet  
LANCAM B Family  
APPLICATION BENEFITS  
DISTINCTIVE CHARACTERISTICS  
•
Low-cost LANCAM family in a space-saving LQFP  
package  
•
•
High density CMOS Content Addressable Memory  
1K (1480B), 2K (2480B) , 4K (4480B), 8K (8480B)  
words  
•
Fast speed allows processing of both DA and SA  
within 450 ns, equivalent to 138 ports of 10 Base-T or  
13 ports of 100 Base-T Ethernet  
•
•
•
•
64-bit per word memory organization  
16-bit I/O  
•
•
•
•
Full CAM features allow all operations to be masked  
on a bit-by-bit basis  
Fast 50 ns compare speed  
Dual configuration register set for rapid context  
switching  
Powerful, LANCAM A/L compatible instruction set  
for any list processing need  
•
•
16-bit CAM/RAM segments with MUSIC’s patented  
partitioning  
Shiftable Comparand and Mask registers assist in  
proximate matching algorithms  
/MA and /MM output flags to enable faster system  
performance  
Cascadable to any practical length with no  
performance penalties  
•
•
Readable Device ID  
•
•
•
Industrial temperature grades for harsh environments  
Dual footprint connections to conserve board space  
3.3 Volt for lower power systems  
Selectable faster operating mode with no wait states  
after a no-match  
•
•
•
•
Validity bit setting accessible from the Status register  
Single cycle reset for Segment Control register  
3.3 Volt operation  
44- and 64-pin LQFP package  
(also available in Lead-Free package)  
DATA (64)  
MUX  
VCC  
GND  
DATA (16)  
DQ (15—0)  
(16)  
TRANSLATE  
802.3 / 802.5  
DEMUX  
DATA (64)  
DATA (16)  
DATA (16)  
COMPARAND  
SOURCE AND  
DESTINATION  
SEGMENT  
MASK 1  
MASK 2  
COMMANDS &  
STATUS (16)  
COUNTERS  
/E  
/W  
/MA  
/MM  
INSTRUCTION (W/O)  
ADDRESS  
CAM ARRAY  
N
CONTROL  
NEXT FREE ADDRESS (R/O)  
CONTROL  
2N WORDS  
X 64 BITS  
/CM  
2
/RESET  
SEGMENT CONTROL  
PAGE ADDRESS (LOCAL)  
DEVICE SELECT (GLOBAL)  
STATUS (15-0) (R/O)  
16  
MATCH ADDR &  
/MA FLAG  
/EC  
N+1  
2
/FF  
/FI  
/MM, /FL  
MATCH  
AND  
FLAG  
STATUS (31-16) (R/O)  
REGISTER SET  
/MF  
/MI  
LOGIC  
Figure 1: LANCAM B Family Block Diagram  
MUSIC Semiconductors, the MUSIC logo, and the phrase "MUSIC Semiconductors" are  
Registered trademarks of MUSIC Semiconductors. MUSIC is a trademark of  
MUSIC Semiconductors.  
February 27, 2008 Rev. 5.2  
LANCAM B Family  
General Description  
GENERAL DESCRIPTION  
The LANCAM consists of various depths of 64-bit  
Content Addressable Memories (CAMs), with a 16-bit  
wide interface.  
the database. The ability to search data words up to 64 bits  
wide allows large address spaces to be searched rapidly  
and efficiently. A patented architecture links each CAM  
entry to associated data and makes this data available for  
use after a successful compare operation.  
CAMs, also known as associative memories, operate in the  
converse way to random access memories (RAM). In  
RAM, the input to the device is an address and the output  
is the data stored at that address. In CAM, the input is a  
data sample and the output is a flag to indicate a match and  
the address of the matching data. As a result, CAM  
searches large databases for matching data in a short,  
constant time period, no matter how many entries are in  
The MUSIC LANCAMs are ideal for address filtering and  
translation applications in LAN switches and routers. The  
LANCAMs are also well suited to encryption, database  
accelerators, and image processing.  
OPERATIONAL OVERVIEW  
To use the LANCAM, the user loads the data into the  
Comparand register, which is automatically compared to  
all valid CAM locations. The device then indicates  
whether or not one or more of the valid CAM locations  
contains data that matches the target data. The status of  
each CAM location is determined by two validity bits at  
each memory location. The two bits are encoded to render  
four validity conditions: Valid, Empty, Skip, and RAM,  
shown in Status Register Bits on page 24 (bits 29:28). The  
memory can be partitioned into CAM and associated  
RAM segments on 16-bit boundaries, but by using one of  
the two available Mask registers, the CAM/RAM  
partitioning can be set at any arbitrary size between zero  
and 64 bits.  
data to the Control, Comparand, and Mask registers  
automatically triggers a compare. Compares also may be  
initiated by a command to the device. Associated RAM  
data is available immediately after a successful compare  
operation. The Status register reports the results of  
compares including all flags and addresses. Two Mask  
registers are available and can be used in two different  
ways: to mask comparisons or to mask data writes. The  
RAM validity type allows additional masks to be stored in  
the CAM array where they may be retrieved rapidly.  
A simple four-wire control interface and commands  
loaded into the Instruction decoder control the device. A  
powerful instruction set increases the control flexibility  
and minimizes software overhead. Additionally, dedicated  
pins for match and multiple-match flags enhance  
performance when the device is controlled by a state  
machine. These and other features make the LANCAM a  
powerful associative memory that drastically reduces  
search delays.  
The LANCAM’s internal data path is 64 bits wide for  
rapid internal comparison and data movement. Vertical  
cascading of additional LANCAMs in a daisy chain  
fashion extends the CAM memory depth for large  
databases. Cascading requires no external logic. Loading  
2
Rev. 5.2  
Pin Descriptions  
LANCAM B Family  
PIN DESCRIPTIONS  
Note: All signals are implemented in CMOS technology with TTL levels. Signal names that start with a slash (“/”) are active LOW.  
Inputs should never be left floating. The CAM architecture draws large currents during compare operations, mandating the use of good  
layout and bypassing techniques. Refer to the DC Electrical Characteristics on page 25 for more information.  
NC  
NC  
GND  
DQ4  
1
2
3
4
5
6
7
8
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
NC  
/MA  
/MI  
/MF  
GND  
GND  
/RESET  
VCC  
VCC  
TEST1  
/E  
GND  
DQ4  
1
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
/MA  
2
/MI  
DQ5  
DQ5  
3
/MF  
VCC  
VCC  
TEST2  
GND  
GND  
GND  
VCC  
VCC  
TEST2  
GND  
GND  
DQ6  
4
GND  
/RESET  
VCC  
VCC  
TEST1  
/E  
5
44-Pin LQFP  
(Top View)  
64-Pin LQFP  
(Top View)  
6
9
10  
11  
7
8
9
GND  
DQ6  
DQ7  
VCC  
NC  
12  
13  
14  
15  
16  
37  
36  
35  
34  
33  
/W  
DQ7  
VCC  
10  
11  
/W  
GND  
GND  
GND  
NC  
NC  
Figure 2: 44-Pin LQFP  
/E (Chip Enable, Input, TTL)  
Figure 3: 64-Pin LQFP  
The /E input enables the device while LOW. The falling  
edge registers the control signals /W, /CM, and /EC. The  
rising edge locks the daisy chain, turns off the DQ pins,  
and clocks the Destination and Source Segment counters.  
The four cycle types enabled by /E are shown in Table 1.  
The /EC signal also enables the /MF–/MI daisy chain,  
which serves to select the device with the highest-priority  
match in a string of LANCAMs. Table 4 explains the  
effect of the /EC signal on a device with or without a  
match in both Standard and Enhanced modes. /EC must be  
HIGH during initialization.  
Table 1: I/O Cycles  
DQ15–0 (Data Bus, I/O, TTL)  
/W  
/CM  
LOW  
HIGH  
LOW  
HIGH  
Cycle Type  
The DQ15–0 lines convey data, commands, and status to  
and from the LANCAM. /W and /CM control the direction  
and nature of the information that flows to or from the  
device. When /E is HIGH, DQ15–0 go to HIGH-Z.  
LOW  
LOW  
HIGH  
HIGH  
Command Write Cycle  
Data Write Cycle  
Command Read Cycle  
Data Read Cycle  
/MF (Match Flag, Output, TTL)  
/W (Write Enable, Input, TTL)  
The /MF output goes LOW when one or more valid  
matches occur during a compare cycle. /MF becomes valid  
after /E goes HIGH on the cycle that enables the daisy  
chain (on the first cycle that /EC is registered LOW by the  
previous falling edge of /E; see Figure 9 on page 14). In a  
daisy chain, valid match(es) in higher priority devices are  
passed from the /MI input to /MF. If the daisy chain is  
enabled but the match flag is disabled in the Control  
register, the /MF output only depends on the /MI input of  
the device (/MF=/MI). /MF is HIGH if there is no match  
or when the daisy chain is disabled (/E goes HIGH when  
/EC was HIGH on the previous falling edge of /E). The  
System Match flag is the /MF pin of the last device in the  
daisy chain. /MF is reset when the active configuration  
register set is changed.  
The /W input selects the direction of data flow during a  
device cycle. /W LOW selects a Write cycle and /W HIGH  
selects a Read cycle.  
/CM (Data/Command Select, Input, TTL)  
The /CM input selects whether the input signals on  
DQ15–0 are data or commands. /CM LOW selects  
Command cycles and /CM HIGH selects Data cycles.  
/EC (Enable Daisy Chain, Input, TTL)  
The /EC signal performs two functions. The /EC input  
enables the /MF output to show the results of a  
comparison, as shown in Figure 9 on page 14. If /EC is  
LOW at the falling edge of /E in a given cycle, the /MF  
output is enabled. Otherwise, the /MF output is held  
HIGH.  
Rev. 5.1  
3
LANCAM B Family  
Pin Descriptions  
/MI (Match Input, Input, TTL)  
/FI (Full Input, Input, TTL)  
The /MI input prioritizes devices in vertically cascaded  
systems. It is connected to the /MF output of the previous  
device in the daisy chain. The /MI pin on the first device in  
the chain must be tied HIGH.  
The /FI input generates a CAM-Memory-System-Full  
indication in vertically cascaded systems. It is connected  
to the /FF output of the previous device in the daisy chain.  
The /FI pin on the first device in a chain must be tied  
LOW.  
/MA (Device Match Flag, Output, TTL)  
/RESET (Reset, Input, TTL)  
The /MA output is LOW when one or more valid matches  
occur during the current or the last previous compare  
cycle. The /MA output is not qualified by /EC or /MI, and  
reflects the match flag from that specific device’s Status  
register. /MA is reset when the active register set is  
changed.  
/RESET must be driven LOW to place the device in a  
known state before operation, which resets the device to  
the conditions shown in Table 3 on page 11. The /RESET  
pin should be driven by TTL levels, not directly by an RC  
timeout. /E must be kept HIGH during /RESET.  
/MM (Device Multiple Match Flag, Output, TTL)  
The /MM output is LOW when more than one valid match  
occurs during the current or the last previous compare  
cycle. The /MM output is not qualified by /EC or /MI, and  
reflects the multiple match flag from that specific device’s  
Status register. /MM is reset when the active register set is  
changed.  
TEST1, TEST2 (Test, Input, TTL)  
These pins enable MUSIC production test modes that are  
not usable in an application. They should be connected to  
ground, either directly or through a pull-down resistor, or  
they may be left unconnected. These pins may not be  
implemented on all versions of these products.  
VCC, GND (Positive Power Supply, Ground)  
/FF (Full Flag, Output, TTL)  
These pins are the power supply connections to the  
LANCAM. VCC must meet the voltage supply  
requirements in the Operating Conditions section relative  
to the GND pins, which are at 0 volts (system reference  
potential), for correct operation of the device. All the  
ground and power pins must be connected to their  
respective planes with adequate bulk and high frequency  
bypassing capacitors in close proximity to the device.  
If enabled in the Control register, the /FF output goes  
LOW when no empty memory locations exist within the  
device (and in the daisy chain above the device as  
indicated by the /FI pin). The System Full flag is the /FF  
pin of the last device in the daisy chain, and the Next Free  
address resides in the device with /FI LOW and /FF  
HIGH. If disabled in the Control register, the /FF output  
only depends on the /FI input (/FF = /FI).  
4
Rev. 5.2  
Functional Description  
LANCAM B Family  
FUNCTIONAL DESCRIPTION  
The LANCAM is a Content Addressable Memory (CAM)  
with 16-bit I/O for network address filtering and  
translation, virtual memory, data compression, caching,  
and table lookup applications. The memory consists of  
static CAM, organized in 64-bit data fields. Each data field  
can be partitioned into a CAM and a RAM subfield on  
16-bit boundaries. The contents of the memory can be  
randomly accessed or associatively accessed by the use of  
a compare. During automatic comparison cycles, data in  
the Comparand register is automatically compared with  
the “Valid” entries in the memory array. The Device ID  
can be read using a TCO PS instruction (see Persistent  
Source Register Bits on page 24).  
Data Movement (Read/Write)  
Data can be moved from one of the data registers (CR,  
MR1, or MR2) to a memory location that is based on the  
results of the last comparison (Highest-Priority Match or  
Next Free), or to an absolute address, or to the location  
pointed to by the active Address register. Data can also be  
written directly to the memory from the DQ bus using any  
of the above addressing modes. The Address register may  
be directly loaded and may be set to increment or  
decrement, allowing DMA-type reading or writing from  
memory.  
Configuration Register Sets  
Two sets of configuration registers (Control, Segment  
Control, Address, Mask Register 1, and Persistent Source  
and Destination) are provided to permit rapid context  
switching between foreground and background activities.  
The currently active set of configuration registers controls  
writes, reads, moves, and compares. The foreground set  
typically would be pre-loaded with values useful for  
comparing input data, often called filtering, while the  
background set would be pre-loaded with values useful for  
housekeeping activities such as purging old entries.  
Moving from the foreground task of filtering to the  
background task of purging can be done by issuing a  
single instruction to change the current set of  
configuration registers. The match condition of the device  
is reset whenever the active register set is changed.  
Data Input and Output Characteristics  
The data inputs and outputs of the LANCAM are  
multiplexed for data and instructions over a 16-bit I/O bus.  
Internally, data is handled on a 64-bit basis, since the  
Comparand register, the Mask registers, and each memory  
entry are 64 bits wide. Memory entries are globally  
configurable into CAM and RAM segments on 16-bit  
boundaries, as described in US Patent 5,383,146 assigned  
to MUSIC Semiconductors. Seven different CAM/RAM  
splits are possible, with the CAM width going from one to  
four segments, and the remaining RAM width going from  
three to zero segments. Finer resolution on compare width  
is possible by invoking a Mask register during a compare,  
which allows global masking on a bit basis. The CAM  
subfield contains the associative data, which enters into  
compares, while the RAM subfield contains the associated  
data, which is not compared. In LAN bridges, the RAM  
subfield could hold, for example, port-address and aging  
information related to the destination or source address  
information held in the CAM subfield of a given location.  
In a translation application, the CAM field could hold the  
dictionary entries, while the RAM field holds the  
translations, with almost instantaneous response.  
Control Register  
The active Control register determines the operating  
conditions within the device. Conditions set by this  
register’s contents are reset, enable or disable Match flag,  
enable or disable Full flag, CAM/RAM partitioning,  
disable or select masking conditions, disable or select  
auto-incrementing or auto-decrementing the Address  
register, and select Standard or Enhanced mode. The  
active Segment Control register contains separate counters  
to control the writing of 16-bit data segments to the  
selected persistent destination, and to control the reading  
of 16-bit data segments from the selected persistent  
source.  
Validity Bits  
Each entry has two validity bits associated with it to define  
its particular type: Empty, Valid, Skip, or RAM. When  
data is written to the active Comparand register, and the  
active Segment Control register reaches its terminal count,  
the contents of the Comparand register are automatically  
compared with the CAM portion of all the valid entries in  
the memory array. For added versatility, the Comparand  
register can be barrel-shifted right or left one bit at a time.  
A Compare instruction then can be used to force another  
compare between the Comparand register and the CAM  
portion of memory entries of any one of the four validity  
types. After a Read or Move from Memory operation, the  
validity bits of the location read or moved are copied into  
the Status register, where they can be read using  
Command Read cycles.  
Mask Registers  
There are two active Mask registers at any one time, which  
can be selected to mask comparisons or data writes. Mask  
Register 1 has both a foreground and background mode to  
support rapid context switching. Mask Register 2 does not  
have this mode, but can be shifted left or right one bit at a  
time. For masking comparisons, data stored in the active  
selected Mask register determines which bits of the  
comparand are compared against the valid contents of the  
memory. If a bit is set HIGH in the Mask register, the same  
bit position in the Comparand register becomes a “don’t  
Rev. 5.1  
5
LANCAM B Family  
Functional Description  
care” for the purpose of the comparison with all the  
memory locations. During a Data Write cycle or a MOV  
instruction, data in the specified active Mask register can  
also determine which bits in the destination are updated. If  
a bit is HIGH in the Mask register, the corresponding bit of  
the destination is unchanged.  
having the Highest-Priority match or the Next Free  
address responds.  
Cascading LANCAMs  
A Page Address register in each device simplifies vertical  
expansion in systems using more than one LANCAM.  
This register is loaded with a specific device address  
during system initialization, which then serves as the  
higher-order address bits. A Device Select register allows  
the user to target a specific device within a vertically  
cascaded system by setting it equal to the Page Address  
Register value, or to address all the devices in a string at  
the same time by setting the Device Select value to  
FFFFH.  
Highest Priority/Multiple Match  
The match line associated with each memory address is  
fed into a priority encoder where multiple responses are  
resolved, and the address of the highest-priority responder  
(the lowest numerical match address) is generated. In  
LAN applications, a multiple response might indicate an  
error. In other applications the existence of multiple  
responders may be valid.  
Figure 4 shows expansion using a daisy chain. Note that  
system flags are generated without the need for external  
logic. The Page Address register allows each device in the  
vertically cascaded chain to supply its own address in the  
event of a match, eliminating the need for an external  
priority encoder to calculate the complete Match address  
at the expense of the ripple-through time to resolve the  
Highest-Priority match. The Full flag daisy-chaining  
allows Associative writes using a Move to Next Free  
Address instruction, which does not need a supplied  
address.  
Input Control Signals and Commands  
Four input control signals and commands loaded into an  
instruction decoder control the LANCAM. Two of the four  
input control signals determine the cycle type. The control  
signals tell the device whether the data on the I/O bus  
represents data or a command, and is input or output.  
Commands are decoded by instruction logic and control  
moves, forced compares, validity bit manipulations, and  
the data path within the device. Registers (Control,  
Segment Control, Address, Next Free Address, etc.) are  
accessed using Temporary Command Override  
instructions. The data path from the DQ bus to/from data  
resources (comparand, masks, and memory) within the  
device are set until changed by Select Persistent Source  
and Destination instructions.  
Figure 5 shows an external PLD implementation of a  
simple priority encoder that eliminates the daisy chain  
ripple-through delays for systems requiring maximum  
performance from many CAMs.  
After a Compare cycle (caused by either a data write to the  
Comparand or Mask registers, a write to the Control  
register, or a forced compare), the Status register contains  
the address of the Highest-Priority Matching location in  
that device, concatenated with its page address, along with  
flags indicating internal match, multiple match, and full.  
When the Status register is read with a Command Read  
cycle, the device with the Highest-Priority Match  
responds, outputting the System Match address to the DQ  
bus. The internal Match (/MA) and Multiple Match (/MM)  
flags are also output on pins. Another set of flags (/MF and  
/FF) that are qualified by the match and full flags of  
previous devices in the system also are available directly  
on output pins, and are independently daisy-chained to  
provide System Match and Full flags in vertically  
cascaded LANCAM arrays. In such arrays, if no match  
occurs during a comparison, read access to the memory  
and all the registers except the Next Free register is denied  
to prevent device contention. In a daisy chain, all devices  
respond to Command and Data Write cycles, depending on  
the conditions shown in Table 4 unless the operation  
involves the Highest-Priority Match address or the Next  
Free address; in which case, only the specific device  
6
Rev. 5.2  
Functional Description  
LANCAM B Family  
Vcc  
16  
DQ15–0  
/E  
/MI  
/FI  
DQ15–0  
/E  
/W  
/W  
LANCAM  
/FF  
/MF  
/CM  
/EC  
/CM  
/EC  
DQ15–0  
/E  
/MI  
/FI  
/W  
LANCAM  
/FF  
/MF  
/CM  
/EC  
DQ15–0  
/MI  
/FI  
/E  
/W  
LANCAM  
/FF  
/MF  
SYSTEM FULL  
/CM  
/EC  
SYSTEM MATCH  
Figure 4: Vertical Cascading  
Vcc  
/MI  
PLD  
LANCAM  
/MA  
/MI  
LANCAM  
/MA  
/MI  
LANCAM  
/MA  
/MI  
LANCAM  
/MA  
SYSTEM  
MATCH  
Figure 5: External Prioritizing  
Rev. 5.1  
7
LANCAM B Family  
Operational Characteristics  
OPERATIONAL CHARACTERISTICS  
Note: Throughout the following, “aaaH” represents a three-digit hexadecimal number “aaa,” while “bbB” represents a two-digit  
binary number “bb.” All memory locations are written to or read from in 16-bit segments. Segment 0 corresponds to the lowest order  
bits (bits 15–0) and Segment 3 corresponds to the highest order bits (bits 63–48).  
Control Bus  
The Register Set  
Refer to Figure 1 on page 1 for the following discussion.  
The inputs Chip Enable (/E), Write Enable (/W),  
Command Enable (/CM), and Enable Daisy Chain (/EC)  
are the primary control mechanism for the LANCAM. The  
/EC input of the Control bus enables the /MF Match flag  
output when LOW and controls the daisy chain operation.  
Instructions are the secondary control mechanism. Logical  
combinations of the Control Bus inputs, coupled with the  
execution of Select Persistent Source (SPS), Select  
Persistent Destination (SPD), and Temporary Command  
Override (TCO) instructions allow the I/O operations to  
and from the DQ15–0 lines to the internal resources, as  
shown in Table 2.  
The Control, Segment Control, Address, Mask Register 1,  
and the Persistent Source and Destination registers are  
duplicated, with one set termed the Foreground set and the  
other the Background set. The active set is chosen by  
issuing Select Foreground Registers or Select Background  
Registers instructions. By default, the Foreground set is  
active after a reset. Having two alternate sets of registers  
that determine the device configuration allows for a rapid  
return to a foreground network filtering task from a  
background housekeeping task.  
Writing a value to the Control register or writing data to  
the last segment of the Comparand or either Mask register  
causes an automatic comparison to occur between the  
contents of the Comparand register and the words in the  
CAM segments of the memory marked valid, masked by  
MR1 or MR2 if selected in the Control register.  
The Comparand register is the default source and  
destination for Data Read and Write cycles. This default  
state can be overridden independently by executing a  
Select Persistent Source or Select Persistent Destination  
instruction, selecting a different source or destination for  
data. Subsequent Data Read or Data Write cycles access  
that source or destination until another SPS or SPD  
instruction is executed. The currently selected persistent  
source or destination can be read back through a TCO PS  
or PD instruction. The sources and destinations available  
for persistent access are those resources on the 64-bit bus:  
Comparand register, Mask Register 1, Mask Register 2,  
and the Memory array.  
Instruction Decoder  
The Instruction decoder is the write-only decode logic for  
instructions and is the default destination for Command  
Write cycles. If an instruction’s Address Field flag (bit 11)  
is set to a 1, it is a two-cycle instruction that is not  
executed immediately. For the next cycle only, the data  
from a Command Write cycle is loaded into the Address  
register and the instruction then completes at that address.  
The Address register then increments, decrements, or stays  
at the same value depending on the setting of Control  
Register bits CT3 and CT2. If the Address Field flag is not  
set, the memory access occurs at the address currently  
contained in the Address register.  
The default destination for Command Write cycles is the  
Instruction decoder, while the default source for  
Command Read cycles is the Status register.  
Temporary Command Override (TCO) instructions  
provide access to the Control register, the Page Address  
register, the Segment Control register, the Address  
register, the Next Free Address register, and Device Select  
register. TCO instructions are active only for one  
Command Read or Write cycle after being loaded into the  
Instruction decoder.  
Control Register (CT)  
The Control register contains a number of switches that  
configure the LANCAM, as shown in Control Register  
Bits on page 23. It is written or read using a TCO CT  
instruction. If bit 15 of the value written during a TCO CT  
is a 0, the device is reset (and all other bits are ignored).  
See Table 3 on page 11 for the Reset states. Bit 15 always  
reads back as a 0. A write to the Control register causes an  
automatic compare to occur (except in the case of a reset).  
Either the Foreground or Background Control register is  
active, depending on which register set has been selected,  
and only the active Control register is written to or read  
from.  
The data and control interfaces to the LANCAM are  
synchronous. During a Write cycle, the Control and Data  
inputs are registered by the falling edge of /E. When  
writing to the persistently selected data destination, the  
Destination Segment counter is clocked by the rising edge  
of /E. During a Read cycle, the Control inputs are  
registered by the falling edge of /E, and the Data outputs  
are enabled while /E is LOW. When reading from the  
persistently selected data source, the Source Segment  
counter is clocked by the rising edge of /E.  
If the Match Flag is disabled through bit 14 and bit 13, the  
internal match condition, /MA(int), used to determine a  
daisy-chained device’s response is forced HIGH as shown  
in Table 4 so that Case 6 is not possible, effectively  
8
Rev. 5.2  
Operational Characteristics  
LANCAM B Family  
removing the device from the daisy chain. With the Match  
Flag disabled, /MF=/MI and operations directed to  
Highest-Priority Match locations are ignored. Normal  
operation of the device is with the /MF enabled. The  
Match Flag Enable field has no effect on the /MA or /MM  
output pins or Status Register bits. These bits always  
reflect the true state of the device.  
Segment Control Register (SC)  
The Segment Control register, as shown in Segment  
Control Register Bits on page 23, is accessed using a TCO  
SC instruction. On read cycles, D15, D10, D5, and D2  
always read back as 0s. Either the Foreground or  
Background Segment Control register is active, depending  
on which register set is selected, and only the active  
Segment Control register is written to or read from.  
If the Full Flag is disabled through bit 12 and bit 11, the  
device behaves as if it is full and ignores instructions to  
Next Free address. Also, writes to the Page Address  
register are disabled. All other instructions operate  
normally. Additionally, with the /FF disabled, /FF=/FI.  
Normal operation of the device is with the /FF enabled.  
The Full Flag Enable field has no effect on the /FL Status  
Register bit. This bit always reflects the true state of the  
device.  
The Segment Control register contains dual independent  
incrementing counters with limits, one for data reads and  
one for data writes. These counters control which 16-bit  
segment of the 64-bit internal resource is accessed during  
a particular data cycle on the 16-bit data bus. The actual  
destination for data writes and source for data reads (called  
the persistent destination and source) are set independently  
with SPD and SPS instructions, respectively.  
The IEEE Translation control at bit 10 and bit 9 can be  
used to enable the translation hardware for writes to 64-bit  
resources in the device. When translation is enabled, the  
bits are reordered as shown in Figure 6.  
Each of the two counters consists of a start limit, an end  
limit, and the current count value that points to the  
segment to be accessed on the next data cycle. The current  
count value can be set to any segment, even if it is outside  
the range set by the start and end limits. The counters  
count up from the current count value to the end limit and  
then jump back to the start limit. If the current count is  
greater than the end limit, the current count value  
increments to three, rolls over to zero, continues  
incrementing until the end limit is reached, and then jumps  
back to the start limit.  
DQ15  
DQ8 DQ7  
DQ0  
If a sequence of data writes or reads is interrupted, the  
Segment Control register can be reset to its initial start  
limit values by using an RSC instruction. After the  
LANCAM is reset, both Source and Destination counters  
are set to count from Segment 0 to Segment 3 with an  
initial value of 0.  
DQ15  
DQ8 DQ7  
DQ0  
Figure 6: IEEE 802.3/802.5 Format Mapping  
Control Register bits 8–6 control the CAM/RAM  
partitioning. The CAM portion of each word may be sized  
from a full 64 bits down to 16 bits in 16-bit increments.  
The RAM portion can be at either end of the 64-bit word.  
Compare masks may be selected by bit 5 and bit 4. Mask  
Register 1, Mask Register 2, or neither may be selected to  
mask compare operations. The address register behavior is  
controlled by bit 3 and bit 2, and may be set to increment,  
decrement, or neither after a memory access. Bit 1 and bit  
0 set the operating mode: Standard or Enhanced as shown  
in Table 4 on page 12. The device resets to the Standard  
mode, and follows the operating responses of the original  
MU9C1480 in Table 4. When operating in Enhanced  
mode, it is not necessary to unlock the daisy chain with a  
NOP instruction before command or data writes after a  
non-matching compare, as required in Standard mode.  
Rev. 5.1  
9
LANCAM B Family  
Operational Characteristics  
Table 2: Input/Output Operations  
Cycle Type  
/E /C  
M
/
W
I/O Status SPS SPD TC Operation  
O
Notes  
Cmd Write  
L
L
L
IN  
IN  
IN  
IN  
IN  
IN  
IN  
Load Instruction decoder  
1
2,3  
3
3
3
3
3
3
3
3
Load Address register  
Load Control register  
Load Page Address register  
Load Segment Control register  
Load Device Select register  
Deselected  
3
10  
Cmd Read  
L
L
H
OUT  
OUT  
3
3
Read Next Free Address register  
Read Address register  
3
3
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
OUT  
HIGH-Z  
Read Status Register bits 15–0  
Read Status Register bits 31–16  
Read Control register  
Read Page Address register  
Read Segment Control register  
Read Device Select register  
Read Current Persistent Source or Destination  
Deselected  
4
5
3
3
3
3
3,11  
10  
3
3
3
3
3
Data Write  
L
H
L
IN  
IN  
IN  
IN  
IN  
IN  
IN  
3
3
3
3
3
3
Load Comparand register  
Load Mask Register 1  
Load Mask Register 2  
Write Memory Array at address  
Write Memory Array at Next Free address  
Write Memory Array at Highest-Priority match  
Deselected  
6,9  
7,9  
7,9  
7,9  
7,9  
7,9  
10  
Data Read  
L
H
X
H
X
OUT  
OUT  
OUT  
OUT  
OUT  
3
3
3
3
3
Read Comparand register  
Read Mask Register 1  
Read Mask Register 2  
Read Memory Array at address  
Read Memory Array at Highest-Priority match  
Deselected  
6, 9  
8, 9  
8, 9  
8, 9  
7, 8  
10  
HIGH-Z  
H
HIGH-Z  
Deselected  
Notes:  
1.  
2.  
Default Command Write cycle destination (does not require a TCO instruction).  
Default Command Write cycle destination (no TCO instruction required) if Address Field flag was set in bit 11 of the instruction loaded in the  
previous cycle.  
3.  
Loaded or read on the Command Write or Read cycle immediately following a TCO instruction. Active for one Command Write or Read cycle only.  
NFA register can not be loaded this way.  
4.  
5.  
Default Command Read cycle source (does not require a TCO instruction).  
Default Command Read cycle source (does not require a TCO instruction) if the previous cycle was a Command Read of Status Register Bits 15–0.  
If next cycle is not a Command Read cycle, any subsequent Command Read cycle accesses the Status Register Bits 15–0.  
Default persistent source and destination on power-up and after Reset. If other resources were sources or destinations, SPD CR or SPS CR restores  
the Comparand register as the destination or source.  
6.  
7.  
8.  
9.  
Selected by executing a Select Persistent Destination instruction.  
Selected by executing a Select Persistent Source instruction.  
Access may require multiple 16-bit Read or Write cycles. The Segment Control register controls the selection of the desired 16-bit segment(s) by  
establishing the Segment counters’ start and end limits and count values.  
10. Device is deselected if Device Select register setting does not equal Page Address register setting, unless the Device Select Register is set to  
FFFFH, which allows only write access to the device. (Writes to the Device Select register are always active.) Device may also be deselected under  
locked daisy chain conditions as shown in Table 4.  
11. A Command Read cycle after a TCO PS or TCO PD reads back the Instruction decoder bits that were last set to select a persistent source or  
destination. The TCO PS instruction also reads back the Device ID.  
10  
Rev. 5.2  
Operational Characteristics  
LANCAM B Family  
Table 3: Device Control State After Reset  
CAM Status  
/RESET Condition  
Validity bits at all memory locations  
Match and Full Flag outputs  
Skip = 0, Empty = 1 (empty)  
Enabled  
IEEE 802.3–802.5 Input Translation  
CAM/RAM Partitioning  
Comparison Masking  
Not translated  
64 bits CAM, 0 bits RAM  
Disabled  
Address register auto-increment or auto-decrement  
Source and Destination Segment counters count ranges  
Address register and Next Free Address register  
Page Address and Device Select registers  
Control register after reset (including CT15)  
Persistent Destination for Command writes  
Persistent Source for Command reads  
Persistent Source and Destination for Data reads and writes  
Operating Mode  
Disabled  
00B to 11B; loaded with 00B  
Contain all 0s  
Contain all 0s (no change on software reset)  
Contains 0008H  
Instruction decoder  
Status register  
Comparand register  
Standard  
Configuration Register set  
Foreground  
Page Address Register (PA)  
The Page Address register is loaded using a TCO PA  
instruction followed by a Command Write cycle of a user  
selected 16-bit value (not FFFFH). The entry in the PA  
register gives a unique address to the different devices in a  
daisy chain. In a daisy chain, the PA value of each device  
is loaded using the SFF instruction to advance to the next  
device, shown in the Setting Page Address Register Values  
on page 16. A software reset (using the Control register)  
does not affect the Page Address register.  
Control Register bits CT3 and CT2 set the Address  
register to automatically increment or decrement (or not  
change) during sequences of Command or Data cycles.  
The Address register changes after executing an  
instruction that includes M@[AR] or M@aaaH, or after a  
data access to the end limit segment (as set in the Segment  
Control register) when the persistent source or destination  
is M@[AR] or M@aaaH.  
Either the Foreground or Background Address register is  
active, depending on which register set is selected, and  
only the active Address register is written to or read from.  
Device Select Register (DS)  
The Device Select register selects a specific (target)  
device. The TCO DS instruction sets the 16-bit DS register  
to the value of the following Command Write cycle. The  
DS register can be read. A device is selected when its DS  
is equal to its PA value. In a daisy chain, setting DS =  
FFFFH selects all devices. However, in this case, the  
ability to read information out of the device is restricted as  
shown in Table 4. A software reset (using the Control  
register) does not affect the Device Select register.  
Next Free Address Register (NF)  
The LANCAM automatically stores the address of the first  
empty memory location in the Next Free Address register,  
which is then used as a memory address pointer for  
M@NF operations. The Next Free Address register,  
shown in Next Free Address Bits on page 24, can be read  
using a TCO NF instruction. By taking /EC LOW during  
the TCO NF instruction cycle, only the device with /FI  
LOW and /FF HIGH outputs the contents of its Next Free  
Address register, giving the Next Free address in a system  
of daisy-chained devices. The Next Free address may be  
read from a specific device in the chain by setting the  
Device Select register to the value of the desired device’s  
Page address and leaving /EC HIGH. The Full Flag daisy  
chain causes only the device whose /FI input is LOW and  
/FF output HIGH to respond to an instruction using the  
Next Free address. After a reset, the Next Free Address  
register is set to zero.  
Address Register (AR)  
The Address register points to the CAM memory location  
to be operated upon when M@[AR] or M@aaaH is part of  
the instruction. It can be loaded directly by using a TCO  
AR instruction or indirectly by using an instruction  
requiring an absolute address, such as MOV aaaH,CR,V.  
After being loaded, the Address register value is the next  
memory access referencing the Address register. A reset  
sets the Address register to zero.  
Rev. 5.1  
11  
LANCAM B Family  
Operational Characteristics  
Table 4: Standard and Enhanced Mode Device Select Response  
Standard Mode  
Case  
Internal  
/EC(int)  
Internal  
/MA(int)  
External  
/MI  
Device Select  
Register  
Command  
Write1  
Data  
Write  
Command  
Read  
Data  
Read  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH  
DS = PA  
NO  
YES  
NO  
NO  
YES  
NO  
DS ≠ FFFFH and  
DS ≠ PA  
NO5  
NO5  
YES5  
4
5
0
0
0
X
1
0
1
1
X
NO  
NO  
NO  
NO  
NO  
NO  
X
62  
YES3  
YES4  
0
X
YES  
Enhanced Mode  
Case  
Internal  
/EC(int)  
Internal  
/MA(int)  
External  
/MI  
Device Select  
Register  
Command  
Write1  
Data  
Write  
Command  
Read  
Data  
Read  
YES3  
YES3  
NO  
YES4  
YES4  
NO  
1
2
3
1
1
1
X
X
X
X
X
X
DS = FFFFH  
DS = PA  
NO  
YES  
NO  
NO  
YES  
NO  
DS ≠ FFFFH and  
DS ≠ PA  
YES3,6  
YES3,6  
YES3  
YES3,7  
YES3,7  
YES4  
NO5  
NO5  
YES5  
4
5
0
0
0
0
1
0
0
X
1
X
X
X
NO  
NO  
62  
YES  
Notes:  
1.  
Exceptions are:  
A) A write to the Device Select register is always active in all devices;  
B) A write to the Page Address register is active in the device with /FI LOW and /FF HIGH; and  
C) The Set Full Flag (SFF) instruction is active in the device with /FI LOW and /FF HIGH.  
If /MF is disabled in the Control register, Internal /MA is forced HIGH preventing a Case 6 response.  
2.  
3.  
4.  
5.  
This is NO for a MOV instruction involving Memory at Next Free address if /FI is HIGH or the device is full.  
This is NO if the Persistent Destination is Memory at Next Free address and /FI is HIGH or the device is full.  
For a Command read following a TCO NF instruction, this is YES if the device contains the first empty location in a daisy chain (i.e., /FI LOW and  
/FF HIGH) and NO if it does not.  
6.  
7.  
This is NO for a MOV or VBC instruction involving Memory at Highest-Priority match.  
This is NO if the Persistent Destination is Memory at Highest-Priority match.  
Status Register  
Comparand Register (CR)  
The 32-bit Status register, shown in Status Register Bits on  
page 24, is the default source for Command Read cycles.  
Bit 31 (internal Full flag) goes LOW if the particular  
device has no empty memory locations. Bit 30 is the  
internal Multiple Match flag, which goes LOW if a  
Multiple match was detected. Bit 29 and Bit 28 are the  
Validity bits, which reflect the validity of the last memory  
location read. After a reset, the Validity bits read 11 until a  
read or move from memory has occurred. The rest of the  
Status register down to bit 1 contains the Page address of  
the device and the address of the Highest-Priority match.  
After a reset or a no-match condition, the match address  
bits are all 1s. Bit 0 is the internal Match flag, which goes  
LOW if a match was found in this particular device.  
The 64-bit Comparand register is the default destination  
for data writes and reads, using the Segment Control  
register to select which 16-bit segment of the Comparand  
register is to be loaded or read out. The persistent source  
and destination for data writes and reads can be changed to  
the Mask registers or memory by SPS and SPD  
instructions. During an automatic or forced compare, the  
Comparand register is simultaneously compared against  
the CAM portion of all memory locations with the correct  
validity condition. Automatic compares always compare  
against valid memory locations, while forced compares,  
using CMP instructions, can compare against memory  
locations tagged with any specific validity condition.  
The Comparand register may be shifted one bit at a time to  
the right or left by issuing a Shift Right or Shift Left  
instruction, with the right and left limits for the  
wrap-around determined by the CAM/RAM partitioning  
12  
Rev. 5.2  
Operational Characteristics  
LANCAM B Family  
set in the Control register. During shift rights, bits shifted  
off the LSB of the CAM partition reappear at the MSB of  
the CAM partition. Likewise, bits shifted off the MSB of  
the CAM partition reappear at the LSB during shift lefts.  
The Memory Array  
Memory Organization  
The Memory array is organized into 64-bit words with  
each word having an additional two validity bits. By  
default, all words are configured to be 64 CAM cells.  
However, bits 8–6 of the Control register can divide each  
word into a CAM field and a RAM field. The RAM field  
can be assigned to the least-significant or most-significant  
portion of each entry.  
Mask Registers (MR1, MR2)  
The Mask registers can be used in two different ways:  
either to mask compares or to mask data writes and moves.  
Either Mask register can be selected in the Control register  
to mask every compare, or selected by instructions to  
participate in data writes or moves to and from Memory. If  
a bit in the selected Mask register is set to a 0, the  
corresponding bit in the Comparand register enters into a  
masked compare operation. If a Mask bit is a 1, the  
corresponding bit in the Comparand register does not enter  
into a masked compare operation. Bits set to 0 in the Mask  
register cause corresponding bits in the destination register  
or memory location to be updated when masking data  
writes or moves, while a bit set to 1 prevents that bit in the  
destination from being changed.  
The CAM/RAM partitioning is allowed on 16-bit  
boundaries, permitting selection of the configuration  
shown in Control Register Bits on page 23, bits 8–6 (e.g.,  
“001” sets the 48 MSBs to CAM and the 16 LSBs to  
RAM). Memory Array bits designated as RAM can be  
used to store and retrieve data associated with the CAM  
content at the same memory location.  
Memory Access  
There are two general ways to get data into and out of the  
Memory array: directly or by moving the data by means of  
the Comparand or Mask registers.  
Either the Foreground or Background MR1 can be set  
active, but after a reset, the Foreground MR1 is active by  
default. MR2 incorporates a sliding mask, where the data  
can be replicated one bit at a time to the right or left with  
no wrap-around by issuing a Shift Right or Shift Left  
instruction. The right and left limits are determined by the  
CAM/RAM partitioning set in the Control register. For a  
Shift Right the upper limit bit is replicated to the next  
lower bit, while for a Shift Left the lower limit bit is  
replicated to the next higher bit.  
The first way, through direct reads or writes, is set up by  
issuing a Set Persistent Destination (SPD) or Set Persistent  
Source (SPS) command. The addresses for the direct  
access can be supplied directly; supplied from the Address  
register, supplied from the Next Free Address register, or  
supplied as the Highest-Priority Match address.  
Additionally, all the direct writes can be masked by either  
Mask register.  
The second way is to move data by means of the  
Comparand or Mask registers. This is accomplished by  
issuing Data Move commands (MOV). Moves using the  
Comparand register can also be masked by either of the  
Mask registers.  
/E  
/W  
/CM  
/EC  
DQ15-0  
DATA OUT  
Figure 7: Read Cycle  
Rev. 5.1  
13  
LANCAM B Family  
Operational Characteristics  
/E  
/W  
/CM  
/EC  
DQ15–0  
Figure 8: Write Cycle  
ASSOCIATED DATA  
READ CYCLE  
COMPARAND WRITE  
CYCLE  
STATUS READ  
CYCLE  
/E  
/CM  
/W  
DQ15–0  
DATA  
DATA  
DATA  
/EC  
/MF  
MATCH FLAG VALID  
/MA, /MM  
/MA AND /MM FLAGS UPDATED  
Figure 9: Cycle-to-Cycle Timing Example  
I/O Cycles  
The LANCAM supports four basic I/O cycles: Data Read,  
Data Write, Command Read, and Command Write. The  
states of the /W and /CM control inputs determine the type  
of cycle. These signals are registered at the beginning of a  
cycle by the falling edge of /E. Table 1 on page 3 shows  
how the /W and /CM signals select the cycle type.  
cycle prior to any cycle that requires a locked daisy chain,  
such as a Status register or associated data read after a  
match. If there is no match in Standard mode, the output  
buffers stay High-Z, and the daisy chain must be unlocked  
by taking /EC HIGH during  
a NOP or other  
non-functioning cycle, as indicated in Table 4 on page 12.  
Figure 9 on page 14 shows how the internal /EC timing  
holds the daisy chain locking effect over into the next  
cycle. In Enhanced mode, this NOP is not needed before  
data or command writes following a non-matching  
compare, as indicated by Table 4 on page 12. A  
single-chip system does not require daisy-chained match  
flag operation, hence /EC could be tied HIGH and the  
/MA pin or flag in the Status register used instead of /MF,  
allowing access to the device regardless of the match  
condition.  
During Read cycles, the DQ15–0 outputs are enabled after  
/E goes LOW. During Write cycles, the data or command  
to be written is captured from DQ15–0 at the beginning of  
the cycle by the falling edge of /E. Figure 10 on page 15  
and Figure 7 on page 13, show Read and Write cycles  
respectively. Figure 8 on page 14, shows typical  
cycle-to-cycle timing with the Match flag valid at the end  
of the Comparand Write. Data writes and reads to the  
comparand, Mask registers, or memory occur in one to  
four 16-bit cycles, depending on the settings in the  
Segment Control register. The Compare operation  
automatically occurs during Data writes to the Comparand  
or Mask registers when the destination segment counter  
reaches the end count set in the Segment Control register.  
If there was a match, the second cycle reads status or  
associated data, depending on the state of /CM. For  
cascaded devices, /EC needs to be LOW at the start of the  
The minimum timings for the /E control signal are given  
in Table 9 on page 27. Note that at minimum timings the  
/E signal is non-symmetrical and that different cycle types  
have different timing requirements, as given in Table 6 on  
page 22.  
14  
Rev. 5.2  
Operational Characteristics  
LANCAM B Family  
Compare Operations  
second, to provide a system wide match flag; third, to lock  
out all devices except the one with the Highest-Priority  
match for instructions such as Status reads after a match.  
The Match flag logic causes only the highest-priority  
device to operate on its Highest-Priority Match location  
while devices with lower-priority matches ignore  
Highest-Priority Match operations. The lock-out feature is  
enabled by the match flag cascading and the use of the /EC  
control signal, as shown in Table 4.  
During a Compare operation, the data in the Comparand  
register is compared to all locations in the Memory array  
simultaneously. Any Mask register used during compares  
must be selected beforehand in the Control register. There  
are two ways compares are initiated: Automatic compare  
and Forced compare.  
Automatic compares perform a compare of the contents of  
the Comparand register against Memory locations that are  
tagged as “Valid,” and occur whenever the following  
happens:  
The ripple delay of the flags when connected in a daisy  
chain requires the extension of the /E HIGH time until the  
logic in all devices has settled out. In a string of “n”  
devices, the /E HIGH time should be greater than  
•
The Destination Segment counter in the Segment  
Control register reaches its end limit during writes to  
the Comparand or Mask registers.  
tEHMFV + (n-2)· tMIVMFV  
•
After a command write of a TCO CT is executed  
(except for a software reset), so that a compare is  
executed with the new settings of the Control register.  
If the last device’s Match flag is required by external logic  
or a state machine before the start of the next CAM cycle,  
one additional tMIVMFV should be added to the /E HIGH  
time along with the setup time and delays for the external  
logic.  
Forced compares are initiated by CMP instructions using  
one of the four validity conditions: V, R, S, and E. The  
forced compare against “Empty” locations automatically  
masks all 64 bits of data to find all locations with the  
validity bits set to “Empty,” while the other forced  
compares are only masked as selected in the Control  
register.  
/E  
/EC  
Vertical Cascading  
/EC (INT)  
/MF  
LANCAMs can be vertically cascaded to increase system  
depth. Through the use of flag daisy-chaining, multiple  
devices respond as an integrated system. The flag daisy  
chain allows all commands to be issued globally, with a  
response only in the device containing the Highest-Priority  
Matching or Next Free location. When connected in a  
daisy chain, the last device’s Full flag and Match flag  
accurately report the condition for the whole string. A  
system in which LANCAMs are vertically cascaded using  
daisy-chaining of the flags is shown in Figure 4 on page 7.  
Figure 10: /EC (Int) Timing Diagram  
Locked Daisy Chain  
In a locked daisy chain, the highest-priority device is the  
one with /MI HIGH and /MF LOW. In Standard mode,  
only this device responds to command and data reads and  
writes, until the daisy chain has been unlocked by taking  
/EC HIGH. This allows reading the associated data field  
from only the Highest-Priority Match location anywhere  
in a string of devices, or the Match address from the Status  
register of the device with the match. It also permits  
updating the entry stored at the Highest-Priority Match  
location. In Enhanced mode, devices are enabled to  
respond to some command and data writes, as noted in  
Table 4 on page 12, but not command and data reads.  
To operate the daisy chain, the Device Select registers are  
set to FFFFH to enable all devices to execute Command  
Write and Data Write cycles. In normal operation, read  
cycles are enabled from the device with the  
Highest-Priority match by locking the daisy chain (see the  
Locked Daisy Chain section). An individual device in the  
chain may be targeted for a read or write operation by  
temporarily setting the Device Select registers to the Page  
address of the target device. Setting the Device Select  
registers back to FFFFH restores the operation of the  
entire daisy chain.  
Table 4 (Standard and Enhanced modes) show when a  
device responds to reads or writes and when does not,  
based on the state of /EC(int), the internal match  
condition, and other control inputs. /EC is latched by the  
falling edge of /E. /EC(int) is registered from the latched  
/EC signal off the rising edge of /E, so it controls what  
happens in the next cycle, as shown in Figure 10 on page  
Match Flag Cascading  
The Match Flag daisy chain cascading has three purposes:  
first, to allow operations on Highest-Priority Match  
addresses to be issued globally over the whole string;  
Rev. 5.1  
15  
LANCAM B Family  
Operational Characteristics  
15. When /EC is first taken LOW in a string of LANCAM  
devices (and assuming the Device Select registers are set  
to FFFFH), all devices respond to that command write or  
data write.  
Full Flag Cascading  
The Full Flag daisy chain cascading has the following  
three purposes:  
•
Allow instructions that address Next Free locations to  
operate globally  
From then on the daisy chain remains locked in each  
subsequent cycle as long as /EC is held LOW on the  
falling edge of /E in the current cycle. When the daisy  
chain is locked in Standard mode, only the  
Highest-Priority Match device responds (See Case 6 of  
Table 4). If, for example, all of the CAM memory  
locations were empty, there would be no match, and /MF  
would stay HIGH. Since none of the devices could then be  
the Highest-Priority Match device, none respond to reads  
or writes until the daisy chain is unlocked by taking /EC  
HIGH and asserting /E for a cycle.  
•
•
Provide a system wide Full flag  
Allow the loading of the Page Address registers  
during initialization using the SFF instruction  
The full flag logic causes only the device containing the  
first empty location to respond to Next Free instructions  
such as MOV NF,CR,V, which moves the contents of the  
Comparand register to the first empty location in a string  
of devices and sets that location Valid, making it available  
for the next automatic compare. With devices connected as  
in Figure 4 on page 7, the /FF output of the last device in a  
string provides a full indication for the entire string.  
If there is a match between the data in the Comparand  
register and one or more locations in memory, then only  
the Highest-Priority Match device responds to any cycle,  
such as an associated data or Status Register read. If there  
is not a match, then a NOP with /EC HIGH needs to be  
inserted before issuing any new instructions, such as Write  
to Next Free Address instruction to learn the data. Since  
Next Free operations are controlled by the /FI–/FF daisy  
chain, only the device with the first empty location  
responds. If an instruction is used to unlock the daisy  
chain, it works only on the Highest-Priority Match device,  
if one exists. If none exists, the instruction has no effect  
except to unlock the daisy chain. To read the Status  
registers of specific devices when there is no match  
requires the use of the TCO DS command to set DS=PA of  
each device. Single chip systems can tie /EC HIGH and  
read the Status register or the /MA and /MM pins to  
monitor match conditions, as the daisy chain lock-out  
feature is not needed in this configuration. This removes  
the need to insert a NOP in the case of a no-match.  
IEEE 802.3/802.5 Format Mapping  
To support the symmetrical mapping between the address  
formats of IEEE 802.3 and IEEE 802.5, the LANCAM  
provides a bit translation facility. Formally expressed, the  
nth input bit, D(n), maps to the xth output bit, Q(x),  
through the following expressions:  
D(n) = Q(7–n) for 0 < n < 7,  
D(n) = Q(23–n) for 8 < n < 15  
Setting Control Register bit 10 and bit 9 selects whether to  
persistently translate, or persistently not to translate, the  
data written onto the 64-bit internal bus. The default  
condition after a Reset command is not to translate the  
incoming data. Figure 6 on page 9 shows the bit mapping  
between the two formats.  
Initializing the Lancam  
Initialization of the LANCAM is required to configure the  
various registers on the device. Since a Control register  
reset establishes the operating conditions shown in Table 3  
on page 11, restoration of operating conditions better  
suited for the application may be required after a reset,  
whether using the Control Register reset, or the /RESET  
pin. When the device powers up, the memory and registers  
are in an unknown state, so the /RESET pin must be  
asserted to place the device in a known state.  
When the Control register is set to Enhanced mode, you  
can continue to write data to the Comparand register or  
issue a Move to Next Free Address instruction without  
first having to issue a NOP with /EC HIGH to unlock the  
daisy chain after a Compare cycle with no match, as  
indicated in cases 4 and 5 of Table 4 on page 12. In  
Enhanced mode, data write cycles as well as command  
write cycles are enabled in all devices even when /EC is  
LOW. Exceptions are data writes, moves, or VBC  
instructions involving HM, which occur only in the device  
with the highest match; and data writes or move  
instructions involving NF, which occur only in the device  
with /FI LOW and /FF HIGH. Enhanced mode speeds up  
system performance by eliminating the need to unlock the  
daisy chain before Command or Data Write cycles.  
Setting Page Address Register Values  
In a vertically cascaded system, the user must set the  
individual Page Address registers to unique values by  
using the Page Address initialization mechanism. Each  
Page Address register must contain a unique value to  
prevent bus contention. This process allows individual  
device selection. The Page Address register initialization  
works as follows: Writes to Page Address registers are  
only active for devices with /FI LOW and /FF HIGH. At  
16  
Rev. 5.2  
Operational Characteristics  
LANCAM B Family  
Vertically Cascaded System Initialization  
initialization, all devices are empty, thus the top device in  
the string responds to a TCO PA instruction, and loads its  
PA register. A Set Full Flag (SFF) instruction advances to  
the next device in the string and is active only for the  
device with /FI LOW and /FF HIGH. The SFF instruction  
changes the first device’s /FF to LOW, although the device  
really is empty, which allows the next device in the string  
to respond to the TCO PA instruction and load its PA  
register. The initialization proceeds through the chain in a  
similar manner filling all the PA registers in turn. Each  
device must have a unique Page Address value stored in  
its PA register, or contention results. After all the PA  
registers are filled, the entire string is reset through the  
Control register, which does not change the values stored  
in the individual PA registers. After the reset, the Device  
Select registers usually are set to FFFFH to enable  
operation in Case 1 of Table 4 on page 12. The Control  
registers and the Segment Control registers are then set to  
their normal operating values for the application.  
Table 5 shows an example of code that initializes a  
daisy-chained string of LANCAM devices. The  
initialization example shows how to set the Page Address  
registers of each of the devices in the chain through the  
use of the Set Full Flag instruction, and how the Control  
registers and Segment counters of all the LANCAM  
devices are set for a typical application. Each Page  
Address register must contain a unique value (not FFFFH)  
to prevent bus contention.  
For typical daisy chain operation, data is loaded into the  
Comparand registers of all the devices in a string  
simultaneously by setting DS=FFFFH. Since reading is  
prohibited when DS=FFFFH (except for the device with a  
match), for a diagnostic operation you need to select a  
specific device by setting DS=PA for the desired device to  
be able to read from it. Refer to Table 4 on page 12 for  
preconditions for reading and writing. Initialization for a  
single LANCAM is similar. The Device Select register in  
this case is usually set to equal the Page Address register  
for normal operations. Also, the dedicated /MA flag output  
can be used instead of /MF, allowing /EC to be tied HIGH.  
Table 5: Initialization Routine Example  
Cycle Type  
Op-Code  
Control Bus  
Comments  
Notes  
on DQ Bus  
/E  
/C  
M
/W /EC  
Command read  
Command write  
Command write  
Command write  
Command write  
Command write  
Command write  
Command write  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
Clear power-up anomalies  
Target Device Select register to disable local device selection.  
Disable Device Select feature.  
Target Control register for reset.  
Causes Reset.  
Target Page Address register to set page for cascaded operation.  
Page Address value.  
Set Full flag; allows access to next device (repeat previous  
two cycles plus this one for each device in chain.  
Target Control register for reset of Full flags, but not Page address.  
Causes Reset.  
Target Control register for initial values.  
Control register value.  
Target Segment Count Control register  
Set both Segment counters to write to Segment 1, 2, and 3, and read from  
Segment 0.  
TCO DS  
FFFFH  
TCO CT  
0000H  
TCO PA  
nnnnH  
SFF  
1
2
2
2,3  
Command write  
Command write  
Command write  
Command write  
Command write  
Command write  
TCO CT  
0000H  
TCO CT  
8040H  
TCO SC  
3808H  
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
1
1
4
4
4
Command write  
SPS M@HM  
L
L
L
H
Set Data reads from Segment 0 of the Highest-Priority match  
Notes:  
1.  
Toggling the /RESET pin generates the same effect as this reset of the Control register, but good programming practice dictates a software reset for  
initialization to account for all possible prior conditions.  
2.  
3.  
This instruction may be omitted for a single LANCAM application.  
The last SFF causes the /FF pin in the last chip in a daisy chain to go LOW. In a daisy chain, DS needs to be set equal to PA to read out a  
particular chip prior to a match condition.  
4.  
A typical LANCAM control environment: Enable match flag; Enable full flag; 48 CAM bits, 16 RAM bits; Disable comparison masking; and  
Enable address increment. See Table on page 23 for Control Register bit assignments  
Rev. 5.1  
17  
LANCAM B Family  
Instruction Set Descriptions  
INSTRUCTION SET DESCRIPTIONS  
Notes: Instruction cycle lengths given in Table 6 on page 22. If f=1, the instruction requires an absolute address to be supplied on the  
following cycle as a Command write. The value supplied on the second cycle of the instruction updates the address register. After  
operations involving M@[AR] or M@aaaH, the Address register increments or decrements depending on the setting in the Control  
register.  
Instruction: Select Persistent Source (SPS)  
Binary Op-Code: 0000 f000 0000 0sss  
Instruction: Temporary Command Override (TCO)  
Binary Op-Code: 0000 0010 00dd d000  
f
sss  
Address Field flag  
Selected source  
ddd  
Register selected as source or  
destination for only the next  
Command Read or Write cycle  
This instruction selects a persistent source for data reads,  
until another SPS instruction changes it or a reset occurs.  
The default source after reset for Data Read cycles is the  
Comparand register. Setting the persistent source to  
M@aaaH loads the Address register with “aaaH” and the  
first access to that persistent source is at aaaH, after which  
the AR value increments or decrements as set in the  
Control register. The SPS M@[AR] instruction does the  
same except the current Address Register value is used.  
The TCO instruction selects a register as the source or  
destination for only the next Command Read or Write  
cycle, so a value can be loaded or read out of the register.  
Subsequent Command Read or Write cycles revert to  
reading the Status register and writing to the Instruction  
decoder. All registers but the NF, PS, and PD can be  
written to, and all can be read from. The Status register is  
only available through non-TCO Command Read cycles.  
Reading the PS register also outputs the Device ID on bits  
15–4 as shown in Persistent Source Register Bits on page  
24.  
Instruction: Select Persistent Destination (SPD)  
Binary Op-Code: 0000 f001 mmdd dvvv  
f
Address Field flag  
Instruction: Data Move (MOV)  
Binary Op-Code: 0000 f011 mmdd dsss or  
0000 f011 mmdd dvss  
mm  
ddd  
vvv  
Mask Register select  
Selected destination  
Validity setting for Memory Location  
destinations  
f
Address Field flag  
mm  
ddd  
sss  
v
Mask Register select  
Destination of data  
Source of data  
Validity setting if destination is a  
Memory location  
This instruction selects a persistent destination for data  
writes, which remains until another SPD instruction  
changes it or a reset occurs. The default destination for  
Data Write cycles is the Comparand register after a reset.  
When the destination is the Comparand register or the  
Memory array, the data written may be masked by either  
Mask Register 1 or Mask Register 2, so that only  
destination bits corresponding to bits in the Mask register  
set to 0 are modified. An automatic compare occurs after  
writing the last segment of the Comparand or Mask  
registers, but not after writing to Memory. Setting the  
persistent destination to M@aaaH loads the Address  
register with “aaaH,” and the first access to that persistent  
destination is at aaaH, after which the AR value  
increments or decrements as set in the Control register.  
The SPD M@[AR] instruction does the same except the  
current Address Register value is used.  
The MOV instruction performs a 64-bit move of the data  
in the selected source to the selected destination. If the  
source or destination is aaaH, the Address register is set to  
“aaaH.” For MOV instructions to or from aaaH or [AR],  
the Address register increments or decrements from that  
value after the move completes, as set in the Control  
register. Data transfers between the Memory array and the  
Comparand register may be masked by either Mask  
Register 1 or Mask Register 2, in which case, only those  
bits in the destination that correspond to bits in the  
selected Mask register set to 0 are changed. A Memory  
location used as a destination for a MOV instruction may  
be set to Valid or left unchanged. If the source and  
destination are the same register, no net change occurs (a  
NOP).  
18  
Rev. 5.2  
Instruction Set Descriptions  
LANCAM B Family  
Instruction: Validity Bit Control (VBC)  
Binary Op-Code: 0000 f100 00dd dvvv  
An RSC instruction resets the Segment Control register  
count values for both the Destination and Source counters  
to the original Start limits.  
f
Address Field flag  
ddd  
vvv  
Destination of data  
Validity setting for Memory location  
The Shift instructions shift the designated register one bit  
right or left. The right and left limits for shifting are  
determined by the CAM/RAM partitioning set in the  
The VBC instruction sets the Validity bits at the selected  
memory locations to the selected state. This feature can be  
used to find all valid entries by using a repetitive sequence  
of CMP V through a mask of all 1s followed by a VBC  
HM, S. If the VBC target is aaaH, the Address register is  
set to “aaaH.” For VBC instructions to or from aaaH or  
[AR], the Address register increments or decrements from  
that value after the operation completes, as set in the  
Control register.  
Control register. The Comparand register is  
a
barrel-shifter, and for the example of a device set to 64 bits  
of CAM executing a Shift Comparand Right instruction,  
bit 0 is moved to bit 63, bit 1 is moved to bit 0, and bit 63  
is moved to bit 62. For a Shift Comparand Left instruction,  
bit 63 is moved to bit 0, bit 0 is moved to bit 1, and bit 62  
is moved to bit 63. MR2 acts as a sliding mask, where for  
a Shift Right instruction bit 1 is moved to bit 0, while bit 0  
“falls off the end,” and bit 63 is replicated to bit 62. For a  
Shift Mask Left instruction, bit 0 is replicated to bit 1, bit  
62 is moved to bit 63, and bit 63 “falls off the end.” With  
shorter width CAM fields, the bit limits on the right or left  
move to match the width of CAM field.  
Instruction: Compare (CMP)  
Binary Op-Code: 0000 0101 0000 0vvv  
vvv  
Validity condition  
A CMP V, S, or R instruction forces a Comparison of  
Valid, Skipped, or Random entries against the Comparand  
register through a Mask register, if one is selected. During  
a CMP E instruction, the compare is only done on the  
Validity bits and all data bits are automatically masked.  
Instruction: Set Full Flag (SFF)  
Binary Op-Code: 0000 0111 0000 0000  
The SFF instruction is a special instruction used to force  
the Full flag LOW to permit setting the Page Address  
register in vertically cascaded systems.  
Instruction: Special Instructions  
Binary Op-Code: 0000 0110 00dd drrr  
Instruction: No Operation (NOP)  
ddd  
rrr  
Target resource  
Operation  
Binary Op-Code: 0000 0011 0000 0000  
The NOP (No-OP) belongs to the MOV instructions,  
where a register is moved to itself. No change occurs  
within the device. This instruction is useful in unlocking  
the daisy chain in Standard mode.  
These instructions are a special set for the LANCAM to  
accommodate the added features over the MU9C1480.  
Two alternate sets of configuration registers can be  
selected by using the Select Foreground and Select  
Background Registers instructions. These registers are the  
Control, Segment Control, Address, Mask Register 1, and  
the PS and PD registers.  
Rev. 5.1  
19  
LANCAM B Family  
Instruction Set Summary  
INSTRUCTION SET SUMMARY  
Mnemonic Format: INS dst, src[msk], val  
Instruction: Select Persistent Destination (continued)  
Operation  
Mnemonic  
Op-Code  
012EH  
016EH  
01AEH  
012FH  
016FH  
01AFH  
0134H  
0174H  
01B4H  
0135H  
0175H  
01B5H  
0136H  
0176H  
01B6H  
0137H  
0177H  
01B7H  
INS: Instruction mnemonic  
dst: Destination of the data  
src: Source of the data  
msk: Mask register used  
val: Validity condition set at the location written  
Mem. at Highest-Prio. Match, Skip  
Masked by MR1  
SPD M@HM,S  
SPD M@HM[MR1],S  
SPD M@HM[MR2],S  
SPD M@HM,R  
Masked by MR2  
Mem. at High.-Prio. Match, Random  
Masked by MR1  
SPD M@HM[MR1],R  
SPD M@HM[MR2],R  
SPD M@NF,V  
Instruction: Select Persistent Source  
Masked by MR2  
Mem. at Next Free Addr., Valid  
Masked by MR1  
Operation  
Mnemonic  
SPS CR  
Op-Code  
0000H  
0001H  
0002H  
0004H  
0804H  
0005H  
SPD M@NF[MR1],V  
SPD M@NF[MR2],V  
SPD M@NF,E  
Comparand Register  
Mask Register 1  
Masked by MR2  
SPS MR1  
Mem. at Next Free Addr., Empty  
MaskedbyMR1  
Mask Register 2  
SPS MR2  
SPD M@NF[MR1],E  
SPD M@NF[MR2],E  
SPD M@NF,S  
Memory Array at Addr. Reg.  
Memory Array at Address  
Mem. at Highest-Priority Match  
SPS M@[AR]  
SPS M@aaaH  
SPS M@HM  
MaskedbyMR2  
Mem. at Next Free Addr., Skip  
Masked by MR1  
SPD M@NF[MR1],S  
SPD M@NF[MR2],S  
SPD M@NF,R  
Masked by MR2  
Mem. at Next Free Addr., Random  
Masked by MR1  
Instruction: Select Persistent Destination  
SPD M@NF[MR1],R  
SPD M@NF[MR2],R  
Masked by MR2  
Operation  
Mnemonic  
Op-Code  
0100H  
0140H  
0180H  
0108H  
0110H  
0124H  
0164H  
01A4H  
0125H  
0165H  
01A5H  
0126H  
0166H  
01A6H  
0127H  
0167H  
01A7H  
0924H  
0964H  
09A4H  
0925H  
0965H  
09A5H  
0926H  
0966H  
09A6H  
0927H  
0967H  
09A7H  
012CH  
016CH  
01ACH  
012DH  
016DH  
01ADH  
Comparand Register  
Masked by MR1  
SPD CR  
SPD CR[MR1]  
Instruction: Temporary Command Override  
Masked by MR2  
SPD CR[MR2]  
Operation  
Mnemonic  
TCO CT  
TCO PA  
TCO SC  
TCO NF  
TCO AR  
TCO DS  
TCO PS  
TCO PD  
Op-Code  
0200H  
0208H  
0210H  
0218H  
0220H  
0228H  
0230H  
0238H  
Mask Register 1  
SPD MR  
Mask Register 2  
SPD MR2  
Control Register  
Mem. at Addr. Reg. set Valid  
Masked by MR1  
SPD M@[AR],V  
Page Address Register  
Segment Control Register  
Read Next Free Address  
Address Register  
SPD M@[AR][MR1],V  
SPD M@[AR][MR2],V  
SPD M@[AR],E  
Masked by MR2  
Mem. at Addr. Reg. set Empty  
Masked by MR1  
SPD M@[AR][MR1],E  
SPD M@[AR][MR2],E  
SPD M@[AR],S  
Device Select Register  
Read Persistent Source  
Read Persistent Destination  
Masked by MR2  
Mem. at Addr. Reg. set Skip  
Masked by MR1  
SPD M@[AR][MR1],S  
SPD M@[AR][MR2],S  
SPD M@[AR],R  
Masked by MR2  
Instruction: Data Move  
Mem. at Addr.Reg. set Random  
Masked by MR1  
SPD M@[AR][MR1],R  
SPD M@[AR][MR2],R  
SPD M@aaaH,V  
Operation  
Mnemonic  
Op-Code  
Masked by MR2  
Comparand Register from:  
No Operation  
Memory at Address set Valid  
Masked by MR1  
NOP  
0300H  
0301H  
0302H  
0304H  
0344H  
0384H  
0B04H  
0B44H  
0B84H  
0305H  
0345H  
0385H  
SPD M@aaaH[MR1],V  
SPD M@aaaH[MR2],V  
SPD M@aaaH,E  
Mask Register 1  
MOV CR,MR1  
Masked by MR2  
Mask Register 2  
MOV CR,MR2  
Memory at Address set Empty  
Masked by MR1  
Memory at Address Reg.  
Masked by MR1  
MOV CR,[AR]  
SPD M@aaaH[MR1],E  
SPD M@aaaH[MR2],E  
SPD M@aaaH,S  
MOV CR,[AR][MR1]  
MOV CR,[AR][MR2]  
MOV CR,aaaH  
Masked by MR2  
Masked by MR2  
Memory at Address set Skip  
Masked by MR1  
Memory at Address  
Masked by MR1  
SPD M@aaaH[MR1],S  
SPD M@aaaH[MR2],S  
SPD M@aaaH,R  
MOV CR,aaaH[MR1]  
MOV CR,aaaH[MR2]  
MOV CR,HM  
Masked by MR2  
Masked by MR2  
Memory at Address set Random  
Masked by MR1  
Mem. at Highest-Prio. Match  
MaskedbyMR1  
SPD M@aaaH[MR1],R  
SPD M@aaaH[MR2],R  
SPD M@HM,V  
MOV CR,HM[MR1]  
MOV CR,HM[MR2]  
Masked by MR2  
MaskedbyMR2  
Mem. at Highest-Prio. Match, Valid  
Masked by MR1  
Mask Register 1 from:  
Comparand Register  
No Operation  
SPD M@HM[MR1],V  
SPD M@HM[MR2],V  
SPD M@HM,E  
MOV MR1,CR  
NOP  
0308H  
0309H  
030AH  
030CH  
0B0CH  
030DH  
Masked by MR2  
Mem. at Highest-Prio. Match, Emp.  
Masked by MR1  
Mask Register 2  
MOV MR1,MR2  
MOV MR1,[AR]  
MOV MR1,aaaH  
MOV MR1,HM  
SPD M@HM[MR1],E  
SPD M@HM[MR2],E  
Memory at Address Reg.  
Memory at Address  
Mem. at Highest-Prio. Match  
Masked by MR2  
20  
Rev. 5.2  
Instruction Set Summary  
LANCAM B Family  
Instruction: Data Move (continued)  
Instruction: Validity Bit Control  
Operation  
Mnemonic  
Op-Code  
Operation  
Mnemonic  
Op-Code  
Mask Register 2 from:  
Comparand Register  
Mask Register 1  
Set Validity bits at Address Register  
Set Valid  
MOV MR2,CR  
MOV MR2,MR1  
NOP  
0310H  
0311H  
0312H  
0314H  
0B14H  
0315H  
VBC [AR],V  
VBC [AR],E  
VBC [AR],S  
VBC [AR],R  
0424H  
0425H  
0426H  
0427H  
Set Empty  
No Operation  
Set Skip  
Memory at Address Reg.  
Memory at Address  
Mem. at Highest-Prio. Match  
MOV MR2,[AR]  
MOV MR2,aaaH  
MOV MR2,HM  
Set Random Access  
Set Validity bits at Address  
Set Valid  
VBC aaaH,V  
VBC aaaH,E  
VBC aaaH,S  
VBC aaaH,R  
0C24H  
0C25H  
0C26H  
0C27H  
Memory at Address Register, No Change to Validity bits, from:  
Set Empty  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV [AR],CR  
0320H  
0360H  
03A0H  
0321H  
0322H  
Set Skip  
MOV [AR],CR[MR1]  
MOV [AR],CR[MR2]  
MOV [AR],MR1  
MOV [AR],MR2  
Set Random Access  
Set Validity bits at Highest-Priority Match  
Set Valid  
VBC HM,V  
042CH  
042DH  
042EH  
042FH  
Set Empty  
VBC HM,E  
VBC HM,S  
VBC HM,R  
Memory at Address Register, Location set Valid, from:  
Set Skip  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV [AR],CR,V  
0324H  
0364H  
03A4H  
0325H  
0326H  
Set Random Access  
MOV [AR],CR[MR1],V  
MOV [AR],CR[MR2],V  
MOV [AR],MR1,V  
MOV [AR],MR2,V  
Set Validity bits at All Matching Locations  
Set Valid  
VBC ALM,V  
043CH  
043DH  
043EH  
043FH  
Set Empty  
VBC ALM,E  
VBC ALM,S  
VBC ALM,R  
Set Skip  
Memory at Address, No Change to Validity bits, from:  
Set Random Access  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV aaaH0,CR  
0B20H  
0B60H  
0BA0H  
0B21H  
0B22H  
MOV aaaH,CR[MR1]  
MOV aaaH,CR[MR2]  
MOV aaaH,MR1  
Instruction: Compare  
Operation  
Mnemonic  
CMP V  
Op-Code  
0504H  
MOV aaaH,MR2  
Compare Valid Locations  
Compare Empty Locations  
Compare Skipped Locations  
Comp. Random Access Locations  
Memory at Address, Location set Valid, from:  
CMP E  
0505H  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV aaaH,CR,V  
0B24H  
0B64H  
0BA4H  
0B25H  
0B26H  
CMP S  
0506H  
MOV aaaH,CR[MR1],V  
MOV aaaH,CR[MR2],V  
MOV aaaH,MR1,V  
CMP R  
0507H  
MOV aaaH,MR2,V  
Instruction: Special Instructions  
Memory at Highest-Priority Match, No Change to Validity bits, from:  
Operation  
Mnemonic  
Op-Code  
0600H  
0601H  
0610H  
0611H  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV HM,CR  
0328H  
0368H  
03A8H  
0329H  
032AH  
Shift Comparand Right  
Shift Comparand Left  
SFT CR, R  
SFT CR, L  
SFT M2, R  
SFT M2, L  
SFR  
MOV HM,CR[MR1]  
MOV HM,CR[MR2]  
MOV HM,MR1  
Shift Mask Register 2 Right  
Shift Mask Register 2 Left  
Select Foreground Registers  
Select Background Registers  
Reset Seg. Cont. Reg. to Initial Val.  
MOV HM,MR2  
0618H  
0619H  
061AH  
Memory at Highest-Priority Match, Location set Valid, from:  
SBR  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV HM,CR,V  
032CH  
036CH  
03ACH  
032DH  
032EH  
RSC  
MOV HM,CR[MR1],V  
MOV HM,CR[MR2],V  
MOV HM,MR1,V  
MOV HM,MR2,V  
Instruction: Miscellaneous  
Operation  
No Operation  
Set Full Flag  
Mnemonic  
NOP  
Op-Code  
0300H  
Memory at Next Free Address, No Change to Validity bits, from:  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV NF,CR  
0330H  
0370H  
03B0H  
0331H  
0332H  
SFF  
0700H  
MOV NF,CR[MR1]  
MOV NF,CR[MR2]  
MOV NF,MR1  
MOV NF,MR2  
Memory at Next Free Address, Location set Valid, from:  
Comparand Register  
Masked by MR1  
Masked by MR2  
Mask Register 1  
Mask Register 2  
MOV NF,CR,V  
0334H  
0374H  
03B4H  
0335H  
0336H  
MOV NF,CR[MR1],V  
MOV NF,CR[MR2],V  
MOV NF,MR1,V  
MOV NF,MR2,V  
Rev. 5.1  
21  
LANCAM B Family  
Instruction Set Summary  
Instruction Cycle Lengths  
Table 6: Instruction Cycle Lengths  
Cycle  
Length  
Cycle Type  
Command Read  
Command Write  
Data Write  
Data Read  
MOV reg, reg (except -70)  
TCO reg (except CT)  
TCO CT (non-reset, HMA invalid)  
SPS, SPD, SFR  
Comparand register  
(not last segment)  
Mask register  
Short  
(not last segment)  
SBR, RSC  
NOP (except -70)  
SFT (8480B)  
MOV reg, mem  
MOV reg, reg (-70)  
TCO CT (reset)  
VBC (NFA invalid)  
SFT (except 8480B)  
NOP (-70)  
Status register or  
16-bit register Sheets  
Memory array  
(NFA invalid)  
Comparand register  
Mask register  
Medium  
MOV mem, reg  
TCO CT (non-reset, HMA valid)  
Memory array  
(NFA valid)  
Memory array  
CMP  
SFF  
VBC (NFA valid)  
Comparand register  
(last segment)  
Mask register  
(last segment)  
Long  
Note: The specific timing requirements for Short, Medium, and Long cycles are given in the Switching Characteristics section under the  
tELEH parameter. For two cycle Command Writes (TCO reg or any instruction with “aaaH” as the source or destination), the first  
cycle is short, and the second cycle is the length given.  
22  
Rev. 5.2  
Register Bit Assignments  
LANCAM B Family  
REGISTER BIT ASSIGNMENTS  
Control Register Bits  
Device  
Bit(s)  
15  
Name  
Description  
RST  
0 = Reset  
14:13  
Match Flag  
00 = Enable  
01 = Disable  
10 = Reserved  
11 = No Change  
12:11  
10:9  
8:6  
Full Flag  
00 = Enable  
01 = Disable  
10 = Reserved  
11 = No Change  
Translation  
CAM/RAM Part  
00 = Input Not Translated  
01 = Input Translated  
10 = Reserved  
11 = No Change  
000 = 64 CAM/0 RAM  
001 = 48 CAM/16 RAM  
010 = 32 CAM/32 RAM  
011 = 16 CAM/48 RAM  
100 = 48 RAM/16 CAM  
101 = 32 RAM/32 CAM  
110 = 16 RAM/48 CAM  
111 = No Change  
All  
5:4  
3:2  
1:0  
Comp. Mask  
AR Inc/Dec  
Mode  
00 = None  
01 = MR1  
10 = MR2  
11 = No Change  
00 = Increment  
01 = Decrement  
10 = Disable  
11 = No Change  
00 = Standard  
01 = Enhanced  
10 = Reserved  
11 = No Change  
Note: D15 reads back as 0.  
Segment Control Register Bits  
Device  
Bit(s)  
Name  
Description  
15  
SDL  
0 = Set Destination Segment Limits  
1 = No Change  
14:13  
12:11  
10  
DCSL  
DCEL  
SSL  
00–11 = Destination Count Start Limit  
00–11 = Destination Count End Limit  
0 = Set Source Segment Limits  
1 = No Change  
9:8  
7:6  
5
SCSL  
SCEL  
LDC  
00–11 = Source Count Start Limit  
00–11 = Source Count End Limit  
All  
0 = Load Destination Segment Count  
1 = No Change  
4:3  
2
DSCV  
LSC  
00–11 = Destination Seg. Count Value  
0 = Load Source Segment Count  
1 = No Change  
1:0  
SSCV  
00–11 = Source Segment Count Value  
Note: D15, D10, D5, and D2 are read back as 0s.  
Rev. 5.1  
23  
LANCAM B Family  
Register Bit Assignments  
Next Free Address Bits  
Device  
Bit(s)  
15:10  
9:0  
Name  
Description  
PA5–0  
NF9-0  
PA4-0  
Page Address  
1480B  
Next Free Address  
Page Address  
15:11  
10:0  
2480B  
4480B  
8480B  
NF10-0  
PA3–0  
NF11-0  
PA2–0  
NF12-0  
Next Free Address  
Page Address  
15:12  
11:0  
Next Free Address  
Page Address  
15:13  
12:0  
Next Free Address  
Note: The Next Free Address register is read only, and is accessed by performing a Command Read cycle immediately following a TCO  
NF instruction.  
Status Register Bits  
Device  
Bit(s)  
31  
Name  
/FL  
Description  
0 = Internal CAM Full  
0 = Internal Multiple Match  
30  
/MM  
VB1-0  
29:28  
00 = Valid  
01 = Empty  
10 = Skip  
11 = RAM  
All  
27  
0
Reserved  
26:16  
15:11  
10:1  
27:16  
15:12  
11:1  
PA15–5  
PA4–0  
AM9–0  
PA15–4  
PA3–0  
AM10–0  
PA14–3  
PA2–0  
AM11–0  
PA13–2  
PA1–0  
AM12–0  
/MA  
Page Address (second read)  
Page Address (first read)  
Match Address  
1480B  
Page Address (second read)  
Page Address (first read)  
Match Address  
2480B  
4480B  
27:16  
15:13  
12:1  
Page Address (second read)  
Page Address (first read)  
Match Address  
27:16  
15:14  
13:1  
Page Address (second read)  
Page Address (first read)  
Match Address  
8480B  
All  
0
Match Flag  
Note: The Status register is read only, and is accessed by performing Command Read cycles. On the first cycle, bits 15–0 are output,  
and if a second Command Read cycle is issued immediately after the first Command Read cycle, bits 31–16 are output.  
Persistent Source Register Bits  
Device  
1480B  
2480B  
4480B  
8480B  
All  
Bit(s)  
15:4  
15:4  
15:4  
15:4  
3:0  
Name  
DEVID  
DEVID  
DEVID  
DEVID  
PS  
Description  
Device ID = 141H  
Device ID = 240H  
Device ID = 440H  
Device ID = 840H  
Persistent Source Setting  
Note: The Persistent Source register is read only, and is accessed by performing a Command Read cycle immediately following a TCO  
PS instruction.  
24  
Rev. 5.2  
Electrical  
LANCAM B Family  
ELECTRICAL  
Absolute Maximum Ratings  
Supply Voltage  
-0.5 to 4.6 Volts  
Stresses exceeding those listed under Absolute Maximum  
Ratings may induce failure. Exposure to absolute maximum  
ratings for extended periods may reduce reliability.  
Functionality at or above these conditions is not implied.  
Voltage on all other pins  
-0.5 to VCC +0.5 Volts  
(-2 Volts for 10 ns, measured at the 50% point)  
Temperature under bias  
Storage Temperature  
DC Output Current  
-55° C to 125° C  
-55° C to 125° C  
All voltages referenced to GND.  
20 mA (per output, one at a time, one second  
duration)  
Operating Conditions  
Voltages referenced to GND at the device pin.  
Symbol  
Parameter  
Min. Typical  
Max.  
Units Notes  
V
3.0  
2.0  
3.3  
3.6  
Volts  
Operating supply voltage  
Input voltage logic 1  
Input voltage logic 0  
CC  
V
V
+ 0.5  
Volts  
IH  
CC  
V
-0.5  
0.8  
Volts 1, 2  
IL  
Commercial  
Industrial  
0
70  
85  
° C  
T
A
Ambient operating temperature  
Still air  
° C  
-40  
Notes:  
1.  
2.  
1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 12 on page 26).  
Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts.  
Average Power Supply Current (mA)  
-50  
-70  
-90  
Device  
1480B  
2480B  
4480B  
8480B  
Typ.  
Max.  
Typ.  
35  
Max.  
60  
Typ.  
30  
Max.  
50  
60  
100  
160  
260  
45  
75  
110  
160  
85  
140  
200  
230  
370  
120  
DC Electrical Characteristics  
Symbol  
Parameter  
Min Typical  
.
Max.  
Units  
Notes  
/E = HIGH  
I
2
mA  
Volts  
Volts  
µA  
Stand-by power supply current  
Output voltage logic 1  
CC(SB)  
V
OH  
2.4  
I
I
= -2.0 mA  
= 4.0 mA  
OH  
OL  
V
Output voltage logic 0  
0.4  
+2  
15  
13  
OL  
IZ  
Others  
-2  
V
V
V
≤ V ≤ V  
SS  
IN  
IN  
IN  
CC  
/RESET  
6
6
9
Kohms  
Kohms  
= 0 V  
I
Input leakage current  
Output leakage current  
Test1,  
Test2  
10  
= V ;10  
CC  
I
-10  
10  
µA  
V
≤ V  
OUT  
≤ V  
CC  
OZ  
SS  
DQ = High Impedance  
N
Capacitance  
Symbol  
Parameter  
Max.  
Units  
Notes  
C
Input capacitance  
Output capacitance  
6
7
pF  
f = 1 MHz, V = 0V  
IN  
IN  
C
pF  
f = 1 MHz, V = 0V  
OUT  
OUT  
Rev. 5.1  
25  
LANCAM B Family  
Switching  
AC Test Conditions  
Table 7: AC Test Conditions  
Input Signal Transitions  
Input Signal Rise Time  
0.0 Volts to 3.0 Volts  
< 3 ns  
Input Signal Fall Time  
< 3 ns  
Input Timing Reference Level  
Output Timing Reference Level  
1.5 Volts  
1.5 Volts  
SWITCHING  
Switching Test Figures  
Vcc  
Input  
Waveform  
R1  
Device  
0V  
Under Test  
IL ( MIN)  
V
C1  
50% Amplitude  
Point  
R2  
10ns  
Figure 11: AC Test Load  
Figure 12: Input Signal Waveform  
Switching Test Figures Component Values  
Table 8: Switching Test Figures Component Values  
Parameter  
VCC  
R1  
All Devices  
Units  
Volts  
Ohms  
Ohms  
pF  
3.3  
635  
702  
30  
R2  
Test Load A  
Test Load B  
C1 (includes jig)  
5
pF  
26  
Rev. 5.2  
Switching  
LANCAM B Family  
Switching Characteristics  
Table 9: Switching Characteristics  
Cycle Time  
-50  
-70  
-90  
No.  
Symbol  
Parameter  
Min. Max. Min. Max. Min. Max  
Notes  
1
t
Chip Enable Compare Cycle Time  
50  
70  
90  
ELEL  
Short Cycle  
15  
30  
45  
5
15  
35  
55  
15  
25  
50  
75  
15  
4
4
4
t
2
Chip Enable LOW Pulse Width  
Chip Enable HIGH Pulse Width  
Medium Cycle  
Long Cycle  
ELEH  
3
4
5
6
t
EHEL  
t
Control Input to Chip Enable LOW Setup Time  
Control Input from Chip Enable LOW Hold Time  
Chip Enable LOW to Outputs Active  
2
10  
3
2
10  
3
2
10  
3
5
5
6
CVEL  
t
ELCX  
t
ELQX  
Register Read  
Memory Read  
30  
40  
10  
30  
52  
10  
50  
75  
15  
4,6  
4,6  
7
t
7
Chip Enable LOW to Outputs Valid  
ELQV  
8
t
Chip Enable HIGH to Outputs HIGH-Z  
Data to Chip Enable LOW Setup Time  
3
2
3
2
3
2
EHQZ  
9
t
DVEL  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
t
Data from Chip Enable LOW Hold Time  
Full In Valid to Chip Enable LOW Setup Time  
Full In Valid to Full Flag Valid  
10  
0
10  
0
10  
0
ELDX  
t
FIVEL  
t
5
5
7
FIVFFV  
t
Chip Enable LOW to Full Flag Valid  
Match in Valid to Chip Enable LOW Setup Time  
Chip Enable HIGH to /MF, /MA, /MM Invalid  
Match In Valid to /MF Valid, /MA, /MM  
Chip Enable HIGH to /MF Valid  
35  
50  
75  
ELFFV  
MIVEL  
t
0
0
0
0
0
0
t
EHMFX  
t
4
5
7
MIVMFV  
t
16  
18  
16  
18  
25  
25  
EHMFV  
t
Chip Enable HIGH to /MA and /MM Valid  
Reset LOW Pulse Width  
EHMXV  
t
50  
100  
100  
8
RLRH  
Notes:  
1.  
2.  
3.  
4.  
5.  
6.  
7.  
8.  
9.  
1.0 Volts for a duration of 10 ns measured at the 50% amplitude points for Input-only lines (see Figure 12 on page 26).  
Common I/O lines are clamped, so that signal transients can not fall below -0.5 Volts.  
Over ambient operating temperature range and Vcc(min.) to Vcc(max.).  
See Table 6 on page 22.  
Control signals are /W, /CM, and /EC.  
With load specified in Figure 11 on page 26, Test Load A.  
With load specified in Figure 11 on page 26, Test Load B.  
/E must be HIGH during this period to ensure accurate default values in the configuration registers.  
With output and I/O pins unloaded.  
10. TEST1 and/or TEST2 may not be implemented on all versions of these products.  
Rev. 5.1  
27  
LANCAM B Family  
Timing Diagrams  
TIMING DIAGRAMS  
2
3
2
3
/E  
/ E  
4
4
5
5
4
5
/W  
/W  
4
4
5
5
/CM  
/ C M  
9
10  
DQ15 - 0  
/ E C  
11  
7
8
/FI  
D Q 1 5 - 0  
12  
13  
6
/FF  
Figure 13: Read Cycle  
Figure 14: Write Cycle  
1
2
3
/E  
4
5
5
/W  
4
/CM  
VALID  
5
4
/EC  
14  
/MI  
15  
16  
/MF  
17  
18  
/MA, /MM  
Figure 15: Compare Cycle  
28  
Rev. 5.2  
Dual Footprint Connections  
LANCAM B Family  
DUAL FOOTPRINT CONNECTIONS  
The following illustration is a suggested dual footprint only, and is not intended as board-ready artwork.  
64  
49  
1
48  
44  
34  
/MA  
1
33  
GND  
DQ4  
DQ5  
VCC  
VCC  
/MI  
/MA  
/MI  
GND  
DQ4  
/MF  
GND  
GND  
/RESET  
VCC  
VCC  
DQ5  
VCC  
/MF  
GND  
/RESET  
VCC  
VCC  
VCC  
GND  
GND  
GND  
GND  
DQ6  
DQ7  
VCC  
GND  
GND  
DQ6  
DQ7  
/E  
/E  
/ W  
/ W  
GND  
GND  
VCC  
GND  
11  
23  
12  
22  
16  
33  
17  
32  
Figure 16: Dual Footprint Connections  
Rev. 5.1  
29  
LANCAM B Family  
Dual Footprint Connections  
Notes  
30  
Rev. 5.2  
LQFP Packages  
LANCAM B Family  
LQFP PACKAGES  
44-Pin LQFP  
He  
E
A2  
A1  
Hd  
D
Pin 1  
L1  
L
c
e
b
Figure 17: 44-Pin LQFP Package  
Table 10: 44-Pin LQFP Dimensions  
Dim. A1  
Dim. A2  
1.35  
Dim. b  
0.22  
Dim. c  
Dim. D  
Dim. E  
Dim. e  
Dim. Hd Dim. He  
12.00 12.00  
Dim. L1  
Dim. L  
0.45  
Min.  
Nom.  
Max.  
0.05  
0.08  
1.40  
0.30  
10.00  
10.00  
0.80  
1.00  
0.60  
0.15  
1.45  
0.38  
0.20  
0.75  
64-Pin LQFP  
He  
E
A2  
A1  
Hd  
D
L1  
Pin 1  
L
c
e
b
Figure 18: 64-Pin LQFP Package  
Table 11: 64-Pin LQFP Dimensions  
Dim. A1  
Dim. A2  
1.35  
Dim. b  
0.22  
Dim. c  
Dim. D  
Dim. E  
Dim. e  
Dim. Hd Dim. He  
16.00 16.00  
Dim. L1  
Dim. L  
0.45  
Min.  
Nom.  
Max.  
0.05  
0.08  
1.40  
0.30  
14.00  
14.00  
0.80  
1.00  
0.60  
0.15  
1.45  
0.38  
0.20  
0.75  
Rev. 5.1  
31  
LANCAM B Family  
Ordering Information  
ORDERING INFORMATION  
Part Number  
Cycle Time  
Package  
Temperature  
Voltage  
MU9C8480B-50TBC  
MU9C8480B-70TBC  
MU9C8480B-90TBC  
50 ns  
70 ns  
90 ns  
64-Pin LQFP  
64-Pin LQFP  
64-Pin LQFP  
0–70° C  
0–70° C  
0–70° C  
3.3 ± 0.3  
3.3 ± 0.3  
3.3 ± 0.3  
MU9C8480B-50TBI **  
MU9C8480B-70TBI  
MU9C8480B-90TBI  
50 ns  
70 ns  
90 ns  
64-Pin LQFP  
64-Pin LQFP  
64-Pin LQFP  
-40–85° C  
-40–85° C  
-40–85° C  
3.3 ± 0.3  
3.3 ± 0.3  
3.3 ± 0.3  
MU9C4480B-70TBC  
MU9C4480B-90TBC  
70 ns  
90 ns  
64-Pin LQFP  
64-Pin LQFP  
0–70° C  
0–70° C  
3.3 ± 0.3  
3.3 ± 0.3  
MU9C4480B-70TBI  
MU9C4480B-90TBI  
70 ns  
90 ns  
64-Pin LQFP  
64-Pin LQFP  
-40–85° C  
-40–85° C  
3.3 ± 0.3  
3.3 ± 0.3  
MU9C2480B-70TBC  
MU9C2480B-90TBC  
70 ns  
90 ns  
64-Pin LQFP  
64-Pin LQFP  
0–70° C  
0–70° C  
3.3 ± 0.3  
3.3 ± 0.3  
MU9C2480B-70TBI  
MU9C2480B-90TBI  
70 ns  
90 ns  
64-Pin LQFP  
64-Pin LQFP  
-40–85° C  
-40–85° C  
3.3 ± 0.3  
3.3 ± 0.3  
MU9C1480B-70TAC  
MU9C1480B-90TAC  
70 ns  
90 ns  
44-Pin LQFP  
44-Pin LQFP  
0–70° C  
0–70° C  
3.3 ± 0.3  
3.3 ± 0.3  
MU9C1480B-90TAI  
90 ns  
44-Pin LQFP  
-40–85° C  
3.3 ± 0.3  
** MOQ required. Please contact your nearest MUSIC office or sales representative.  
ORDERING INFORMATION LEAD-FREE PRODUCTS  
For ordering Lead-Free products please add an "F" directly after the product name (in front of the speed grade).  
Example: MU9C8480BF-50TBC  
MUSIC Semiconductors reserves the right to make changes to its products and specifications at  
MUSIC Semiconductors’ agent or distributor:  
any time in order to improve on performance, manufacturability or reliability. Information  
furnished by MUSIC is believed to be accurate, but no responsibility is assumed by MUSIC  
Semiconductors for the use of said information, nor for any infringements of patents or of other  
third-party rights which may result from said use. No license is granted by implication or  
otherwise under any patent or patent rights of any MUSIC company.  
© Copyright 2000 and 2002, MUSIC Semiconductors  
North American Sales  
Asian Headquarters  
European Headquarters  
MUSIC Semiconductors  
Tel: 908-619-6818  
Fax: 828-278-0218  
MUSIC Semiconductors  
110 Excellence Ave., SEPZ 1  
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Canlubang, Laguna  
MUSIC Semiconductors  
Raadhuisplein 10  
6436 BW Amstenrade  
The Netherlands  
email: traciev@musicsemi.com  
Philippines 4028  
Tel: +63 49 549-1480  
Fax: +63 49 549-1024  
Tel: +31 43 455-2675  
Fax: +31 43 455-1573  
http: //www.musicsemi.com  
email: info@musicsemi.com  
32  
Rev. 5.2  

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