MX10F201FC_技术文档

MX10F201FC

FEATURES OF MX10F201FC (80C51 with MTP memory and LCD)

- 80C51 CPU core

- Two standard 16-bit Timers

- On-chip Watch Dog Timer

- Two channel PWM outputs

- UART

- 4.5 ~ 5.5V voltage range

- 2 to 16MHz clock frequency

- 16K bytes MTP memory for code memory

- 512 bytes internal data RAM

- Low power consumption

- 8 interrupt sources

- 100 pin PQFP package

- Single clock or dual clock

- EMI compatibility

- Up to 16 digits LCD driver/controller

- Four 8 bit general purpose I/O ports

Features list

- 80C51 CPU core

- 4.5 ~ 5.5V operation voltage range

- 2 to 16MHz clock frequency

- 16K bytes MTP memory for code memory

- More than 100 times program/erase cycles

- More than 10 years data retention

- 512 bytes internal data RAM

- Low operation current

- Power saving modes

- User friendly power control for active mode current

- Idle mode

- Sleep mode

- Power down mode, can be wake up by external interrupts or RESET

- LCD driver/controller

- Max. 16-digits display at 1/4 duty LCD

- 1:1(static), 1:2, 1:3 or 1:4 selectable LCD multiplexing rate

- 4 backplane driver, 32 segment driver

- LCD directly drive capability with display memory

- VLCD to control LCD driving voltage, (VLCD-VSS)

- 4x8 general purpose I/O ports

- Provide software I²C capability

- Two standard 16-bit Timers (Timer 0,1)

- On-chip Watch Dog Timer (WDT)

- Two channel PWM outputs

- UART

- Up to 8 interrupt sources and 8 interrupt vectors

- 4 external sources

- 4 internal sources(Timer0,Timer1,watch Timer and UART)

- 100 pin PQFP package

- Single clock or dual clock

- single clock mode : 2~16MHz system clock for CPU,Timer0/1,WDT,UART and LCD

- dual clock mode : 2~16MHz system clock for CPU,Timer0/1,WDT,UART; while 32.768KHz sub-system

clock for LCD and watch timer.

- system clock is either crystal or RC activated

- EMC(Electro-Magnetic Compatibility) improved

P/N:PM0730

REV. 0.1, FEB. 14, 2003

1

MX10F201FC

PINNING

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

NC

S5

S6

S7

NC

P26

P25

P24

P23

P22

P21

P20

NC

P37/INT3

P36/INT2

P35/T1

P34/T0

P33/INT1

P32/INT0

P31/TxD

P30/RxD

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

S8

S9

S10

S11

S12

S13

S14

S15

S16

S17

S18

S19

S20

S21

S22

MX10F201FC

Fig.1 Pinning

P/N:PM0730

REV. 0.1, FEB. 14, 2003

2

MX10F201FC

Table. 1 Pin Description

I/O SYMBOL PIN \QFP 100

DESCRIPTION

O

BP0-BP3 71~74

S00-S31 75-79,83-100,

Backplane drive output line 0 to 3.

Segment drive output line 0 to 31.

O

2-10

I/O P00-P07

I/O P20-P27

22-29

Port:8-bit open drain bidirectional I/O Port

Port: 8-bit quasi-bidirectional I/O Port with

internal pull-up

42-48,51

I/O P10-P17

P14

56-63

Quasi-bidirectional I/O lines

also for PWM channel 0

P15

also for PWM channel 1

I/O P30-P37

P30

31-38

31

Quasi-bidirectional I/O lines

also for UART Receive

P31

32

also for UART Transmit

P32-P33,

P36-P37

P34

also for external interrupt 0-3

also for Timer0 external input

also for Timer1 external input

P35

I

RESET

VDD

15

reset input

I

18,69

13,20,67

16

Positive power supply

I

VSS

Ground

I

XTAL1

XTAL2

XTAL3

XTAL4

RCP

XTAL connection input

XTAL connection output

32.768KHz, XTAL input

32.768KHz, XTAL output

RC oscillator resistor connection input

Supply 12V power for programming / erasing

LCD driver power supply

O

17

I

66

O

65

I

21

I

TEST/VPP 54

VLCD 11

I

Note:

1. To avoid a 'Latch-up' effect at power-on , the voltage on any pin (at any time )must not be higher than V +0.5 V

DD

or lower Vss-0.5V respectively

2. The generation or use of a Port 3 pin as an alternative function is carried out automatically by the associated

Special Function Register (SFR) bit is properly written .

P/N:PM0730

REV. 0.1, FEB. 14, 2003

3

MX10F201FC

3

VSS PWM0 PWM1

3

VPP

VDD

VLCD

T0 T1 INT0/1/2/3

T D R D

XTAL1

XTAL2

RESET

T0/T1

CPU

Program

Memory

16KB

Watch

Dog

Timer

Data

Memory

512x8 RAM

PWM

Two 16-bit

Counter

Serial

Port

8-bit internal Bus

Parallel I/O

Ports

LCD Unit

8

S00-S31 BP3

BP2

BP1 BP0

P0 P1 P2 P3

3

Alternative Function of Port3

Fig.2 Block Diagram

Internal Bus

8

LCD Freq

Divider

LCD Duty

LCON

ENLCD

BIAS

LCD Segment

Display Register

Ext.CLK

LCD_CLK

BP0_SEG[31:0]

BP3_SEG[31:0]

Timing/Duty

Control,

Voltage

Selector

Backplane Gen.

Segment Gen.

4 BP_Output [1:0]

32 Seg_Output [1:0]

VLCD

VSS

LCD

BIAS

Gen.

BP Driver

4

Seg. Driver

32

SEG31 SEG30….SEG0

LCD Panel

BP0

BP1

BP2

BP3

Fig.3 LCD Driver Block Diagram

P/N:PM0730

REV. 0.1, FEB. 14, 2003

4

MX10F201FC

FUNCTIONAL DESCTIPTION

General

The MX10F201FC is a stand-alone high-performance and low power microcontroller designed for use in many

applications which need code programmability.

The Flash EPROM offers customers to program the device themselves. This feature increases the flexibility in

many applications, not only in development stage, but also in mass production stage.

In addition to the 80C51 standard functions, the MX10F201FC provides a number of dedicated hardware functions.

MX10F201FC is a control-oriented CPU with on-chip program and data memory. It can execute program with internal

memory up to 16k bytes. MX10F201FC has four software selectable modes of reduced activity for power reduction :

active power control, idle, sleep, and Power-down. The idle mode freezes the CPU while allowing the RAM, Timers,

serial ports, interrupt system and other peripherals to continue functioning. The Power-down mode saves the RAM

contents but freezes the oscillator causing all other chip functions to be inoperative. Power-down mode can be

terminated by an external reset ,and in addition , by either of the four external interrupts. The sleep mode behaves like

power down mode, but with LCD and oscillator still turning on. And sleep mode can be terminated as the power down

mode does.

Instruction Set Execution

The MX10F201FC uses the powerful instruction set of the 80C51. Additional SFRs are incorporated to control the

on-chip peripherals. The instruction set consists of 49 single-byte, 46 two-bytes, and 16 three-bytes instructions.

When using a 16MHz oscillator, 64 instructions execute in 750 ns and 45 instructions execute in 1.5 us. Multiply and

divide instructions execute in 3 us.

MEMORY ORGANIZATION

The Central Processing Unit (CPU) manipulates operands in three memory spaces; these are the 256 bytes

internal data memory (RAM), 256 byte auxiliary data memory (AUX-RAM) and 16k byte internal MTP program memory

(FEPROM).

Program Memory

The program memory address space of the MX10F201FC comprises an internal and an external memory space.

The MX10F201FC has 16k byte of program memory on-chip.

Program Protection

If the user choose to set security lock in MTP memory, the program content is protected from reading out of chip.

Internal Data Memory

The internal data memory is divided into three physically separated parts: 256 byte of RAM, 256 bytes of AUX-

RAM, and 128 bytes special function register area (SFR). These parts can be addressed as follows (see Fig.4 and

Table. 2)

- RAM 0 to 127 can be addressed directly and indirectly as in the 80C51. Address pointers are R0 and R1 of

the selected register bank.

- RAM 128 to 255 can only be addressed indirectly . Address pointers are R0 and R1 of the selected register

bank.

- AUX-RAM 0 to 255 is indirectly addressable as the external data memory locations 0 to 255 with the MOVX

instructions. Address pointers are R0 and R1 of the selected register bank and DPTR. When executing from

internal program memory, an access to AUX_RAM 0 to 255 will not affect the ports P0,P2,P3.6 and P3.7.

SFRs can only be addressed directly in the address range from 128 to 255.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

5

MX10F201FC

Table. 2 Internal data memory access

LOCATION

ADDRESSED

RAM 0 to 127

DIRECT and INDIRECT

INDIRECT only

RAM 128 to 255

AUX-RAM 0 to 255

INDIRECT only with MOVX

DIRECT only

Special Function Register (SFR) 128 to 255

Fig. 4 shows the internal memory address space. Table 3 shows the Special Function Register (SFR) memory

map. Location 0 to 31 at the lower RAM area can be devided into four 8-bit register banks. Only one of these

banks may be enabled at a time. The next 16 bytes, locations 32 through 47, contain 128 directly addressable bit

locations.

The stack can be located anywhere in the internal 256 byte RAM. The stack depth is only limited by the available

internal RAM space of 256 bytes. All registers except the Program Counter and the four 8-byte register banks

reside in the SFR address space.

- Register

- Direct

- Register-Indirect

- Immediate

- Base-Register plus Index-Register-Indirect.

The first three methods can be used for addressing destination operands. Most instructions have a 'destination /

source' field that specifies the data type, addressing methods and operands involved. For operations other than

MOVs, the destination operand is also a source operand.

Access to memory addresses is as follows:

- Register in one of the four 8-byte register banks through Direct or Register-Indirect addressing.

- 256 bytes of internal RAM through Direct or Register-Indirect addressing. Bytes 0-127 of internal RAM may be

only be addressed indirectly as data RAM.

- SFR through direct addressing at address location 128-255.

OVERLAPPED SPACE with different access schemes

INTERNAL DATA MEMORY

255

127

16K

0

INDIRECT ONLY

---------------------

AUXILIARY

RAM

through

internal

program

memory

SFRs

Direct only

MOVX access

DIRECT AND

INDIRECT

0

MAIN RAM

SFRs

AUX-RAM

PROGRAM MEMORY

Fig. 4 Internal program and data memory address space

P/N:PM0730

REV. 0.1, FEB. 14, 2003

6

MX10F201FC

Table. 3 SFR Registers Map

Symbol

P0

Direct Address(ex)

Reset Value

1111,1111

0000,0111

0000,0000

1111,1111

0000,0000

xxxx,xxxx

1111,1111

0000,0000

1111,1111

x000,0000

x001,1100

0000,0000

xx00,0000

xxxx,xx00

xxxx,001x

0000,0000

x000,0100

xxxx,xx00

0000,0000

1111,1111

80H

81

SP

DPL

82

DPH

83

PCON

TCON

TMOD

TL0

87

88

89

8A

8B

8C

8D

90

TL1

TH0

TH1

P1

SCON

SBUF

P2

98

99

A0

A8

B0

B8

BA

BB

BC

BD

BE

BF

C0

C1

C2

C3

C4

C5

C6

C7

D0

D1

D2

D3

D4

E0

E3

E4

E8

EB

F0

F1

F8

FC

FD

FE

FF

IE

P3

IP

LCON

LCD0

LCD1

LCD2

LCD3

LCD4

INTCON

LCD5

LCD6

LCD7

LCD8

LCD9

LCDA

LCDB

PSW

LCDC

LCDD

LCDE

LCDF

ACC

WTL

WTH

IEN1

EBTCON

B

PCON1

IP1

PWM0

PWM1

PWMP

T3 (WDT)

P/N:PM0730

REV. 0.1, FEB. 14, 2003

7

MX10F201FC

I/O facilities

MX10F201FC has one 8 bits port, port 0, which is open drain, and three 8 bits ports, port 1/2/3, which are quasi bi-

directional ports. These four ports are fully compatible to standard 80C51's port 0/1/2/3.

- Port1: pins can be configured individually to provide 2 PWM outputs.

- Port3: pins can be configured individually to provide: external interrupt inputs (external interrupt 0/1/2/3);

external inputs for Timer/ counter 0 and Timer /counter1, and UART receive / transmit.

Port pins which are not used for alternate functions may be used as normal bidirectional I/O pins. The generation or

use of a Port 1 or Port 3 pin as an alternate function is carried out automatically by writing the associated SFR bit with

proper value.

+5V

2 oscillator

penods

P2

strong pull-up

P1

P3

I/O PORT

1,2,3

O

from port latch

n

input data

INPUT

BUFFER

read port pin

Fig. 5 I/O buffers in the MX10F201FC (Ports 1,2,3)

P/N:PM0730

REV. 0.1, FEB. 14, 2003

8

MX10F201FC

Timer/Counter

MX10F201FC's Timer/Counter 0 and 1 are fully compatible to standard 80C51's.

The MX10F201FC's contains two 16-bit Timer/counters, Timer 0 and Timer 1. Timer 0 and Timer 1 may be

programmed to carry out the following functions:

- measure time intervals and pulse durations

- count events

- generate interrupt requests.

Timer 0 and Timer 1

Timers 0 and 1 each have a control bit in TMOD SFR that selects the Timer or counter function of the

corresponding Timer. In the Timer function, the register is incremented every machine cycle. Thus, one can think of

it as counting machine cycles. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of

the oscillator frequency.

In the counter function, the register is incremented in response to a HIGH-to-LOW transition at the corresponding

samples, when the transition shows a HIGH in one cycle and a LOW in the next cycle, the counter is incremented.

Thus, it takes two machine cycles (24 oscillator periods) to recognize a HIGH-to-LOW transition. There are no

restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once

before it changes, it should be held for at least one full machine cycle.

Timer 0 and Timer 1 can be programmed independently to operate in one of four modes (refer to table 5) :

- Mode 0 : 8-bit Timer/counter with devided-by-32 prescaler

- Mode 1 : 16-bit Timer/counter

- Mode 2 : 8-bit Timer/counter with automatic reload

- Mode 3 : Timer 0 :one 8-bit Timer/counter and one 8-bits Timer. Timer 1 :stopped.

When Timer 0 is in Mode 3, Timer 1 can be programmed to operate in Modes 0, 1 or 2 but cannot set an interrupt

request flag and generate an interrupt. However, the overflow from Timer 1 can be used to pulse the Serial Port

transmission-rgate generator. With a 16 MHz crystal, the counting frequency of these Timer/counters is as follows:

- in the Timer function, the Timer is incremented at a frequency of 1.33 MHz (oscillator frequency divided by 12).

- in the counter function, the frequency handling range for external inputs is 0 Hz to 0.66 MHz (oscillator

frequency divided by 24).

Both internal and external inputs can be gated to the Timer by a second external source for directly measuring

pulse duration.

The Timers are started and stopped under software control. Each one sets its interrupt request flag when it

overflows from all logic 1's to all logic 0's (respectively, the automatic reload value), with the exception of Mode 3

as previously described.

TMOD : TIMER/COUNTER MODE CONTROL REGISTER

This register is located at address 89H.

Table. 4 TMOD SFR (89H)

7

6

5

4

3

2

1

0

GATE

(MSB)

TIMER 1

C/ T

M1

M0

GATE

C/ T

M1

M0

(LSB)

TIMER 0

keep the above table with the following table

P/N:PM0730

REV. 0.1, FEB. 14, 2003

9

MX10F201FC

Table. 5 Description of TMOD bits

MNEMONIC

TIMER 1

GATE

POSITION

TMOD.7

FUNCTION

Timer 1 gating control : when set, Timer/counter '1' is enabled only while 'Int1'

pin is high and 'tr1' control bit is set. when cleared, Timer/counter '1' is enabled

whenever 'tr1' control bit is set.

C/T

TMOD.6

Timer or counter selector: cleared for Timer operation (input from internal

system clock). set for counter operation (input from 'T1' input pin).

Operation mode: see table 6.

M1

TMOD.5

TMOD.4

M0

Operation mode: see table 6.

TIMER 0

GATE

TMOD.3

Timer 0 gating control: when set, Timer/Counter '0' is enabled only while 'Int0'

pin is high and 'tr0' control bit is set. when cleared, Timer/counter '0' is enabled

whenever 'tr0' control bit is set.

C/T

TMOD.2

Timer or counter selector: cleared for Timer operation (input from internal

system clock). set for counter operation (input from 'T0' input pin).

Operation mode: see table 6.

M1

M0

TMOD.1

TMOD.0

Operation mode: see table 6.

Table. 6 TMOD M1 and M0 operating modes

M1

0

M0 FUNCTION

0

1

0

8-bit Timer/counter : 'THx' with 5-bit prescaler.

0

16-bit Timer/counter : 'THx' and 'TLx' are cascaded, there is no prescaler.

8-bit autoload Timer/counter : 'THx' holds a value which is to be reloaded into 'TLx' each time it

overflows.

1

Timer 0: TL0 is an 8-bit Timer/counter controlled by the standard Timer 0 control bits. TH0 is an 8-

bit Timer controlled by Timer 1 control bits.

Timer 1 : Timer/counter 1 stopped.

TCON : TIMER/COUNTER CONTROL REGISTER

This register is located at address 88H.

Table. 7 TCON SFR (88H)

7

6

5

4

3

2

1

0

TF1

(MSB)

TR1

TF0

TR0

IE1

IT1

IE0

IT0

(LSB)

keep the above table with the following table

P/N:PM0730

REV. 0.1, FEB. 14, 2003

10

MX10F201FC

Table. 8 Description of TCON bits

MNEMONIC POSITION FUNCTION

TF1

TR1

TF0

TCON.7

TCON.6

TCON.5

Timer 1 overflow flag : set by hardware on Timer/Counter overflow. Cleared when

interrupt is processed.

Timer 0 overflow flag : set by hardware on Timer/Counter overflow. Cleared when

interrupt is processed.

Timer 0 overflow flag: set by hardware on Timer/Counter overflow. Cleared when

interrupt is processed.

TR0

IE1

TCON.4

TCON.3

Timer 0 control bit : set/cleared by software to turn Timer/counter ON/OFF.

Interrupt 1 edge flag: set by hardware when external interrupt is detected. Cleared

when interrupt is processed.

IT1

IE0

IT0

TCON.2

TOCN.1

TOCN.0

Interrupt 1 type control bit : set/cleared by software to specify falling edge/LOW

level triggered external interrupt.

Interrupt 0 edge flag: set by hardware when external interrupt is detected. Cleared

when interrupt is processed.

Interrupt 0 type control bit: set/cleared by software tospecify falling edge/LOW

level triggered external interrupt.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

11

MX10F201FC

Interrupt system

The MX10F201FC contains a 8-source 4 external interrupts, Timer 0, Timer1, watch timer and UART structures

with two priority levels.

Each External interrupts INT0, INT1, INT2, and INT3 can be either level-activated or transition-activated depending

on bits IT0 and IT1 in TCON SFR and IT2, IT3 in INTCON SFR. The flags that actually generate these interrupts

are bits IE0, IE1 in TCON and IE2,IE3 in INTCON. When an external interrupt is generated, the corresponding

request flag is cleared by the hardware when the service routine is vectored to, if the interrupt is transition-

activated. If the interrupt is level-activated the external source has to hold the request active until the requested

interrupt is actually generated. Then it has to deactive the request before the interrupt service routine is completed,

otherwise another interrupt will be generated.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective

Timer/counter register (except for Timer 0 in Mode 3 of the serial interface). When a Timer interrupt is generated,

the flag that generated it is cleared by the on-chip hardware when the service routine is vectored to.

IE : INTERRUPT ENABLE REGISTER

This register is located at address A8H.

Table. 9 IE SFR (A8H)

7

6

5

4

3

2

1

0

EA

EX3

EX2

ES

ET1

EX1

ET0

EX0

(LSB)

(MSB)

keep the above table with the following table

Table. 10 Description of IE bits

MNEMONIC POSITION

FUNCTION

Disable all interrupt

- Low, all disabled.

EA

IE.7

- High, each interrupt source is individually enabled or disabled by setting or

clearing its enable bit.

EX3

EX2

ES

IE.6

IE.5

IE.4

Enable / Disable External interrupt 3.

- Low, disabled

- High, enabled

Enable / Disable External Interrupt 2.

- Low, disabled

- High, enabled

Enable / Disable UART interrupt.

- Low, disabled

- High, enabled

ET1

EX1

IE.3

IE.2

Enable / Disable Timer1 overflow interrupt.

Enable / Disable External interrupt 1.

- Low, disabled

- High, enabled

ET0

EX0

IE.1

IE.0

Enable / disable Timer0 overflow interrupt.

Enable / Disable External interrupt 0.

- Low, disabled

- High, enabled

P/N:PM0730

REV. 0.1, FEB. 14, 2003

12

MX10F201FC

IEN1 : INTERRUPT ENABLE REGISTER 2

Table. 11 IEN1 SFR (E8H)

7

6

5

4

3

2

-

1

0

-

EWT

EWT : Enable / Disable Watch Timer interrupt.

IP : INTERRUPT PRIORITY REGISTER

This register is located at address B8H.

Table. 12 IP SFR (B8H)

7

6

5

4

3

2

1

0

-

PX3

PX2

PS

PT1

PX1

PT0

PX0 (LSB)

keep the above table with the following table

Table. 13 Description of IP bits

MNEMONIC POSITION

FUNCTION

RESERVED

-

IP.7

IP.6

PX3

Define External interrupt 3 interrupt priority level.

- High, assign a high priority level.

PX2

IP.5

Define External interrupt 2 interrupt priority level.

- High, assign a high priority level.

PS1

PT1

PX1

IP.4

IP.3

IP.2

Define interrupt priority level of UART.

Define Timer1 overflow interrupt priority level.

Define External interrupt 1 interrupt priority level.

- High, assign a high priority level.

PT0

PX0

IP.1

IP.0

Define Timer0 overflow interrupt priority level.

Define External interrupt 0 interrupt priority level.

- High, assign a high priority level.

IP1 : INTERRUPT PRIORITY REGISTER 2

Table. 14 IP1 SFR (F8H)

7

6

5

4

3

2

1

0

-

PWT

0

PWT : Define Watch Timer interrupt priority level.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

13

MX10F201FC

Table. 15 INTCON SFR (C0H)

7

6

5

4

3

2

1

0

WTF

WTR IE3

IT3

IE2

IT2

Table. 16 Description of INTCON bits

IE3/2 : External interrupt 3/2 edge flag. Set by H/W when exteranl interrupt is detected, and cleared when interrupt

is processed.

IT3/2 : External interrupt 3/2 type control bit. Set/cleared by S/W to specify falling edge/low level triggered external

interrupt.

WTF : Watch timer overflow interrupt flog. Set by H/W when watch timer overflow occurred, and cleared by S/W or

warm/cold reset.

WTR : Watch timer enable bit. Set/ cleared by S/W

Table. 17 INTERRUPT VECTORS & PRIORITY WITHIN LEVELS

source

name

IE0

Priority Within Level

Vector Address

0003H

Ext. interrupt0

Timer0 overflow

Ext. interrupt1

Timer1 overflow

UART interrupt

Ext. interrupt2

Ext. interrupt3

Watch timer overflow

1(Highest)

TF0

IE1

2

3

4

5

6

7

8

000BH

0013H

TF1

IS

001BH

0023H

IE2

002BH

IE3

0033H

WTF

003BH

P/N:PM0730

REV. 0.1, FEB. 14, 2003

14

MX10F201FC

Watch Timer

The watch timer module (see Fig. 6) is clocked by 32.768KHz external crystal, and generates interrupt request

every 0.5 second. This value is derived from f = f / (256x64). The watch timer consists of an 8-bit timer

timer

osc

register WTL and a 6-bit timer registers WTH. The WTL register is triggered by the 32.768KHz external crystal, and

the WTH register increases its value while WTL overflow occurs. When the overflow of WTH occurs, the WTF bit in

SFR INTCON is set High automatically and an interrupt request is sent to the microcontroller.

Both of the timer registers WTL and WTH can be loaded values by software. Therefore the time interval of the

watch timer interrupt request can be adjusted. This allows the watch timer to send interrupt request more frequently

for some special application.

The WTF can be set both by hardware and software, but it can only be cleared by software. The 32.768KHz

external oscillator is gated by the WTR bit in SFR INTCON. If WTR is cleared, the watch timer registers will hold

their values.

In the idle and sleep states the watch timer remains active, and it wakes up the microcontroller while the watch

timer overflow (i.e. WTF is set HIGH) occurs.

Since this module is clocked by the 32.768KHz external crystal, this module is disabled and consumes no power if

there is no such crystal connected to the chip.

Internal Bus

WTH

(6-bit)

Load

WTF

(1-bit)

Load

OSC

32.768K

WTL

(8-bit)

Load

Interrupt

Request

WTR

Write WTF, WTL, WTH

Fig. 6 Watch Timer

P/N:PM0730

REV. 0.1, FEB. 14, 2003

15

MX10F201FC

LCD drivers

The LCD module includes 4 by 32 pixel memory and can drive directly 4 backplanes and 32 segments outputs. Thus,

for common digit-typed LCD, MX10F201FC can have maximum 16 digits display.

LCD Control Register (LCON)

Since MX10F201FC has several possible clocking alternatives : 2 to 16MHz system clock with possible second

32.768KHz sub-system clock, programmers need to set up this register to get proper LCD frame scan rate.

Table. 18 LCON SFR (BAH)

7

6

5

4

3

2

1

0

-

LCDF2 LCDF1 LCDF0 MD1

MD0

Bias

ENLCD

. LCDF2,LCDF1,LCDF0: Selection of LCD frame scan frequency

Table. 19

Frame scan freq (Hz)

Fclk

(ext. clk)

- 000 : 16Mhz Fclk/2^18

- 001 : 12Mhz Fclk/(2^16*3) 61

Divider

Select

1/4 Duty

61

1/3 Duty

81

1/2 Duty

Static

61

64

81

61

- 010 : 8Mhz

- 011 : 4Mhz

- 100 : 2Mhz

- 101 : 1Mhz

Fclk/2^17

Fclk/2^16

Fclk/2^15

Fclk/2^14

61

64

81

61

81

61

81

61

81

61

- 110 :0.5Mhz Fclk/2^13

* - 111 : 32Khz Fclk/2^9

81

61

85

64

* Note : Dual clock mode is set by writing as "111".

. MD1,MD0: Mode bits, determine the LCD multiplex rate.

Table. 20

No of Backplanes

Pixel

32

Digits

4

- 00 : static

- 01 : 1:2

- 10 : 1:3

- 11 : 1:4

1 (BP0)

2 (BP0,1)

3 (BP0,1,2)

4 (BP0,1,2,3)

64

8

96

12

16

128

. Bias: set LCD voltage bias generator.

- High, bias is 1/2(VLCD-VSS)

- Low, bias is 1/3(VLCD-VSS)

P/N:PM0730

REV. 0.1, FEB. 14, 2003

16

MX10F201FC

Table. 21

LCD Drive Mode No of BPs

LCD Bias

static

1/2

Voff(rms)

0

Von(rms)

1

Contrast

infinity

2.236

static

1

2

3

4

1:2

1:3

1:4

0.354

0.333

0.791

0.745

0.638

0.577

1/3

2.236

1/3

1.915

1/3

1.732

. ENLCD: Enable/Disable LCD

- Low, all segment and backplanes drivers are set to the Vss level.

- High, the LCD is enable and digits display is possible.

LCD segment display register : contain the on/off information of 4 by 32 segments of LCD

Table. 22

Register Address

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

LCD0

LCD1

LCD2

LCD3

LCD4

LCD5

LCD6

LCD7

LCD8

LCD9

LCDA

LCDB

LCDC

LCDD

LCDE

LCDF

BBH

BCH

BDH

BEH

BFH

C1H

C2H

C3H

C4H

C5H

C6H

C7H

D1H

D2H

D3H

D4H

SEG1

SEG0

SEG3

SEG2

SEG5

SEG4

SEG7

SEG6

SEG9

SEG8

SEG11

SEG13

SEG15

SEG17

SEG19

SEG21

SEG23

SEG25

SEG27

SEG29

SEG31

SEG10

SEG12

SEG14

SEG16

SEG18

SEG20

SEG22

SEG24

SEG26

SEG28

SEG30

BP3

BP2

BP1

BP0

BP3

BP2

BP1

BP0

LCD drive mode waveform : used to control the voltage level of backplane and segment outputs

. Static drive mode

. 1:2 multiplex drive mode with 1/2 bias

. 1:2 multiplex drive mode with 1/3 bias

. 1:3 multiplex drive mode with 1/3 bias

. 1:4 multiplex drive mode with 1/3 bias

P/N:PM0730

REV. 0.1, FEB. 14, 2003

17

MX10F201FC

SEG0

SEG1

SEG6

SEG5

SEG4

SEG3

SEG2

SEG7

COM0

ENLCD

SEG0

-- VLCD

display data area

address

-- VSS

-- VLCD

-- VSS

BBH

BCH

BDH

BEH

***0 ***1

***1 ***1

***1 ***0

***0 ***1

SEG4

SEG7

COM0

-- VLCD

-- VSS

(Note) *: don't care

-- VLCD

-- VSS

-- VLCD

-

COM0-SEG0

(Selected)

-

-- -VLCD

-- VLCD

-

0

-

COM0-SEG4

(Non-Selected)

-- -VLCD

Fig. 7 Static Drive

P/N:PM0730

REV. 0.1, FEB. 14, 2003

18

MX10F201FC

COM0

COM1

SEG0

SEG3

SEG2

SEG1

ENLCD

SEG0

-- VLCD

display data area

address

-- VSS

BBH

BCH

**01 **01

**11 **10

-- VLCD

SEG1

SEG2

-- VSS

(Note) *: don't care

-- VLCD

-- VSS

-- VLCD

-

SEG3

-- VSS

-- VLCD

-- VSS

COM0

COM1

-- VLCD

-- VSS

-- VLCD

-

0

-

COM0-SEG1

(Selected)

-- VSS

-- VLCD

-

0

-

COM0-SEG2

(Non-Selected)

-- VSS

Fig. 8 1/2 Duty (1/2 Bias) Drive

P/N:PM0730

REV. 0.1, FEB. 14, 2003

19

MX10F201FC

COM0

COM1

SEG0

SEG3

SEG2

SEG1

ENLCD

-- VLCD

-

SEG0

SEG1

-- VSS

-- VLCD

-

-- VSS

-- VLCD

-

SEG2

SEG3

-- VSS

display data area

address

-- VLCD

-

BBH

BCH

**01 **01

**11 **10

-- VSS

-- VLCD

-

COM0

COM1

-- VSS

-- VLCD

-

-- VSS

-- VLCD - VSS

-

COM0-SEG1

(Selected)

0

-

-- -(VLCD -

VSS)

-- VLCD -

VSS

-

COM0-SEG2

(Non-Selected)

0

-

-- -(VLCD -

VSS)

Fig. 9 1/2 Duty (1/3 Bias) Drive

P/N:PM0730

REV. 0.1, FEB. 14, 2003

20

MX10F201FC

SEG1

SEG0

SEG2

COM0

COM1

COM2

ENLCD

SEG0

-- VLCD

-- VSS

-- VLCD

-- VSS

SEG1

SEG2

-- VLCD

-- VSS

display data area

address

BBH

BCH

*111 *010

**** **01

-- VLCD

-

-- VSS

COM0

(Note) *: don't care

-- VLCD

-

-- VSS

COM1

COM2

-- VLCD

-

-- VSS

-- VLCD

-

COM0-SEG1

(Selected)

0

-

-- -VLCD

-- VLCD

-

COM0-SEG2

(Non-Selected)

0

-

-- -VLCD

Fig. 10 1/3 Duty (1/2 Bias) Drive

P/N:PM0730

REV. 0.1, FEB. 14, 2003

21

MX10F201FC

SEG1

SEG0

SEG2

COM0

COM1

COM2

ENLCD

SEG0

-- VLCD

-

-- VSS

-- VLCD

-

SEG1

-

display data area

address

-- VSS

-- VLCD

-

BBH

BCH

*111 *010

**** **01

SEG2

COM0

-

-- VSS

-- VLCD

-

(Note) *: don't care

-

-- VSS

-- VLCD

-

COM1

COM2

-- VSS

-- VLCD

-

-- VSS

-- VLCD

-

COM0-SEG1

(Selected)

0

-

-- -VLCD

-- VLCD

-

COM0-SEG2

(Non-Selected)

0

-

-- -VLCD

Fig. 11 1/3 Duty (1/3 Bias) Drive

P/N:PM0730

REV. 0.1, FEB. 14, 2003

22

MX10F201FC

COM0

COM1

SEG1

COM2

COM3

SEG0

ENLCD

SEG0

-- VLCD

-

-- VSS

-- VLCD

-

SEG1

COM0

-

-- VSS

-- VLCD

-

-- VSS

-- VLCD

display data area

address

-

COM1

COM2

-- VSS

BBH

10110101

-- VLCD

-

-- VSS

-- VLCD

-

COM3

-- VSS

-- VLCD

COM0-SEG0

(Selected)

-

0

-

-- -VLCD

-- VLCD

-

COM0-SEG1

(Non-Selected)

0

-

-- -VLCD

Fig .12 1/4 Duty (1/3 Bias) Drive

P/N:PM0730

REV. 0.1, FEB. 14, 2003

23

MX10F201FC

Power saving modes : active power control, idle, sleep and power down modes

In order to enable lowest power consumption in system application, MX10F201FC has user friendly power control

mechanism as follows :

1) Active power control : used to turn off un-used peripherals in specific applications. For instance, UART might

not be used in audio CD application, then programmer can disable it to save power.

2) Idle mode : used to turn off 80C51 during certain conditions.

3) Sleep mode : used to turn off the whole system except LCD and possibly watch Timer.

4) Power down mode : turn off the whole system.

PCON : Power Control Register (PCON)

PCON SFR (87H)

7

6

5

4

3

2

1

0

SMOD -

SCEER WLE CF1

CF0 PD

IDC

SMOD : Doubl band rate bit for UART.

SLEEP : Sleep mode bit. Setting it activates sleep mode, and could be terminated as the way to terminate the pull

down mode.

WLE : Watch dog load enable. This flag must be set prior to loading WDT and is cleaned when WDT is loaded.

CF1/CF0 : general-prepose flag bit.

PD : Power - down bit. Setting it activates power - down mode.

IDL : idle mode bit. Setting it activates idle mode.

Active power control mode

PCON1 : POWER CONTROL REGISTER 2

Table. 23 PCON1 SFR (F1H)

7

6

5

4

3

2

1

0

-

TD

UARTD WDTD PWMD

1

WTD LCDD

Table. 24 Description of PCON1 bits

. TD : Timer0/1 Disable bit. Setting it to shut-down Timer0/1.

. UARTD: UART Disable bit. Setting it to shut-down UART.

. WDTD : WatchDog Timer Disable bit. Setting it to shut-down WDT.

. PWMD : Pulse Width Modulation Disable bit. Setting it to shut-down PWM.

. WTD : Watch Timer Disable bit, Setting it to shu-down W T.

. BIT 2 must write "1"

. LCDD : LCD Disable bit. Setting it to shut-down all LCD relative modules.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

24

MX10F201FC

RC oscillator function

MX10F201FC provides a RC oscillator function for the application that does not need very accurate system clock

frequency and has to save the cost of crystal oscillator. As shown in Fig. 13, to use the RC oscillator function as

the system clock source, a suggested 50K~200K can be connected between the RCP pin and ground. The XTAL1

pin has to be connected to ground or the internal clock system may be failed. When the system clock source

comes from the crystal oscillator, the RCP pin is suggested to connect to VDD. The following table shows

approximately the relationship between the RC oscillator clock frequency and the resistor value.

Table. 25 RC oscillator reference table

Resistor Value (K ohm)

RC oscillator clock frequency (MHz)

5V

3V

50

75

12~14

10~12

9~10

8~9

9~11

7.5~9

6.5~8

6~7.5

5.5~6.5

5.2~5.8

4.7~5.3

100

125

150

175

200

~7.5

~6.5

~6

XTAL1

XTAL2

RCP

VDD

Resistor

RCP

(a)

(b)

Fig. 13 System clock connection way : (a) Use RC oscillator as system

clock source, (b) Use crystal oscillator as system clock source.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

25

MX10F201FC

Clock system

MX10F201FC has two possible clocking schemes with four combinations as follows :

System clock

Sub-system clock

Single clock mode

External 2 ~ 16MHz crystal (XTAL1,XTAL2)

RC oscillator with external resister (RCP)

and XTAC1 is connected to GND

External 2 ~ 16MHz crystal (XTAL1,XTAL2)

RC oscillator with external resister (RCP)

and XTAC1 is connected to GND

XTAL3 is connected to GND

Dual clock mode

32.768KHzcrystal (XTAL3,XTAL4)

32.768KHz crystal (XTAL3,XTAL4)

The interaction between power saving modes and clock system is listed as follows :

Single clock

Dual clock

80C51

System clock

Timer0/1, WDT, UART

LCD

System clock

Sub-system clock

Active mode

All are active except watch Timer

All are active

Power control active mode Individual peripheral is disabled by

corresponding active power control bit

Individual peripheral is disabled by

corresponding active power control bit

1) 80C51 is stopped

Idle mode

1) 80C51 is stopped

2) can be wake up by any interrupt

1) All are stopped except LCD, system

oscillator.

2) can be wake up by any interrupt

1)All are stopped except watch Timer,

LCD, sub-system oscillator.

2) can be wake up by external

interrupts,watch Timer or RESET

1) All are stopped

Sleep mode

2) can be wake up by external interrupts,

Power down mode

1)All are stopped

2) can be wake up by external interrupts

or RESET

2) can be wake up by external

interrupts or RESET

P/N:PM0730

REV. 0.1, FEB. 14, 2003

26

MX10F201FC

Watchdog Timer

The Watchdog Timer (WDT) see Fig.14 , consists of an 11-bit prescaler and an 8-bit Timer formed by SFR T3. The

Timer is incremented every 1.5 ms, derived from the system clock frequency of 16 MHz by the following formula :

= f / (12 x (2048)). The 8-bit Timer increments every 12 x 2048 cycles of the on-chip oscillator. When a Timer

f

Timer

clk

overflow occurs, the microcontroller is reset. The internal RESET signal is not inhibited when the external RST pin

is kept 0 into high impedance, no matter if the XTAL-clock is running or not.

To prevent a system reset the Timer must be reloaded in time by the application software. If the processor suffers

a hardware / software malfunction, the software will fail to reload the Timer. This failure will result in an overflow

thus prevent the processor from running out of control. This time interval is determined by the 8-bit reload value

that is written into register T3.

Watchdog time interval = [T3] x 12 x 2048 / oscillator frequency

The watch-dog Timer can only be reloaded if the condition flag WLE (SFR PCON bit 4) has been previously set

high by software. At the moment the counter is loaded WLE is automatically cleared.

In the idle state the watchdog Timer and reset circuitry remain active.

The watchdog Timer is controlled by the watchdog enable signal EW (SFR EBTCON bit 1). A LOW level enables

the watchdog Timer. A HIGH level disable the watchdog Timer.

Internal Bus

Timer T3

(8-bit)

Prescaler

(11-bit)

f

CLK/12

to reset circuitry

LOAD LOADEN

Clear

Write T3

Clear

WLE

PD

LOADEN

PCON. 4

PCON. 1

EW

Internal Bus

Fig. 14 Watchdog Timer T3

P/N:PM0730

REV. 0.1, FEB. 14, 2003

27

MX10F201FC

Pulse Width Modulated Outputs

The MX10F201FC contains two pulse width modulated output channels (see Figure. 15). These channels generate

pulses of programmable length and interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which

supplies the clock for the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter

counts modulo 255, i.e., from 0 to 254 inclusive. The value of the 8-bit counter is compared to the contents of two

registers: PWM0 and PWM1. Provided the contents of either of these registers is greater than the counter value,

the corresponding PWM0 or PWM1 output is set LOW. If the contents of these registers are equal to, or less than

the counter value, the output will be HIGH. The pulse-width-ratio is therefore defined by the contents of the

registers PWM0 and PWM1. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments

of 1/255.

Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be proportional to

the contents of PWMn. The PWM outputs may also be configured as a dual DAC. In this application, the PWM

outputs must be integrated using conventional operational amplifier circuitry. If the resulting output voltages have

to be accurate, external buffers with their own analog supply should be used to buffer the PWM outputs before

they are integrated. The repetition frequency f , at the PWMn outputs is give by :

PWM

f

OSC

f

=

PWM

2 x (1 + PWMP) x 255

This gives a repetition frequency range of 123Hz to 31.4KHz (f = 16MHz). At f = 24MHz, the frequency range

OSC

is 184Hz to 47.1KHz. By loading the PWM registers with either 00H or FFH, the PWM channels will output a

constant HIGH or LOW level, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach

the value of the PWM registers when they are loaded with FFH.

When a compare register (PWM0 or PWM1) is loaded with a new value, the associated output is updated

immediately. It does not have to wait until the end of the current counter period. Both PWMn output pins are driven

by push-pull drivers. These pins are not used for any other purpose.

The PWM function is enabled by setting SPR EBTCON bit 2,3. After reset, SFR EBTCON bit 2,3 need to be set to

use P1.4 or P1.5 as the PWM output, otherwise P1.4& P1.5 are general I/O ports.

Prescaler frequency control register PWMP

Reset Value = 00H

PWMP (FEH)

7

6

5

4

3

2

1

0

MSB

Prescaler dividsion factor = PWMP +1.

LSB

PWMP.0-7

Reading PWMP gives the current reload value. The actual count of the prescaler cannot be read.

Reset Value = 00H

PWM0 (FCH)

7

6

5

4

3

2

1

0

PWM1 (FDH) MSB

LSB

(PWMn)

PWM0/1.0-7} Low/high ratio of PWMn =

255 - ( PWMn)

EBTCON SFR (EBH)

7

6

5

4

3

2

1

0

-

PWM1E PWM0E /EW

-

PWM1E : Selection of P1.4 function as either PWM output or a port line, After reset PWM1E bit is low, and P1.4

is a normal port line.

PWM0E : Selection of P1.5 function as either PWM output or a port line, After reset PWM0E bit is low, and P1.5

is a normal port line.

/EW : After reset, /EW bit is set, and WDT is disable.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

28

MX10F201FC

PWM0

OUTPUT

BUFFER

8-BIT COMPARATOR

8-BIT COUNTER

8-BIT COMPARATOR

PWM0

t

OSC

1/2

PRESCALER

PWMP

OUTPUT

PWM1

BUFFER

PWM1

Fig. 15 Functional Diagram of Pulse Width Modulated Outputs

P/N:PM0730

REV. 0.1, FEB. 14, 2003

29

MX10F201FC

UART

This module is fully compatible to standard 80C51's UART.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

30

MX10F201FC

MTP Program Memory

Features

- 16 kilobyte electrically erasable internal MTP program momory.

- Programming and erasing voltage 12 Volt

- MTP (re) programming mechanism :

- EPROM like parallel programming protocol

- Parallel programming :

- Byte programming (8 us typical)

- Chip erase less than 0.5 second typical

- 100 minimum erase/program cycles

- Advanced CMOS flash memory technology

- One security bit to protect internal ROM code.

General Description

MX10F201FC's MTP memory stores memory contents even after 100 erase and program cycles. The cell is

designed to optimize the erase and programming mechanisms. In addition, the combination of advanced tunnel

oxide processing and low internal electric fields for erase and programming operations produces reliable cycling.

The MX10F201FC uses 12 Volt VPP supply to perform the Program/Erase algorithms.

PROGRAMMING AND PROGRAM VERIFY

MX10F201FC is byte programmable by using 10us programming pulse and it requires separate program verify

pulse to read out the data to check if program is ok or not. The typical programming time for each 1k bytes is

about 10ms at room temperature.

P/N:PM0730

REV. 0.1, FEB. 14, 2003

31

MX10F201FC

PROGRAMMING SPECIFICATION

Parallel Programming Mode

The parallel programming works in EPROM-like programming protocol. The MX10F201FC MTP provides 100 times

cycles endurance. And the MX10F201FC MTP needs a 11.5~12.5 Volt VPP supply to perform the Program/Erase

operation. Specially note that LOCK 2 is used to security protection. So if LOCK 2 bit is programmed, then PGMVFY,

ERSVFY and normal READ are disabled from parallel programming mode. LOCK 1 and LOCK 3 are not used in this

chip.

4.5/5.5V

VDD

1

0000

RESET

BP[3:0]

VPP

XTAL1

XTAL2

11.5V ~ 12.5V

PCEB

P33

MX10F201FC

POEB

P27

PWEB

P32

A[13:0]

P2[5:0] P1[7:0]

P0[7:0]

Q[7:0]

MS[3:0]

P26, P37, P31, P30

VSS

Table. 26 Pin Description

PIN NAME

SYMBOL

FUNCTION

P25~P20, P17~P10

PA13~PA8, PA7~PA0

Q[7:0]

Address Input

P07~ P00

Data Input/Output

Chip Enable Input

Output Enable Input

Write Enable Input

Program Supply Voltage

Flash Mode Selection

Power Supply Voltage (5V)

Ground Pin

P33

PCEB

P27

POEB

P32

PWEB

VPP

P26, P37, P31, P30

MS[3:0]

VDD

VSS

GND

P/N:PM0730

REV. 0.1, FEB. 14, 2003

32

MX10F201FC

Table. 27 parallel programming modes

External

EA

P33

P27

P32

P2[5:0]

P1[7:0]

PCEB POEB PWEB PA[13:0]

P26, P37, P0[7:0]

P0[7:0]

P31, P30

Module I/O

PVPP

MS[3:0]

PUOUT[7:0]

PDOUT[7:0]

FF,00

DI or

DIA

X

Lock[3:1]

Standby

12V

1

0

X

0

1

X

Normal Read

Initialize

1

PA[13:0]

0000

1110

Data

Z

0.5sec X

pulse

FF,00

X

000

Chip Erase

Program

12V

0

1

0.5sec X

pulse

0001

0011

FF,00

X

10us

pulses

1

PA[13:0]

D[7:0]

Erase Verify

Program Verify

Pgm LOCK

12V

0

1

PA[13:0]

PA[1:0]

0100

0101

0110

Data

FF,00

Z

X

1

10us

pulse

1

Lock[i]

0 ->1

Erase Verify

LOCK

12V

0

PA[1:0]=00 1001

PA[1:0]=00 1011

LOCK[3:1]

MftID(C2H)

Z

Pgm Verify

LOCK

1

Read Mft ID

0

1

PA[1:0]=00 1111

PA[1:0]=01 1111

Read DeviceID 12V

DeviceID(0DH) Z

Note : 1. Program lock bits, program LOCK [1] to be 1 if PA [1:0] = 00

Program lock bits, program LOCK [2] to be 1 if PA [1:0] = 01

Program lock bits, program LOCK [3] to be 1 if PA [1:0] = 1x

2. Verify erased LOCK bits if PA [1:0] = 00

3. Verify programmed LOCK bits if PA [1:0] = 00

4. Read Manufacture ID, Device ID

PA [1:0] = 00 : Manufacture ID (C2H)

PA [1:0] = 01 : Device ID (0DH)

P/N:PM0730

REV. 0.1, FEB. 14, 2003

33

MX10F201FC

PROGRAM AND PROGRAM VERIFY FLOWCHART

START

First Address

VDD= 5V

VPP = 12V

X=0

Program One

10us pulse

No

Program

Verify

Fail

x=x+1

X=20

YES

No

Increment

Address

Last

Address

Yes

YES

Fail

Fail Device

Normal Read All

Pass

Pass Device

P/N:PM0730

REV. 0.1, FEB. 14, 2003

34

MX10F201FC

ERASE and VERIFY FLOWCHART

START

X = 0

VDD= 5V

VPP = 12V

Program array all zero

(0 ~ 16KB) & LOCK

Chip Erase

(0.5s)

No

Erase Verify

LOCK

fail

=>

x=x+1

Erase Verify Array

(16KB)

X = 30

Yes

pass

Pass Device

Fail Device

P/N:PM0730

REV. 0.1, FEB. 14, 2003

35

MX10F201FC

PROGRAM LOCK AND PROGRAM VERIFY LOCK FLOWCHART

START

LOCK Address PA [1:0]

VDD= 5V

VPP = 12V

X=0

Program LOCK

10us pulse

No

Program

Verify LOCK

Fail

x=x+1

X=20

Yes

Pass

Fail Device

Pass Device

P/N:PM0730

REV. 0.1, FEB. 14, 2003

36

MX10F201FC

A. Timing diagram of Read signature and Normal read operations

VPP

WEB

ADDRESS

A 0=0 / A 0=1

tAA

CEB

OEB

tDF

tCE

tOE

MS[3:1]

tMSCE

DATA

Mfg ID / Device ID

OUT

tAA

tCE

tOE

tDF

0

tMSCE

Min.

100

Max.

unit

130

ns

130

ns

50

ns

20

ns

P/N:PM0730

REV. 0.1, FEB. 14, 2003

37

MX10F201FC

B. Timing Diagram of Erase and Erase Verify Array Operation

tVPS

2

tMS

200

tCES

100

tER

100

tEW

0.5

tEV

tMSCE

100

Min.

Max.

unit

200

ns

us

ns

s

ns

P/N:PM0730

REV. 0.1, FEB. 14, 2003

38

MX10F201FC

C. Timing Diagram of Erase and Erase Verify LOCK Operation

tVPS

2

tMS

200

tCES

100

tER

100

tEW

0.5

tEV

tMSCE

100

Min.

Max.

unit

200

ns

us

ns

s

ns

P/N:PM0730

REV. 0.1, FEB. 14, 2003

39

MX10F201FC

D. Timing Diagram of Program and Program Verify Operation

tAS

100

tDS

100

tDH

100

tVPS

2

tCES

100

tMS

200

tPR

100

tPW

8

tPV

tMSCE

100

Min.

Max.

unit

200

ns

us

ns

us

ns

P/N:PM0730

REV. 0.1, FEB. 14, 2003

40

MX10F201FC

E. Timing Diagram of Program LOCK and Program Verify LOCK Operation

PA [1:0]

PA [1:0] =00

0110

1011

tAS

100

tDS

100

tDH

tVPS

2

tCES

100

tMS

200

tPR

100

tPW

8

tPV

tMSCE

100

Min.

Max.

unit

100

200

ns

us

ns

us

ns

Note : OUT = { xxxx, LOCK [3], LOCK [2], LOCK [1], x}

P/N:PM0730

REV. 0.1, FEB. 14, 2003

41

MX10F201FC

Limiting Value

SYMBOL

VDD

PARAMETER

MIN

4.5

-0.5

0

MAX

5.5

UNIT

V

Supply voltage

Vi

Input voltage (all inputs)

Voltage on VPP pin to VSS

Maximum IOL per I/O pin

Storage temperature

VDD + 0.5

13

V

VPP

V

I

15

mA

^OC

OL(max)

Tstg

-65

0

150

Tamb

Operating ambient temperature(for all devices)

70

DC ELEECTRICAL CHARACTERISTICS

SYMBOL

Supply

VDD

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

Normal operation supply voltage

Operation supply current

4.5

5.5

20

V

I

f

=16MHZ

=12MHZ

=4MHZ

10

8

mA

DD

OSC

4

I

Supply current in idle mode

=16MHZ

=12MHZ

=4MHZ

8

12

ID

6

2

I

SLP

Supply current in single sleep mode

Supply current in dual sleep mode

Supply current in power-sown mode

=16MHZ

=12MHZ

=4MHZ

4

8

mA

uA

3

1

I

=16MHZ

=12MHZ

=4MHZ

50

45

25

1

100

DSLP

I

=16MHZ

=12MHZ

=4MHZ

30

PD

1

Inputs

R

Input resistance RESET

Input leakage current; RESET

Input high voltage to

VDD=4.5V to 5.5V

VDD=5V

15

100

120

kohm

uA

INP

I

L

V

IH1

0.7VDD

VDD+0.5 V

XTAL1, XTAL3, RESET

PORTS P0~P3

V

Input low voltage

-0.5

0.2VDD-0.1 V

VDD+0.5 V

IL

V

IH

Input high voltage, except

XTAL1, XTAL3, RST

0.2VDD

+0.9

-1

I

IL

Logical 0 input current

Logical 1 to 0 transition current

VIN=0.4V, VDD=5V

VIN=2.0V

-100

-650

uA

I

TL

P/N:PM0730

REV. 0.1, FEB. 14, 2003

42

MX10F201FC

Outputs : P0~P3

SYMBOL

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

V

OL

Output low voltage

VDD=4.5V, I =1.6mA

OL

0.4

V

Output high voltage

VDD=4.5V, I =- 3.3mA VDD-0.7

OH

V

OH

I

Low level output sink current

High level pull-up output source current

Strong pull-up

V <0.4V, VDD=5V

O

10

13

mA

OL

I

OH

V =VDD-0.4V, VDD=5V

O

4

6

mA

uA

pF

Weak pull-up

V =VDD-0.4V, VDD=5V 15

O

30

C

Pin capacitance (except EA)

15

IO

LCD DRIVER CHARACTERISTICS

SYMBOL

Supply

VLCD

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

LCD operation supply voltage

DC voltage component; all backplane

and segment drivers

4.5

VDD

100

V

VSS

mV

LCD driver outputs

Output impedance BP0~BP3

Output impedance S0~S31

LCD scan frequency

R

6

20

kohm

Hz

BP

R

S

f

Ratio: 1:1, 1:2, 1:4

Ratio: 1:3

61

81

LCD

Hz

P/N:PM0730

REV. 0.1, FEB. 14, 2003

43

MX10F201FC

RCP OSCILLATOR CHARACTERISTICS

5.5

5

4.5

3.3

7.4

3

2.7

100kohm

40kohm

9.36 9.19 8.7

6.48 6.15

15.98 14.81 14.29 10.95 10.12 8.99

Fosc - Vdd

20

15

100Kohm

40Kohm

MHz 10

5

0

5.5

5

4.5

3.3

3

2.7

V

AC CHARACTERISTICS

SYMBOL

System (CPU) clock

fC Oscillator frequency

32.768KHz LCD Oscillator

32.768KHz Oscillator frequency

PARAMETER

CONDITIONS

MIN. TYP. MAX. UNIT

2

16

MHz

KHz

f

32.768

xtal

P/N:PM0730

REV. 0.1, FEB. 14, 2003

44

MX10F201FC

PACKAGE INFORMATION

100-PIN PQFP

A

B

ITEM

A

MILLIMETERS

24.80 ± .40

20.00 ± .13

14.00 ± .13

18.80 ± .40

12.35 [REF]

.83 [REF]

INCHES

.976 ± .016

.787 ± .005

.551 ± .005

.740 ± .016

.486 [REF]

.033 [REF]

.023 [REF]

.012 [Typ.]

.026 [Typ.]

.094 [Typ.]

.047 [Typ.]

.006 [Typ.]

.004 max.

.108 ± .006

.004 min.

B

C

D

E

80

81

51

50

F

G

H

I

.58 [REF]

E

C

D

.30 [Typ.]

.65 [Typ.]

2.40 [Typ.]

1.20 [Typ.]

.15 [Typ.]

.10 max.

J

K

31

100

1

P

L

03

F

M

N

O

P

O

2.75 ± .15

.10 min.

G

H

I

3.30 max.

.130 max.

J

NOTE: Each lead centerline is located within

.25mm[.01 inch] of its true position [TP] at a

maximum material condition.

N

L

M

K

P/N:PM0730

REV. 0.1, FEB. 14, 2003

45

MX10F201FC

REVISION

DESCRIPTION

PAGE

DATE

0.1

Modify Table. 15 INTCON SFR (C8H) --> (C0H)

P14

SEP/06/2002

P/N:PM0730

REV. 0.1, FEB. 14, 2003

46

MX10FM201FC

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX10F201FC
厂家：	MACRONIX INTERNATIONAL
描述：	High-Performance and Low Power Microcontroller designed for Use Many Applications 高性能和低功耗微控制器设计用于多种应用微控制器
文件：	总47页 (文件大小：244K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX10F201FC [Macronix]

相关型号：

MX10F202FC

MX10F203FC

MX10FMAXDPC

MX10FMAXDPCG

MX10FMAXDQC

MX10FMAXDQCG

MX10L8050FC

MX10L8050FI

MX10L8050PC

MX10L8050PI

MX10L8050QC

MX10L8050QI