MX25L12805DMI-20G [Macronix]
128M-BIT [x 1] CMOS SERIAL FLASH; 128M - BIT [ ×1 ] CMOS串行FLASH
| 型号： | MX25L12805DMI-20G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 128M-BIT [x 1] CMOS SERIAL FLASH |
| 文件： | 总42页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25L12805D
128M-BIT [x 1] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure
• 4096 equal sectors with 4K byte each
256 equal sectors with 64K byte each
- Any sector can be erased
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.5V to 2.5V
PERFORMANCE
• High Performance
- Fast access time: 50MHz serial clock (30pF + 1TTL Load)
- Fast program time: 1.4ms/page (typical, 256-byte per page) and 9us/byte (typical)
- Fast erase time: 60ms/sector (4KB per sector), 0.7s/block (64KB per block) and 80s/chip
- Acceleration mode:
- Chip erase time: 50s (typical)
• Low Power Consumption
- Low active read current: 25mA (max.) at 50MHz
- Low active programming current: 20mA (max.)
- Low active erase current: 20mA (max.)
- Low standby current: 20uA (max.)
-Deeppower-downmode20uA(max.)
• Typical100,000erase/programcycle
• 10 years data retention
SOFTWAREFEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions
- Additional 512-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector
- Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
• Status Register Feature
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte Device ID
- RES command, 1-byte Device ID
- REMS command, ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
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MX25L12805D
HARDWAREFEATURES
• SCLK Input
- Serial clock input
• SI Input
- Serial Data Input
• SO
- Serial Data Output
• WP#/ACC Pin
- Hardware write protection and Program/erase acceleration
• HOLD# pin
- pause the chip without diselecting the chip
• PACKAGE
- 16-pin SOP (300mil)
- All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
TheMX25L12805DisaCMOS134,217,728bitserialFlashMemory,whichisconfiguredas16,777,216x8internally.The
MX25L12805Dfeaturesaserialperipheralinterfaceandsoftwareprotocolallowingoperationonasimple3-wirebus. The
three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the
device is enabled by CS# input.
The MX25L12805D provides sequential read operation on whole chip. User may start to read from any byte of the array.
While the end of the array is reached, the device will wrap around to the beginning of the array and continuously outputs
data until CS# goes high.
Afterprogram/erasecommandisissued,autoprogram/erasealgorithmswhichprogram/eraseandverifythespecifiedpage
locationswillbeexecuted. Programcommandisexecutedonbytebasis,orpage(256bytes)basis,anderasecommand
is executed on sector (4K-byte), or block(64K-byte), or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for more
details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 20uA DC current.
The MX25L12805D utilizes MXIC's proprietary memory cell which reliably stores memory contents even after 100,000
program and erase cycles.
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MX25L12805D
PIN CONFIGURATIONS
16-PIN SOP (300 mil)
PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
SI
Chip Select
Serial Data Input
SCLK
SI
HOLD#
1
16
15
14
13
12
11
10
9
SO
Serial Data Output
Clock Input
VCC
2
SCLK
HOLD#
NC
NC
3
NC
NC
4
Hold, to pause the serial communication
NC
NC
5
WP#/ACC Write Protection: connect to GND;
11Vforprogram/eraseacceleration:
connect to 11V
NC
NC
6
GND
WP#/ACC
CS#
7
SO
8
VCC
GND
NC
+ 3.3V Power Supply
Ground
NoInternalConnection
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MX25L12805D
BLOCK DIAGRAM
Address
Generator
Memory Array
Data
Register
SI
Y-Decoder
SRAM
Buffer
Output
Buffer
Sense
Amplifier
Mode
Logic
State
Machine
CS#, ACC,
WP#,HOLD#
HV
Generator
SO
SCLK
Clock Generator
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DATA PROTECTION
TheMX25L12805Daredesignedtoofferprotectionagainstaccidentalerasureorprogrammingcausedbyspurioussystem
level signals that may exist during power transition. During power up the device automatically resets the state machine
in the Read mode. In addition, with its control register architecture, alteration of the memory contents only occurs after
successful completion of specific command sequences. The device also incorporates several features to prevent
inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
•
Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset and
tPUW (internal timer) may protect the Flash.
• Validcommandlengthchecking:Thecommandlengthwillbecheckedwhetheritisatbytebaseandcompletedonbyte
boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other
command to change data. The WEL bit will return to reset stage under following situation:
-Power-up
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
•
•
•
Software Protection Mode (SPM): by using BP0-BP3 bits to set the part of Flash protected from data change.
HardwareProtectionMode(HPM):byusingWP#goinglowtoprotecttheBP0-BP3bitsandSRWDbitfromdatachange.
DeepPowerDownMode:Byenteringdeeppowerdownmode,theflashdevicealsoisunderprotectedfromwritingall
commandsexceptReleasefromdeeppowerdownmodecommand(RDP)andReadElectronicSignaturecommand
(RES).
•
AdvancedSecurityFeatures:therearesomeprotectionandsecuruityfeatureswhichprotectcontentfrominadvertent
write and hostile access.
I. Block lock protection
- TheSoftwareProtectedMode(SPM)use(BP3, BP2, BP1, BP0)bitstoallowpartofmemorytobeprotectedasread
only. The proected area definition is shown as table of "Protected Area Sizes", the protected areas are more flexible
which may protect various area by setting value of BP0-BP3 bits.
Please refer to table of "protected area sizes".
- The Hardware Proteced Mode (HPM) use WP#/ACC to protect the (BP3, BP2, BP1, BP0) bits and SRWD bit.
II. Additional 512-bit secured OTP for unique identifier: to provide 512-bit one-time program area for setting device
unique serial number - Which may be set by factory or system customer. Please refer to table 3. 512-bit secured OTP
definition.
- Security register bit 0 indicates whether the chip is locked by factory or not.
-Toprogramthe512-bitsecuredOTPbyentering512-bitsecuredOTPmode(withENSOcommand),andgoingthrough
normal program procedure, and then exiting 512-bit secured OTP mode by writing EXSO command.
-Customermaylock-downthecustomerlockablesecuredOTPbywritingWRSCUR(writesecurityregister)command
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MX25L12805D
to set customer lock-down bit1 as "1". Please refer to table of "security register definition" for security register bit
definition and table of "512-bit secured OTP definition" for address range definition.
-Note:Oncelock-downwhateverbyfactoryorcustomer,itcannotbechangedanymore.Whilein512-bitsecuredOTP
mode, array access is not allowed.
512-bitSecuredOTPDefinition
Addressrange
xxxx00~xxxx0F
xxxx10~xxxx3F
Size
Standard
Factory Lock
CustomerLock
128-bit
384-bit
ESN (electrical serial number)
Determinedbycustomer
N/A
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Table 1. Protected Area Sizes
Statusbit
ProtectionArea
BP3 BP2
BP1
1
BP0
1
128Mb
All
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
All
0
1
All
0
0
All
1
1
All
1
0
All
0
1
All
0
0
Upper half (hundrend and twenty-eight sectors: 128 to 255)
Upper quarter (sixty-four sectors: 192 to 255)
Upper eighth (thirty-two sectors: 224 to 255)
Upper sixteenth (sixteen sectors: 240 to 255)
Upper 32nd (eight sectors: 248 to 255)
Upper 64th (four sectors: 252 to 255)
Upper 128th (two sectors: 254 and 255)
Upper 256th (one sector: 255)
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
None
Note:
1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP3, BP2, BP1, BP0) are 0.
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HOLD FEATURE
HOLD#pinsignalgoeslowtoholdanyserialcommunicationswiththedevice.TheHOLDfeaturewillnotstoptheoperation
of write status register, programming, or erasing in progress.
TheoperationofHOLDrequiresChipSelect(CS#)keepinglowandstartsonfallingedgeofHOLD#pinsignalwhileSerial
Clock (SCLK) signal is being low (if Serial Clock signal is not being low, HOLD operation will not start until Serial Clock
signal being low). The HOLD condition ends on the rising edge of HOLD# pin signal while Serial Clock(SCLK) signal is
being low( if Serial Clock signal is not being low, HOLD operation will not end until Serial Clock being low), see Figure 1.
Figure 1. Hold Condition Operation
CS#
SCLK
HOLD#
Hold
Condition
(standard)
Hold
Condition
(non-standard)
TheSerialDataOutput(SO)ishighimpedance, bothSerialDataInput(SI)andSerialClock(SCLK)aredon'tcareduring
the HOLD operation. If Chip Select (CS#) drives high during HOLD operation, it will reset the internal logic of the device.
To re-start communication with chip, the HOLD# must be at high and CS# must be at low.
PROGRAM/ERASE ACCELERATION
Toactivatetheprogram/eraseaccelerationfunctionrequiresACCpinconnectingto11Vvoltage(seeFigure2),andthen
to be followed by the normal program/erase process. By utilizing the program/erase acceleration operation, the
performances are improved as shown on table of "ERASE AND PROGRAM PERFORMACE".
Figure 2. ACCELERATED PROGRAM TIMING DIAGRAM
VHH
11V
VIL or VIH
VIL or VIH
ACC
tVHH
tVHH
Note: tVHH (VHH Rise and Fall Time) min. 250ns
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Table 2. COMMAND DEFINITION
COMMAND WREN (write WRDI (write RDID (read
RDSR (read WRSR (write READ (read FAST READ SE (Sector
(byte)
enable)
disable)
identification) status
register)
status
register)
01 (hex)
data)
(fast read
data)
0B (hex)
AD1
AD2
AD3
erase)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
06 (hex
04 (hex)
9F (hex)
05 (hex)
03 (hex)
AD1
AD2
20 (hex)
AD1
AD2
AD3
AD3
X
sets the
resets the
outputs
to read out
to write new n bytes read n bytes read to erase the
(WEL) write (WEL) write JEDEC ID: 1- the values of values to the out until CS# out until CS# selected
enable latch enable latch byte
the status
status
goes high
goes high
sector
bit
bit
manufacturer register
ID & 2-byte
register
device ID
COMMAND
(byte)
BE (block
erase)
CE (chip erase) PP (Page
DP (Deep
power down)
RDP (Release RES (read
REMS (read
electronic
program)
from deep
electronic ID)
power down)
manufacturer &
device ID)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
D8 (hex)
AD1
AD2
60 or C7 (hex) 02 (hex)
B9 (hex)
AB (hex)
AB (hex)
90 (hex)
x
x
AD1
AD2
AD3
x
x
x
AD3
ADD(note 1)
to erase the
selected block chip
to erase whole to program the enters deep
release from
deep power
down mode
to read out 1- outout the
byte device ID manufacturer ID
& device ID
selected page power down
mode
Note 1: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first
COMMAND
(byte)
ENSO (enter
secured OTP)
EXSO (exit secured RDSCUR (read
WRSCUR (write
security register)
OTP)
security register)
1st byte
2nd byte
3rd byte
4th byte
5th byte
Action
B1 (hex)
C1 (hex)
2B (hex)
2F (hex)
to enter the 512-bit to exit the 512-bit
secured OTP mode secured OTP mode security register
to read value of
to set the lock-down
bit as "1" (once
lock-down, cannot
be updated)
Note 2: It is not recommoded to adopt any other code not in the command definition table, which will potentially emter the hidden mode.
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Table 3. Memory Organization
Block
Sector
4095
Address Range
FFF000h FFFFFFh
255
4080
4079
FF0000h FF0FFFh
FEF000h FEFFFFh
254
253
252
251
250
4064
4063
FE0000h FE0FFFh
FDF000h FDFFFFh
4048
4047
FD0000h FD0FFFh
FCF000h FCFFFFh
4032
4031
FC0000h FC0FFFh
FBF000h FBFFFFh
4016
4015
FB0000h FB0FFFh
FAF000h FAFFFFh
4000
FA0000h FA0FFFh
95
05F000h 05FFFFh
5
4
3
2
1
0
80
79
050000h 050FFFh
04F000h 04FFFFh
64
63
040000h 040FFFh
03F000h 03FFFFh
48
47
030000h 030FFFh
02F000h 02FFFFh
32
31
020000h 020FFFh
01F000h 01FFFFh
16
15
010000h 010FFFh
00F000h 00FFFFh
0
000000h 000FFFh
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MX25L12805D
DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation.
2. When incorrect command is inputted to this LSI, this LSI becomes standby mode and keeps the standby mode until
next CS# falling edge. In standby mode, SO pin of this LSI should be High-Z.
3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next
CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The
difference of Serial mode 0 and mode 3 is shown as Figure 3.
5. Forthefollowinginstructions:RDID,RDSR,RDSCUR,READ,FAST_READ,RESandREMStheshifted-ininstruction
sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the
followinginstructions:WREN,WRDI,WRSR,SE,BE,CE,PP,RDP,DP,ENSO,EXSO,and WRSCUR,theCS#must
go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed.
6. DuringtheprogressofWriteStatusRegister,Program,Eraseoperation,toaccessthememoryarrayisneglectedand
not affect the current operation of Write Status Register, Program, Erase.
Figure 3. Serial Modes Supported
CPOL CPHA
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
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MX25L12805D
COMMAND DESCRIPTION
(1) Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE,
CE, and WRSR, which are intended to change the device content, should be set every time after the WREN instruction
setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low-> sending WREN instruction code-> CS# goes high. (see
Figure12)
(2) Write Disable (WRDI)
The Write Disable (WRDI) instruction is for re-setting Write Enable Latch (WEL) bit.
ThesequenceofissuingWRDIinstructionis:CS#goeslow->sendingWRDIinstructioncode->CS#goeshigh.(seeFigure
13)
The WEL bit is reset by following situations:
-Power-up
- Write Disable (WRDI) instruction completion
- Write Status Register (WRSR) instruction completion
- Page Program (PP) instruction completion
- Sector Erase (SE) instruction completion
- Block Erase (BE) instruction completion
- Chip Erase (CE) instruction completion
(3) Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The MXIC
Manufacturer ID is C2(hex), the memory type ID is 20(hex) as the first-byte device ID, and the individual device ID of
second-byte ID is as followings: 18(hex).
ThesequenceofissuingRDIDinstructionis:CS#goeslow->sendingRDIDinstructioncode->24-bitsIDdataoutonSO
-> to end RDID operation can use CS# to high at any time during data out. (see Figure. 14)
While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of
program/erase operation which is currently in progress. When CS# goes high, the device is at standby stage.
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MX25L12805D
(4) Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in
program/erase/writestatusregistercondition)andcontinuously. ItisrecommendedtochecktheWriteinProgress(WIP)
bit before sending a new instruction when a program, erase, or write status register operation is in progress.
ThesequenceofissuingRDSRinstructionis:CS#goeslow->sendingRDSRinstructioncode->StatusRegisterdataout
on SO (see Figure. 15)
The definition of the status register bits is as below:
WIP bit. TheWriteinProgress(WIP)bit, avolatilebit, indicateswhetherthedeviceisbusyinprogram/erase/writestatus
registerprogress.WhenWIPbitsetsto1,whichmeansthedeviceisbusyinprogram/erase/writestatusregisterprogress.
When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register cycle.
WELbit.TheWriteEnableLatch(WEL)bit, avolatilebit, indicateswhetherthedeviceissettointernalwriteenablelatch.
When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/erase/write
status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept
program/erase/writestatusregisterinstruction.Theprogram/erasecommandwillbeignoredandnotaffectvalueofWEL
bit if it is applied to a protected memory area.
BP3, BP2, BP1, BP0bits. TheBlockProtect(BP3, BP2, BP1, BP0)bits, non-volatilebits, indicatetheprotectedarea(as
defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To
write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed.
Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE)
and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed).
SRWDbit.TheStatusRegisterWriteDisable(SRWD)bit,non-volatilebit,isoperatedtogetherwithWriteProtection(WP#)
pinforprovidinghardwareprotectionmode. ThehardwareprotectionmoderequiresSRWDsetsto1andWP#pinsignal
is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for
execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only.
bit 7
SRWD
bit 6
bit 5
BP3
bit 4
BP2
bit 3
BP1
bit 2
BP0
bit 1
bit 0
WIP
WEL
Status
reserved the level of the level of the level of the level of
(writeenable (writeinprogress
latch) bit)
RegisterWrite
Protect
protected protected
protected
block
protected
block
block
block
1= status
registerwrite
disable
1=writeenable 1=writeoperation
(note1)
(note1)
(note1)
(note1)
0=notwrite
enable
0=not in write
operation
Note: 1. see the table "Protected Area Sizes".
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MX25L12805D
(5) Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write
Enable(WREN)instructionmustbedecodedandexecutedtosettheWriteEnableLatch(WEL)bitinadvance.TheWRSR
instruction can change the value of Block Protect (BP3, BP2, BP1, BP0) bits to define the protected area of memory (as
shownintable1).TheWRSRalsocansetorresettheStatusRegisterWriteDisable(SRWD)bitinaccordancewithWrite
Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is
entered.
The sequence of issuing WRSR instruction is: CS# goes low-> sending WRSR instruction code-> Status Register data
on SI-> CS# goes high. (see Figure 16)
The WRSR instruction has no effect on b6, b1, b0 of the status register.
TheCS#mustgohighexactlyatthebyteboundary;otherwise, theinstructionwillberejectedandnotexecuted. Theself-
timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing,
and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset.
Table 4. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
Software protection
mode(SPM)
The protected area cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
Hardware protection
mode (HPM)
The protected area cannot
be program or erase.
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in Table 1.
Astheabovetableshowing, thesummaryoftheSoftwareProtectedMode(SPM)andHardwareProtectedMode(HPM).
Software Protected Mode (SPM):
-
WhenSRWDbit=0,nomatterWP#isloworhigh,theWRENinstructionmaysettheWELbitandcanchangethevalues
ofSRWD,BP3,BP2,BP1,BP0. Theprotectedarea,whichisdefinedbyBP3,BP2,BP1,BP0,isatsoftwareprotected
mode(SPM).
-
WhenSRWDbit=1andWP#ishigh,theWRENinstructionmaysettheWELbitcanchangethevaluesofSRWD, BP3,
BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software protected mode (SPM)
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MX25L12805D
Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been
set. It is rejected to write the Status Register and not be executed.
HardwareProtectedMode(HPM):
-
When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode
(HPM).ThedataoftheprotectedareaisprotectedbysoftwareprotectedmodebyBP3,BP2,BP1,BP0andhardware
protected mode by the WP# to against data modification.
Note:toexitthehardwareprotectedmoderequiresWP#drivinghighoncethehardwareprotectedmodeisentered.Ifthe
WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software
protected mode via BP3, BP2, BP1, BP0.
(6) Read Data Bytes (READ)
Thereadinstructionisforreadingdataout.TheaddressislatchedonrisingedgeofSCLK,anddatashiftsoutonthefalling
edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address is automatically
increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single
READ instruction. The address counter rolls over to 0 when the highest address has been reached.
The sequence of issuing READ instruction is: CS# goes low-> sending READ instruction code-> 3-byte address on SI
-> data out on SO-> to end READ operation can use CS# to high at any time during data out. (see Figure. 17)
(7) Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of
each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location.
Theaddressisautomaticallyincreasedtothenexthigheraddressaftereachbytedataisshiftedout,sothewholememory
can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has
beenreached.
The sequence of issuing FAST_READ instruction is: CS# goes low-> sending FAST_READ instruction code-> 3-byte
address on SI-> 1-dummy byte address on SI->data out on SO-> to end FAST_READ operation can use CS# to high at
any time during data out. (see Figure. 18)
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
(8) Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any
4K-bytesectorand1K-byteparametersectorwhileparametersectorsareenable.AWriteEnable(WREN)instructionmust
execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (see
table3)isavalidaddressforSectorErase(SE)instruction. TheCS#mustgohighexactlyatthebyteboundary(thelatest
eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low -> sending SE instruction code-> 3-byte address on SI -> CS#
goes high. (see Figure 20)
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The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and
sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the page.
(9) Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-
byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit
before sending the Block Erase (BE). Any address of the block (see table 3) is a valid address for Block Erase (BE)
instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in);
otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low -> sending BE instruction code-> 3-byte address on SI -> CS#
goes high. (see Figure 21)
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and
sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the page.
(10) Chip Erase (CE)
TheChipErase(CE)instructionisforerasingthedataofthewholechiptobe"1".AWriteEnable(WREN)instructionmust
executetosettheWriteEnableLatch(WEL)bitbeforesendingtheChipErase(CE). Anyaddressofthesector(seetable
3)isavalidaddressforChipErase(CE)instruction. TheCS#mustgohighexactlyatthebyteboundary(thelatesteighth
of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low-> sending CE instruction code-> CS# goes high. (see Figure
22)
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress
(WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tBE timing, and
sets0whenChipEraseCycleiscompleted,andtheWriteEnableLatch(WEL)bitisreset.Ifthechipisprotectedby BP3,
BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only executed when BP3, BP2, BP1,
BP0 all set to "0".
(11) Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must
execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). If the eight least significant
address bits (A7-A0) are not all 0, all transmitted data which goes beyond the end of the current page are programmed
from the start address if the same page (from the address whose 8 least significant address bits (A7-A0) are all 0). The
CS# must keep during the whole Page Program cycle. The CS# must go high exactly at the byte boundary( the latest
eighthofaddressbytebeenlatched-in);otherwise,theinstructionwillberejectedandnotexecuted. Ifmorethan256bytes
aresenttothedevice,thedataofthelast256-byteisprogrammedattherequestpageandpreviousdatawillbedisregarded.
If less than 256 bytes are sent to the device, the data is programmed at the request address of the page without effect
on other address of the same page.
ThesequenceofissuingPPinstructionis:CS#goeslow->sendingPPinstructioncode->3-byteaddressonSI->atleast
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1-byte on data on SI-> CS# goes high. (see Figure 19)
Theself-timedPageProgramCycletime(tPP)isinitiatedassoonasChipSelect(CS#)goeshigh. TheWriteinProgress
(WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and
sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the page is protected by
BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
(12) Deep Power-down (DP)
TheDeepPower-down(DP)instructionisforsettingthedeviceontheminimizingthepowerconsumption(toenteringthe
DeepPower-downmode), thestandbycurrentisreducedfromISB1toISB2). TheDeepPower-downmoderequiresthe
Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not active and all Write/
Program/Eraseinstructionareignored. WhenCS#goeshigh, it'sonlyinstandbymodenotdeeppower-downmode. It's
different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low-> sending DP instruction code-> CS# goes high. (see Figure
23)
OncetheDPinstructionisset,allinstructionwillbeignoredexcepttheReleasefromDeepPower-downmode(RDP)and
ReadElectronicSignature(RES)instruction.(RESinstructiontoallowtheIDbeenreadout).WhenPower-down,thedeep
power-down mode automatically stops, and when power-up, the device automatically is in standby mode. For RDP
instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in);
otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before
entering the Deep Power-down mode and reducing the current to ISB2.
(13) Release from Deep Power-down (RDP), Read Electronic Signature (RES)
TheReleasefromDeepPower-down(RDP)instructionisterminatedbydrivingChipSelect(CS#)High.WhenChipSelect
(CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the Deep Power-
downmode,thetransitiontotheStand-byPowermodeisimmediate.IfthedevicewaspreviouslyintheDeepPower-down
mode,though,thetransitiontotheStand-byPowermodeisdelayedbytRES2,andChipSe-lect(CS#)mustremainHigh
for at least tRES2(max), as specified in Table 6. Once in the Stand-by Power mode, the device waits to be selected, so
that it can receive, decode and execute instructions.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as table of ID
Definitions. ThisisnotthesameasRDIDinstruction.Itisnotrecommendedtousefornewdesign.Fornewdesign,please
useRDID instruction. EveninDeeppower-downmode,theRDP,RES,andREMSarealsoallowedtobeexecuted,only
except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle
inprogress.
The sequence is shown as Figure 24,25.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly if
continuouslysendtheadditionalclockcyclesonSCLKwhileCS#isatlow. IfthedevicewasnotpreviouslyinDeepPower-
downmode,thedevicetransitiontostandbymodeisimmediate. IfthedevicewaspreviouslyinDeepPower-downmode,
there'sadelayoftRES2totransittostandbymode,andCS#mustremaintohighatleasttRES2(max). Onceinthestandby
mode, the device waits to be selected, so it can be receive, decode, and execute instruction.
The RDP instruction is for releasing from Deep Power Down Mode.
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(14) Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initiated
by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes address
(A7~A0). After which, the Manufacturer ID for MXIC (C2h) and the Device ID are shifted out on the falling edge of SCLK
with most significant bit (MSB) first as shown in Figure 26. The Device ID values are listed in Table of ID Definitions on
page 20. If the one-byte address is initially set to 01h, then the device ID will be read first and then followed by the
Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The
instruction is completed by driving CS# high.
Table of ID Definitions:
1. RDID:
manufacturer ID
C2
memory type
20
memory density
18
MX25L12805D
2. RES:
electronic ID
17
MX25L12805D
3. REMS:
manufacturer ID
C2
device ID
17
MX25L12805D
(15) Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 512-bit secured OTP mode. The additional 512-bit secured OTP is
independentfrommainarray,whichmayusetostoreuniqueserialnumberforsystemidentifier.AfterenteringtheSecured
OTP mode, and then follow standard read or program, procedure to read out the data or update data. The Secured OTP
data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low-> sending ENSO instruction to enter Secured OTP mode
-> CS# goes high.
PleasenotethatWRSR/WRSCURcommandsarenotacceptableduringtheaccessofsecureOTPregion,oncesecurity
OTP is lock down, only read related commands are valid.
(16) Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 512-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low-> sending EXSO instruction to exit Secured OTP mode->
CS# goes high.
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MX25L12805D
(17) Read Security Register (RDSCUR)
TheRDSCURinstructionisforreadingthevalueofSecurityRegisterbits. TheReadSecurityRegistercanbereadatany
time (even in program/erase/write status register/write security register condition) and continuously.
ThesequenceofissuingRDSCURinstructionis:CS#goeslow->sendingRDSCURinstruction->SecurityRegisterdata
out on SO-> CS# goes high.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or not.
When it is "0", it indicates non- factory lock; "1" indicates factory- lock.
Lock-downSecuredOTP(LDSO)bit.BywritingWRSCURinstruction,theLDSObitmaybesetto"1" forcustomerlock-
down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 512-bit Secured OTP area cannot
be update any more. While it is in 512-bit secured OTP mode, array access is not allowed.
Table of Security Register Definition
bit7
bit6
bit5
bit4
x
bit3
x
bit2
x
bit1
LDSO
bit0
(indicate if Secrured OTP
x
x
x
lock-down
0 = not lock-
down
indicator bit
1 = lock-down
(cannot
0 = non-
factory lock
reserved
reserved
reserved
reserved
reserved
0
program/erase 1 = factory
OTP) lock
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit
volatile bit non-volatile bit non-volatile bit
(18) Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. Unlike write status register, the WREN
instructionisnotrequiredbeforesendingWRSCURinstruction. TheWRSCURinstructionmaychangethevaluesofbit1
(LDSO bit) for customer to lock-down the 512-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP
area cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low-> sending WRSCUR instruction -> CS# goes high.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
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MX25L12805D
POWER-ON STATE
The device is at below states when power-up:
- Standby mode ( please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level:
- VCC minimum at power-up stage and then after a delay of tVSL
-GNDatpower-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
Aninternalpower-onreset(POR)circuitmayprotectthedevicefromdatacorruptionandinadvertentdatachangeduring
powerupstate.WhenVCCislowerthanVWI(PORthresholdvoltagevalue),theinternallogicisresetandtheflashdevice
has no response to any command.
For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the device
is fully accessible for commands like write enable(WREN), page program (PP), sector erase(SE), block erase (BE), chip
erase(CE) and write status register(WRSR). If the VCC does not reach the VCC minimum level, the correct operation is
not guaranteed. The write, erase, and program command should be sent after the below time delay:
- tPUW after VCC reached VWI level
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of tPUW
has not passed.
Please refer to the figure of "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is
recommended.(generallyaround0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response to any
command. The data corruption might occur during the stage while a write, program, erase cycle is in progress.
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MX25L12805D
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
RATING
VALUE
AmbientOperatingTemperature
StorageTemperature
-40°Cto85° CforIndustrialgrade
-55°Cto125°C
Applied Input Voltage
-0.5V to 4.6V
AppliedOutputVoltage
VCC to Ground Potential
-0.5V to 4.6V
-0.5V to 4.6V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to 4.6V or -0.5V for period up to 20ns.
4. All input and output pins may overshoot to VCC+0.5V while VCC+0.5V is smaller than or equal to 4.6V.
Figure 4.Maximum Negative Overshoot Waveform
Figure5.MaximumPositiveOvershootWaveform
20ns
4.6V
0V
3.6V
-0.5V
20ns
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL
CIN
PARAMETER
MIN.
TYP
MAX.
10
UNIT
pF
CONDITIONS
VIN = 0V
InputCapacitance
OutputCapacitance
COUT
10
pF
VOUT = 0V
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MX25L12805D
Figure 6. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
Output timing referance level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 7. OUTPUT LOADING
DEVICE UNDER
TEST
2.7K ohm
+3.3V
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=30pF Including jig capacitance
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MX25L12805D
Table 5. DC CHARACTERISTICS (Temperature = -40° C to 85°C, VCC = 2.7V ~ 3.6V)
SYMBOL PARAMETER
NOTES
MIN.
TYP
MAX. UNITS TESTCONDITIONS
ILI
InputLoad
Current
1
2
uA
uA
uA
uA
uA
VCC = VCC Max
VIN = VCC or GND
VCC = VCC Max
VIN = VCC or GND
WP#/ACC=11.5V
ILO
OutputLeakage
Current
1
1
2
ILIHV
ISB1
ISB2
ICC1
ICC2
ICC3
HV pin input Leakage
Current
35
VCCStandby
Current
20
20
VIN = VCC or GND
CS# = VCC
DeepPower-down
Current
VIN = VCC or GND
CS# = VCC
VCCRead
1
1
25
15
20
mA
mA
mA
f=50MHz(serial)
f=33MHz(serial)
PrograminProgress
CS# = VCC
VCCProgram
Current(PP)
VCC Write Status
Register(WRSR)
Current
20
mA
Programstatusregisterinprogress
CS#=VCC
ICC4
ICC5
VHH
VCC Sector Erase
Current(SE)
1
1
1
20
20
mA
mA
V
Erase in Progress
CS#=VCC
VCC Chip Erase
Current(CE)
Erase in Progress
CS#=VCC
Voltage for ACC
ProgramAcceleration
Input Low Voltage
Input High Voltage
OutputLowVoltage
OutputHighVoltage
11
11.5
VCC=2.7V~3.6V
VIL
-0.5
0.3VCC
VCC+0.4
0.4
V
V
V
V
VIH
VOL
VOH
0.7VCC
IOL = 1.6mA
IOH = -100uA
VCC-0.2
NOTES:
1. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product versions (package and speeds).
2. Typical value is calculated by simulation.
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MX25L12805D
Table 6. AC CHARACTERISTICS (Temperature = -40° C to 85°C, VCC = 2.7V ~ 3.6V)
Symbol
Alt.
Parameter
Min.
Typ. Max.
Unit
fSCLK
fC
Clock Frequency for the following instructions:
FAST_READ, PP, SE, BE, CE, DP, RES,RDP
WREN, WRDI, RDID, RDSR, WRSR
Clock Frequency for READ instructions
10K
50M
(Condition:30pF)
Hz
fRSCLK
tCH(1)
tCL(1)
fR
10K
7
7
33M
Hz
tCLH Clock High Time
tCLL Clock Low Time
ns
ns
V/ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
ms
us
ms
ms
s
tCLCH(2)
tCHCL(2)
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
Clock Rise Time (3) (peak to peak)
0.1
0.1
5
5
2
5
5
5
100
Clock Fall Time (3) (peak to peak)
tCSS CS# Active Setup Time (relative to SCLK)
CS# Not Active Hold Time (relative to SCLK)
tDSU Data In Setup Time
tDH
Data In Hold Time
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
tCSH CS# Deselect Time
tSHQZ(2) tDIS Output Disable Time
2.7V-3.6V
3.0V-3.6V
2.7V-3.6V
3.0V-3.6V
10
8
10
8
tCLQV
tV
Clock Low to Output Valid
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tHO
Output Hold Time
0
5
5
5
5
HOLD# Setup Time (relative to SCLK)
HOLD# Hold Time (relative to SCLK)
HOLD Setup Time (relative to SCLK)
HOLD Hold Time (relative to SCLK)
HOLD to Output Low-Z
tHHQX(2) tLZ
2.7V-3.6V
3.0V-3.6V
2.7V-3.6V
3.0V-3.6V
10
8
10
8
tHLQZ(2) tHZ
HOLD# to OutputHigh-Z
tWHSL(4)
tSHWL(4)
tDP(2)
tRES1(2)
tRES2(2)
tW
tBP
tPP
tSE
tBE
Write Protect Setup Time
Write Protect Hold Time
CS#HightoDeepPower-downMode
CS# High to Standby Mode without Electronic Signature Read
CS# High to Standby Mode with Electronic Signature Read
Write Status Register Cycle Time
Byte-Program
Page Program Cycle Time
Sector Erase Cycle Time
20
100
10
8.8
8.8
100
300
5
300
2
200
40
9
1.4
60
0.7
80
Block Erase Cycle Time
Chip Erase Cycle Time
tCE
s
Notes:
1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. Test condition is shown as Figure 5.
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MX25L12805D
Table 7. Power-Up Timing and VWI Threshold
Symbol
tVSL(1)
tPUW(1)
VWI(1)
Parameter
Min.
200
1
Max.
Unit
us
VCC(min) to CS# low
Time delay to Write instruction
Write Inhibit Voltage
10
ms
V
1.5
2.5
Note: 1. These parameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register
contains 00h (all Status Register bits are 0).
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MX25L12805D
Figure 8. Serial Input Timing
tSHSL
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 9. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
tCLQX
LSB
SO
SI
tQLQH
tQHQL
ADDR.LSB IN
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MX25L12805D
Figure 10. Hold Timing
CS#
tHLCH
tCHHH
tCHHL
tHLQZ
tHHCH
tHHQX
SCLK
SO
HOLD#
* SI is "don't care" during HOLD operation.
Figure 11. WP# Disable Setup and Hold Timing during WRSR when SRWD=1
WP#
tSHWL
tWHSL
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01
SI
High-Z
SO
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Figure 12. Write Enable (WREN) Sequence (Command 06)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
06
SI
High-Z
SO
Figure 13. Write Disable (WRDI) Sequence (Command 04)
CS#
0
1
2
3
4
5
6
7
SCLK
Command
04
SI
High-Z
SO
Figure 14. Read Identification (RDID) Sequence (Command 9F)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
SCLK
SI
Command
9F
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
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Figure 15. Read Status Register (RDSR) Sequence (Command 05)
CS#
SCLK
SI
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
command
05
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 16. Write Status Register (WRSR) Sequence (Command 01)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCLK
command
01
Status
Register In
SI
7
6
5
4
3
2
0
1
MSB
High-Z
SO
Figure 17. Read Data Bytes (READ) Sequence (Command 03)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
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MX25L12805D
Figure 18. Read Data Bytes at Higher Speed (FAST_READ) Sequence (Command 0B)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
0B
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Byte
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
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MX25L12805D
Figure 19. Page Program (PP) Sequence (Command 02)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
Figure 20. Sector Erase (SE) Sequence (Command 20)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
20
24 Bit Address
2
SI
23 22
MSB
0
1
Note: SE command is 20(hex).
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MX25L12805D
Figure 21. Block Erase (BE) Sequence (Command D8)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
Command
D8
24 Bit Address
SI
23 22
MSB
2
0
1
Note: BE command is D8(hex).
Figure 22. Chip Erase (CE) Sequence (Command 60 or C7)
CS#
0
1
2
3
4
5
6
7
SCLK
SI
Command
60 or C7
Note: CE command is 60(hex) or C7(hex).
Figure 23. Deep Power-down (DP) Sequence (Command B9)
CS#
t
DP
0
1
2
3
4
5
6
7
SCLK
SI
Command
B9
Stand-by Mode
Deep Power-down Mode
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MX25L12805D
Figure 24. Release from Deep Power-down and Read Electronic Signature (RES) Sequence
(Command AB)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
AB
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
Figure 25. Release from Deep Power-down (RDP) Sequence (Command AB)
CS#
t
RES1
0
1
2
3
4
5
6
7
SCLK
SI
Command
AB
High-Z
SO
Deep Power-down Mode
Stand-by Mode
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33
MX25L12805D
Figure 26. Read Electronic Manufacturer & Device ID (REMS) Sequence (Command 90)
CS#
0
1
2
3
4
5
6
7
8
9 10
SCLK
Command
90
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
X
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first
(2) Instruction is 90(hex).
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34
MX25L12805D
Figure 27. Power-up Timing
V
CC
V
(max)
CC
Program, Erase and Write Commands are Ignored
Chip Selection is Not Allowed
V
(min)
CC
tVSL
Read Command is
allowed
Device is fully
accessible
Reset State
of the
Flash
V
WI
tPUW
time
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35
MX25L12805D
RECOMMENDED OPERATING CONDITIONS
AtDevicePower-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If
the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tSHSL
tVR
CS#
tCHSL
tSLCH
tCHSH
tSHCH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Figure A. AC Timing at Device Power-Up
Symbol
Parameter
VCC Rise Time
Notes
Min.
Max.
500000
Unit
tVR
1
20
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to "AC
CHARACTERISTICS"table.
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MX25L12805D
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Min.
TYP. (1)
40
Max.(2)
100
300
2
UNIT
ms
ms
s
Write Status Register Cycle Time
Sector Erase Time
60
Block Erase Time
0.7
Chip Erase Time
80
200
125
300
5
s
Chip Erase Time (at ACC mode)
Byte Program Time (via page program command)
PageProgramTime
50
s
9
us
1.4
ms
ms
cycles
Page Program Time (at ACC mode)
Erase/ProgramCycle
1.4
5
100,000
Note:
1. Typical program and erase time assumes the following conditions: 25° C, 3.3V, and checker board pattern.
2. Under worst conditions of 85°C and 2.7V.
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command.
4. Themaximumchipprogrammingtimeisevaluatedundertheworstconditionsof0C, VCC=3.0V, and100Kcyclewith
90% confidence level.
5. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
11.5V
Input Voltage with respect to GND on ACC
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
-1.0V
2 VCCmax
VCC + 1.0V
+100mA
-1.0V
Current
-100mA
Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.
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37
MX25L12805D
ORDERING INFORMATION
PARTNO.
SERIALCLOCK
READ
STANDBY
Temperature PACKAGE Remark
RATE
CURRENT(max.) CURRENT(max.)
MX25L12805DMI-20G
50MHz
25mA
20uA
-40~85°C
16-SOP
Pb-free
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MX25L12805D
PART NAME DESCRIPTION
MX 25
L
12805D
M
I
20 G
OPTION:
G: Pb-free
SPEED:
20: 50MHz
TEMPERATURE RANGE:
I: Industrial (-40˚C to 85˚C)
PACKAGE:
M: 300mil 16-SOP
DENSITY & MODE:
12805D: 128Mb
TYPE:
L: 3V
DEVICE:
25: Serial Flash
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MX25L12805D
PACKAGE INFORMATION
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MX25L12805D
REVISION HISTORY
RevisionNo. Description
Page
P1
P24,37
Date
FEB/26/2008
OCT/01/2008
1.0
1.1
Removed "Advanced Information" on page 1
Revised sector erase time spec from 90ms(typ.) to 60ms(typ.)
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REV. 1.1, OCT. 01, 2008
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MX25L12805D
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure
of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons
or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix
and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due
to use of Macronix's products in the prohibited applications.
MACRONIX INTERNATIONALCO., LTD.
Taipei Office
Headquarters
Macronix, Int'l Co., Ltd.
Macronix, Int'l Co., Ltd.
16, Li-Hsin Road, Science Park,
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SingaporeOffice
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Singapore 449408
Tel: +65-6346-5505
Fax: +65-6348-8096
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5 Science Park West Avenue, Sha Tin, N.T.
Tel: +86-852-2607-4289
Fax: +86-852-2607-4229
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
42
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