MX25U6435FZNI-10G [Macronix]
Flash, 16MX4, PDSO8, WSON-8;
| 型号： | MX25U6435FZNI-10G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 16MX4, PDSO8, WSON-8 时钟 光电二极管 内存集成电路 |
| 文件： | 总91页 (文件大小：2874K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX25U3235F
MX25U6435F
MX25U3235F/MX25U6435F
DATASHEET
P/N: PM1698
REV. 1.0, FEB. 03, 2012
1
MX25U3235F
MX25U6435F
Contents
1. FEATURES ..............................................................................................................................................................4
2. GENERAL DESCRIPTION .....................................................................................................................................6
Table 1. Additional Feature Comparison .....................................................................................................7
3. PIN CONFIGURATIONS .........................................................................................................................................8
4. PIN DESCRIPTION..................................................................................................................................................8
5. BLOCK DIAGRAM...................................................................................................................................................9
6. DATA PROTECTION..............................................................................................................................................10
Table 2. Protected Area Sizes...................................................................................................................11
Table 3. 4K-bit Secured OTP Definition ....................................................................................................12
7. Memory Organization...........................................................................................................................................13
Table 4. Memory Organization ..................................................................................................................13
8. DEVICE OPERATION............................................................................................................................................15
8-1. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 17
9. COMMAND DESCRIPTION...................................................................................................................................18
Table 5. Command Set..............................................................................................................................18
9-1. Write Enable (WREN).............................................................................................................................. 22
9-2. Write Disable (WRDI)............................................................................................................................... 23
9-3. Read Identification (RDID)....................................................................................................................... 24
9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 25
9-5. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................... 27
9-6. QPI ID Read (QPIID) ............................................................................................................................... 28
Table 6. ID Definitions ..............................................................................................................................28
9-7. Read Status Register (RDSR)................................................................................................................. 29
9-8. Write Status Register (WRSR)................................................................................................................. 33
Table 7. Protection Modes.........................................................................................................................34
9-9. Read Data Bytes (READ) ........................................................................................................................ 37
9-10. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 38
9-11. 2 x I/O Read Mode (2READ) ................................................................................................................... 40
9-12. 4 x I/O Read Mode (4READ) ................................................................................................................... 41
9-13. Burst Read............................................................................................................................................... 44
9-14. Performance Enhance Mode................................................................................................................... 45
9-15. Performance Enhance Mode Reset (FFh)............................................................................................... 48
9-16. Sector Erase (SE).................................................................................................................................... 49
9-17. Block Erase (BE32K)............................................................................................................................... 50
9-18. Block Erase (BE) ..................................................................................................................................... 51
9-19. Chip Erase (CE)....................................................................................................................................... 52
9-20. Page Program (PP) ................................................................................................................................. 53
9-21. 4 x I/O Page Program (4PP).................................................................................................................... 55
9-22. Deep Power-down (DP)........................................................................................................................... 56
9-23. Enter Secured OTP (ENSO).................................................................................................................... 57
9-24. Exit Secured OTP (EXSO)....................................................................................................................... 57
9-25. Read Security Register (RDSCUR)......................................................................................................... 57
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Table 8. Security Register Definition .........................................................................................................58
9-26. Write Security Register (WRSCUR)......................................................................................................... 58
9-27. Write Protection Selection (WPSEL)........................................................................................................ 59
9-28. Single Block Lock/Unlock Protection (SBLK/SBULK).............................................................................. 62
9-29. Read Block Lock Status (RDBLOCK)...................................................................................................... 64
9-30. Gang Block Lock/Unlock (GBLK/GBULK) ............................................................................................... 64
9-31. Program/ Erase Suspend/ Resume......................................................................................................... 65
9-32. Erase Suspend ........................................................................................................................................ 65
9-33. Program Suspend.................................................................................................................................... 65
9-34. Write-Resume.......................................................................................................................................... 67
9-35. No Operation (NOP) ................................................................................................................................ 67
9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 67
9-37. Read SFDP Mode (RDSFDP).................................................................................................................. 69
Table 9. Signature and Parameter Identification Data Values ..................................................................70
Table 10. Parameter Table (0): JEDEC Flash Parameter Tables..............................................................71
Table 11. Parameter Table (1): Macronix Flash Parameter Tables............................................................73
10. RESET..................................................................................................................................................................75
Table 12. Reset Timing..............................................................................................................................75
11. POWER-ON STATE .............................................................................................................................................76
12. ELECTRICAL SPECIFICATIONS........................................................................................................................77
Table 13. ABSOLUTE MAXIMUM RATINGS ............................................................................................77
Table 14. CAPACITANCE TA = 25°C, f = 1.0 MHz....................................................................................77
Table 15. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V) .....................79
°
°
Table 16. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V) ....................80
°
°
13. OPERATING CONDITIONS.................................................................................................................................82
Table 17. Power-Up Timing and VWI Threshold .......................................................................................84
13-1. INITIAL DELIVERY STATE...................................................................................................................... 84
14. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................85
15. LATCH-UP CHARACTERISTICS........................................................................................................................85
16. ORDERING INFORMATION................................................................................................................................86
17. PART NAME DESCRIPTION...............................................................................................................................87
18. PACKAGE INFORMATION..................................................................................................................................88
19. REVISION HISTORY ...........................................................................................................................................90
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MX25U3235F
MX25U6435F
1.8V 32/64M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM (SERIAL MULTI I/O)
FLASH MEMORY
1. FEATURES
GENERAL
•
Serial Peripheral Interface compatible -- Mode 0 and Mode 3
•
32Mb: 33,554,432 x 1 bit structure or 16,777,216 x 2 bits (two I/O mode) structure or 8,388,608 x 4 bits (four I/
O mode) structure
64Mb: 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two I/O mode) structure or 16,777,216 x 4 bits (four I/
O mode) structure
•
•
Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each
- Any Block can be erased individually
Single Power Supply Operation
- 1.65 to 2.0 volt for read, erase, and program operations
Latch-up protected to 100mA from -1V to Vcc +1V
Low Vcc write inhibit is from 1.0V to 1.4V
•
•
PERFORMANCE
•
High Performance
- Fast read for SPI mode
- 1 I/O: 104MHz with 8 dummy cycles
- 2 I/O: 84MHz with 4 dummy cycles, equivalent to 168MHz
- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz
- Fast read for QPI mode
- 4 I/O: 84MHz with 2+2 dummy cycles, equivalent to 336MHz
- 4 I/O: 104MHz with 2+4 dummy cycles, equivalent to 416MHz
- Fast program time: 1.2ms(typ.) and 3ms(max.)/page (256-byte per page)
- Byte program time: 12us (typical)
- 8/16/32/64 byte Wrap-Around Burst Read Mode
- Fast erase time: 60ms (typ.)/sector (4K-byte per sector); 250ms(typ.)/block (32K-byte per block), 500ms(typ.) /
block (64K-byte per block)
•
Low Power Consumption
- Low active read current: 20mA(typ.) at 104MHz, 15mA(typ.) at 84MHz
- Low active erase/programming current: 20mA (typ.)
- Standby current: 30uA (typ.)
•
•
•
Deep Power Down: 5uA(typ.)
Typical 100,000 erase/program cycles
10 years data retention
SOFTWARE FEATURES
•
Input Data Format
- 1-byte Command code
•
Advanced Security Features
- Block lock protection
The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instruc-
tions
- Additional 4k-bit secured OTP for unique identifier
Auto Erase and Auto Program Algorithm
•
Automatically erases and verifies data at selected sector or block
-
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Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
Status Register Feature
-
•
•
•
•
Command Reset
Program/Erase Suspend
Electronic Identification
JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID
-
- REMS command for 1-byte manufacturer ID and 1-byte device ID
Support Serial Flash Discoverable Parameters (SFDP) mode
•
HARDWARE FEATURES
•
•
•
•
•
•
SCLK Input
- Serial clock input
SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode
PACKAGE
-8-pin SOP (200mil)
-8-land WSON (6x5mm)
- All devices are RoHS Compliant
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2. GENERAL DESCRIPTION
MX25U3235F is 32Mb bits serial Flash memory, which is configured as 4,194,304 x 8 internally. When it is in two
or four I/O mode, the structure becomes 16,777,216 bits x 2 or 8,388,608 bits x 4. MX25U6435F is 64Mb bits serial
Flash memory, which is configured as 8,388,608 x 8 internally. When it is in two or four I/O mode, the structure be-
comes 33,554,432 bits x 2 or 16,777,216 bits x 4. MX25U3235F/MX25U6435F feature a serial peripheral interface
and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals
are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is ena-
bled by CS# input.
When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits in-
put and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0
pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.
The MX25U3235F/MX25U6435F MXSMIOTM (Serial Multi I/O) provides sequential read operation on whole chip.
After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the
specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256
bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),
or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
Advanced security features enhance the protection and security functions, please see security features section for
more details.
When the device is not in operation and CS# is high, it is put in standby mode and draws less than 30uA DC cur-
rent.
The MX25U3235F/MX25U6435F utilizes Macronix's proprietary memory cell, which reliably stores memory con-
tents even after 100,000 program and erase cycles.
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Table 1. Additional Feature Comparison
Read Performance
SPI
Additional
Protection and Security
Features
QPI
Flexible Block
Protection
(BP0-BP3)
Part
Name
4K-bit security
1 I/O
8
2 I/O
4
4 I/O
4
4 I/O
6
4 I/O
4
4 I/O
6
OTP
Dummy Cycle
MX25U3235F
MX25U6435F
V
V
V
V
104MHz 84 MHz 84 MHz 104MHz 84 MHz 104MHz
104MHz 84 MHz 84 MHz 104MHz 84 MHz 104MHz
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3. PIN CONFIGURATIONS
8-PIN SOP (200mil)
4. PIN DESCRIPTION
SYMBOL DESCRIPTION
CS#
Chip Select
Serial Data Input (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
1
2
3
4
CS#
SO/SIO1
WP#/SIO2
GND
VCC
8
7
6
5
RESET#/SIO3
SCLK
SI/SIO0
SI/SIO0
Serial Data Output (for 1 x I/O)/ Serial
Data Input & Output (for 2xI/O or 4xI/
O read mode)
SO/SIO1
SCLK
Clock Input
8-LAND WSON (6x5mm)
Write protection: connect to GND or
WP#/SIO2 Serial Data Input & Output (for 4xI/O
read mode)
Hardware Reset Pin Active low or
RESET#/SIO3 Serial Data Input & Output (for 4xI/O
read mode)
1
2
3
4
VCC
CS#
SO/SIO1
WP#/SIO2
GND
8
7
6
5
RESET#/SIO3
SCLK
SI/SIO0
VCC
GND
+ 1.8V Power Supply
Ground
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5. BLOCK DIAGRAM
Address
Generator
Memory Array
Page Buffer
Data
Register
SI/SIO0
Y-Decoder
SRAM
Buffer
Sense
Amplifier
CS#
WP#/SIO2
Reset#/SIO3
Mode
Logic
State
Machine
HV
Generator
SCLK
Clock Generator
Output
Buffer
SO/SIO1
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6. DATA PROTECTION
The device is designed to offer protection against accidental erasure or programming caused by spurious system
level signals that may exist during power transition. During power up the device automatically resets the state ma-
chine in the Read mode. In addition, with its control register architecture, alteration of the memory contents only oc-
curs after successful completion of specific command sequences. The device also incorporates several features to
prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise.
•
Power-on reset and tPUW: to avoid sudden power switch by system power supply transition, the power-on reset
and tPUW (internal timer) may protect the Flash.
• Valid command length checking: The command length will be checked whether it is at byte base and completed
on byte boundary.
• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before
other command to change data. The WEL bit will return to reset stage under following situation:
- Power-up
- Reset# pin driven low
- Write Disable (WRDI) command completion
- Write Status Register (WRSR) command completion
- Page Program (PP) command completion
- Sector Erase (SE) command completion
- Block Erase 32KB (BE32K) command completion
- Block Erase (BE) command completion
- Chip Erase (CE) command completion
- Program/Erase Suspend
- Softreset command completion
- Write Security Register (WRSCUR) command completion
- Write Protection Selection (WPSEL) command completion
•
•
Deep Power Down Mode: By entering deep power down mode, the flash device is under protected from writing
all commands except Release from deep power down mode command (RDP) and Read Electronic Signature
command (RES) and softreset command.
Advanced Security Features: there are some protection and security features which protect content from inad-
vertent write and hostile access.
I. Block lock protection
- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0) bits to allow part of memory to be protected
as read only. The protected area definition is shown as Table 2 Protected Area Sizes, the protected areas are
more flexible which may protect various area by setting value of BP0-BP3 bits.
- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status Reg-
ister Write Protect bit.
- In four I/O and QPI mode, the feature of HPM will be disabled.
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Table 2. Protected Area Sizes
Status bit
Protect Level
BP3 BP2 BP1 BP0
32Mb
64Mb
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0 (none)
0 (none)
1 (1block, protected block 63rd)
1 (1 block, protected block 127th)
2 (2blocks, protected block 62nd~63rd)
3 (4blocks, protected block 60th~63rd)
4 (8blocks, protected block 56th-63rd)
5 (16blocks, protected block 48th~63rd)
6 (32blocks, protected block 32nd~63rd)
7 (64blocks, protected all)
2 (2 blocks, protected block 126th~127th)
3 (4 blocks, protected block 124th~127th)
4 (8 blocks, protected block 120th~127th)
5 (16 blocks, protected block 112nd~127th)
6 (32 blocks, protected block 96th~127th)
7 (64 blocks, protected block 64th~127th)
8 (64 blocks, protected block 0th~63th)
9 (96 blocks, protected block 0th~95th)
8 (64blocks, protected all)
9 (32blocks, protected block 0th~31st)
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
10 (48blocks, protected block 0th~47th)
11 (56blocks, protected block 0th~55th)
12 (60blocks, protected block 0th~59th)
13 (62blocks, protected block 0th~61st)
14 (63blocks, protected block 0th~62nd)
15 (64blocks, protected all)
10 (112 blocks, protected block 0th~111st)
11 (120 blocks, protected block 0th~119th)
12 (124 blocks, protected block 0th~123rd)
13 (126 blocks, protected block 0th~125th)
14 (127 blocks, protected block 0th~126th)
15 (128 blocks, protected all)
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II. Additional 4K-bit secured OTP for unique identifier: to provide 4K-bit one-time program area for setting de-
vice unique serial number - Which may be set by factory or system customer.
- Security register bit 0 indicates whether the chip is locked by factory or not.
- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command),
and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security
OTP command.
- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register) com-
mand to set customer lock-down bit1 as "1". Please refer to Table 8 of "security register definition" for security
register bit definition and Table 3 of "4K-bit secured OTP definition" for address range definition.
- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured
OTP mode, array access is not allowed.
Table 3. 4K-bit Secured OTP Definition
Address range
xxx000~xxx00F
xxx010~xxx1FF
Size
Standard Factory Lock
ESN (electrical serial number)
N/A
Customer Lock
128-bit
3968-bit
Determined by customer
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7. Memory Organization
Table 4. Memory Organization
MX25U3235F
Block(64K-byte) Block(32K-byte) Sector (4K-byte)
Address Range
1023
3FF000h
3FFFFFh
127
individual 16 sectors
lock/unlock unit:4K-byte
1016
1015
3F8000h
3F7000h
3F8FFFh
3F7FFFh
63
126
125
124
123
122
1008
1007
3F0000h
3EF000h
3F0FFFh
3EFFFFh
1000
999
3E8000h
3E7000h
3E8FFFh
3E7FFFh
62
individual block
lock/unlock unit:64K-byte
992
991
3E0000h
3DF000h
3E0FFFh
3DFFFFh
984
983
3D8000h
3D7000h
3D8FFFh
3D7FFFh
61
976
3D0000h
3D0FFFh
individual block
lock/unlock unit:64K-byte
47
02F000h
02FFFFh
5
4
3
2
1
0
40
39
028000h
027000h
028FFFh
027FFFh
2
1
individual block
lock/unlock unit:64K-byte
32
31
020000h
01F000h
020FFFh
01FFFFh
24
23
018000h
017000h
018FFFh
017FFFh
16
15
010000h
00F000h
010FFFh
00FFFFh
8
7
008000h
007000h
008FFFh
007FFFh
individual 16 sectors
lock/unlock unit:4K-byte
0
0
000000h
000FFFh
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Block(64K-byte) Block(32K-byte) Sector (4K-byte)
Address Range
2047
7FF000h
7FFFFFh
255
individual 16 sectors
lock/unlock unit:4K-byte
2040
2039
7F8000h
7F7000h
7F8FFFh
7F7FFFh
127
254
2032
7F0000h
7EF000h
7F0FFFh
7EFFFFh
2031
253
2024
2023
7E8000h
7E7000h
7E8FFFh
7E7FFFh
126
252
individual block
lock/unlock unit:64K-byte
2016
7E0000h
7DF000h
7E0FFFh
7DFFFFh
2015
251
2008
2007
7D8000h
7D7000h
7D8FFFh
7D7FFFh
125
250
2000
7D0000h
7D0FFFh
individual block
lock/unlock unit:64K-byte
47
02F000h
02FFFFh
5
40
39
028000h
027000h
028FFFh
027FFFh
2
4
individual block
lock/unlock unit:64K-byte
32
020000h
01F000h
020FFFh
01FFFFh
31
3
24
23
018000h
017000h
018FFFh
017FFFh
1
2
16
010000h
00F000h
010FFFh
00FFFFh
15
1
8
008000h
007000h
008FFFh
007FFFh
individual 16 sectors
lock/unlock unit:4K-byte
0
7
0
0
000000h
000FFFh
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8. DEVICE OPERATION
1. Before a command is issued, status register should be checked to ensure device is ready for the intended op-
eration.
2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby
mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.
3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode
until next CS# rising edge.
4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.
The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".
5. For the following instructions: RDID, RDSR, RDSCUR, READ, FAST_READ, 2READ, 4READ, W4READ, RDS-
FDP, RES, REMS, QPIID, RDBLOCK, the shifted-in instruction sequence is followed by a data-out sequence. Af-
ter any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR,
SE, BE32K, BE, CE, PP, 4PP, DP, ENSO, EXSO, WRSCUR, WPSEL, SBLK, SBULK, GBULK, SUSPEND,
RESUME, NOP, RSTEN, RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise,
the instruction will be rejected and not executed.
6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is neglect-
ed and not affect the current operation of Write Status Register, Program, Erase.
Figure 1. Serial Modes Supported
CPOL CPHA
shift in
shift out
SCLK
SCLK
(Serial mode 0)
(Serial mode 3)
0
1
0
1
SI
MSB
SO
MSB
Note:
CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not
transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is
supported.
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Figure 2. Serial Input Timing
tSHSL
tSHCH
tCHCL
CS#
tCHSL
tSLCH
tCHSH
SCLK
tDVCH
tCHDX
tCLCH
MSB
LSB
SI
High-Z
SO
Figure 3. Output Timing
CS#
tCH
SCLK
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
SO
tCLQX
LSB
ADDR.LSB IN
SI
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8-1. Quad Peripheral Interface (QPI) Read Mode
QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in
command cycles, address cycles and as well as data output cycles.
Enable QPI mode
By issuing 35H command, the QPI mode is enable.
Figure 4. Enable QPI Sequence (Command 35H)
CS#
MODE 3
MODE 0
2
3
4
5
6
7
0
1
SCLK
SIO0
35
SIO[3:1]
Reset QPI (RSTQIO)
The Reset QPI instruction, F5H, resets the device to SPI protocol operation. To execute a Reset QPI operation, the
host drives CS# low, sends the Reset QPI command cycle (F5h) then, drives CS# high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
Note:
For EQIO/RSTQIO/SBL CS# high width has to follow "write spec" tSHSL as 30ns for next instruction.
Figure 5. Reset QPI Mode (Command F5H)
CS#
SCLK
SIO[3:0]
F5
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9. COMMAND DESCRIPTION
Table 5. Command Set
Read/Write Array Commands
Mode
SPI
SPI/QPI
SPI
SPI/QPI
4READ
SPI
2READ
(2 x I/O read
command) Note1
Command
(byte)
READ
(normal read)
FAST READ
(fast read data)
W4READ
(4 x I/O read)
1st byte
2nd byte
3rd byte
4th byte
5th byte
03 (hex)
ADD1(8)
ADD2(8)
ADD3(8)
0B (hex)
ADD1(8)
BB (hex)
ADD1(4)
ADD2(4)
ADD3(4)
Dummy(4)
EB (hex)
ADD1(2)
E7 (hex)
ADD1
ADD2(8)
ADD2(2)
ADD2
ADD3(8)
ADD3(2)
ADD3
Dummy(8)/(4)*
Dummy(6)
Quad I/O read
Dummy(4)
Quad I/O read
n bytes read out n bytes read out n bytes read out
until CS# goes
until CS# goes
by 2 x I/O until
with 6 dummy for with 4 dummy
high
high
CS# goes high
cycles
cycles
Action
Mode
SPI/QPI
SPI
SPI/QPI
SPI/QPI
SPI/QPI
SPI/QPI
4PP
(quad page
program)
BE 32K
(block erase
32KB)
BE
Command
(byte)
PP
SE
CE
(chip erase)
(block erase
64KB)
(page program)
(sector erase)
1st byte
2nd byte
3rd byte
4th byte
5th byte
02 (hex)
ADD1
ADD2
ADD3
38 (hex)
ADD1
ADD2
ADD3
20 (hex)
ADD1
ADD2
ADD3
52 (hex)
ADD1
ADD2
ADD3
D8 (hex)
ADD1
60 or C7 (hex)
ADD2
ADD3
to program the
selected page
quad input to
program the
selected page
to erase the
selected sector
to erase the
selected 32K
block
to erase the
selected block
to erase whole
chip
Action
* The fast read command (0Bh) when under QPI mode, the dummy cycle is 4 clocks.
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Register/Setting Commands
RDSR
(read status
register)
WRSR
(write status
register)
WPSEL
EQIO
Command
(byte)
WREN
(write enable)
WRDI
(write disable)
(Write Protect
Selection)
(Enable QPI)
Mode
SPI/QPI
06 (hex)
SPI/QPI
04 (hex)
SPI/QPI
05 (hex)
SPI/QPI
01 (hex)
Values
SPI/QPI
68 (hex)
SPI
1st byte
2nd byte
3rd byte
4th byte
5th byte
35 (hex)
sets the (WEL) resets the (WEL) to read out the
to write new
values of the
status register
to enter and
enable individal
block protect
mode
Entering the QPI
mode
write enable latch write enable latch
values of the
bit
bit
status register
Action
PGM/ERS
Suspend
(Suspends
PGM/ERS
Resume
(Resumes
RDP
(Release from
deep power
down)
DP
Command
(byte)
RSTQIO
(Reset QPI)
SBL
(Deep power
down)
(Set Burst Length)
Program/Erase) Program/Erase)
Mode
QPI
SPI/QPI
B0 (hex)
SPI/QPI
30 (hex)
SPI/QPI
B9 (hex)
SPI/QPI
SPI/QPI
C0 (hex)
Value
1st byte
2nd byte
3rd byte
4th byte
5th byte
F5 (hex)
AB (hex)
Exiting the QPI
mode
enters deep
power down
mode
release from
deep power down
mode
to set Burst length
Action
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ID/Security Commands
REMS (read
electronic
electronic ID) manufacturer (QPI ID Read)
& device ID)
RDID
(read identific-
Command
(byte)
RES (read
QPIID
ENSO (enter EXSO (exit
RDSFDP
secured OTP) secured OTP)
ation)
Mode
SPI
SPI/QPI
SPI
QPI
SPI/QPI
5A (hex)
SPI/QPI
B1 (hex)
SPI/QPI
C1 (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
9F (hex)
AB (hex)
90 (hex)
AF (hex)
x
x
x
x
ADD1(8)
x
ADD2(8)
ADD (Note 2)
ADD3(8)
Dummy(8)
n bytes read
out until CS# 4K-bit secured bit secured
outputs JEDEC to read out
output the
ID in QPI
interface
to enter the to exit the 4K-
ID: 1-byte
Manufacturer
ID & 2-byte
Device ID
1-byte Device Manufacturer
ID
ID & Device ID
goes high
OTP mode
OTP mode
Action
RDSCUR
WRSCUR
SBLK
SBULK
RDBLOCK
GBLK
GBULK
(gang block
unlock)
COMMAND
(byte)
(read security (write security (single block (single block (block protect (gang block
register)
SPI/QPI
2B (hex)
register)
SPI/QPI
2F (hex)
lock
SPI/QPI
36 (hex)
unlock)
SPI/QPI
39 (hex)
read)
SPI/QPI
3C (hex)
lock)
SPI/QPI
7E (hex)
Mode
SPI/QPI
1st byte
2nd byte
3rd byte
4th byte
5th byte
98 (hex)
ADD1
ADD2
ADD3
ADD1
ADD2
ADD3
ADD1
ADD2
ADD3
to read value to set the lock-
individual
block (64K-
individual block read individual whole chip
(64K-byte) or block or sector write protect
whole chip
unprotect
of security
register
down bit as
"1" (once lock- byte) or sector sector (4K-
down, cannot (4K-byte) write byte) unprotect
write protect
status
Action
be update)
protect
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Reset Commands
RST
(Reset
Memory)
COMMAND
NOP
RSTEN
Release Read
Enhanced
(byte)
(No Operation) (Reset Enable)
Mode
SPI/QPI
00 (hex)
SPI/QPI
66 (hex)
SPI/QPI
99 (hex)
SPI/QPI
FF (hex)
1st byte
2nd byte
3rd byte
4th byte
5th byte
All these
commands
FFh, 00h, AAh
or 55h will
escape the
performance
mode
Action
(Note 4)
Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different
from 1 x I/O condition.
Note 2: ADD=00H will output the manufacturer ID first and ADD=01H will output device ID first.
Note 3: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hid-
den mode.
Note 4: RST command only executed if RSTEN command is executed first. Any intervening command will disable Reset.
Note 5:
The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example,
"Data(8)" represents there are 8 clock cycles for the data in.
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9-1. Write Enable (WREN)
The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, 4PP,
SE, BE32K, BE, CE, and WRSR, which are intended to change the device content WEL bit should be set every time
after the WREN instruction setting the WEL bit.
The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
Figure 6. Write Enable (WREN) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
Command
06h
SI
High-Z
SO
Figure 7. Write Enable (WREN) Sequence (QPI Mode)
CS#
0
1
Mode 3
SCLK
Mode 0
Command
SIO[3:0]
06h
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9-2. Write Disable (WRDI)
The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.
The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The WEL bit is reset by following situations:
- Power-up
- Reset# pin driven low
- Completion of Write Disable (WRDI) instruction
- Completion of Write Status Register (WRSR) instruction
- Completion of Page Program (PP) instruction
- Completion of Quad Page Program (4PP) instruction
- Completion of Sector Erase (SE) instruction
- Completion of Block Erase 32KB (BE32K) instruction
- Completion of Block Erase (BE) instruction
- Completion of Chip Erase (CE) instruction
- Pgm/Ers Suspend
Figure 8. Write Disable (WRDI) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
Command
04h
SI
High-Z
SO
Figure 9. Write Disable (WRDI) Sequence (QPI Mode)
CS#
0
1
Mode 3
SCLK
Mode 0
Command
SIO[3:0]
04h
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9-3. Read Identification (RDID)
The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macro-
nix Manufacturer ID and Device ID are listed as Table 6 ID Definitions.
The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out
on SO→ to end RDID operation can drive CS# to high at any time during data out.
While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on
the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby
stage.
Figure 10. Read Identification (RDID) Sequence (SPI mode only)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
Mode 3
Mode 0
SCLK
SI
Command
9Fh
Manufacturer Identification
Device Identification
High-Z
SO
7
6
5
3
2
1
0
15 14 13
MSB
3
2
1
0
MSB
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9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)
The Release from Deep Power-down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip
Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the
Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in
the Deep Power-down mode, the transition to the Stand-by Power mode is delayed by tRES2, and Chip Select (CS#)
must remain High for at least tRES2(max), as specified in Table 16. AC Characteristics. Once in the Stand-by Power
mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction
is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from deep power
down mode.
RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 6 ID
Definitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,
please use RDID instruction.
Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in
progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeat-
edly if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously
in Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in
Deep Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least
tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute
instruction.
Figure 11. Read Electronic Signature (RES) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
SCLK
Command
ABh
t
3 Dummy Bytes
RES2
SI
23 22 21
MSB
3
2
1
0
Electronic Signature Out
High-Z
7
6
5
4
3
2
0
1
SO
MSB
Deep Power-down Mode
Stand-by Mode
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Figure 12. Read Electronic Signature (RES) Sequence (QPI Mode)
CS#
MODE 3
0
1
2
3
4
5
6
7
SCLK
MODE 0
3 Dummy Bytes
Command
ABh
SIO[3:0]
X
X
X
X
X
X
H0 L0
MSB LSB
Data Out
Data In
Stand-by Mode
Deep Power-down Mode
Figure 13. Release from Deep Power-down (RDP) Sequence (SPI Mode)
CS#
t
RES1
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
SI
Command
ABh
High-Z
SO
Deep Power-down Mode
Stand-by Mode
Figure 14. Release from Deep Power-down (RDP) Sequence (QPI Mode)
CS#
t
RES1
Mode 3
Mode 0
0
1
SCLK
Command
SIO[3:0]
ABh
Deep Power-down Mode
Stand-by Mode
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9-5. Read Electronic Manufacturer ID & Device ID (REMS)
The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the
JEDEC assigned manufacturer ID and the specific device ID.
The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is initi-
ated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes ad-
dress (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out on the falling
edge of SCLK with most significant bit (MSB) first. The Device ID values are listed in Table 6 of ID Definitions. If the
one-byte address is initially set to 01h, then the device ID will be read first and then followed by the Manufacturer
ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The instruction is
completed by driving CS# high.
Figure 15. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)
CS#
0
1
2
3
4
5
6
7
8
9 10
Mode 3
Mode 0
SCLK
Command
90h
2 Dummy Bytes
SI
15 14 13
3
2
1
0
High-Z
SO
CS#
47
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
ADD (1)
7
6
5
4
3
2
0
1
SI
Manufacturer ID
Device ID
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Notes:
(1) ADD=00H will output the manufacturer's ID first and ADD=01H will output device ID first.
(2) Instruction is either 90(hex).
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9-6. QPI ID Read (QPIID)
The QPIID Read instruction identifies the devices as MX25U3235F/MX25U6435F and manufacturer as Macronix.
The sequence of issue QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes
high. Most significant bit (MSB) first.
Immediately following the command cycle the device outputs data on the falling edge of the SCLK signal. The data
output stream is continuous until terminated by a low-to-high transition of CS#. The device outputs three bytes of
data: "Manufactory ID, Memory type and Memory density".
Table 6. ID Definitions
Command Type Command
MX25U3235F
Manufactory ID
C2
Memory type
Memory density
36
RDID / QPIID
RES
9Fh / AFh
ABh
25
Electronic ID
36
Manufactory ID
C2
Device ID
36
REMS
90h
Command Type Command
MX25U6435F
Manufactory ID
C2
Memory type
Memory density
37
RDID / QPIID
RES
9Fh / AFh
ABh
25
Electronic ID
37
Manufactory ID
C2
Device ID
37
REMS
90h
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9-7. Read Status Register (RDSR)
The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even
in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before
sending a new instruction when a program, erase, or write status register operation is in progress.
The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data
out on SO.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
Figure 16. Read Status Register (RDSR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Mode 3
Mode 0
SCLK
SI
command
05h
Status Register Out
Status Register Out
High-Z
SO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
Figure 17. Read Status Register (RDSR) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
N
SCLK
SIO[3:0]
05h
H0 L0 H0 L0 H0 L0
H1 L1
MSB
LSB
Status Byte Status Byte Status Byte
Status Byte
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For user to check if Program/Erase operation is finished or not, RDSR instruction flow are shown as follows:
Figure 18. Program/Erase flow with read array data
start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
Read array data
(same address of PGM/ERS)
No
Verify OK?
Yes
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDBLOCK to check the block status.
No
Program/erase completed
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Figure 19. Program/Erase flow without read array data (read P_FAIL/E_FAIL flag)
start
WREN command
RDSR command*
No
WREN=1?
Yes
Program/erase command
Write program data/address
(Write erase address)
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
RDSCUR command
P_FAIL/E_FAIL =1 ?
Yes
No
Program/erase successfully
Program/erase fail
Yes
Program/erase
another block?
* Issue RDSR to check BP[3:0].
* If WPSEL = 1, issue RDBLOCK to check the block status.
No
Program/erase completed
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Status Register
The definition of the status register bits is as below:
WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta-
tus register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status register
progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status register
cycle.
WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable
latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/
erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the device
will not accept program/erase/write status register instruction. The program/erase command will be ignored if it is ap-
plied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next program/
erase/operations, WIP bit needs to be confirm to be 0 before polling WEL bit. After WIP bit confirmed, WEL bit needs
to be confirmed as 0.
BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area (as
defined in Table 2) of the device to against the program/erase instruction without hardware protection mode being set.
To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be ex-
ecuted. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block
Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0) set to 0,
the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default, which is un-protected.
QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,
RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other
word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET will be disabled.
SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection
(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and
WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is
no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The
SRWD bit defaults to be "0".
Status Register
bit7
bit6
bit5
BP3
(level of
protected
block)
bit4
BP2
(level of
protected
block)
bit3
BP1
(level of
protected
block)
bit2
BP0
(level of
protected
block)
bit1
bit0
SRWD (status
register write
protect)
QE
(Quad
Enable)
WEL
(write enable
latch)
WIP
(write in
progress bit)
1=Quad
Enable
0=not Quad
Enable
1=write
enable
0=not write 0=not in write
1=write
operation
1=status
register write
disable
(note 1)
(note 1)
(note 1)
(note 1)
enable
operation
Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile
bit bit bit bit bit bit
volatile bit
volatile bit
Note 1: see the Table 2 "Protected Area Size".
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MX25U6435F
9-8. Write Status Register (WRSR)
The WRSR instruction is for changing the values of Status Register Bits and Configuration Register Bits. Before
sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write
Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,
BP0) bits to define the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad
enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/
SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot
be executed once the Hardware Protected Mode (HPM) is entered.
The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register
data on SI→CS# goes high.
If Reset# goes low during WRSR execution (SPI mode), the device will be reset to Standby mode after tREC (Recovery
Time from Erase). Please note that the correct operation of WRSR is not guaranteed in this situation.
The CS# must go high exactly at the 8 bites or 16 bits data boundary; otherwise, the instruction will be rejected and
not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes
high. The Write in Progress (WIP) bit still can be checked during the Write Status Register cycle is in progress. The
WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable
Latch (WEL) bit is reset.
Figure 20. Write Status Register (WRSR) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Mode 3
Mode 0
SCLK
command
01h
Status
Register In
SI
4
2
1
0
7
6
5
3
MSB
High-Z
SO
Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.
Figure 21. Write Status Register (WRSR) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
SCLK
SR in
Command
01h
H0 L0
SIO[3:0]
P/N: PM1698
REV. 1.0, FEB. 03, 2012
33
MX25U3235F
MX25U6435F
Software Protected Mode (SPM):
-
When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can
change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1,
BP0, is at software protected mode (SPM).
-
When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values of
SRWD, BP3, BP2, BP1, BP0. The protected area, which is defined by BP3, BP2, BP1, BP0, is at software pro-
tected mode (SPM)
Note:
If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously
been set. It is rejected to write the Status Register and not be executed.
Hardware Protected Mode (HPM):
-
When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware
protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,
BP1, BP0 and hardware protected mode by the WP#/SIO2 to against data modification.
Note:
To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.
If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only can
use software protected mode via BP3, BP2, BP1, BP0.
If the system enter QPI or set QE=1, the feature of HPM will be disabled.
Table 7. Protection Modes
Mode
Status register condition
WP# and SRWD bit status
Memory
Status register can be written
in (WEL bit is set to "1") and
the SRWD, BP0-BP3
Software protection
mode (SPM)
WP#=1 and SRWD bit=0, or
WP#=0 and SRWD bit=0, or
WP#=1 and SRWD=1
The protected area
cannot
be program or erase.
bits can be changed
The SRWD, BP0-BP3 of
status register bits cannot be
changed
The protected area
cannot
be program or erase.
Hardware protection
mode (HPM)
WP#=0, SRWD bit=1
Note:
1. As defined by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
P/N: PM1698
REV. 1.0, FEB. 03, 2012
34
MX25U3235F
MX25U6435F
Figure 22. WRSR flow
start
WREN command
RDSR command
No
WREN=1?
Yes
WRSR command
Write status register
data
RDSR command
No
WIP=0?
Yes
RDSR command
Read WEL=0, BP[3:0], QE,
and SRWD data
No
Verify OK?
Yes
WRSR successfully
WRSR fail
P/N: PM1698
REV. 1.0, FEB. 03, 2012
35
MX25U3235F
MX25U6435F
Figure 23. WP# Setup Timing and Hold Timing during WRSR when SRWD=1
WP#
CS#
tSHWL
tWHSL
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14
15
SCLK
01h
SI
High-Z
SO
P/N: PM1698
REV. 1.0, FEB. 03, 2012
36
MX25U3235F
MX25U6435F
9-9. Read Data Bytes (READ)
The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on
the falling edge of SCLK at a maximum frequency fR. The first address byte can be at any location. The address
is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can
be read out at a single READ instruction. The address counter rolls over to 0 when the highest address has been
reached.
The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte address on
SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.
Figure 24. Read Data Bytes (READ) Sequence (SPI Mode only)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
command
03h
24-Bit Address
23 22 21
MSB
3
2
1
0
SI
Data Out 1
Data Out 2
High-Z
2
7
6
5
4
3
1
7
0
SO
MSB
P/N: PM1698
REV. 1.0, FEB. 03, 2012
37
MX25U3235F
MX25U6435F
9-10. Read Data Bytes at Higher Speed (FAST_READ)
The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and
data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at
any location. The address is automatically increased to the next higher address after each byte data is shifted out,
so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when
the highest address has been reached.
Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ
instruction code→ 3-byte address on SI→1-dummy byte (default) address on SI→ data out on SO→ to end FAST_
READ operation can use CS# to high at any time during data out.
Read on QPI Mode The sequence of issuing FAST_READ instruction in QPI mode is: CS# goes low→ sending
FAST_READ instruction, 2 cycles→ 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0→4 dummy cycles→data
out interleave on SIO3, SIO2, SIO1 & SIO0→ to end QPI FAST_READ operation can use CS# to high at any time
during data out.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h,5Ah,F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-
wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any im-
pact on the Program/Erase/Write Status Register current cycle.
P/N: PM1698
REV. 1.0, FEB. 03, 2012
38
MX25U3235F
MX25U6435F
Figure 25. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
Mode 3
Mode 0
SCLK
Command
0Bh
24-Bit Address
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
Figure 26. Read at Higher Speed (FAST_READ) Sequence (QPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCLK
Command
0Bh
SIO(3:0)
X
X
H0 L0 H1 L1
A5 A4 A3 A2 A1 A0
24-Bit Address
X
X
MSB LSB MSB LSB
Data Out 1 Data Out 2
Data In
P/N: PM1698
REV. 1.0, FEB. 03, 2012
39
MX25U3235F
MX25U6435F
9-11. 2 x I/O Read Mode (2READ)
The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising
edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a maxi-
mum frequency fT. The first address byte can be at any location. The address is automatically increased to the next
higher address after each byte data is shifted out, so the whole memory can be read out at a single 2READ instruc-
tion. The address counter rolls over to 0 when the highest address has been reached. Once writing 2READ instruc-
tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit.
The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 24-bit address inter-
→
→
leave on SIO1 & SIO0 4 dummy cycles on SIO1 & SIO0 data out interleave on SIO1 & SIO0 to end 2READ
→
→
→
operation can use CS# to high at any time during data out.
While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
Figure 27. 2 x I/O Read Mode Sequence (SPI Mode only)
CS#
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
17 18 19 20 21 22 23 24 25 26 27 28 29 30
SCLK
Data
Data
4 Dummy
cycle
12 ADD Cycles
Command
Out 1
Out 2
D6 D4 D2 D0 D6 D4 D2 D0
A22 A20 A18
A23 A21 A19
A4 A2 A0
BBh
SI/SIO0
D7 D5 D3 D1 D7 D5 D3 D1
A5 A3 A1
SO/SIO1
P/N: PM1698
REV. 1.0, FEB. 03, 2012
40
MX25U3235F
MX25U6435F
9-12. 4 x I/O Read Mode (4READ)
The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status Reg-
ister must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK, and
data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency fQ.
The first address byte can be at any location. The address is automatically increased to the next higher address af-
ter each byte data is shifted out, so the whole memory can be read out at a single 4READ instruction. The address
counter rolls over to 0 when the highest address has been reached. Once writing 4READ instruction, the following
address/dummy/data out will perform as 4-bit instead of previous 1-bit.
4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending
→
4READ instruction 24-bit address interleave on SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles data out inter-
→
→
→
leave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time during data out.
→
4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence of
issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 24-bit address interleave on
→
→
SIO3, SIO2, SIO1 & SIO0 2+4 dummy cycles data out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ
→
→
→
operation can use CS# to high at any time during data out.
Another sequence of issuing 4 READ instruction especially useful in random access is : CS# goes low sending
→
4 READ instruction 3-bytes address interleave on SIO3, SIO2, SIO1 & SIO0 performance enhance toggling bit
→
→
P[7:0] 4 dummy cycles data out still CS# goes high
CS# goes low (reduce 4 Read instruction) 24-bit ran-
→
→
→
→
dom access address.
In the performance-enhancing mode, P[7:4] must be toggling with P[3:0] ; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh can
make this mode continue and reduce the next 4READ instruction. Once P[7:4] is no longer toggling with P[3:0]; like-
wise P[7:0]=FFh,00h,AAh or 55h and afterwards CS# is raised and then lowered, the system then will escape from
performance enhance mode and return to normal operation.
While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact
on the Program/Erase/Write Status Register current cycle.
P/N: PM1698
REV. 1.0, FEB. 03, 2012
41
MX25U3235F
MX25U6435F
Figure 28. 4 x I/O Read Mode Sequence (SPI Mode)
CS#
23 24
10 11 12 13 14 15 16 17 18 19 20 21 22
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
SCLK
Data
Out 1
Data
Out 2 Out 3
Data
4 Dummy
Cycles
Command
EBh
6 ADD Cycles
Performance
enhance
indicator (Note)
A20 A16 A12 A8 A4 A0
D4 D0 D4 D0 D4 D0
P4 P0
SIO0
SIO1
SIO2
SIO3
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2
P5 P1
P6 P2
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3 D7 D3
P7 P3
Note:
1. Hi-impedance is inhibited for the two clock cycles.
2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.
Figure 29. 4 x I/O Read Mode Sequence (QPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MODE 3
MODE 0
MODE 3
MODE 0
SCLK
EB
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
A5 A4 A3 A2 A1 A0
24-bit Address
X
X
X
X
X
X
MSB
Data Out
Data In
P/N: PM1698
REV. 1.0, FEB. 03, 2012
42
MX25U3235F
MX25U6435F
Figure 30. W4READ (Quad Read with 4 dummy cycles) Sequence
CS#
Mode 3
０
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCLK
Mode ０
4 Dummy
Cycles
Data Data Data
Out 1 Out 2 Out 3
Command
E7h
6 ADD Cycles
D4 D0 D4 D0 D4 D0
D4
A20 A16 A12 A8 A4 A0
SIO0
SIO1
SIO2
D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2
D5
D6
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3 D7 D3
D7
SIO3
P/N: PM1698
REV. 1.0, FEB. 03, 2012
43
MX25U3235F
MX25U6435F
9-13. Burst Read
This device supports Burst Read in both SPI and QPI mode.
To set the Burst length, following command operation is required
Issuing command: “C0h” in the first Byte (8-clocks), following 4 clocks defining wrap around enable with “0h” and
disable with“1h”.
Next 4 clocks is to define wrap around depth. Definition as following table:
Data
1xh
1xh
1xh
1xh
Wrap Around
Wrap Depth
Data
00h
01h
02h
03h
Wrap Around
Wrap Depth
8-byte
No
No
No
No
X
X
X
X
Yes
Yes
Yes
Yes
16-byte
32-byte
64-byte
The wrap around unit is defined within the 256Byte page, with random initial address. It’s defined as “wrap-around
mode disable” for the default state of the device. To exit wrap around, it is required to issue another “C0” command
in which data=‘1xh”. Otherwise, wrap around status will be retained until power down or reset command. To change
wrap around depth, it is requried to issue another “C0” command in which data=“0xh”. QPI “0Bh” “EBh” and SPI “EBh”
“E7h” support wrap around feature after wrap around enable. Burst read is supported in both SPI and QPI mode.
The device id default without Burst read.
Figure 31. SPI Mode
CS#
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCLK
SIO
D7
D6
D5
D4
D3
D2
D1
D0
C0h
Figure 32. QPI Mode
CS#
0
1
2
3
Mode 3
Mode 0
SCLK
C0h
H0
L0
SIO[3:0]
MSB LSB
Note: MSB=Most Significant Bit
LSB=Least Significant Bit
P/N: PM1698
REV. 1.0, FEB. 03, 2012
44
MX25U3235F
MX25U6435F
9-14. Performance Enhance Mode
The device could waive the command cycle bits if the two cycle bits after address cycle toggles.
Performance enhance mode is supported in both SPI and QPI mode.
In QPI mode, “EBh” “0Bh” and SPI “EBh” “E7h” commands support enhance mode. The performance enhance
mode is not supported in dual I/O mode.
After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of
the first clock as address instead of command cycle.
To exit enhance mode, a new fast read command whose first two dummy cycles is not toggle then exit. Or issue
”FFh” command to exit enhance mode.
P/N: PM1698
REV. 1.0, FEB. 03, 2012
45
MX25U3235F
MX25U6435F
Figure 33. 4 x I/O Read enhance performance Mode Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
n
SCLK
Data
Out 1
Data
Out 2
Data
Out n
4 Dummy
Cycles
Command
EBh
6 ADD Cycles
Performance
enhance
indicator (Note)
P4 P0
D4 D0 D4 D0
D4 D0
A20 A16 A12 A8 A4 A0
SIO0
SIO1
SIO2
SIO3
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
D5 D1 D5 D1
D6 D2 D6 D2
D5 D1
D6 D2
P5 P1
P6 P2
A23 A19 A15 A11 A7 A3
D7 D3 D7 D3
D7 D3
P7 P3
CS#
n+1
...........
n+7......n+9 ........... n+13
...........
Mode 3
Mode 0
SCLK
4 Dummy
Cycles
Data
Out 1
Data
Out 2
Data
Out n
6 ADD Cycles
Performance
enhance
indicator (Note)
D4 D0 D4 D0
D4 D0
P4 P0
A20 A16 A12 A8 A4 A0
SIO0
SIO1
SIO2
SIO3
D5 D1 D5 D1
D6 D2 D6 D2
D5 D1
D6 D2
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
P5 P1
P6 P2
D7 D3 D7 D3
D7 D3
A23 A19 A15 A11 A7 A3
P7 P3
Note:
1. Performance enhance mode, if P7≠P3 & P6≠P2 & P5≠P1 & P4≠P0 (Toggling), ex: A5, 5A, 0F, if not using
performance enhance recommend to keep 1 or 0 in performance enhance indicator.
2. Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF
P/N: PM1698
REV. 1.0, FEB. 03, 2012
46
MX25U3235F
MX25U6435F
Figure 34. 4 x I/O Read enhance performance Mode Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCLK
EBh
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
Data In
4 dummy
cycles
Data Out
performance
enhance
indicator
CS#
SCLK
n+1 .............
Mode 0
SIO[3:0]
X
X
X
X
H0 L0 H1 L1
MSB LSB MSB LSB
A5 A4 A3 A2 A1 A0
P(7:4)P(3:0)
4 dummy
cycles
Data Out
6 Address cycles
performance
enhance
indicator
P/N: PM1698
REV. 1.0, FEB. 03, 2012
47
MX25U3235F
MX25U6435F
9-15. Performance Enhance Mode Reset (FFh)
To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh command code, 8 clocks, should be
issued in 1I/O sequence. In QPI Mode, FFFFFFFFh command code, 8 clocks, in 4I/O should be issued.
If the system controller is being Reset during operation, the flash device will return to the standard SPI operation.
Upon Reset of main chip, SPI instruction would be issued from the system. Instructions like Read ID (9Fh) or Fast
Read (0Bh) would be issued.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
Figure 35. Performance Enhance Mode Reset for Fast Read Quad I/O (SPI and QPI Mode)
Mode Bit Reset
for Quad I/O
CS#
Mode 3
Mode 3
０
1
2
3
4
5
6
7
SCLK
Mode ０
Mode ０
FFh (SPI)
SIO0
SIO1
SIO2
FFFFFFFFh (QPI)
Don’t Care (SPI)
FFFFFFFFh (QPI)
Don’t Care (SPI)
FFFFFFFFh (QPI)
Don’t Care (SPI)
SIO3
FFFFFFFFh (QPI)
P/N: PM1698
REV. 1.0, FEB. 03, 2012
48
MX25U3235F
MX25U6435F
9-16. Sector Erase (SE)
The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for
any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before
sending the Sector Erase (SE). Any address of the sector (see Table 4 memory organization) is a valid address
for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address
byte been latched-in); otherwise, the instruction will be rejected and not executed.
Address bits [Am-A12] (Am is the most significant address) select the sector address.
The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte address on SI→
CS# goes high.
If Reset# goes low during SE execution (SPI mode), the device will be reset to Standby mode after tREC (Recovery
Time from Erase). Please note that the correct operation of SE is not guaranteed in this situation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Sector Erase cycle is in progress. The WIP sets 1 during the
tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the sector is protected by BP3, BP2, BP1, BP0 bits, the Sector Erase (SE) instruction will not be executed on the
sector.
Figure 36. Sector Erase (SE) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
SCLK
24-Bit Address
Command
20h
SI
23 22
2
1
0
MSB
Figure 37. Sector Erase (SE) Sequence (QPI Mode)
CS#
Mode 3
0
1
2
3
4
5
6
7
SCLK
Mode 0
24-Bit Address
Command
SIO[3:0]
20h A5 A4 A3 A2 A1 A0
MSB LSB
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9-17. Block Erase (BE32K)
The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
32K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE32K). Any address of the block (see Table 4 memory organization) is a valid
address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte boundary (the latest eighth
of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte address
on SI→CS# goes high.
If Reset# goes low during BE32K execution (SPI mode), the device will be reset to Standby mode after tREC (Recovery
Time from Erase). Please note that the correct operation of BE32K is not guaranteed in this situation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write
in Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the
tBE32K timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If
the block is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (tBE32K) instruction will not be executed on the
block.
Figure 38. Block Erase 32KB (BE32K) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
SCLK
Command
52h
24-Bit Address
SI
23 22
MSB
2
0
1
Figure 39. Block Erase 32KB (BE32K) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
24-Bit Address
Command
SIO[3:0]
52h A5 A4 A3 A2 A1 A0
MSB
P/N: PM1698
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MX25U6435F
9-18. Block Erase (BE)
The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for
64K-byte block erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL)
bit before sending the Block Erase (BE). Any address of the block (Please refer to Table 4 memory organization)
is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest
eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed.
The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte address on SI→
CS# goes high.
If Reset# goes low during BE execution (SPI mode), the device will be reset to Standby mode after tREC (Recovery
Time from Erase). Please note that the correct operation of BE is not guaranteed in this situation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Block Erase cycle is in progress. The WIP sets 1 during the tBE
timing, and sets 0 when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the block
is protected by BP3, BP2, BP1, BP0 bits, the Block Erase (BE) instruction will not be executed on the block.
Figure 40. Block Erase (BE) Sequence (SPI Mode)
CS#
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
SCLK
Command
D8h
24-Bit Address
SI
23 22
2
0
1
MSB
Figure 41. Block Erase (BE) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
24-Bit Address
Command
SIO[3:0]
D8h A5 A4 A3 A2 A1 A0
MSB
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9-19. Chip Erase (CE)
The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruc-
tion must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS# must go
high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.
The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.
If Reset# goes low during CE execution (SPI mode), the device will be reset to Standby mode after tREC (Recovery
Time from Erase). Please note that the correct operation of CE is not guaranteed in this situation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE
timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the chip is
protected by BP3, BP2, BP1, BP0 bits, the Chip Erase (CE) instruction will not be executed. It will be only execut-
ed when BP3, BP2, BP1, BP0 all set to "0".
Figure 42. Chip Erase (CE) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCLK
SI
Command
60h or C7h
Figure 43. Chip Erase (CE) Sequence (QPI Mode)
CS#
0
1
Mode 3
SCLK
Command
60h or C7h
Mode 0
SIO[3:0]
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9-20. Page Program (PP)
The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction
must be executed to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). The device pro-
grams only the last 256 data bytes sent to the device. If the entire 256 data bytes are going to be programmed, A7-
A0 (The eight least significant address bits) should be set to 0. If the eight least significant address bits (A7-A0) are
not all 0, all transmitted data going beyond the end of the current page are programmed from the start address of
the same page (from the address A7-A0 are all 0). If more than 256 bytes are sent to the device, the data of the last
256-byte is programmed at the request page and previous data will be disregarded. If less than 256 bytes are sent
to the device, the data is programmed at the requested address of the page without effect on other address of the
same page.
The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte address on SI→ at
least 1-byte on data on SI→ CS# goes high.
If Reset# goes low during PP execution (SPI mode), the device will be reset to Standby mode after tREC (Recovery
Time from Erase). Please note that the correct operation of PP is not guaranteed in this situation.
The CS# must be kept low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary (the
latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed.
The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in
Progress (WIP) bit still can be checked during the Page Program cycle is in progress. The WIP sets 1 during the
tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the
page is protected by BP3, BP2, BP1, BP0 bits, the Page Program (PP) instruction will not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
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Figure 44. Page Program (PP) Sequence (SPI Mode)
CS#
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
SCLK
Command
02h
Data Byte 1
24-Bit Address
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
SI
MSB
CS#
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCLK
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
SI
MSB
MSB
MSB
Figure 45. Page Program (PP) Sequence (QPI Mode)
CS#
Mode 3
Mode 0
0
1
2
SCLK
Command
02h
24-Bit Address
SIO[3:0]
H0 L0 H1 L1 H2 L2 H3 L3
H255 L255
A5 A4 A3 A2 A1 A0
......
Data Byte Data Byte Data Byte Data Byte
Data Byte
256
Data In
1
2
3
4
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9-21. 4 x I/O Page Program (4PP)
The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN) in-
struction must execute to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to "1" before
sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1, SIO2, and
SIO3 as address and data input, which can improve programmer performance and the effectiveness of application.
The 4PP operation frequency supports as fast as 104MHz. The other function descriptions are as same as standard
page program.
The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte address on
SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.
Figure 46. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)
CS#
10 11 12 13 14 15 16 17 18 19 20 21
Data Data Data Data
0
1
2
3
4
5
6
7
8
9
Mode 3
Mode 0
SCLK
Command
38h
6 ADD cycles
Byte 1 Byte 2 Byte 3 Byte 4
A16 A12 A8 A4 A0
A20
D4 D0 D4 D0 D4 D0
D0
D4
SIO0
SIO1
SIO2
SIO3
A21 A17 A13 A9 A5 A1
A22 A18 A14 A10 A6 A2
D5 D1 D5 D1 D5 D1 D5 D1
D6 D2 D6 D2 D6 D2 D6 D2
A23 A19 A15 A11 A7 A3 D7 D3 D7 D3 D7 D3 D7 D3
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MX25U6435F
9-22. Deep Power-down (DP)
The Deep Power-down (DP) instruction is for setting the device on the minimizing the power consumption (to enter-
ing the Deep Power-down mode), the standby current is reduced from ISB1 to ISB2). The Deep Power-down mode
requires the Deep Power-down (DP) instruction to enter, during the Deep Power-down mode, the device is not ac-
tive and all Write/Program/Erase instruction are ignored. When CS# goes high, it's only in deep power-down mode
not standby mode. It's different from Standby mode.
The sequence of issuing DP instruction is: CS# goes low→sending DP instruction code→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
Once the DP instruction is set, all instructions will be ignored except the Release from Deep Power-down mode
(RDP) and Read Electronic Signature (RES) instruction and softreset command. (those instructions allow the ID be-
ing reading out). When Power-down, or software reset command the deep power-down mode automatically stops,
and when power-up, the device automatically is in standby mode. For DP instruction the CS# must go high exactly
at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not be
executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power-down
mode.
Figure 47. Deep Power-down (DP) Sequence (SPI Mode)
CS#
tDP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCLK
SI
Command
B9h
Stand-by Mode
Deep Power-down Mode
Figure 48. Deep Power-down (DP) Sequence (QPI Mode)
CS#
t
DP
Mode 3
Mode 0
0
1
SCLK
Command
SIO[3:0]
B9h
Stand-by Mode
Deep Power-down Mode
P/N: PM1698
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9-23. Enter Secured OTP (ENSO)
The ENSO instruction is for entering the additional 4K-bit secured OTP mode. The additional 4K-bit secured OTP is
independent from main array, which may use to store unique serial number for system identifier. After entering the
Secured OTP mode, and then follow standard read or program procedure to read out the data or update data. The
Secured OTP data cannot be updated again once it is lock-down.
The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
Please note that WRSR/WRSCUR commands are not acceptable during the access of secure OTP region, once se-
curity OTP is lock down, only read related commands are valid.
9-24. Exit Secured OTP (EXSO)
The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.
The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP
mode→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
9-25. Read Security Register (RDSCUR)
The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read
at any time (even in program/erase/write status register/write security register condition) and continuously.
The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register
data out on SO→ CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The definition of the Security Register bits is as below:
Secured OTP Indicator bit. The Secured OTP indicator bit shows the chip is locked by factory before ex- factory or
not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.
Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for cus-
tomer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured OTP
area cannot be update any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.
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Table 8. Security Register Definition
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
ESB
(Erase
PSB
(Program
LDSO
(indicate if
Secured OTP
indicator bit
WPSEL
E_FAIL
P_FAIL
Reserved
Suspend bit) Suspend bit) lock-down)
0=normal
Program
succeed
1=indicate
Program
failed
0 = not lock-
0=normal
Erase
succeed
1=individual
Erase failed
(default=0)
0=Erase
is not
suspended suspended
1= Erase 1= Program
suspended suspended
0=Program
is not
0=normal
WP mode
1=individual
mode
down
1 = lock-down
(cannot
program/
erase
0 = non-
factory
lock
1 = factory
lock
-
(default=0)
(default=0)
(default=0)
(default=0)
OTP)
Non-volatile
bit
Non-volatile
bit (OTP)
Non-volatile
bit (OTP)
Volatile bit
Volatile bit
Volatile bit
Volatile bit
Volatile bit
(OTP)
9-26. Write Security Register (WRSCUR)
The WRSCUR instruction is for changing the values of Security Register Bits. The WREN (Write Enable) instruction
is required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO
bit) for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area
cannot be updated any more.
The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.
If Reset# goes low during WRSCUR execution (SPI mode), the device will be reset to Standby mode after tREC
(Recovery Time from Erase). Please note that the correct operation of WRSCUR is not guaranteed in this situation.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.
P/N: PM1698
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9-27. Write Protection Selection (WPSEL)
There are two write protection methods, (1) BP protection mode (2) individual block protection mode. If WPSEL=0,
flash is under BP protection mode . If WPSEL=1, flash is under individual block protection mode. The default value
of WPSEL is “0”. WPSEL command can be used to set WPSEL=1. Please note that WPSEL is an OTP bit. Once
WPSEL is set to 1, there is no chance to recover WPSEL bit back to “0”. If the flash is under BP mode, the indi-
vidual block protection mode is disabled. Contrarily, if flash is on the individual block protection mode, the BP mode
is disabled.
Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all
the blocks or sectors will be write protected by default. User may only unlock the blocks or sectors via SBULK
and GBULK instruction. Program or erase functions can only be operated after the Unlock instruction is conducted.
BP protection mode, WPSEL=0:
ARRAY is protected by BP3~BP0 and BP3~BP0 bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7
of status register that can be set by WRSR command.
Individual block protection mode, WPSEL=1:
Blocks are individually protected by their own SRAM lock bits which are set to “1” after power up. SBULK and SBLK
command can set SRAM lock bit to “0” and “1”. When the system accepts and executes WPSEL instruction, the bit
7 in security register will be set. It will activate SBLK, SBULK, RDBLOCK, GBLK, GBULK etc instructions to conduct
block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0) indicated block meth-
ods.Under the individual block protection mode (WPSEL=1), hardware protection is performed by driving WP#=0.
Once WP#=0 all array blocks/sectors are protected regardless of the contents of SRAM lock bits.
The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual
block protect mode → CS# goes high.
WPSEL instruction function flow is as follows:
BP and SRWD if WPSEL=0
WP# pin
BP3 BP2 BP1 BP0
SRWD
64KB
64KB
64KB
(1) BP3~BP0 is used to define the protection group region.
(The protected area size see Table 2)
(2) “SRWD=1 and WP#=0” is used to protect BP3~BP0. In this
case, SRWD and BP3~BP0 of status register bits can not
be changed by WRSR
.
.
.
64KB
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The individual block lock mode is effective after setting WPSEL=1
4KB
4KB
SRAM
SRAM
• Power-Up: All SRAM bits=1 (all blocks are default protected).
All array cannot be programmed/erased
TOP 4KBx16
Sectors
• SBLK/SBULK(36h/39h):
- SBLK(36h): Set SRAM bit=1 (protect) : array can not be
programmed/erased
4KB
SRAM
SRAM
- SBULK(39h): Set SRAM bit=0 (unprotect): array can be
programmed/erased
64KB
- All top 4KBx16 sectors and bottom 4KBx16 sectors
and other 64KB uniform blocks can be protected and
unprotected by SRAM bits individually by SBLK/SBULK
command set.
SRAM
Uniform
64KB blocks
• GBLK/GBULK(7Eh/98h):
- GBLK(7Eh): Set all SRAM bits=1,whole chip is protected
and cannot be programmed/erased.
- GBULK(98h): Set all SRAM bits=0,whole chip is
unprotected and can be programmed/erased.
- All sectors and blocks SRAM bits of whole chip can be
protected and unprotected at one time by GBLK/GBULK
command set.
64KB
4KB
SRAM
SRAM
Bottom
4KBx16
Sectors
• RDBLOCK(3Ch):
- use RDBLOCK mode to check the SRAM bits status after
SBULK /SBLK/GBULK/GBLK command set.
4KB
SBULK / SBLK / GBULK / GBLK / RDBLOCK
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Figure 49. WPSEL Flow
start
WREN command
RDSCUR(2Bh) command
WPSEL=1?
Yes
No
WPSEL disable,
block protected by BP[3:0]
WPSEL(68h) command
RDSR command
WIP=0?
No
Yes
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL set successfully
WPSEL set fail
WPSEL enable.
Block protected by individual lock
(SBLK, SBULK,
… etc).
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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9-28. Single Block Lock/Unlock Protection (SBLK/SBULK)
These instructions are only effective after WPSEL was executed. The SBLK instruction is for write protection a spec-
ified block (or sector) of memory, using AMAX-A16 or (AMAX-A12) address bits to assign a 64Kbyte block (or 4K bytes
sector) to be protected as read only. The SBULK instruction will cancel the block (or sector) write protection state.
This feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (GBULK).
The WREN (Write Enable) instruction is required before issuing SBLK/SBULK instruction.
The sequence of issuing SBLK/SBULK instruction is: CS# goes low → send SBLK/SBULK (36h/39h)
instruction→send 3-byte address assign one block (or sector) to be protected on SI pin → CS# goes high. The CS#
must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
SBLK/SBULK instruction function flow is as follows:
Figure 50. Block Lock Flow
Start
RDSCUR(2Bh) command
No
WPSEL=1?
WPSEL command
Yes
WREN command
SBLK command
( 36h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command
( 3Ch + 24bit address )
No
Data = FFh ?
Yes
Block lock successfully
Block lock fail
Yes
Lock another block?
No
Block lock completed
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Figure 51. Block Unlock Flow
start
RDSCUR(2Bh) command
No
WPSEL=1?
Yes
WPSEL command
WREN command
SBULK command
( 39h + 24bit address )
RDSR command
No
WIP=0?
Yes
RDBLOCK command to verify
( 3Ch + 24bit address )
Yes
Data = FF ?
No
Block unlock successfully
Block unlock fail
Yes
Unlock another block?
Unlock block completed?
P/N: PM1698
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9-29. Read Block Lock Status (RDBLOCK)
This instruction is only effective after WPSEL was executed. The RDBLOCK instruction is for reading the status of
protection lock of a specified block (or sector), using AMAX-A16 (or AMAX-A12) address bits to assign a 64K bytes block (4K
bytes sector) and read protection lock status bit which the first byte of Read-out cycle. The status bit is"1" to indicate
that this block has be protected, that user can read only but cannot write/program /erase this block. The status bit is
"0" to indicate that this block hasn't be protected, and user can read and write this block.
The sequence of issuing RDBLOCK instruction is: CS# goes low → send RDBLOCK (3Ch) instruction → send
3-byte address to assign one block on SI pin → read block's protection lock status bit on SO pin → CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
9-30. Gang Block Lock/Unlock (GBLK/GBULK)
These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is for enable/disable
the lock protection block of the whole chip.
The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.
The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction
→CS# goes high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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MX25U6435F
9-31. Program/ Erase Suspend/ Resume
The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other
operations. Details as follows.
To enter the suspend/ resume mode: issuing B0h for suspend; 30h for resume (SPI/QPI all acceptable)
Read security register bit2 (PSB) and bit3 (ESB) (please refer to Table 8) to check suspend ready information.
Suspend to suspend ready timing: 20us.
Resume to another suspend timing: 1ms.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
9-32. Erase Suspend
Erase suspend allows the interruption of all erase operations.
After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including:
03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 30h, 66h, 99h, C0h, 35h, F5h, 00h, ABh )
After issuing erase suspend command, latency time 20us is needed before issuing another command.
ESB bit (Erase Suspend Bit) indicates the status of Erase suspend operation. ESB bit is set to "1" when suspend
command is issued during erase operation. When erase operation resumes, ESB bit is reset to "0".
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
When ESB bit is issued, the Write Enable Latch (WEL) bit will be reset.
9-33. Program Suspend
Program suspend allows the interruption of all program operations.
After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.
(including: 03h, 0Bh, BBh, EBh, E7h, 9Fh, AFh, 90h, 05h, 2Bh, B1h, C1h, 5Ah, 3Ch, 30h, 66h, 99h, C0h, 35h, F5h,
00h, ABh )
After issuing program suspend command, latency time 20us is needed before issuing another command.
PSB bit (Program Suspend Bit) indicates the status of Program suspend operation. PSB bit is set to "1" when
suspend command is issued during program operation. When program operation resumes, PSB bit is reset to "0".
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
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Figure 52. Suspend to Read Latency
Program latency : 20us
Erase latency:20us
Suspend Command
Read Command
CS#
[B0]
Figure 53. Resume to Read Latency
TSE/TBE/TPP
Resume Command
Read Command
CS#
[30]
Figure 54. Resume to Suspend Latency
1ms
Suspend
Command
[B0]
Resume Command
CS#
[30]
P/N: PM1698
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9-34. Write-Resume
The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in
Status register will be changed back to “0”
The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30H) → drive
CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed
or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming.
WREN (command "06" is not required to issue before resume. Resume to another suspend operation requires
latency time of 1ms.
Please note that, if "performance enhance mode" is executed during suspend operation, the device can not
be resumed. To restart the write command, disable the "performance enhance mode" is required. After the
"performance enhance mode" is disable, the write-resume command is effective.
9-35. No Operation (NOP)
The No Operation command only cancels a Reset Enable command. NOP has no impact on any other command.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
9-36. Software Reset (Reset-Enable (RSTEN) and Reset (RST))
The Reset operation is used as a system (software) reset that puts the device in normal operating Ready mode.
This operation consists of two commands: Reset-Enable (RSTEN) and Reset (RST).
To reset the device the host drives CS# low, sends the Reset-Enable command (66H), and drives CS# high. Next,
the host drives CS# low again, sends the Reset command (99H), and drives CS# high.
Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are "don't care"
in SPI mode.
The Reset operation requires the Reset-Enable command followed by the Reset command. Any command other
than the Reset command after the Reset-Enable command will disable the Reset-Enable.
A successful command execution will reset the device to SPI stand-by read mode, which is its default state. A
device reset during an active Program or Erase operation aborts the operation, which can cause the data of the
targeted address range to be corrupted or lost. Depending on the prior operation, the reset time may vary. Recovery
from a write operation requires more latency time than recovery from other operations.
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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Figure 55. Software Reset Recovery
Stand-by Mode
66
99
CS#
tRCR
tRCP
tREC
Mode
tRCR: 20us (Recovery Time from Read)
tRCP: 20us (Recovery Time from Program)
tREC: 12ms (Recovery Time from Erase)
Figure 56. Reset Sequence (SPI mode)
CS#
SCLK
SIO0
Mode 3
Mode 0
Mode 3
Mode 0
Command
66h
Command
99h
Figure 57. Reset Sequence (QPI mode)
tSHSL
CS#
MODE 3
MODE 3
MODE 0
MODE 3
MODE 0
SCLK
MODE 0
Command
Command
SIO[3:0]
66h
99h
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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9-37. Read SFDP Mode (RDSFDP)
The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional
and feature capabilities of serial flash devices in a standard set of internal parameter tables. These parameter tables
can be interrogated by host system software to enable adjustments needed to accommodate divergent features
from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on
CFI.
The sequence of issuing RDSFDP instruction is same as FAST_READ: CS# goes low→send RDSFDP instruction
(5Ah)→send 3 address bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP
operation can use CS# to high at any time during data out.
SFDP is a standard of JEDEC. JESD216. v1.0.
Figure 58. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence
CS#
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
SCLK
Command
5Ah
24 BIT ADDRESS
SI
23 22 21
3
2
1
0
High-Z
SO
CS#
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
SCLK
Dummy Cycle
7
6
5
4
3
2
0
1
SI
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
SO
MSB
MSB
MSB
P/N: PM1698
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Table 9. Signature and Parameter Identification Data Values
Description Comment
Add (h) DW Add Data (h/b)
Data
(h)
(Byte)
(Bit)
(Note1)
00h
07:00
53h
53h
46h
44h
50h
00h
01h
01h
01h
02h
03h
04h
05h
06h
15:08
23:16
31:24
07:00
15:08
23:16
46h
44h
50h
00h
01h
01h
SFDP Signature
Fixed: 50444653h
SFDP Minor Revision Number
SFDP Major Revision Number
Number of Parameter Headers
Start from 00h
Start from 01h
Start from 00h
Contains 0xFFh and can never be
changed
00h: it indicates a JEDEC specified
header.
Unused
07h
08h
09h
0Ah
0Bh
31:24
07:00
15:08
23:16
31:24
FFh
00h
00h
01h
09h
FFh
00h
00h
01h
09h
ID number (JEDEC)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Parameter Table Length
(in double word)
Start from 0x00h
Start from 0x01h
How many DWORDs in the
Parameter table
0Ch
0Dh
0Eh
07:00
15:08
23:16
30h
00h
00h
30h
00h
00h
First address of JEDEC Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
Contains 0xFFh and can never be
changed
it indicates Macronix manufacturer
ID
0Fh
10h
11h
12h
13h
31:24
07:00
15:08
23:16
31:24
FFh
C2h
00h
01h
04h
FFh
C2h
00h
01h
04h
ID number
(Macronix manufacturer ID)
Parameter Table Minor Revision
Number
Parameter Table Major Revision
Number
Start from 0x00h
Start from 0x01h
Parameter Table Length
(in double word)
How many DWORDs in the
Parameter table
14h
15h
16h
07:00
15:08
23:16
60h
00h
00h
60h
00h
00h
First address of Macronix Flash
Parameter table
Parameter Table Pointer (PTP)
Unused
Contains 0xFFh and can never be
changed
17h
31:24
FFh
FFh
P/N: PM1698
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Table 10. Parameter Table (0): JEDEC Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
00: Reserved, 01: 4KB erase,
10: Reserved,
Block/Sector Erase sizes
01:00
01b
11: not suport 4KB erase
Write Granularity
0: 1Byte, 1: 64Byte or larger
02
03
1b
0b
Write Enable Instruction
Requested for Writing to Volatile 1: Volatitle status bit
0: Nonvolatitle status bit
Status Registers
(BP status register bit)
30h
E5h
0: use 50h opcode,
1: use 06h opcode
Write Enable Opcode Select for
Writing to Volatile Status Registers
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
0b
Contains 111b and can never be
changed
Unused
07:05
111b
4KB Erase Opcode
31h
32h
33h
15:08
16
20h
0b
20h
B0h
FFh
(1-1-2) Fast Read (Note2)
0=not support 1=support
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
19
00b
0b
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
(1-2-2) Fast Read
(1-4-4) Fast Read
(1-1-4) Fast Read
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
20
21
1b
1b
22
0b
23
1b
Unused
31:24
FFh
(32Mb)
Flash Memory Density
(64Mb)
37h:34h 31:00
37h:34h 31:00
01FFFFFFh
03FFFFFFh
(1-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
38h
0 0100b
states (Note3)
Clocks) not support
44h
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
010b
EBh
(1-4-4) Fast Read Opcode
39h
3Ah
3Bh
15:08
20:16
EBh
00h
FFh
(1-1-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0000b
states
Clocks) not support
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
31:24
000b
FFh
(1-1-4) Fast Read Opcode
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Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
(Byte)
(Bit)
(Note1)
(1-1-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
04:00
0 0000b
states
Clocks) not support
3Ch
00h
FFh
04h
BBh
(1-1-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
07:05
15:08
20:16
000b
FFh
(1-1-2) Fast Read Opcode
3Dh
3Eh
3Fh
(1-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
0 0100b
states
Clocks) not support
(1-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
000b
(1-2-2) Fast Read Opcode
(2-2-2) Fast Read
Unused
31:24
00
BBh
0b
0=not support 1=support
0=not support 1=support
03:01
04
111b
1b
40h
FEh
(4-4-4) Fast Read
Unused
07:05
111b
0xFFh
0xFFh
Unused
43h:41h 31:08
45h:44h 15:00
0xFFh
0xFFh
Unused
(2-2-2) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
46h
0 0000b
000b
states
Clocks) not support
00h
(2-2-2) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(2-2-2) Fast Read Opcode
Unused
47h
31:24
FFh
FFh
49h:48h 15:00
0xFFh
0xFFh
(4-4-4) Fast Read Number of Wait 0 0000b: Wait states (Dummy
20:16
4Ah
0 0100b
states
Clocks) not support
44h
(4-4-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
010b
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
(4-4-4) Fast Read Opcode
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
31:24
07:00
15:08
23:16
31:24
07:00
15:08
23:16
31:24
EBh
0Ch
20h
0Fh
52h
10h
D8h
00h
FFh
Sector/block size = 2^N bytes (Note5)
0x00b: this sector type doesn't exist
Sector Type 1 Size
Sector Type 1 erase Opcode
Sector Type 2 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 2 erase Opcode
Sector Type 3 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 3 erase Opcode
Sector Type 4 Size
Sector/block size = 2^N bytes
0x00b: this sector type doesn't exist
Sector Type 4 erase Opcode
P/N: PM1698
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Table 11. Parameter Table (1): Macronix Flash Parameter Tables
Add (h) DW Add Data (h/b)
Data
(h)
Description
Comment
2000h=2.000V
2700h=2.700V
3600h=3.600V
(Byte)
(Bit)
(Note1)
07:00
15:08
00h
20h
00h
20h
Vcc Supply Maximum Voltage
61h:60h
1650h=1.650V
2250h=2.250V
2350h=2.350V
2700h=2.700V
23:16
31:24
50h
16h
50h
16h
Vcc Supply Minimum Voltage
63h:62h
HW Reset# pin
0=not support 1=support
00
1b
HW Hold# pin
0=not support 1=support
0=not support 1=support
0=not support 1=support
01
02
03
0b
1b
1b
Deep Power Down Mode
SW Reset
Reset Enable (66h) should be issued
before Reset command
1001 1001b
(99h)
65h:64h
F99Dh
SW Reset Opcode
11:04
Program Suspend/Resume
Erase Suspend/Resume
Unused
0=not support 1=support
0=not support 1=support
12
13
1b
1b
14
1b
Wrap-Around Read mode
Wrap-Around Read mode Opcode
0=not support 1=support
15
1b
66h
67h
23:16
C0h
C0h
64h
08h:support 8B wrap-around read
16h:8B&16B
32h:8B&16B&32B
Wrap-Around Read data length
31:24
64h
64h:8B&16B&32B&64B
Individual block lock
0=not support 1=support
0=Volatile 1=Nonvolatile
00
01
1b
0b
Individual block lock bit
(Volatile/Nonvolatile)
0011 0110b
(36h)
Individual block lock Opcode
09:02
10
Individual block lock Volatile
protect bit default protect status
0=protect 1=unprotect
0b
C8D9h
6Bh:68h
Secured OTP
Read Lock
Permanent Lock
Unused
0=not support 1=support
0=not support 1=support
0=not support 1=support
11
12
1b
0b
13
0b
15:14
31:16
11b
FFh
0xFFh
Unused
FFh
Unused
6Fh:6Ch 31:00
0xFFh
P/N: PM1698
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Note 1: h/b is hexadecimal or binary.
Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),
address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),
and (4-4-4)
Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.
Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller
if they are specified. (eg,read performance enhance toggling bits)
Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h
Note 6: Memory within the SFDP address space that has not yet been defined or used, default to all 0xFFh.
Note 7: The maximum clock rate=33MHz when reading SFDP area.
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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10. RESET
Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at
the following states:
- Standby mode
- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.
If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data
could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to
minimum.
Figure 59. RESET Timing
CS#
tRHRL
SCLK
tRH
tRS
RESET#
tRLRH
Table 12. Reset Timing
Symbol Alt. Parameter
Min.
1
15
15
Typ.
Max.
Unit
us
ns
tRLRH
tRS
Reset Pulse Width
Reset Setup Time
Reset Hold Time
tRH
ns
Reset Recovery Time (During instruction decoding)
Read
20
20
12
20
20
us
us
ms
us
us
tRCR
tRHRL tREC Reset Recovery Time
tRCP
Erase
Program
Reset Recovery Time (for WRSR operation)
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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11. POWER-ON STATE
The device is at below states when power-up:
- Standby mode (please note it is not deep power-down mode)
- Write Enable Latch (WEL) bit is reset
The device must not be selected during power-up and power-down stage unless the VCC achieves below correct
level:
- VCC minimum at power-up stage and then after a delay of tVSL
- GND at power-down
Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.
An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change
during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and
the flash device has no response to any command.
For further protection on the device, after VCC reaching the VWI level, a tPUW time delay is required before the
device is fully accessible for commands like write enable (WREN), page program (PP), quad page program (4PP),
sector erase (SE), block erase 32KB (BE32K), block erase (BE), chip erase (CE), WRSCUR and write status regis-
ter (WRSR). If the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The write,
erase, and program command should be sent after the below time delay:
- tPUW after VCC reached VWI level
- tVSL after VCC reached VCC minimum level
The device can accept read command after VCC reached VCC minimum and a time delay of tVSL, even time of
tPUW has not passed.
Please refer to the "power-up timing".
Note:
- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommend-
ed. (generally around 0.1uF)
- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response
to any command. The data corruption might occur during the stage while a write, program, erase cycle is in
progress.
P/N: PM1698
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12. ELECTRICAL SPECIFICATIONS
Table 13. ABSOLUTE MAXIMUM RATINGS
Rating
Value
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
Industrial grade
-40°C to 85°C
-65°C to 150°C
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
-0.5V to VCC+0.5V
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specifications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot to VCC+1.0V or -0.5V for period up to 20ns.
4. All input and output pins may overshoot to VCC+0.2V.
Figure 61. Maximum Positive Overshoot Waveform
Figure 60. Maximum Negative Overshoot Waveform
20ns
0V
VCC+1.0V
-0.5V
2.0V
20ns
Table 14. CAPACITANCE TA = 25°C, f = 1.0 MHz
Symbol Parameter
Min.
Typ.
Max.
Unit
pF
Conditions
VIN = 0V
CIN
Input Capacitance
6
8
COUT Output Capacitance
pF
VOUT = 0V
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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Figure 62. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
Input timing referance level
Output timing referance level
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AC
Measurement
Level
0.5VCC
Note: Input pulse rise and fall time are <5ns
Figure 63. OUTPUT LOADING
25K ohm
DEVICE UNDER
TEST
+1.8V
CL
25K ohm
CL=30pF Including jig capacitance
P/N: PM1698
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Table 15. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V)
°
°
Symbol Parameter
Notes
Min.
Typ.
Max.
Units Test Conditions
VCC = VCC Max,
uA
ILI
Input Load Current
Output Leakage Current
1
±2
VIN = VCC or GND
VCC = VCC Max,
uA
ILO
1
1
±2
80
20
VOUT = VCC or GND
VIN = VCC or GND,
CS# = VCC
ISB1 VCC Standby Current
30
5
uA
Deep Power-down
Current
VIN = VCC or GND,
CS# = VCC
ISB2
uA
f=104MHz, (4 x I/O read)
mA SCLK=0.1VCC/0.9VCC,
SO=Open
20
15
ICC1 VCC Read
1
1
f=84MHz,
mA SCLK=0.1VCC/0.9VCC,
SO=Open
VCC Program Current
Program in Progress,
CS# = VCC
ICC2
(PP)
20
25
20
mA
VCC Write Status
ICC3
Program status register in
mA
Register (WRSR) Current
progress, CS#=VCC
VCC Sector/Block (32K,
ICC4 64K) Erase Current
(SE/BE/BE32K)
Erase in Progress,
CS#=VCC
1
1
20
20
25
25
mA
VCC Chip Erase Current
Erase in Progress,
CS#=VCC
ICC5
(CE)
mA
VIL
VIH
VOL
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.2VCC
VCC+0.4
0.2
V
V
0.8VCC
V
V
IOL = 100uA
IOH = -100uA
VOH Output High Voltage
VCC-0.2
Notes :
1. Typical values at VCC = 1.8V, T = 25 C. These currents are valid for all product versions (package and speeds).
°
2. Typical value is calculated by simulation.
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Table 16. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 1.65V ~ 2.0V)
°
°
Symbol Alt. Parameter
Min.
Typ.(2)
Max.
Unit
Clock Frequency for the following instructions:
fC FAST_READ, PP, SE, BE, CE, DP, RES, RDP,
WREN, WRDI, RDID, RDSR, WRSR
fSCLK
D.C.
104
MHz
fRSCLK
fTSCLK
fR Clock Frequency for READ instructions (6)
fT Clock Frequency for 2READ instructions
fQ Clock Frequency for 4READ instructions (5)
50
84
MHz
MHz
84/104 MHz
Others (fSCLK)
Normal Read (fRSCLK)
Others (fSCLK)
4.5
9
4.5
9
0.1
0.1
5
ns
ns
ns
tCH(1)
tCLH Clock High Time
tCL(1)
tCLL Clock Low Time
Normal Read (fRSCLK)
ns
tCLCH(2)
tCHCL(2)
Clock Rise Time (3) (peak to peak)
V/ns
V/ns
ns
ns
ns
Clock Fall Time (3) (peak to peak)
tSLCH tCSS CS# Active Setup Time (relative to SCLK)
tCHSL CS# Not Active Hold Time (relative to SCLK)
tDVCH tDSU Data In Setup Time
5
2
tCHDX
tCHSH
tSHCH
tDH Data In Hold Time
3
2
3
5
ns
ns
ns
ns
CS# Active Hold Time (relative to SCLK)
CS# Not Active Setup Time (relative to SCLK)
Read
tSHSL(3) tCSH CS# Deselect Time
Write/Erase/Program
30
ns
tSHQZ(2) tDIS Output Disable Time
8
8
6
ns
ns
ns
ns
ns
ns
us
Loading: 30pF
Loading: 15pF
Clock Low to Output Valid
tCLQV
tV
Loading: 30pF/15pF
tHO Output Hold Time
Write Protect Setup Time
Write Protect Hold Time
tCLQX
tWHSL
tSHWL
tDP(2)
0
10
10
CS# High to Deep Power-down Mode
CS# High to Standby Mode without Electronic Signature
Read
CS# High to Standby Mode with Electronic Signature
Read
10
30
tRES1(2)
us
us
tRES2(2)
30
tRCR
tRCP
tRCE
tW
tBP
tPP
Recovery Time from Read
Recovery Time from Program
Recovery Time from Erase
Write Status Register Cycle Time
Byte-Program
20
20
12
40
30
3
us
us
ms
ms
us
12
1.2
Page Program Cycle Time
ms
0.008+
(nx0.004) (8)
60
tPP(7)
Page Program Cycle Time (n bytes)
3
ms
tSE
tBE32
tBE
Sector Erase Cycle Time
Block Erase (32KB) Cycle Time
Block Erase (64KB) Cycle Time
200
1
2
ms
s
s
0.25
0.5
32Mb
25
50
50
100
s
s
tCE
Chip Erase Cycle Time
64Mb
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Notes:
1. tCH + tCL must be greater than or equal to 1/ Frequency.
2. Typical values given for TA=25 C. Not 100% tested.
°
3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
4. Test condition is shown as Figure 62, Figure 63.
5. When dummy cycle=4 (In both QPI & SPI mode), maximum clock rate=84MHz; when dummy cycle=6 (In both
QPI & SPI mode), maximum clock rate=104MHz.
6. The maximum clock rate=33MHz when reading secured OTP area.
7. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to pro-
gram the whole 256 bytes or only a few bytes between 1~256 bytes.
8. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us.
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13. OPERATING CONDITIONS
At Device Power-Up and Power-Down
AC timing illustrated in Figure 64 and Figure 65 are for the supply voltages and the control signals at device power-
up and power-down. If the timing in the figures is ignored, the device will not operate correctly.
During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be
selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.
Figure 64. AC Timing at Device Power-Up
VCC(min)
VCC
GND
tVR
tSHSL
CS#
tSHCH
tSLCH
tCHSL
tCHSH
SCLK
tDVCH
tCHCL
tCHDX
tCLCH
MSB IN
LSB IN
SI
High Impedance
SO
Symbol
Parameter
Notes
Min.
Max.
Unit
tVR
VCC Rise Time
1
20
500000
us/V
Notes :
1. Sampled, not 100% tested.
2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the figure, please refer to
Table 16 AC CHARACTERISTICS.
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Figure 65. Power-Down Sequence
During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.
VCC
CS#
SCLK
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Figure 66. Power-up Timing
V
CC
V
(max)
CC
Chip Selection is Not Allowed
V
(min)
CC
Device is fully accessible
tVSL
V
WI
time
Note: VCC (max.) is 2.0V and VCC (min.) is 1.65V.
Table 17. Power-Up Timing and VWI Threshold
Symbol Parameter
Min.
500
1.0
Max.
Unit
us
V
tVSL(1)
VWI(1)
VCC(min) to CS# low (VCC Rise Time)
Command Inhibit Voltage
1.4
Note: 1. These parameters are characterized only.
13-1. INITIAL DELIVERY STATE
The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status
Register contains 00h (all Status Register bits are 0).
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14. ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
Min.
Typ. (1)
Max. (2)
Unit
ms
ms
s
Write Status Register Cycle Time
Sector Erase Cycle Time (4KB)
Block Erase Cycle Time (32KB)
Block Erase Cycle Time (64KB)
40
200
1
60
0.25
0.5
2
s
32Mb
25
50
100
30
3
s
Chip Erase Cycle Time
64Mb
50
s
Byte Program Time (via page program command)
Page Program Time
12
us
1.2
ms
cycles
Erase/Program Cycle
100,000
Note:
1. Typical program and erase time assumes the following conditions: 25 C, 1.8V, and all zero pattern.
°
2. Under worst conditions of 85 C and 1.65V.
°
3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming com-
mand.
4. The maximum chip programming time is evaluated under the worst conditions of 0C, VCC=1.8V, and 100K cycle
with 90% confidence level.
15. LATCH-UP CHARACTERISTICS
Min.
-1.0V
Max.
Input Voltage with respect to GND on all power pins, SI, CS#
Input Voltage with respect to GND on SO
2 VCCmax
VCC + 1.0V
+100mA
-1.0V
Current
-100mA
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.
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16. ORDERING INFORMATION
32Mb
PART NO.
CLOCK (MHz)
TEMPERATURE
-40 C~85 C
PACKAGE
8-SOP
(200mil)
8-WSON
(6x5mm)
Remark
MX25U3235FM2I-10G
104
104
°
°
MX25U3235FZNI-10G
-40 C~85 C
° °
64Mb
PART NO.
CLOCK (MHz)
TEMPERATURE
-40 C~85 C
PACKAGE
8-SOP
(200mil)
8-WSON
(6x5mm)
Remark
MX25U6435FM2I-10G
104
°
°
MX25U6435FZNI-10G
104
-40 C~85 C
° °
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17. PART NAME DESCRIPTION
MX 25 U 3235F ZN
I
10 G
OPTION:
G: RoHS Compliant
SPEED:
10: 104MHz
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
M2: 8-SOP(200mil)
ZN: 8-WSON
DENSITY & MODE:
3235F: 32Mb
6435F: 64Mb
TYPE:
U: 1.8V
DEVICE:
25: Serial Flash
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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18. PACKAGE INFORMATION
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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MX25U6435F
P/N: PM1698
REV. 1.0, FEB. 03, 2012
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19. REVISION HISTORY
Revision No. Description
Page
P78,83
P82
Date
AUG/25/2011
0.01
1. Modified Chip Erase Cycle Time
2. Modified tVSL(min.) from 500us to 800us
0.02
1. Changed title from "Advanced Information" to "Preliminary"
2. Modified Write Protection Selection (WPSEL) description
3. Modified Power-up Timing
P4
P59,60
P84
OCT/06/2011
1.0
1. Modified tVSL(min.) in Power-Up Timing Table
2. Modified value of tWHSL, tSHWL, tCHDX, tCHSH, tSHCH,
tSHSL and ISB1(max.) in CHARACTERISTICS Table
P84
P79,80
FEB/03/2012
3. Added Reset# description for write/erase execution
P33,49,50~53,58,75
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Copyright© Macronix International Co., Ltd. 2011~2012. All rights reserved, including the trademarks and
tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit,
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91
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