MX26LV400TTC-70_技术文档

MX26LV400

Macronix NBit^TMMemory Family

4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE

3V ONLY BOOT SECTOR HIGH SPEED eLiteFlash^TMMEMORY

FEATURES

• Extended single - supply voltage range 3.0V to 3.6V

• 524,288 x 8/262,144 x 16 switchable

• Singlepowersupplyoperation

• Status Reply

- Data# polling & Toggle bit for detection of program

anderaseoperationcompletion.

• Ready/Busy# pin (RY/BY#)

-Providesahardwaremethodofdetectingprogramor

eraseoperationcompletion.

- 3.0V only operation for read, erase and program

operation

• Fast access time: 55/70ns

• Lowpowerconsumption

• 2,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Sector Architecture

- 30mA maximum active current

- 30uA typical standby current

• Commandregisterarchitecture

-Byte/wordProgramming(typical)

- Sector Erase (Sector structure 16K-Bytex1,

8K-Bytex2, 32K-Bytex1, and 64K-Byte x7)

• Auto Erase (chip & sector) and Auto Program

-Automaticallyeraseanycombinationofsectorswith

Erase verify capability.

- T = Top Boot Sector

- B = Bottom Boot Sector

• Package type:

- 48-pin TSOP

- 48-ball CSP

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

- Automatically program and verify data at specified

address

• 20 years data retention

GENERAL DESCRIPTION

The MX26LV400 is a 4-mega bit high speed Flash memory

organized as 512K bytes of 8 bits or 256K words of 16

bits. MXIC's high speed Flash memories offer the most

cost-effective and reliable read/write non-volatile random

access memory. The MX26LV400 is packaged in 48-pin

TSOP, and 48-ball CSP. It is designed to be repro-

grammed and erased in system or in standard EPROM

programmers.

for 100% TTL level control inputs and fixed power sup-

ply levels during erase and programming, while main-

taining maximum EPROM compatibility.

MXIC high speed Flash technology reliably stores

memory contents even after 2,000 erase and program

cycles. The MXIC cell is designed to optimize the erase

and programming mechanisms. In addition, the combi-

nation of advanced tunnel oxide processing and low in-

ternal electric fields for erase and program operations

produces reliable cycling. The MX26LV400 uses a

3.0V~3.6V VCC supply to perform the High Reliability

Erase and auto Program/Erase algorithms.

The standard MX26LV400 offers access time as fast as

55ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention, the

MX26LV400 has separate chip enable (CE#) and output

enable (OE#) controls.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamperes on

address and data pin from -1V to VCC + 1V.

MXIC's high speed Flash memories augment EPROM

functionality with in-circuit electrical erasure and program-

ming. The MX26LV400 uses a command register to

manage this functionality. The command register allows

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MX26LV400

PIN CONFIGURATIONS

PIN DESCRIPTION

48 TSOP (Standard Type) (12mm x 20mm)

SYMBOL PIN NAME

A0~A17 Address Input

Q0~Q14 Data Input/Output

A15

A14

A13

A12

A11

A10

A9

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

GND

Q15/A-1

Q7

2

3

4

Q15/A-1

CE#

Q15(Word mode)/LSB addr(Byte mode)

5

6

Q14

Q6

Chip Enable Input

7

A8

8

Q13

Q5

WE#

Write Enable Input

NC

9

NC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Q12

Q4

BYTE#

Word/Byte Selection input

WE#

RESET#

NC

VCC

Q11

Q3

MX26LV400

RESET# Hardware Reset Pin

NC

OE#

Output Enable Input

Ready/Busy Output

Power Supply Pin (3.0V~3.6V)

Ground Pin

RY/BY#

NC

Q10

Q2

RY/BY#

VCC

A17

A7

Q9

Q1

A6

Q8

A5

Q0

GND

A4

OE#

GND

CE#

A0

A3

A2

A1

48-Ball CSP Ball Pitch = 0.8 mm,Top View, Balls Facing Down

A

B

C

D

E

F

G

H

6

5

4

3

2

1

A13

A9

A12

A8

A14

A10

NC

A6

A15

A11

NC

A5

A16

Q7

Q5

Q2

Q0

A0

BYTE# Q15/A-1 GND

Q14

Q12

Q10

Q8

Q13

Vcc

Q11

Q9

Q6

Q4

WE# RESET#

RY/BY#

A7

NC

A17

A4

Q3

Q1

A3

A2

A1

CE#

OE#

GND

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MX26LV400

BLOCK STRUCTURE

Table 1: MX26LV400T SECTOR ARCHITECTURE

Sector

Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode (x8)

Word Mode (x16) A17 A16 A15 A14 A13 A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

64Kbytes

32Kbytes

8Kbytes

32Kwords

16Kwords

4Kwords

00000-0FFFF

10000-1FFFF

20000-2FFFF

30000-3FFFF

40000-4FFFF

50000-5FFFF

60000-6FFFF

70000-77FFF

78000-79FFF

7A000-7BFFF

7C000-7FFFF

00000-07FFF

08000-0FFFF

10000-17FFF

18000-1FFFF

20000-27FFF

28000-2FFFF

30000-37FFF

38000-3BFFF

3C000-3CFFF

3D000-3DFFF

3E000-3FFFF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

1

8Kbytes

4Kwords

1

0

1

SA10 16Kbytes

8Kwords

1

X

Note:Byte mode:address range A17:A-1, word mode:address range A17:A0.

Table 2: MX26LV400B SECTOR ARCHITECTURE

Sector

Sector Size

Address range

Sector Address

Byte Mode Word Mode Byte Mode (x8)

Word Mode (x16) A17 A16 A15 A14 A13 A12

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

16Kbytes

8Kbytes

8Kwords

4Kwords

00000-03FFF

04000-05FFF

06000-07FFF

08000-0FFFF

10000-1FFFF

20000-2FFFF

30000-3FFFF

40000-4FFFF

50000-5FFFF

60000-6FFFF

70000-7FFFF

00000-01FFF

02000-02FFF

03000-03FFF

04000-07FFF

08000-0FFFF

10000-17FFF

18000-1FFFF

20000-27FFF

28000-2FFFF

30000-37FFF

38000-3FFFF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

8Kbytes

4Kwords

0

1

32Kbytes

64Kbytes

16Kwords

32Kwords

1

X

SA10 64Kbytes

Note:Byte mode:address range A17:A-1, word mode:address range A17:A0.

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MX26LV400

BLOCK DIAGRAM

WRITE

STATE

CE#

OE#

WE#

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

MACHINE

(WSM)

RESET#

LOGIC

STATE

REGISTER

ADDRESS

LATCH

FLASH

ARRAY

A0-A17

SOURCE

HV

AND

COMMAND

DATA

BUFFER

Y-PASS GATE

DECODER

PGM

DATA

HV

SENSE

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

I/O BUFFER

Q0-Q15/A-1

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MX26LV400

the device automatically times the erase pulse width,

provides the erase verification, and counts the number of

sequences. A status bit toggling between consecutive

read cycles provides feedback to the user as to the sta-

tus of the erasing operation.

AUTOMATIC PROGRAMMING

The MX26LV400 is word/byte programmable using the

Automatic Programming algorithm. The Automatic Pro-

gramming algorithm makes the external system do not

need to have time out sequence nor to verify the data

programmed.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE# or CE#, whichever

happens first.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (including

2 unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

A status bit similar to DATA# polling and a status bit

toggling between consecutive read cycles, provide feed-

back to the user as to the status of the programming

operation.Refer to write operation status, table 7, for more

information on these status bits.

MXIC's high speed Flash technology combines years of

EPROM experience to produce the highest levels of

quality, reliability, and cost effectiveness.The MX26LV400

electrically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by us-

ing the EPROM programming mechanism of hot electron

injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

The Automatic Erase algorithm automatically programs

the entire array prior to electrical erase. The timing and

verification of electrical erase are controlled internally

within the device.

AUTOMATIC SELECT

The auto select mode provides manufacturer and de-

vice identification, through identifier codes output on

Q7~Q0. This mode is mainly adapted for programming

equipment on the device to be programmed with its pro-

gramming algorithm.When programming by high voltage

method, automatic select mode requires VID (11V to

12V) on address pin A9 and other address pin A6, A1

and A0 as referring to Table 3. In addition, to access the

automatic select codes in-system, the host can issue

the automatic select command through the command

register without requiring VID, as shown in table 4.

AUTOMATIC SECTOR ERASE

The MX26LV400 is sector(s) erasable using MXIC's Auto

Sector Erase algorithm. The Automatic Sector Erase

algorithm automatically programs the specified sector(s)

prior to electrical erase. The timing and verification of

electrical erase are controlled internally within the de-

vice. An erase operation can erase one sector, multiple

sectors, or the entire device.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

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MX26LV400

TABLE 3. MX26LV400 AUTO SELECT MODE OPERATION

A17 A11 A9 A8 A6 A5 A1 A0

Description

Mode CE# OE# WE#

|

Q15~Q0

A12 A10

A7

A2

Manufacturer Code

L

H

X

VID

X

L

X

L

C2H

Read Device ID

Word

Byte

Word

X

H

22B9H

XXB9H

22BAH

XXBAH

Silicon (Top Boot Block)

ID

Device ID

(Bottom Boot Block) Byte

NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High

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MX26LV400

TABLE 4. MX26LV400 COMMAND DEFINITIONS

First Bus

Bus Cycle

Second Bus Third Bus

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Cycle

Cycle Addr Data Addr

Data Addr

Data Addr Data Addr

Data Addr Data

Reset

1

4

6

XXXH F0H

RA RD

Read

Read Silicon ID Word

Byte

555H AAH 2AAH 55H 555H 90H ADI

AAAH AAH 555H 55H AAAH 90H ADI

555H AAH 2AAH 55H 555H A0H PA

AAAH AAH 555H 55H AAAH A0H PA

DDI

PD

Program

Word

Byte

Word

Byte

Word

Byte

PD

Chip Erase

Sector Erase

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H

AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H

555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H

AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H

555H 10H

AAAH 10H

SA

30H

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A17=do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 22B9/B9(Top), and 22BA/BA(Bottom) for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address of the sector.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).

Write Sequence may be initiated with A11~A17 in either state.

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MX26LV400

COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. Table 5 defines the valid register command

sequences.

TABLE 5. MX26LV400 BUS OPERATION

ADDRESS

CE# OE# WE# RESET# A17 A10 A9 A8 A6 A5 A1 A0

Q8~Q15

DESCRIPTION

Q0~Q7

BYTE

=VIH

BYTE

=VIL

A12 A11

A7

A2

Read

L

H

AIN

Dout

Dout Q8~Q14

=High Z

Q15=A-1

Write

L

X

H

X

H

X

L

X

H

X

H

L

AIN

X

DIN(3)

High Z

DIN

Reset

High Z High Z

Output Disable

Standby

L

H

X

Vcc±

0.3V

Vcc±

0.3V

X

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 4.

2. VID is the Silicon-ID-Read high voltage, 11V to 12V.

3. Refer to Table 5 for valid Data-In during a write operation.

4. X can be VIL or VIH.

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MX26LV400

Characteristics" section contains timing specification

table and timing diagrams for write operations.

REQUIREMENTS FOR READING ARRAY

DATA

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins.WE# should re-

main at VIH.

STANDBY MODE

When using both pins of CE# and RESET#, the device

enter CMOS Standby with both pins held at Vcc ± 0.3V.

If CE# and RESET# are held at VIH, but not within the

range ofVCC ± 0.3V, the device will still be in the standby

mode, but the standby current will be larger.During Auto

Algorithm operation,Vcc active current (Icc2) is required

even CE# = "H" until the operation is completed. The

device can be read with standard access time (tCE) from

either of these standby modes, before it is ready to read

data.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address on

the device address inputs produce valid data on the de-

vice data outputs. The device remains enabled for read

access until the command register contents are altered.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output

from the devices are disabled.This will cause the output

pins to be in a high impedance state.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory

, the system must drive WE# and CE# to VIL, and OE#

to VIH.

RESET# OPERATION

The "word/byte Program Command Sequence" section

has details on programming data to the device.

The RESET# pin provides a hardware method of reset-

ting the device to reading array data.When the RESET#

pin is driven low for at least a period of tRP, the device

immediately terminates any operation in progress, tri-

states all output pins, and ignores all read/write com-

mands for the duration of the RESET# pulse. The de-

vice also resets the internal state machine to reading

array data.The operation that was interrupted should be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

An erase operation can erase one sector, multiple sec-

tors , or the entire device. Table indicates the address

space that each sector occupies. A "sector address"

consists of the address bits required to uniquely select a

sector.The "Writing specific address and data commands

or sequences into the command register initiates device

operations. Table 1 defines the valid register command

sequences.Writing incorrect address and data values or

writing them in the improper sequence resets the device

to reading array data. Section has details on erasing a

sector or the entire chip.

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at VSS±0.3V, the device draws

CMOS standby current (ICC4).If RESET# is held atVIL

but not within VSS±0.3V, the standby current will be

greater.

After the system writes the autoselect command se-

quence, the device enters the autoselect mode.The sys-

tem can then read autoselect codes from the internal

register (which is separate from the memory array) on

Q7-Q0. Standard read cycle timings apply in this mode.

Refer to the Autoselect Mode and Autoselect Command

Sequence section for more information.

The RESET# pin may be tied to system reset circuitry.

A system reset would that also reset the high speed

Flash, enabling the system to read the boot-up firmware

from the high speed Flash.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC

If RESET# is asserted during a program or erase opera-

tion, the RY/BY# pin remains a "0" (busy) until the inter-

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MX26LV400

nal reset operation is complete, which requires a time of

tREADY (during Embedded Algorithms).The system can

thus monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asserted when a

program or erase operation is completed within a time of

tREADY (not during Embedded Algorithms). The sys-

tem can read data tRH after the RESET# pin returns to

VIH.

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H or

sector erase command 30H.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 14 for the timing diagram.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

register contents are altered.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required).

If the Erase operation was unsuccessful, the data on

Q5 is "1" (see Table 7), indicating the erase operation

exceed internal timing limit.

SILICON-ID READ COMMAND

High speed Flash memories are intended for use in ap-

plications where the local CPU alters memory contents.

As such, manufacturer and device codes must be ac-

cessible while the device resides in the target system.

PROM programmers typically access signature codes

by raising A9 to a high voltage (VID). However, multi-

plexing high voltage onto address lines is not generally

desired system design practice.

The automatic erase begins on the rising edge of the

last WE# or CE# pulse, whichever happens first in the

command sequence and terminates when the data on

Q7 is "1" at which time the device returns to the Read

mode, or the data on Q6 stops toggling for two consecu-

tive read cycles at which time the device returns to the

Read mode.

The MX26LV400 contains a Silicon-ID-Read operation to

supple traditional PROM programming methodology. The

operation is initiated by writing the read silicon ID com-

mand sequence into the command register. Following

the command write, a read cycle with A1=VIL, A0=VIL

retrieves the manufacturer code of C2H/00C2H.

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MX26LV400

TABLE 6. SILICON ID CODE

Pins

A0

A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)

Manufacture code Word VIL VIL 00H

Byte VIL VIL

Word VIH VIL 22H

Byte VIH VIL

Word VIH VIL 22H

Byte VIH VIL

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00C2H

C2H

X

Device code

22B9H

B9H

for MX26LV400T

Device code

X

22BAH

BAH

for MX26LV400B

X

READING ARRAY DATA

RESET COMMAND

The device is automatically set to reading array data

after device power-up. No commands are required to re-

trieve data.The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algorithm.

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don't care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data.Once erasure begins, however, the device ignores

reset commands until the operation is complete.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or

while in the autoselect mode. See the "Reset Command"

section, next.

The reset command may be written between the se-

quence cycles in a program command sequence before

programming begins. This resets the device to reading

array data.Once programming begins, however, the de-

vice ignores reset commands until the operation is com-

plete.

The reset command may be written between the se-

quence cycles in an SILICON ID READ command se-

quence. Once in the SILICON ID READ mode, the reset

command must be written to return to reading array data.

If Q5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data.

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MX26LV400

followed by the program set-up command.The program

address and data are written next, which in turn initiate

the Embedded Program algorithm. The system is not

required to provide further controls or timings. The de-

vice automatically generates the program pulses and

verifies the programmed cell margin.Table 1 shows the

address and data requirements for the word/byte pro-

gram command sequence.

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-

vice to be entirely pre-programmed prior to executing

the Automatic Sector Erase Set-up command and Au-

tomatic Sector Erase command. Upon executing the

Automatic Sector Erase command, the device will auto-

matically program and verify the sector(s) memory for

an all-zero data pattern. The system is not required to

provide any control or timing during these operations.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using Q7,

Q6, or RY/BY#. See "Write Operation Status" for infor-

mation on these status bits.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when either the data on Q7 is "1" at which time the de-

vice returns to the Read mode, or the data on Q6 stops

toggling for two consecutive read cycles at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

Any commands written to the device during the Em-bed-

ded Program Algorithm are ignored. Note that a hard-

ware reset immediately terminates the programming

operation.The word/byte Program command sequence

should be reinitiated once the device has reset to read-

ing array data, to ensure data integrity.

When using the Automatic sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two "un-

lock" write cycles. These are followed by writing the

set-up command 80H. Two more "unlock" write cycles

are then followed by the sector erase command 30H.

The sector address is latched on the falling edge of WE#

or CE#, whichever happens later, while the command

(data) is latched on the rising edge of WE# or CE#,

whichever happens first. Sector addresses selected are

loaded into internal register on the sixth falling edge of

WE# or CE#, whichever happens later. Each succes-

sive sector load cycle started by the falling edge of WE#

or CE#, whichever happens later must begin within 50us

from the rising edge of the preceding WE# or CE#, which-

ever happens first. Otherwise, the loading period ends

and internal auto sector erase cycle starts. (Monitor Q3

to determine if the sector erase timer window is still open,

see section Q3, Sector EraseTimer.) Any command other

than Sector Erase (30H) during the time-out period re-

sets the device to read mode.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the op-

eration and set Q5 to "1" , or cause the Data# Polling

algorithm to indicate the operation was successful. How-

ever, a succeeding read will show that the data is still

"0". Only erase operations can convert a "0" to a "1".

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/

BY#.Table 7 and the following subsections describe the

functions of these bits. Q7, RY/BY#, and Q6 each offer

a method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

WORD/BYTE PROGRAM COMMAND SEQUENCE

The device programs one byte of data for each program

operation. The command sequence requires four bus

cycles, and is initiated by writing two unlock write cycles,

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MX26LV400

Q7: Data# Polling

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete. Toggle

Bit I may be read at any address, and is valid after the

rising edge of the final WE# or CE#, whichever happens

first, in the command sequence (prior to the program or

erase operation), and during the sector time-out.

The Data# Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command se-

quence.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7. When the Automatic Program algorithm is com-

plete, the device outputs the datum programmed to Q7.

The system must provide the program address to read

valid status information on Q7.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

control the read cycles.When the operation is complete,

Q6 stops toggling.

When the device is actively erasing (that is, the Auto-

matic Erase algorithm is in progress), Q6 toggling. How-

ever, the system must also use Q2 to determine which

sectors are erasing. Alternatively, the system can use

Q7.

During the Automatic Erase algorithm, Data# Polling pro-

duces a "0" on Q7. When the Automatic Erase algo-

rithm is complete, Data# Polling produces a "1" on Q7.

This is analogous to the complement/true datum out-put

described for the Automatic Program algorithm: the erase

function changes all the bits in a sector to "1" prior to

this, the device outputs the "complement," or "0". The

system must provide an address within any of the sec-

tors selected for erasure to read valid status information

on Q7.

Q6 stops toggling once the Automatic Program algo-

rithm is complete.

Table 7 shows the outputs for Toggle Bit I on Q6.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output En-

able (OE#) is asserted low.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process). Toggle Bit

II is valid after the rising edge of the final WE# or CE#,

whichever happens first, in the command sequence.

RY/BY# : Ready/Busy

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE# or CE# to control the read

cycles.) But Q2 cannot distinguish when the sector is

actively erasing. Q6, by comparison, indicates when

the device is actively erasing, but cannot distinguish

which sectors are selected for erasure. Thus, both sta-

tus bits are required for sectors and mode information.

Refer to Table 8 to compare outputs for Q2 and Q6.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program algorithm

is in progress or complete. The RY/BY# status is valid

after the rising edge of the final WE# or CE#, whichever

happens first, in the command sequence.Since RY/BY#

is an open-drain output, several RY/BY# pins can be

tied together in parallel with a pull-up resistor to VCC.

If the output is low (Busy), the device is actively erasing

or programming. If the output is high (Ready), the device

is ready to read array data, or is in the standby mode.

Reading Toggle Bits Q6/ Q2

Table 7 shows the outputs for RY/BY# during write op-

eration.

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

P/N:PM1094

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MX26LV400

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the word/byte

programming operation, it specifies that the entire sec-

tor containing that byte is bad and this sector may not

be reused, (other sectors are still functional and can be

reused).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase op-

eration. If it is still toggling, the device did not complete

the operation successfully, and the system must write

the reset command to return to reading array data.

The time-out condition will not appear if a user tries to

program a non blank location without erasing. Please

note that this is not a device failure condition since the

device was incorrectly used.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alterna-

tively, it may choose to perform other system tasks. In

this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the

operation.

Q5

ExceededTiming Limits

Q5 will indicate if the program or erase time has ex-

ceeded the specified limits (internal pulse count). Under

these conditions Q5 will produce a "1". This time-out

condition indicates that the program or erase cycle was

not successfully completed. Data# Polling and Toggle

Bit are the only operating functions of the device under

this condition.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

If this time-out condition occurs during the chip erase

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MX26LV400

TABLE 7. WRITE OPERATION STATUS

Status

Q7

Q6

Q5

(Note2)

0

Q3

Q2 RY/BY#

(Note1)

In Progress Word/Byte Program in Auto Program Algorithm

Q7# Toggle

N/A

No

0

Toggle

No

Auto Erase Algorithm

0

Toggle

0

1

0

Exceeded Word/Byte Program in Auto Program Algorithm

Time

Q7# Toggle

N/A

Toggle

Limits

Auto Erase Algorithm

0

Toggle

1

0

Note:

1. Q7 and Q2 require a valid address when reading status information.Refer to the appropriate subsection for further

details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5 : Exceeded Timing Limits" for more information.

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15

MX26LV400

Q3

POWER SUPPLY DECOUPLING

Sector Erase Timer

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data# Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

POWER-UP SEQUENCE

The MX26LV400 powers up in the Read only mode. In

addition, the memory contents may only be altered after

successful completion of the predefined command se-

quences.

If Data# Polling or the Toggle Bit indicates the device

has been written with a valid erase command, Q3 may

be used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data# Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept

additional sector erase commands. To insure the com-

mand has been accepted, the system software should

check the status of Q3 prior to and following each sub-

sequent sector erase command. If Q3 were high on the

second status check, the command may not have been

accepted.

DATA PROTECTION

The MX26LV400 is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tion. During power up the device automatically resets

the state machine in the Read mode. In addition, with its

control register architecture, alteration of the memory

contents only occurs after successful completion of spe-

cific command sequences. The device also incorporates

several features to prevent inadvertent write cycles re-

sulting fromVCC power-up and power-down transition or

system noise.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

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16

MX26LV400

ABSOLUTE MAXIMUM RATINGS

OPERATING RATINGS

StorageTemperature

Plastic Packages . . . . . . . . . . . . . ..... -65^oC to +150^oC

Commercial (C) Devices

Ambient Temperature (T^A). . . . . . . . . . . . 0° C to +70°C

V^CCSupply Voltages

AmbientTemperature

with Power Applied. . . . . . . . . . . . . .... -65^oC to +125^oC

Voltage with Respect to Ground

V^CCfor full voltage range. . . . . . . . . . . +3.0 V to 3.6 V

Operating ranges define those limits between which the

functionality of the device is guaranteed.

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, and

RESET# (Note 2) . . . . . . . . . . . . . . . . -0.5 V to +12 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-

mum DC voltage on input or I/O pins is VCC +0.5 V.

During voltage transitions, input or I/O pins may over-

shoot to VCC +2.0 V for periods up to 20 ns.

2.Minimum DC input voltage on pins A9, OE#, and RE-

SET# is -0.5 V. During voltage transitions, A9, OE#,

and RESET# may overshoot VSS to -2.0 V for peri-

ods of up to 20 ns. Maximum DC input voltage on pin

A9 is +12V which may overshoot to 13.5V for periods

up to 20 ns.

3.No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

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MX26LV400

CAPACITANCE TA = 25^oC, f = 1.0 MHz

SYMBOL PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

CIN1

CIN2

COUT

Input Capacitance

Control Pin Capacitance

Output Capacitance

12

pF

VIN = 0V

12

pF

VOUT = 0V

TABLE 8. DC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 3.0V~3.6V

MX26LV400

Symbol PARAMETER

MIN.

TYP

± 1

MAX.

± 3

UNIT

uA

CONDITIONS

ILI

Input Leakage Current

VIN = VSS to VCC

VCC=VCC max;

A9=12V

ILIT

A9 Input Leakage Current

Output Leakage Current

VCC Active Read Current

35

200

uA

ILO

± 1

uA

VOUT = VSS to VCC,

VCC=VCC max

ICC1

20

8

30

14

mA

uA

CE#=VIL,

OE#=VIH

@5MHz

@1MHz

ICC2

ICC3

ICC4

VCC Active write Current

VCC Standby Current

During Reset

26

30

CE#=VIL, OE#=VIH

100

CE#; RESET#=VCC ±0.3V

RESET#=VSS ± 0.3V

uA

VIL

VIH

VID

Input Low Voltage (Note 1)

Input HighVoltage

Voltage for Automatic

Select

-0.5

0.7xVCC

11

0.8

VCC+0.3

12

V

VCC=3.3V

VOL

Output LowVoltage

0.45

V

IOL = 4.0mA,

VCC= VCC min

IOH = -2mA,

VOH1

VOH2

Output HighVoltage (TTL)

0.85xVCC

VCC-0.4

VCC=VCC min

IOH = -100uA, VCC min

Output HighVoltage

(CMOS)

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.

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MX26LV400

AC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 3.0V~3.6V

TABLE 9. READ OPERATIONS

26LV400-55

26LV400-70

SYMBOLPARAMETER

MIN.

MAX.

MIN.

MAX. UNIT CONDITIONS

tRC

Read CycleTime (Note 1)

55

70

ns

tACC

tCE

Address to Output Delay

CE# to Output Delay

55

25

70

30

25

ns

CE#=OE#=VIL

OE#=VIL

tOE

tDF

OE# to Output Delay

CE#=VIL

OE# High to Output Float (Note1)

0

CE#=VIL

tOEH

Output

Read

0

Enable

Toggle and

Data# Polling

10

HoldTime

tOH

Address to Output hold

0

ns

CE#=OE#=VIL

NOTE:

1. Not 100% tested.

2. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

TEST CONDITIONS:

• Input pulse levels: 0V/3.0V.

• Input rise and fall times is equal to or less than 5ns.

• Outputload:1TTLgate+100pF(Includingscopeand

jig), for 26LV400-70. 1 TTL gate + 30pF (Including

scope and jig) for 26LV400-55.

• Reference levels for measuring timing: 1.5V.

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MX26LV400

SWITCHING TEST CIRCUITS

DEVICE UNDER

TEST

2.7K ohm

+3.3V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL= 100pF Including jig capacitance for MX26LV400T/B-70

(30pF for MX26LV400T/B-55)

SWITCHING TEST WAVEFORMS

3.0V

TEST POINTS

0V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

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MX26LV400

FIGURE 1. READ TIMING WAVEFORMS

tRC

VIH

ADD Valid

Addresses

VIL

tACC

tCE

VIH

CE#

VIL

VIH

WE#

VIL

tOE

tDF

tOEH

VIH

OE#

VIL

tACC

tOH

HIGH Z

VOH

VOL

Outputs

DATA Valid

VIH

VIL

RESET#

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MX26LV400

AC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 3.0V~3.6V

TABLE 10. Erase/Program Operations

26LV400-55

26LV400-70

SYM-

UNIT

ns

BOL

tWC

tAS

PARAMETER

MIN.

55

0

MAX.

MIN.

70

0

MAX.

Write Cycle Time (Note 1)

Address Setup Time

ns

tAH

Address Hold Time

45

35

0

45

35

0

ns

tDS

Data Setup Time

ns

tDH

Data Hold Time

ns

tOES

tGHWL

Output Enable Setup Time

Read Recovery Time Before Write

(OE# High to WE# Low)

CE# Setup Time

0

ns

0

ns

tCS

0

ns

us

tCH

CE# Hold Time

0

tWP

Write Pulse Width

35

30

35

tWPH

tWHWH1

Write Pulse Width High

ProgrammingOperation(Note2)

(Byte/Wordprogramtime)

Sector Erase Operation (Note 2)

VCC Setup Time (Note 1)

Recovery Time from RY/BY#

Program/Erase Valid to RY/BY# Delay

Sector Address Load Time

30

55/70(TYP.)

tWHWH2

tVCS

2.4(TYP.)

sec

us

50

0

50

0

tRB

ns

tBUSY

tBAL

90

50

90

50

ns

us

NOTES:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

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MX26LV400

AC CHARACTERISTICS TA = 0^oC to 70^oC, VCC = 3.0V~3.6V

TABLE 11. Alternate CE# Controlled Erase/Program Operations

26LV400-55

26LV400-70

SYMBOL

tWC

PARAMETER

MIN.

MAX.

MIN.

MAX.

UNIT

ns

Write Cycle Time (Note 1)

Address SetupTime

Address HoldTime

Data SetupTime

55

70

tAS

0

ns

tAH

45

ns

tDS

35

ns

tDH

Data HoldTime

0

ns

tOES

tGHEL

tWS

Output Enable SetupTime

Read RecoveryTime Before Write

WE# SetupTime

0

ns

0

ns

0

ns

tWH

WE# HoldTime

0

ns

tCP

CE# PulseWidth

35

ns

tCPH

tWHWH1

CE# Pulse Width High

30

ns

Programming

Byte

55(Typ.)

70(Typ.)

2.4(Typ.)

55(Typ.)

70(Typ.)

2.4(Typ.)

us

Operation(note2)

Word

us

tWHWH2

Sector Erase Operation (note2)

sec

NOTE:

1. Not 100% tested.

2. See the "Erase and Programming Performance" section for more information.

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MX26LV400

FIGURE 2. COMMAND WRITE TIMING WAVEFORM

VCC

3V

VIH

Addresses

ADD Valid

VIL

tAH

tAS

VIH

VIL

WE#

CE#

tOES

tWPH

tWP

tCWC

VIH

VIL

tCS

tCH

tDH

VIH

VIL

OE#

Data

tDS

VIH

VIL

DIN

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MX26LV400

AUTOMATIC PROGRAMMING TIMING WAVEFORM

ing after automatic programming starts. Device outputs

DATA# during programming and DATA# after program-

ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA#

polling, timing waveform)

One byte data is programmed. Verify in fast algorithm

and additional verification by external control are not re-

quired because these operations are executed automati-

cally by internal control circuit. Programming comple-

tion can be verified by DATA# polling and toggle bit check-

FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM

Program Command Sequence(last two cycle)

Read Status Data (last two cycle)

tWC

tAS

PA

555h

PA

Address

CE#

tAH

tCH

tGHWL

OE#

WE#

tWHWH1

tWP

tCS

tWPH

tDS tDH

Status

A0h

PD

DOUT

Data

tBUSY

tRB

RY/BY#

tVCS

VCC

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

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MX26LV400

FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Data# Poll

from system

Increment

Address

No

Verify Byte Ok ?

YES

Last Address ?

YES

Auto Program Completed

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MX26LV400

FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM

PA for program

555 for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Address

PA

tWC

tWH

tAS

tAH

WE#

OE#

tGHEL

tCP

tWHWH1 or 2

CE#

Data

tWS

tDS

tCPH

tBUSY

tDH

DOUT

DQ7

PD for program

30 for sector erase

10 for chip erase

A0 for program

55 for erase

tRH

RESET#

RY/BY#

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

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MX26LV400

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verification is

not required because data is verified automatically by

internal control circuit. Erasure completion can be veri-

fied by DATA# polling and toggle bit checking after auto-

matic erase starts. Device outputs 0 during erasure

and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle

bit, DATA# polling, timing waveform)

FIGURE 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

VA

tWC

tAS

VA

2AAh

555h

Address

CE#

tAH

tCH

tGHWL

OE#

WE#

tWHWH2

tWP

tCS

tWPH

tDS tDH

In

Progress

55h

10h

Complete

Data

tBUSY

tRB

RY/BY#

tVCS

VCC

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

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MX26LV400

FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data Pall from System

NO

Data=FFh ?

YES

Auto Chip Erase Completed

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29

MX26LV400

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector indicated by A12 to A17 are erased. External

erase verify is not required because data are verified

automatically by internal control circuit. Erasure comple-

tion can be verified by DATA# polling and toggle bit check-

ing after automatic erase starts. Device outputs 0 dur-

ing erasure and 1 after erasure on Q7. (Q6 is for toggle

bit; see toggle bit, DATA# polling, timing waveform)

FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

VA

tWC

tAS

Sector

VA

2AAh

Address

CE#

Address 0

Address 1

Address n

tAH

tCH

tGHWL

OE#

WE#

tWHWH2

tBAL

tWP

tCS

tWPH

tDS tDH

In

Progress

55h

30h

Complete

Data

tBUSY

tRB

RY/BY#

tVCS

VCC

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

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MX26LV400

FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Last Sector

to Erase

YES

Data Poll from System

NO

Data=FFh

YES

Auto Sector Erase Completed

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MX26LV400

WRITE OPERATION STATUS

FIGURE 10. DATA# POLLING ALGORITHM

Start

Read Q7~Q0

Add.=VA(1)

Yes

Q7 = Data ?

No

Q5 = 1 ?

Yes

Read Q7~Q0

Add.=VA

Yes

Q7 = Data ?

(2)

No

FAIL

Pass

NOTE : 1.VA=Valid address for programming

2.Q7 should be re-checked even Q5="1" because Q7 may change

simultaneously with Q5.

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MX26LV400

FIGURE 11. TOGGLE BIT ALGORITHM

Start

Read Q7-Q0

(Note 1)

NO

Toggle Bit Q6 =

Toggle ?

YES

NO

Q5= 1?

YES

Read Q7~Q0 Twice

(Note 1,2)

NO

Toggle bit Q6=

Toggle?

YES

Program/Erase Operation

Not Complete,Write

Reset Command

Program/Erase

operation Complete

Note:1.Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 change to "1".

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MX26LV400

FIGURE 12. Data# Polling Timings (During Automatic Algorithms)

tRC

VA

Address

CE#

tACC

tCE

tCH

tOE

OE#

WE#

tOEH

tDF

tOH

High Z

Complement

Status Data

Complement

Status Data

True

Valid Data

Q7

Q0-Q6

tBUSY

RY/BY#

NOTES:

1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

2. CE# must be toggled when DATA# polling.

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MX26LV400

FIGURE 13. Toggle Bit Timings (During Automatic Algorithms)

tRC

VA

tACC

tCE

VA

Address

CE#

tCH

tOE

OE#

tDF

tOEH

WE#

tOH

High Z

Valid Status

(second read)

Valid Status

(first raed)

Valid Data

Q6/Q2

(stops toggling)

tBUSY

RY/BY#

NOTES:

1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,

and array data read cycle.

2. CE# must be toggled when toggle bit toggling.

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MX26LV400

TABLE 12. AC CHARACTERISTICS

Parameter Std Description

Test Setup All Speed Options Unit

tREADY1

RESET# PIN Low (During Automatic Algorithms)

MAX

20

us

to Read or Write (See Note)

tREADY2

RESET# PIN Low (NOT During Automatic

Algorithms) to Read or Write (See Note)

RESET# Pulse Width (During Automatic Algorithms)

RESET# HighTime Before Read (See Note)

RY/BY# Recovery Time (to CE#, OE# go low)

MAX

500

ns

tRP

tRH

tRB

MIN

500

50

0

ns

Note: Not 100% tested

FIGURE 14. RESET# TIMING WAVEFORM

RY/BY#

CE#, OE#

tRH

RESET#

tRP

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY#

tRB

CE#, OE#

RESET#

tRP

Reset Timing during Automatic Algorithms

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MX26LV400

AC CHARACTERISTICS

TABLE 13. WORD/BYTE CONFIGURATION (BYTE#)

Parameter

Description

Speed Options

Unit

JEDEC Std

-55

-70

tELFL/tELFH CE# to BYTE# Switching Low or High

Max

Min

5

ns

tFLQZ

tFHQV

BYTE# Switching Low to Output HIGH Z

BYTE# Switching High to Output Active

25

55

25

70

FIGURE 15. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte

mode to word mode)

CE#

OE#

tELFH

BYTE#

DOUT

(Q0-Q7)

DOUT

(Q0-Q14)

Q0~Q14

Q15/A-1

DOUT

(Q15)

VA

tFHQV

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MX26LV400

FIGURE 16. BYTE# TIMINGWAVEFORM FOR READ OPERATIONS (BYTE# switching from word

mode to byte mode)

CE#

OE#

tELFH

BYTE#

DOUT

(Q0-Q14)

DOUT

(Q0-Q7)

Q0~Q14

Q15/A-1

DOUT

(Q15)

VA

tFLQZ

FIGURE 17. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS

CE#

The falling edge of the last WE# signal

WE#

BYTE#

tAS

tAH

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MX26LV400

FIGURE 18. ID CODE READ TIMING WAVEFORM

VCC

3V

VID

ADD

A9

VIH

VIL

VIH

VIL

ADD

A0

tACC

VIH

VIL

A1

ADD

A2-A8

VIH

A10-A17 VIL

CE#

VIH

VIL

VIH

VIL

tCE

WE#

OE#

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q15

DATA OUT

B9H/BAH (Byte)

C2H/00C2H

22B9H/22BAH (Word)

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MX26LV400

TABLE 14. ERASE AND PROGRAMMING PERFORMANCE (1)

LIMITS

PARAMETER

MIN.

TYP. (2)

2.4

MAX. (3)

15

UNITS

sec

Sector Erase Time

Chip Erase Time

20

120

220

sec

Byte Programming Time

Word Programming Time

Chip Programming Time (Word/Byte Mode)

Erase/Program Cycles

55

us

70

280

us

18

36

sec

2K (6)

Cycles

Note:

1. Not 100% tested.

2. Typical program and erase times assume the following conditions : 25° C, 3.3V VCC. Programming spec. assume

that all bits are programmed to checkerboard pattern.

3. Maximum values are measured at VCC=3.0V, worst case temperature. Maximum values are up to including 2K

program/erase cycles.

4. System-level overhead is the time required to execute the command sequences for the all program command.

5. Excludes 00H programming prior to erasure. (In the pre-programming step of the embedded erase algorithm, all bits

are programmed to 00H before erasure)

6. Min.erase/program cycles is under :3.3VVCC, 25°C, checkerboard pattern conditions, and without baking process.

TABLE 15. LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

12V

Input Voltage with respect to GND on ACC, OE#, RESET#, A9

Input Voltage with respect to GND on all power pins, Address pins, CE# and WE#

Input Voltage with respect to GND on all I/O pins

-1.0V

VCC + 1.0V

+100mA

-1.0V

Current

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

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MX26LV400

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS

OPERATING

STANDBY

PACKAGE

Remark

TIME (ns) Current MAX. (mA) Current MAX. (uA)

MX26LV400TTC-55

MX26LV400BTC-55

MX26LV400TTC-70

MX26LV400BTC-70

MX26LV400TXBC-55

MX26LV400BXBC-55

MX26LV400TXBC-70

MX26LV400BXBC-70

MX26LV400TXEC-55

MX26LV400BXEC-55

MX26LV400TXEC-70

MX26LV400BXEC-70

MX26LV400TTC-55G

MX26LV400BTC-55G

MX26LV400TTC-70G

MX26LV400BTC-70G

MX26LV400TXBC-55G

MX26LV400BXBC-55G

MX26LV400TXBC-70G

MX26LV400BXBC-70G

MX26LV400TXEC-55G

MX26LV400BXEC-55G

MX26LV400TXEC-70G

MX26LV400BXEC-70G

55

70

55

70

55

70

55

70

55

70

55

70

30

100

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

(Ball size:0.4mm)

48 Ball CSP

(Ball size:0.4mm)

48 Ball CSP

(Ball size:0.4mm)

48 Ball CSP

(Ball size:0.4mm)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Pin TSOP

(NormalType)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

(Ball size:0.3mm)

48 Ball CSP

Pb-free

(Ball size:0.4mm)

48 Ball CSP

(Ball size:0.4mm)

48 Ball CSP

(Ball size:0.4mm)

48 Ball CSP

(Ball size:0.4mm)

P/N:PM1094

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MX26LV400

PACKAGE INFORMATION

P/N:PM1094

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42

MX26LV400

48-Ball CSP (for MX26LV400ATXBC/ATXBI/ABXBC/ABXBI)

P/N:PM1094

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MX26LV400

48-Ball CSP (for MX26LV400ATXEC/ATXEI/ABXEC/ABXEI)

P/N:PM1094

REV. 1.0, NOV. 08, 2004

44

MX26LV400

REVISION HISTORY

Revision No. Description

Page

Date

1.0

1. Removed "Preliminary"

P1

NOV/08/2004

P/N:PM1094

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45

MX26LV400

MACRONIX INTERNATIONALCO., LTD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX26LV400TTC-70
厂家：	MACRONIX INTERNATIONAL
描述：	4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE 3V ONLY BOOT SECTOR HIGH SPEED eLiteFlashTM MEMORY 4M- BIT [ 512Kx8 / 256Kx16 ] CMOS单电压3V只引导扇区高速eLiteFlashTM记忆
文件：	总46页 (文件大小：550K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX26LV400TTC-70 [Macronix]

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