MX27C8111PC-90_技术文档

PRELIMINARY

MX27C8111

8M-BIT [1M x8/512K x16] CMOS OTP ROM

WITH PAGE MODE

FEATURES

• With Page Mode function, 8-word/16-byte page

• 1M x 8 or 512K x 16 organization

• +12.5V programming voltage

• Completely TTL compatible

• Operating current: 60mA

• Standby current: 100uA

• Fast access time:90/100/120/150 ns

• Page mode access time 50/60/75 ns

• Totally static operation

• Package type:

- 42 pin plastic DIP

- 44 pin SOP

GENERAL DESCRIPTION

The MX27C8111 is a 8M-bit, One Time Programmable

Read Only Memory with page mode. It is organized as

1M x 8 or 512K x 16, operates from a single + 5 volt

supply, has a static standby mode, and features fast

singleaddresslocationprogramming. Allprogramming

signals are TTL levels, requiring a single pulse. For

programming outside from the system, existing

EPROM programmers may be used. The MX27C8111

supportsaintelligentfastprogrammingalgorithmwhich

canresultinprogrammingtimeoflessthantwominutes.

MX27C8111 provides Page Read Access Mode which

can greatly reduce the read access time. Normal read

accesstimeandPageModereadaccesstime isasfast

as 90/50ns. It is designed to be compatible with all

microprocessors and similar applications in which high

perofmrance, large bit storage and simple interfacing

are important design considerations.

This One Time Programmable Read Only Memory is

packagedinindustrystandard42pindual-in-lineplastic

package and 44 pin SOP packages.

PIN CONFIGURATIONS

PDIP

SOP

NC

A8

A9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

NC

A18

A17

A7

A6

A5

A4

A3

A2

A1

A18

A17

A7

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A8

2

A9

3

A10

A11

A12

A13

A14

A15

A16

BYTE/VPP

GND

Q15/A-1

Q7

A6

4

A10

A11

A12

A13

A14

A15

A16

BYTE/VPP

GND

Q15/A1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

A5

5

A4

6

A3

7

A2

8

A1

9

A0

10

11

12

13

14

15

16

17

18

19

20

21

A0

CE

GND

OE

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

CE

GND

OE

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

Q14

Q6

Q13

Q5

Q12

Q4

VCC

P/N: PM0329

REV. 2.6, AUG. 22, 2001

1

MX27C8111

PIN DESCRIPTION

BLOCK DIAGRAM

SYMBOL

A0~A18

Q0~Q14

CE

PIN NAME

CE

OE

Q0~Q14

Q15/A-1

CONTROL

LOGIC

OUTPUT

Address Input

BUFFERS

BYTE/VPP

Data Input/Output

Chip Enable Input

Output Enable Input

Word/Byte Selection

/Program Supply Voltage

Q15(Word mode)/

LSB addr. (Byte mode)

Power Supply Pin (+5V)

Ground Pin

.

Y-DECODER

X-DECODER

Y-SELECT

OE

BYTE/VPP

A0~A18

8M BIT

CELL

ADDRESS

INPUTS

Q15/A-1

MAXTRIX

VCC

GND

VCC

GND

TRUTH TABLE OF BYTE FUNCTION

BYTE MODE(BYTE = GND)

CE

H

OE

X

Q15/A-1

MODE

Q0-Q7

High Z

DOUT

SUPPLY CURRENT

Standby(ICC2)

X

Non selected

Selected

L

H

X

Operating(ICC1)

L

A-1 input

WORD MODE(BYTE = VCC)

CE

H

OE

X

Q15/A-1

High Z

DOUT

MODE

Q0-Q14

High Z

DOUT

SUPPLY CURRENT

Standby(ICC2)

Non selected

Selected

L

H

Operating(ICC1)

L

NOTE : X = H or L

P/N: PM0329

REV. 2.6, AUG. 22, 2001

2

MX27C8111

at VIH, VPP at its programming voltage.

FUNCTIONAL DESCRIPTION

THE PROGRAMMING OF THE MX27C8111

AUTO IDENTIFY MODE

When the MX27C8111 is delivered, the chip has all

8Mbitsinthe"ONE"orHIGHstate."ZEROs"areloaded

into the MX27C8111 through the procedure of

programming.

Theautoidentifymodeallowsthereadingoutofabinary

code from an One Time Programmable Read Only

Memory that will identify its manufacturer and device

type. This mode is intended for use by programming

equipmentforthepurposeofautomaticallymatchingthe

device to be programmed with its corresponding

programming algorithm. This mode is functional in the

25°C±5°C ambient temperature range that is required

when programming the MX27C8111.

Forprogramming,thedatatobeprogrammedisapplied

with 16 bits in parallel to the data pins.

Vcc must be applied simultaneously or before Vpp, and

removed simultaneously or after Vpp. When

programming an MXIC One Time Programmable Read

Only Memory, a 0.1uF capacitor is required across Vpp

and ground to suppress spurious voltage transients

which may damage the device.

To activate this mode, the programming equipment

must force 12.0±0.5VonaddresslineA9ofthedevice.

Two identifier bytes may then be sequenced from the

device outputs by toggling address line A0 from VIL to

VIH. All other address lines must be held at VIL during

auto identify mode.

FAST PROGRAMMING

Byte 0 ( A0 = VIL) represents the manufacturer code,

andbyte1(A0=VIH), thedeviceidentifiercode. Forthe

MX27C8111, these two identifier bytes are given in the

Mode Select Table. All identifiers for manufacturer and

device codes will possess odd parity, with the MSB

(Q15) defined as the parity bit.

Thedeviceissetupinthefastprogrammingmodewhen

the programming voltage VPP = 12.75V is applied, with

VCC = 6.25 V and OE = VIH (Algorithm is shown in

Figure 1). The programming is achieved by applying a

single TTL low level 50us pulse to the CE input after

addresses and data line are stable. If the data is not

verified, an additional pulse is applied for a maximum of

25 pulses. This process is repeated while sequencing

through each address of the device. When the

programmingmodeiscompleted,thedatainalladdress

is verified at VCC = VPP = 5V ±10%.

READ MODE

The MX27C8111 provides page mode with 8 words/16

bytes per page. In order to get the benefit of fast page

read, the user should keep chip enable(CE) low and

toggle address A0~A2 in word mode or A-1~A2 in byte

mode. PageReadaccesstime(tPA)isequaltothedelay

from address stable to data output. It is twice as fast as

normal tACC and is highly recommended.

PROGRAM INHIBIT MODE

Programming of multiple MX27C8111's in parallel with

different data is also easily accomplished by using the

Program Inhibit Mode. Except for CE and OE, all like

inputs of the parallel MX27C8111 may be common. A

TTL low-level program pulse applied to an MX27C8111

CE input with VPP = 12.5 ± 0.5 V will program the

MX27C8111. A high-level CE input inhibits the other

MX27C8111s from being programmed.

WORD-WIDE MODE

With BYTE/VPP at VCC ±0.2V outputs Q0-7 present

data Q0-7 and outputs Q8-15 present data Q8-15, after

CE and OE are appropriately enabled.

PROGRAM VERIFY MODE

BYTE-WIDE MODE

Verification should be performed on the programmed

bits to determine that they were correctly programmed.

TheverificationshouldbeperformedwithOE atVIL,CE

With BYTE/VPP at GND ±0.2V, outputs Q8-15 are tri-

stated. IfQ15/A-1=VIH, outputsQ0-7presentdatabits

P/N: PM0329

REV. 2.6, AUG. 22, 2001

3

MX27C8111

primary device-selecting function, while OE be made a

common connection to all devices in the array and

connectedtotheREADlinefromthesystemcontrolbus.

This assures that all deselected memory devices are in

their low-power standby mode and that the output pins

are only active when data is desired from a particular

memory device.

Q8-15. If Q15/A-1 = VIL, outputs Q0-7 present data bits

Q0-7.

STANDBY MODE

The MX27C8111 has a CMOS standby mode which

reduces the maximum VCC current to 100 uA. It is

placed in CMOS standby when CE is at VCC ±0.3 V.

The MX27C8111 also has a TTL-standby mode which

reduces the maximum VCC current to 1.5 mA. It is

placed in TTL-standby when CE is at VIH. When in

standby mode, the outputs are in a high-impedance

state, independent of the OE input.

SYSTEM CONSIDERATIONS

During the switch between active and standby

conditions, transient current peaks are produced on the

rising and falling edges of Chip Enable. The magnitude

of these transient current peaks is dependent on the

outputcapacitanceloadingofthedevice. Ataminimum,

a0.1uFceramiccapacitor(highfrequency,lowinherent

inductance) should be used on each device between

Vcc and GND to minimize transient effects. In addition,

to overcome the voltage drop caused by the inductive

effects of the printed circuit board traces on One Time

ProgrammableReadOnlyMemoryarrays, a4.7uFbulk

electrolytic capacitor should be used between VCC and

GND for each eight devices. The location of the

capacitor should be close to where the power supply is

connected to the array.

TWO-LINE OUTPUT CONTROL FUNCTION

To accommodate multiple memory connections, a two-

line control function is provided to allow for:

1. Low memory power dissipation,

2. Assurance that output bus contention will not

occur.

It is recommended that CE be decoded and used as the

MODE SELECT TABLE

BYTE/

MODE

CE

OE

VIL

VIH

X

A9

X

A0

X

Q15/A-1

Q15 Out

VIH

VPP(5)

VCC

GND

X

Q8-14

Q0-7

Read (Word)

VIL

VIH

VIL

VIH

VIL

Q8-14 Out

High Z

Q8-14 In

Q8-14 Out

High Z

00H

Q0-7 Out

Q8-15 Out

Q0-7 Out

High Z

Q0-7 In

Q0-7 Out

High Z

C2H

Read (Upper Byte)

Read (Lower Byte)

Output Disable

Standby

X

VIL

X

High Z

Q15 In

Q15 Out

High Z

0B

X

Program

VIH

VIL

VIH

VIL

X

VPP

VCC

Program Verify

Program Inhibit

Manufacturer Code(3)

Device Code(3)

X

VH

VIL

VIH

1B

38H

16H

4. See DC Programming Characteristics for VPP voltages.

5. BYTE/VPP is intended for operation under DC Voltage conditions

only.

NOTES: 1. VH = 12.0V ±0.5V

2. X = Either VIH or VIL.

3. A1-A8, A10-A18 = VIL(for auto select)

6. Manufacture code = 00C2H

Device code = B816H

P/N: PM0329

REV. 2.6, AUG. 22, 2001

4

MX27C8111

FIGURE 1. FAST PROGRAMMING FLOW CHART

START

ADDRESS = FIRST LOCATION

VCC = 6.25V

VPP = 12.75V

X = 0

PROGRAM ONE 50us PULSE

INCREMENT X

INTERACTIVE

SECTION

YES

X = 25?

NO

FAIL

VERIFY WORD

?

PASS

NO

LAST ADDRESS

INCREMENT ADDRESS

FAIL

YES

VCC = VPP = 5.25V

VERIFY SECTION

FAIL

DEVICE FAILED

VERIFY ALL WORDS

?

PASS

DEVICE PASSED

P/N: PM0329

REV. 2.6, AUG. 22, 2001

5

MX27C8111

SWITCHING TEST CIRCUITS

DEVICE

UNDER

TEST

1.8K ohm

+5V

DIODES = IN3064

OR EQUIVALENT

CL

6.2K ohm

CL = 100 pF including jig capacitance

SWITCHING TEST WAVEFORMS

2.0V

0.8V

2.0V

TEST POINTS

AC driving levels

0.8V

OUTPUT

INPUT

AC TESTING: AC driving levels are 2.4V/0.4V.

Input pulse rise and fall times are < 10ns.

P/N: PM0329

REV. 2.6, AUG. 22, 2001

6

MX27C8111

ABSOLUTE MAXIMUM RATINGS

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended period may affect reliability.

RATING

VALUE

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9 & VPP

0^oC to 70^oC

-65^oC to 125^oC

-0.5V to 7.0V

NOTICE:

-0.5V to VCC + 0.5V

-0.5V to 7.0V

Specifications contained within the following tables are subject to

change.

-0.5V to 13.5V

DC/AC Operating Conditions for Read Operation

MX27C8111

-90

-10

-12

-15

Operating Temperature

Vcc Power Supply

Commercial

0°C to 70°C

5V ±5%

0°C to 70°C

5V ±10%

0°C to 70°C

5V ±10%

0°C to 70°C

5V ±10%

DC CHARACTERISTICS

SYMBOL

VOH

VOL

VIH

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

Output High Voltage

Output Low Voltage

Input High Voltage

2.4

V

IOH = -0.4mA

IOL = 2.1mA

0.4

VCC + 0.5

0.8

2.0

-0.3

-10

V

VIL

Input Low Voltage

V

ILI

Input Leakage Current

Output Leakage Current

VCC Power-Down Current

VCC Standby Current

VCC Active Current

VPP Supply Current Read

10

uA

mA

uA

VIN = 0 to 5.5V

ILO

10

VOUT = 0 to 5.5V

CE = VCC ±0.3V

ICC3

ICC2

ICC1

IPP

100

1.5

CE = VIH

60

CE = VIL, f=5MHz, Iout = 0mA

CE = OE = VIL, VPP = 5.5V

10

CAPACITANCE TA = 25^oC, f = 1.0 MHz (Sampled only)

SYMBOL

CIN

PARAMETER

TYP.

8

MAX.

12

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Output Capacitance

VPP Capacitance

COUT

CVPP

8

12

pF

VOUT = 0V

VPP = 0V

18

25

pF

P/N: PM0329

REV. 2.6, AUG. 22, 2001

7

MX27C8111

AC CHARACTERISTICS

27C8111-90

27C8111-10

27C8111-12

27C8111-15

SYMBOL PARAMETER

MIN.

MAX.

90

MIN. MAX. MIN. MAX. MIN. MAX. UNIT CONDITIONS

tACC

tCE

tPA

Address to Output Delay

Chip Enable to Output Delay

Page Address to Output Delay

Output Enable to Output Delay

OE High to Output Float,

or CE High to Output Float

Output Hold from Address,

CE or OE which ever occurred first

BYTE Access Time

100

50

120

60

150

75

ns

CE = OE = VIL

OE = VIL

90

50

CE = OE =VIL

CE = VIL

tOE

tDF

45

50

65

0

30

0

30

0

35

0

50

0

tOH

0

ns

tBHA

tOHB

tBHZ

90

70

100

70

120

70

150

70

ns

BYTE Output Hold Time

0

BYTE Output Delay Time

tBLZ

BYTE Output Set Time

10

ns

DC PROGRAMMING CHARACTERISTICS TA = 25^oC ±5^oC

SYMBOL

VOH

VOL

VIH

PARAMETER

MIN.

MAX.

UNIT

CONDITIONS

IOH = -0.40mA

IOL = 2.1mA

Output High Voltage

2.4

V

Output Low Voltage

0.4

V

Input High Voltage

2.0

VCC + 0.5

0.8

V

VIL

Input Low Voltage

-0.3

-10

V

ILI

Input Leakage Current

A9 Auto Select Voltage

VCC Supply Current (Program & Verify)

VPP Supply Current(Program)

Fast Programming Supply Voltage

Fast Programming Voltage

10

uA

V

VIN = 0 to 5.5V

VH

11.5

12.5

50

ICC3

IPP2

VCC1

VPP1

mA

V

30

CE = VIL, OE = VIH

6.00

12.5

6.50

13.0

V

AC PROGRAMMING CHARACTERISTICS TA = 25^oC ±5^oC

SYMBOL

tAS

PARAMETER

MIN.

2.0

0

TYP.

MAX.

UNIT

Address Setup Time

OE Setup Time

us

ns

us

ns

tOES

tDS

Data Setup Time

tAH

Address Hold Time

Data Hold Time

tDH

2.0

0

tDFP

tVCS

tVPS

tPW

Chip Enable to Output Float Delay

VCC Setup Time

130

150

2.0

BYTE/VPP Setup Time

CE initial Program Pulse Width

Data valid from OE

50

tOE

P/N: PM0329

REV. 2.6, AUG. 22, 2001

8

MX27C8111

WAVEFORMS

NORMAL READ CYCLE(WORD MODE)

ADDRESS

INPUTS

DATA ADDRESS

tACC

CE

OE

tCE

tDF

DATA

OUT

VALID DATA

tOE

tOH

PAGE MODE READ CYCLE

A4-A18

VALID ADDRESS

A0~A2 (Word mode)

A-1~A2 (Byte mode)

tACC

CE

tPA

OE

tDF

tOH

tOE

DATA OUT

P/N: PM0329

REV. 2.6, AUG. 22, 2001

9

MX27C8111

WAVEFORMS

NORMAL READ CYCLE(BYTE MODE)

HIGH-Z

A-1

tACC

tOH

BYTE/VPP

Q0-Q7

VALID DATA

tBHA

tOHB

VALID DATA

Q15-Q8

tBHZ

tBLZ

FAST PROGRAMMING ALGORITHM WAVEFORM

PROGRAM

VERIFY

VIH

Addresses

VALID ADDRESS

VIL

tAH

tAS

DATA OUT VALID

DATA SET

DATA

tDFP

tDS

tDH

VPP1

VCC

BYTE/VPP

tVPS

tVCS

VCC1

VCC

CE

VIH

VIL

tOE

tOES

tPW

VIH

VIL

OE

P/N: PM0329

REV. 2.6, AUG. 22, 2001

10

MX27C8111

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS TIME

OPERATING CURRENT

STANDBY CURRENT

PACKAGE

(ns)

90

MAX.(mA)

MAX.(uA)

100

MX27C8111MC-90

MX27C8111MC-10

MX27C8111MC-12

MX27C8111MC-15

MX27C8111PC-90

MX27C8111PC-10

MX27C8111PC-12

MX27C8111PC-15

60

44 PIn SOP (ROM pin out)

44 Pin SOP(ROM pin out)

42 PIn PDIP (ROM pin out)

42 PIn PDIP(ROM pin out)

42 Pin PDIP(ROM pin out)

100

120

150

90

100

120

150

100

P/N: PM0329

REV. 2.6, AUG. 22, 2001

11

MX27C8111

PACKAGE INFORMATION

42-PIN PLASTIC DIP(600 mil)

P/N: PM0329

REV. 2.6, AUG. 22, 2001

12

MX27C8111

44-PIN PLASTIC SOP

P/N: PM0329

REV. 2.6, AUG. 22, 2001

13

MX27C8111

Revision History

Revision No. Description

Page

Date

2.0

1) Eliminate Interactive Programming Mode.

5/30/1997

2) Programming pulse change, from 100us to 50us

IPP : 100uA---->10uA

2.1

2.2

2.3

2.4

2.5

2.6

8/8/1997

Add 100ns speed grade.

1/31/1998

Add 90ns speed grade.

4/07/1998

90ns speed grade VCC=5V±10%-->5V±5%

Correct 42PIN plastic DIP package information error

To modify Package Information

5/06/1998

P12

MAR/02/2000

AUG/22/2001

P12,13

P/N: PM0329

REV. 2.6, AUG. 22, 2001

14

MX27C8111

MACRONIX INTERNATIONAL CO., LTD.

HEADQUARTERS:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

EUROPE OFFICE:

TEL:+32-2-456-8020

FAX:+32-2-456-8021

JAPAN OFFICE:

TEL:+81-44-246-9100

FAX:+81-44-246-9105

SINGAPORE OFFICE:

TEL:+65-348-8385

FAX:+65-348-8096

TAIPEI OFFICE:

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-453-8088

FAX:+1-408-453-8488

CHICAGO OFFICE:

TEL:+1-847-963-1900

FAX:+1-847-963-1909

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

15


型号：	MX27C8111PC-90
厂家：	MACRONIX INTERNATIONAL
描述：	8M-BIT [1M x8/512K x16] CMOS OTP ROM WITH PAGE MODE 8M - BIT [ 1M ×8 / 512K X16 ]的CMOS OTP配页模式ROM OTP只读存储器
文件：	总15页 (文件大小：490K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX27C8111PC-90 [Macronix]

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