MX28F160C3BXAI-12 [Macronix]
Flash Memory;
| 型号： | MX28F160C3BXAI-12 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash Memory |
| 文件： | 总43页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX28F160C3T/B
8M-BIT[512Kx16]CMOSSINGLEVOLTAGE
3VONLYFLASHMEMORY
FEATURES
• Bit Organization: 1,048,576 x 16
• Singlepowersupplyoperation
- 3.0V only operation for read, erase and program
operation
• Automatic Suspend Enhance
- Word/byte write suspend to read
- Sector erase suspend to word/byte write
- Sector erase suspend to read register report
• Automaticsectorerase,fullchiperase,wordwriteand
sector lock/unlock configuration
• Status Reply
- VCC=VPP=2.7~3.6V
-VCC=12fastproductionprogramming
- 1.65V~2.5V or 2.7V~3.6V I/O Option (VCCQ)
-Operatingtemperature:-40°C~85°C
• Fast access time : 70/90/120ns
• Lowpowerconsumption
- Detection of program and erase operation comple-
tion.
- Command User Interface (CUI)
- Status Register (SR)
-9mAmaximumactivereadcurrent, f=5MHz(CMOS
input)
• Data Protection Performance
-Includebootsectorsandparameterandmainsectors
to be block/unblock
- 21mA program erase current maximum
(VPP=1.65~3.6V)
- 7uA typical standby current under power saving
mode
• 100,000minimumerase/programcycles
• Common Flash Interface (CFI)
• 128-bitProtectionRegister
• Sectorarchitecture
- Sector Erase (Sector structure : 4Kword x 2 (boot
sectors), 4Kword x 6 (parameter sectors), 32Kword x
31(parametersectors)
- 64-bit Unique Device Identifier
-64-bitUser-Programmable
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- Top/Bottom Boot
• Auto Erase (chip & sector) and Auto Program
- Automatically program and verify data at specified
address
- 48-pin TSOP (12mm x 20mm)
- 48-ball CSP (8mm x 6mm)
fast as 70ns, allowing operation of high-speed micropro-
cessors without wait states.
GENERAL DESCRIPTION
The MX28F160C3T/B is a 16-mega bit Flash memory
organized as 1M words of 16 bits. The 1M word of data
is arranged in eight 4Kword boot and parameter sectors,
and 31 32Kword main sector which are individually eras-
able. MXIC's Flash memories offer the most cost-effec-
tive and reliable read/write non-volatile random access
memory. The MX28F160C3T/B is packaged in 48-pin
TSOP and 48-ball CSP. It is designed to be repro-
grammed and erased in system or in standard EPROM
programmers.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX28F160C3T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
The standard MX28F160C3T/B offers access time as
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MX28F160C3T/B
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX28F160C3T/B uses a 2.7V~3.6VVCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
tially reduces active current when the device is in static
mode (addresses not switching). In this mode, the typi-
cal ICCS current is 7uA (CMOS) at 3.0V VCC.
As CE and RP are atVCC, ICC CMOS standby mode is
enabled.When RP is at GND, the reset mode is enabled
which minimize power consumption and provide data
write protection.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
A reset time (tPHQV) is required from RP switching high
until outputs are valid. Similarly, the device has a wake
time (tPHEL) from RP-high until writes to the CUI are
recognized.With RP at GND, the WSM is reset and the
status register is cleared.
The dedicated VPP pin gives complete data protection
when VPP< VPPLK.
A Command User Interface (CUI) serves as the inter-
face between the system processor and internal opera-
tion of the device. A valid command sequence written to
the CUI initiates device automation. An internal Write
State Machine (WSM) automatically executes the algo-
rithms and timings necessary for erase, full chip erase,
word/byte write and sector lock/unlock configuration op-
erations.
A sector erase operation erases one of the device's 32K-
word sectors typically within 1.0s, 4K-word sectors typi-
cally within 0.5s independent of other sectors. Each sec-
tor can be independently erased minimum 100,000 times.
Sector erase suspend mode allows system software to
suspend sector erase to read or write data from any other
sector.
Writing memory data is performed in word increments of
the device's 32K-word sectors typically within 0.8s and
4K-word sectors typically within 0.1s.Word program sus-
pend mode enables the system to read data or execute
code from any other memory array location.
MX28F160C3T/B features with individual sectors lock-
ing by using a combination of bits thirty-nine sector lock-
bits and WP, to lock and unlock sectors.
The status register indicates when the WSM's sector
erase, full chip erase, word program or lock configura-
tion operation is done.
The access time is 70/90/120ns (tELQV) over the oper-
ating temperature range (-40°C to +80°C) andVCC sup-
ply voltage range of 2.7V~3.6V.
MX28F160C3T/B's power saving mode feature substan-
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MX28F160C3T/B
BLOCK DIAGRAM
DQ0~DQ7
Output
Buffer
Input
Buffer
I/O
VCC
Logic
Identifier
Register
CS
WE
Command
User
Interface
OE
RP
WP
Status
Register
Data
Comparator
Write
State
Machine
Y
VPP
Program/Erase
Voltage Switch
Input
Buffer
Y-Gating
A0~A19
Decoder
VCC
GND
32K-Word
Main Sector
x31
Address
Latch
X
Decoder
Address
Counter
.......
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MX28F160C3T/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
A10
A9
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VCCQ
GND
Q15
Q7
2
3
4
5
6
Q14
Q6
7
A8
8
Q13
Q5
NC
NC
WE
RP
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q12
Q4
MX28F160C3T/B
VCC
Q11
Q3
VPP
WP
A19
A18
A17
A7
Q10
Q2
Q9
Q1
A6
Q8
A5
Q0
A4
OE
A3
GND
CE
A2
A1
A0
48 Ball CSP (8mm x 6mm) Top View, Ball Down for MX28F160C3T/BXA
(Ball Pitch=0.75mm, Ball Width=0.3mm)
A1
A2
A3
A8
A4
A5
A6
A7
A7
A8
A4
A13
A11
VPP
WP
A19
B1
B2
B3
B4
B5
B6
B7
A5
B8
A2
A14
A10
WE
RP
A18
A17
C1
C2
C3
A9
C4
C5
C6
A6
C7
A3
C8
A1
A15
A12
NC
NC
6.0 mm
D1
D2
D3
D4
D5
D6
D7
CE
D8
A0
A16
DQ14
DQ5
DQ11
DQ2
DQ8
E1
E2
E3
E4
E5
E6
E7
E8
VCCQ
DQ15
DQ6
DQ12
DQ3
DQ9
DQ0
GND
F1
F2
F3
F4
F5
F6
F7
F8
GND
DQ7
DQ13
DQ4
VCC
DQ10
DQ1
OE
8.0 mm
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MX28F160C3T/B
Table 1. Pin Description
Symbol
Type
Description and Function
A0-A19
input
Address inputs for memory address. Data pin float to high-impedance when the chip is
deselected or outputs are disable. Addresses are internally latched during a write or
erase cycle.
DQ0-DQ15 input/output Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-
gram command. Data is internally latched. Outputs array and configuration data. The
data pin float to tri-state when the chip is de-selected.
CE
input
Activates the device's control logic, input buffers, and sense amplifiers. CE high de-
selects the memory device and reduce power consumption to standby level. CE is
active low.
RP
input
Reset Deep Power Down:when RP=VIL, the device is in reset/deep power down mode,
which drives the outputs to High Z, resets the WSM and minimizes current level.
When RP=VIH, the device is normal operation.When RP transition the device defaults
to the read array mode.
WE
input
Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The
data and address is latched WE on the rising edge of the second WE pulse.
VPP
input/supply Program/Erase Power Supply:(1.65V~3.6V or 11.4V~12.6V)
Lower VPP<VPPLK, to protect any contents against Program and Erase Command.
Set VPP=VCC for in-system Read, Program and Erase Operation.
Raise VPP to 12V±5% for faster program and erase in a production environment.
OE
input
input
Output enable: gates the device's outputs during a real cycle.
Write protect:whenWP isVIL, the boot sectors cannot be written or erased.WhenWP
is VIH, locked boot sectors cannot be written or erase. WP is not affected parameter
and main sectors.
WP
VCC
supply
input
Device power supply: (2.7V~3.6V).
VCCQ
GND
I/O Power Supply: supplies for input/output buffers. (Refer to section 6.2.6)
Ground voltage: all the GND pin shall not be connected.
supply
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MX28F160C3T/B
SECTOR STRUCTURE (TOP)
Sector
Sector Size
4KWord
Address Range (h)
FF000 ~ FFFFF
FE000 ~ FEFFF
FD000 ~ FDFFF
FC000 ~ FCFFF
FB000 ~ FBFFF
FA000 ~ FAFFF
F9000 ~ F9FFF
F8000 ~ F8FFF
F0000 ~ F7FFF
E8000 ~ EFFFF
E0000 ~ E7FFF
D8000 ~ DFFFF
D0000 ~ D7FFF
C8000 ~ CFFFF
C0000 ~ C7FFF
B8000 ~ BFFFF
B0000 ~ B7FFF
A8000 ~ AFFFF
A0000 ~ A7FFF
98000 ~ 9FFFF
90000 ~ 97FFF
88000 ~ 8FFFF
80000 ~ 87FFF
78000 ~ 7FFFF
70000 ~ 77FFF
68000 ~ 6FFFF
60000 ~ 67FFF
58000 ~ 5FFFF
50000 ~ 57FFF
48000 ~ 4FFFF
40000 ~ 47FFF
38000 ~ 3FFFF
30000 ~ 37FFF
28000 ~ 2FFFF
20000 ~ 27FFF
18000 ~ 1FFFF
10000 ~ 17FFF
08000 ~ 0FFFF
00000 ~ 07FFF
Boot Sector 0
Boot Sector 1
4KWord
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
4KWord
4KWord
4KWord
4KWord
4KWord
4KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
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MX28F160C3T/B
SECTOR STRUCTURE (BOTTOM)
Sector
Sector Size
Address Range (h)
00000 ~ 00FFF
01000 ~ 01FFF
02000 ~ 02FFF
03000 ~ 03FFF
04000 ~ 04FFF
05000 ~ 05FFF
06000 ~ 06FFF
07000 ~ 07FFF
08000 ~ 0FFFF
10000 ~ 17FFF
18000 ~ 1FFFF
20000 ~ 27FFFF
28000 ~ 2FFFF
30000 ~ 37FFF
38000 ~ 3FFFF
40000 ~ 47FFF
48000 ~ 4FFFF
50000 ~ 57FFFF
58000 ~ 5FFFF
60000 ~ 67FFF
68000 ~ 6FFFF
70000 ~ 77FFF
78000 ~ 7FFFF
80000 ~ 87FFF
88000 ~ 8FFFF
90000 ~ 97FFF
98000 ~ 9FFFF
A0000 ~ A7FFF
A8000 ~ AFFFF
B0000 ~ B7FFF
B8000 ~ BFFFF
C0000 ~ C7FFF
C8000 ~ CFFFF
D0000 ~ D7FFF
D8000 ~ DFFFF
E0000 ~ E7FFF
E8000 ~ EFFFF
F0000 ~ F7FFF
F8000 ~ FFFFF
Boot Sector 0
4KWord
4KWord
Boot Sector 1
Parameter Sector 0
Parameter Sector 1
Parameter Sector 2
Parameter Sector 3
Parameter Sector 4
Parameter Sector 5
Main Sector 0
Main Sector 1
Main Sector 2
Main Sector 3
Main Sector 4
Main Sector 5
Main Sector 6
Main Sector 7
Main Sector 8
Main Sector 9
Main Sector 10
Main Sector 11
Main Sector 12
Main Sector 13
Main Sector 14
Main Sector 15
Main Sector 16
Main Sector 17
Main Sector 18
Main Sector 19
Main Sector 20
Main Sector 21
Main Sector 22
Main Sector 23
Main Sector 24
Main Sector 25
Main Sector 26
Main Sector 27
Main Sector 28
Main Sector 29
Main Sector 30
4KWord
4KWord
4KWord
4KWord
4KWord
4KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
32KWord
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MX28F160C3T/B
2 PRINCIPLES OF OPERATION
3 BUS OPERATION
The product includes an on-chip WSM to manage sec-
tor erase, word/byte write and lock-bit configuration func-
tions.
The local CPU reads and writes flash memory in-sys-
tem. All bus cycles to or from the flash memory conform
to standard microprocessor bus cycles.
After initial device power-up or return from reset mode
(see section on Bus Operations), the device defaults to
read array mode. Manipulation of external memory con-
trol pins allow array read, standby and output disable
operations.
3.1 Read
Information can be read from any sector, configuration
codes or status register independent of the VPP volt-
age. RP can be at VIH.
Status register and identifier codes can be accessed
through the CUI independent of the VPP voltage. All
functions associated with altering memory contents-sec-
tor erase, word/byte write, sector lock/unlock, status and
identifier codes - are accessed via the CUI and verified
through the status register.
The first task is to write the appropriate read mode com-
mand (Read Array, Read Configuration, Read Query or
Read Status Register) to the CUI. Upon initial device
power-up or after exit from reset mode, the device auto-
matically resets to read array mode. In order to read
data, control pins set for CE, OE, WE, RP andWP must
be driven to active. CE and OE must be active to obtain
data at the outputs. CE is the device selection control.
OE is the data output (DQ0-DQ15) control and active
drives the selected memory data onto the I/O bus, WE
must be VIH, RP must be VIH, WP must be at VIL or
VIH.
Commands are written using standard microprocessor
write timings. The CUI contents serve as input to the
WSM, which controls the sector erase, word/byte write
and sector lock/unlock.The internal algorithms are regu-
lated by the WSM, including pulse repetition, internal
verification and margining of data. Addresses and data
are internally latched during write cycles. Address is
latched at falling edge of CE and data latched at rising
edge of WE. Writing the appropriate command outputs
array data, accesses the identifier codes or outputs sta-
tus register data.
3.2 Output Disable
With OE at a logic-high level (VIH), the device outputs
are disabled. Output pins (DQ0-DQ15) are placed in a
high-impedance state.
Interface software that initiates and polls progress of
sector erase, full chip erase, word/byte write and sector
lock/unlock can be stored in any sector. This code is
copied to and executed from system RAM during flash
memory updates. After successful completion, reads are
again possible via the Read Array command. Sector
erase suspend allows system software to suspend a
sector erase to read/write data from/to sectors other than
that which is suspend.Word/byte write suspend allows
system software to suspend a word/byte write to read
data from any other flash memory array location.
3.3 Standby
CE at a logic-high level (VIH) places the device in
standby mode which substantially reduces device power
consumption. DQ0~DQ15 outputs are placed in a high-
impedance state independent of OE. If deselected dur-
ing sector erase, word/byte write or sector lock/unlock,
the device continues functioning, and consuming active
power until the operation completes.
With the mechanism of sector lock, memory contents
cannot be altered due to noise or unwanted operation.
When RP=VIH and VCC<VLKO (lockout voltage), any
data write alteration can be failure. During read opera-
tion, if write VPP voltage is below VPPLK, then hard-
ware level data protection is achieved. With CUI's two-
step command sequence sector erase, word/byte write
or sector lock/unlock, software level data protection is
achieved also.
3.4 Reset
As RP=VIL, it initiates the reset mode. The device en-
ters reset/deep power down mode. However, the data
stored in the memory has to be sustained at least 100ns
in the read mode before the device becomes deselected
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MX28F160C3T/B
and output high impedance state.
mands require the command and address within the de-
vice or sector within the device (Sector Lock) to be
locked. The Clear Sector Lock-Bits command requires
the command and address within the device.
In read modes, RP-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP must be held low for a minimum of
100ns. Time tPHQV is required after return from reset
mode until initial memory access outputs are valid. Af-
ter this wake-up interval tPHEL or tPHWL, normal op-
eration is restored.The CUI is reset to read array mode
and status register is set to 80H. Sector lock bit is set at
lock status.
The CUI does not occupy an addressable memory loca-
tion.It is written whenWE and CE are active (whichever
goes high first). The address and data needed to ex-
ecute a command are latched on the rising edge of WE
or CE. Standard microprocessor write timings are used.
During sector erase, word/byte write or sector lock/un-
lock modes, RP-low will abort the operation. Memory
contents being altered are no longer valid; the data may
be partially erased or written.
In addition, CUI will go into either array read mode or
erase/write interrupted mode.When power is up and the
device reset subsequently, it is necessary to read sta-
tus register in order to assure the status of the device.
Recognizing status register (SR.7~0) will assure if the
device goes back to normal reset and enters array read
mode.
3.5 Read Configuration Codes
The read configuration codes operation outputs the manu-
facturer code, device code, sector lock configuration
codes, and the protection register Using the manufac-
turer and device codes, the system CPU can automati-
cally match the device with its proper algorithms. The
sector lock codes identify locked and unlocked sectors.
3.6 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection
and clearing of the status register.WhenVCC=2.7V-3.6V
and VPP=VPPH1/2, the CUI additionally controls sec-
tor erase, full chip erase, word/byte write and sector lock/
unlock.
The Sector Erase command requires appropriate com-
mand data and an address within the sector to be erased.
The Full Chip Erase command requires appropriate com-
mand data and an address within the device.TheWord/
ByteWrite command requires the command and address
of the location to be written. Set Sector lock/unlock com-
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MX28F160C3T/B
4 COMMAND DEFINITIONS
When the VPP voltage < VPPLK, read operations from
the status register, identifier codes, or sectors are en-
abled. Placing VPP on VPPH1/2 enables successful
sector erase, full chip erase, word/byte write and sector
lock/unlock.
Device operations are selected by writing specific com-
mands into the CUI.Table 3 defines these commands.
Table 2. Bus Operation 1,2
Mode
Notes
RP
VIH
VIH
VIH
VIL
VIH
CE
VIL
VIL
VIH
X
OE
VIL
VIH
X
WE
VIH
VIH
X
DQ0~DQ15
DOUT
High Z
High Z
High Z
DIN
Read
1,2
Output Disable
Standby
Reset
2
2
2
X
X
Write
2,3,4,5
VIL
VIH
VIL
Notes:
1. Refer to DC Characteristics for VPPLK, VPP1, VPP2, VPP3 voltage.
2. X can be VIL or VIH for pin and addresses.
3. RP at GND±0.2 to ensure the lowest power consumption.
4. Refer to Table 3 for valid DIN during a write operation.
5. To program or erase the lockable sectors holds WP at VIH.
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MX28F160C3T/B
Table 3. Command Definition (1)
Command
Bus
Notes
First Bus Cycle
Operation Address
Second Bus Cycle
Cycles
Data Operation Address Data
Required
(1)
(2)
X
X
X
X
X
X
X
X
(3)
FFH
(1)
(2)
(3)
Read Array
1
> 2
2
Write
Write
Write
Write
Write
Write
Write
Write
Read Configuration
Read Query
3,4
2,7
3
90H
Read
Read
Read
IA
QA
X
ID
98H
QD
Read Status Register
Clear Status Register
Sector Erase/Confirm
Word/Byte Write
2
70H
SRD
1
3
50H
2
20H
Write
Write
BA
D0H
WD
2
5
40H/10H
B0H
WA
Program/Erase Suspend
1
Program/Erase Resume
1
Write
X
D0H
Sector Lock
2
2
2
2
Write
Write
Write
Write
X
X
X
X
60H
60H
60H
C0H
Write
Write
Write
Write
BA
BA
BA
PA
01H
D0H
2FH
PPH
Sector Unlock
6
Lock-Down Sector
Protection Program
Notes:
1. Bus operation are defined inTable 2 and referred to ACTiming Waveform.
2. X=Any address within device
IA=ID-Code Address (refer to Table 4)
BA=Sector within the sector being erased
WA=Address of memory location to be written
QA=Query Address, QD=Query Data
3. Data is latched from the rising edge of WE or CE (whichever goes high first)
SRD=Data read from status register, see Table 6 for description of the status register bits.
WD=Data to be written at location WA. ID=Data read from identifier codes
4. Following the Read configuration codes command, read operation access manufacturer, device codes, sector
lock/unlock codes, see chapter 4.2.
5. Either 40H or 10H are recognized by the WSM as word/byte write setup.
6. The sector unlock operation simultaneously clear all sector lock.
7. Read Query Command is read for CFI query information.
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MX28F160C3T/B
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from reset
mode, the device defaults to read array mode.This op-
eration is also initiated by writing the Read Array com-
mand. The device remains enabled for reads until an-
other command is written. Once the internal WSM has
started a sector erase, word/byte write or sector lock
configuration the device will not recognize the Read Ar-
ray command until the WSM completes its operation
unless the WSM is suspended via a Sector Erase Sus-
pend or Word Write Suspend command. If RP=VIL de-
vice is in read Read Array command mode, this read
operation no longer requiresVPP.The Read Array com-
mand functions independently of the VPP voltage and
RP can be VIH.
CUI writes read status command (70H).The status reg-
ister may be read to determine when a sector erase,
word/byte write or lock-bit configuration is complete and
whether the operation completed successfully. (refer to
table 6) It may be read at any time by writing the Read
Status Register command. After writing this command,
all subsequent read operations output data from the sta-
tus register until another valid command is written.The
status register contents are latched on the falling edge
of CE or OE, whichever occurs. CE or OE must toggle
toVIH before further reads to update the status register
latch.The Read Status Register command functions in-
dependently of the VPP voltage. RP can be VIH.
4.4 Clear Status Register Command
4.2 Read Configuration Codes Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to
"1"s by the WSM and can only be reset by the Clear
Status Register command (50H). These bits indicate
various failure conditions (seeTable 6).By allowing sys-
tem software to reset these bits, several operations (such
as cumulatively erasing multiple sectors or writing sev-
eral words/bytes in sequence) may be performed. The
status register may be polled to determine if an error
occurred during the sequence.
The configuration code operation is initiated by writing
the Read Configuration Codes command (90H). To re-
turn to read array mode, write the Read Array Command
(FFH). Following the command write, read cycles from
addresses shown in Table 4 retrieve the manufacturer,
device, sector lock configuration codes (see Table 4 for
configuration code values).To terminate the operation,
write another valid command. Like the Read Array com-
mand, the Read Configuration Codes command func-
tions independently of the VPP voltage and RP can be
VIH. Following the Read Configuration Codes command,
the information is shown:
To clear the status register, the Clear Status Register
command (50H) is written on CUI. It functions indepen-
dently of the applied VPP Voltage. RP can be VIH.This
command is not functional during sector erase or word
write suspend modes.
Table 4: ID Code
Code
Address
(A19-A0)
00000H
00001H
Data
(DQ15-DQ0)
00C2H
88C2/88C3H
LocK
Manufacturer Code
Device Code
Sector Lock Configuration XX002H
- Sector is unlocked
DQ0=0
DQ0=1
DQ1=1
PR-LK
- Sector is locked
- Sector is locked-down
Protection Register Lock 80
Protection Register
81-88
PR
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MX28F160C3T/B
When word/byte write is complete, status register bit
SR.4 should be checked. If word/byte write error is de-
tected, the status register should be cleared.The inter-
nal WSM verify only detects errors for "1"s that do not
successfully write to "0"s.The CUI remains in read sta-
tus register mode until it receives another command.
4.5 Sector Erase Command
Erase is executed one sector at a time and initiated by a
two-cycle command. A sector erase setup is first writ-
ten (20H), followed by a sector erase confirm (D0H).This
command sequence requires appropriate sequencing and
an address within the sector to be erased. Sector pre-
conditioning, erase, and verify are handled internally by
the WSM. After the two-cycle sector erase sequence is
written, the device automatically outputs status register
data when read (see Figure 8).The CPU can detect sec-
tor erase completion by analyzing the output data of the
status register bit SR.7.
Reliable word/byte writes can only occur when
VCC=2.7V~3.6V andVPP=VPPH1/2.In the absence of
this high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
VPP<VPPLK, status register bits SR.3 and SR.4 will be
set to "1". Successful word/byte write requires for boot
sector that WP is VIH the corresponding sector lock-bit
be cleared. In parameter and main sectors case, it must
be cleared the corresponding sector lock-bit. If word/
byte write is attempted when the excepting above sec-
tor being clocked conditions, SR.1 and SR.4 will be set
to "1".Word write is not functional.
When the sector erase is complete, status register bit
SR.5 should be checked. If a sector erase error is de-
tected, the status register should be cleared before sys-
tem software attempts corrective actions. The CUI re-
mains in read status register mode until a new com-
mand is issued.
4.7 Sector Erase Suspend Command
This two-step command sequence of set-up followed by
execution ensures that sector contents are not acciden-
tally erased. An invalid sector Erase command sequence
will result in both status register bits SR.4 and SR.5
being set to "1". Also, reliable sector erasure can only
occur when 2.7V~3.6V and VPP=VPPH1/2. In the ab-
sence of this high voltage, sector contents are protected
against erasure. If sector erase is attempted while
VPP<VPPLK SR.3 and SR.5 will be set to "1". To suc-
cessfully erase the boot sector, the corresponding sec-
tor lock-bit must be clear first. In parameter and sectors
case, it must be cleared the corresponding sector lock-
bit. If sector erase is attempted when the excepting
above sector being locked conditions, SR.1 and SR.5
will be set to "1". Sector erase is not functional.
The Sector Erase Suspend command (50H) allows sec-
tor-erase interruption to read or word/byte write data in
another sector of memory. Once the sector erase pro-
cess starts, writing the Sector Erase Suspend command
requests that the WSM suspend the sector erase se-
quence at a predetermined point in the algorithm. The
device outputs status register data when read after the
Sector Erase Suspend command is written.Polling sta-
tus register bits SR.7 and SR.6 can determine when the
sector erase operation has been suspended (both will
be set to "1"). Specification tWHR12 defines the sector
erase suspend latency.
When Sector Erase Suspend command write to the CUI,
if sector erase was finished, the device places read ar-
ray mode.Therefore, after Sector Erase Suspend com-
mand write to the CUI, Read Status Register command
(70H) has to write to CUI, then status register bit SR.6
should be checked for placing the device in suspend
mode.
4.6 Word/Byte Write Command
Word/Byte write is executed by a two-cycle command
sequence.Word/Byte write setup (standard 40H or alter-
nate 10H) is written, followed by a second write that speci-
fies the address and data. The WSM then takes over,
controlling the word/byte write and write verify algorithms
internally.After the word/byte write sequence is written,
the device automatically outputs status register data when
read (see Figure 6).The CPU can detect the completion
of the word/byte write event by analyzing the status reg-
ister bit SR.7.
At this point, a Read Array command can be written to
read data from sectors other than that which is sus-
pended. A Word/Byte Write commands sequence can
also be issued during erase suspend to program data in
other sectors.Using theWord/Byte Write Suspend com-
mand (see Section 4.9), a word/byte write operation can
also be suspended. During a word/byte write operation
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MX28F160C3T/B
with sector erase suspended, status register bit SR.7
will return to "0". However, SR.6 will remain "1" to indi-
cate sector erase suspend status.
pended.The only other valid commands while word/byte
write is suspended are Read Status Register andWord/
ByteWrite Resume.AfterWord/ByteWrite Resume com-
mand is written to the flash memory, the WSM will con-
tinue the Word/Byte write process. Status register bits
SR.2 and SR.7 will automatically clear. After the Word/
ByteWrite Resume command is written, the device au-
tomatically outputs status register data when read (see
Figure 4).VPP must remain at VPPH1/2 while in word/
byte write suspend mode.RP must also remain atVIL or
VHH (the same RP level used for word write).
The only other valid commands while sector erase is
suspended are Read Status Register and sector erase
Resume. After a Sector Erase Resume command is writ-
ten to the flash memory, the WSM will continue the sec-
tor erase process. Status register bits SR.6 and SR.7
will automatically clear. After the Erase Resume com-
mand is written, the device automatically outputs status
register data when read (see Figure 4). VPP must re-
main at VPPH1/2 while sector erase is suspended. RP
must also remain at VIL or VHH (the same RP level
used for sector erase). WP must also remain at VIL or
VIH (the same WP level used for sector erase). Sector
cannot resume until word/byte write operations initiated
during sector erase suspend has completed.
If the time between writing the Word/Byte Write Resume
command and writing theWord/ByteWrite Suspend com-
mand is short and both commands are written repeat-
edly, a longer time is required than standard word/byte
write until the completion of the operation.
If the time between writing the Sector Erase Resume
command and writing the Sector Erase Suspend com-
mand is shorter than 15ms and both commands are writ-
ten repeatedly, a longer time is required than standard
sector erase until the completion of the operation.
4.8 Word/Byte Write Suspend Command
The Word/Byte Write Suspend command allows word/
byte write interruption to read data in other flash memory
locations.Once the word/byte write process starts, writ-
ing the Word/Byte Write Suspend command requests
that theWSM suspend the Word/Byte write sequence at
a predetermined point in the algorithm.The device con-
tinues to output status register data when read after the
Word/Byte Write Suspend command is written. Polling
status register bits SR.7 and SR.2 can determine when
the word/byte write operation has been suspended (both
will be set to "1"). Specification tWHR11 defines the word/
byte write suspend latency.
When Word/Byte Write Suspend command write to the
CUI, if word/byte write was finished, the device places
read array mode.Therefore, afterWord/Byte Write Sus-
pend command write to the CUI, Read Status Register
command (70H) has to write to CUI, then status register
bit SR.2 should be checked for placing the device in
suspend mode.
At this point, a Read Array command can be written to
read data from locations other than that which is sus-
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MX28F160C3T/B
4.9 Sector Lock/Unlock /Lockdown Command
4.9.1 Sector Locked State
4.9.4 Read Sector Lock Status
The lock status of every sector can be read through
Read Configuration mode.To enter this mode first com-
mand write 90H to the device.The next sector reads at
address +00002 will output the lock status of this sec-
tor. The lock status can be read from the lowest two
output pins DQ0 and DQ1. DQ0, DQ0 indicates the sec-
tor lock/unlock status and set by the lock command and
cleared by the unlock command. When entering lock-
down, the lock status is automatically set. DQ1 indi-
cates lock-down status and is set by the lock-down com-
mand. It cannot be further cleared by software, only by
device reset or power-down.
The default status of all sectors when power-up or reset
is locked. Any attempt on program or erase operations
will result in an error on bit SR.1 of a locked sector.The
status of a locked sector can be changed to unlocked or
lock-down using software commands. An unlocked sec-
tor can be locked by locked by writing the sector lock
command sequence, 60H followed by 01H.
4.9.2 Sector Unlocked State
An unlocked sector can be programmed or erased. All
unlocked sector return to the locked state when the de-
vice is either reset or powered down. The status of an
unlocked sector can be changed to locked or locked-
down using software commands. A locked sector can
be unlocked by writing unlock command sequence, 60H
followed by D0H.
Sector Lock ConfigurationTable
Lock Status
Data
Sector is unlocked
Sector is locked
Sector is locked-down
DQ0=0
DQ0=1
DQ1=1
4.9.3 Sector Locked-Down State
Sectors which are locked-down are protected from pro-
gram and erase operation; however, the protection sta-
tus of three sectors cannot be changed using software
commands alone. Any sector locked or unlocked can be
locked-down by writing the lock-down command se-
quence, 60H followed by 2FH.When the device is reset
or powered down, the locked-down sectors will revert to
the locked state.
The status of WP will determine the function of sector
lock-down and is summarized is followed:
WP
Sector Lock-down Description
WP=0
- sectors are protected from program, erase,
and lock status changes
WP=1
- the sector lock-down function is disabled
- an individual lock-down sector can be un-
locked and relocked via software command.
Once WP goes low, sectors that previously
locked-down returns to lock-down state
regardless of any changes whenWP was
high.
In addition, sector lock-down is cleared only when the
device is reset or powered down.
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MX28F160C3T/B
sector is being placed in erase suspend, the locking sta-
tus bits will be changed immediately, but when the erase
is resumed, the erase operation will complete.
4.9.5 Sector Locking while Erase Suspend
The sector lock status can be performed during an erase
suspend by using standard locking command sequences
to unlock, lock, or lock-down a sector.
Locking operation cannot be performed during a program
suspend.
In order to change sector locking during an erase opera-
tion, the write erase suspend command (B0H) is placed
first; then check the status register until it is shown that
the actual erase operation has been suspended. Subse-
quent writing the desired lock command sequence to a
sector and the lock status will be changed. When com-
pleting any desired lock, read or program operation, re-
sume the erase operation with the Erase Resume Com-
mand (D0H).
4.9.6 Status Register Error Checking
The operation of locking system for this device can be
used the term "state (X,Y,Z)" to specify locking status,
where X=value of WP,Y=bit DQ1 of the sector lock sta-
tus register, and Z=bit DQ0 of the sector lock status
register. DQ0 indicates if a sector is locked (1) or un-
locked (0). DQ1 indicates if a sector has been locked-
down(1) or not (0).
If a sector is locked or locked-down during the same
Table 5. Sector Locking State Transitions
Current State
Erase/Prog.
Operation if
Lock Command Input Result (Next State)
(X,Y, Z)=
(X,Y, Z)=
WP DQ1 DQ0
Name
Unlocked
Enable ?
Yes
No
Lock
(001)
Unlock
Unchanged
Unchanged
Unchanged
Unchanged
(100)
Lock-Down
(011)
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
1
1
0
1
0
1
Locked
Unchanged
Unchanged
(101)
(011)
Locked-Down
Unlocked
No
Unchanged
(111)
Yes
No
Locked
Unchanged
(111)
(111)
Lock-Down Disabled
Lock-Down Disabled
Yes
No
Unchanged
(110)
(111)
Unchanged
Unchanged
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MX28F160C3T/B
Table 6. Status Register Definition
WSMS
7
BESS
6
ES
5
PS
4
VPPS
3
PSS
2
BLS
1
R
0
NOTES:
Check WSM bit first to determine word program or sec-
tor Erase completion, before checking Program or Erase
Status bits.
SR.7 = WRITE STATE MACHINE STATUS (WSMS)
1 = Ready
0 = Busy
When Erase Suspend is issued, WSM halts execution
and sets both WSMs and ESS bits to "1". ESS bit re-
mains set to "1" until an Erase Resume command is
issued.
SR.6 = SECTOR ERASE SUSPEND STATUS (BSS)
1 = Sector ERASE Suspended
0 = Sector Erase in Progress/Completed
SR.5 = ERASE STATUS (ES)
1 = Error in Programming
0 = Successful Sector Erase or Clear Sector Lock-
Bits
When this bit (SR.5) is set to "1", it means WSM is
unable to verify successful sector erasure.
When this bit is set to "1",WSM has attempted but failed
to program a word/byte.
SR.4 = PROGRAM STATUS (PS)
1 = Error in Programming
0 = Successful Programming
SR.3 bit is not guaranteed to report accurate feedback
between VPPLK and VPP min.
SR.3 = VPP STATUS (VPPS)
1 = VPP Low Detect, Operation Abort
0 = VPP OK
When program suspend is issued, WSM halts the ex-
ecution and sets both WSMs and SR.2 bit to "1". SR.2
remains set to "1" until a Program Resume command is
issued.
SR.2 = PROGRAM SUSPEND STATUS (WWSS)
1 = Program Suspended
0 = Program in Progress/Completed
If a program or erase operation is attempted to one of
the locked sectors, this bit is set by the WSM. The op-
eration specified is aborted and the device is returned to
read status mode.
SR.1 = SECTOR LOCK STATUS
1 =Program/Erase attempted an a locked sector;
operation aborted
0 = No operation to locked sectors
SR. 0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE ENHANCEMENTS
(R)
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MX28F160C3T/B
read cycles from addresses shown in Table 7 will re-
trieve the specified information. To return to read array
mode, write the Read Array Command (FFH).
5. 128-Bit Protection Register
The 128-bits of protection register are divided into two
64-bit segments. One of the segments is programmed
at MXIC side with unique 64-bit number; where changes
are forbidden. The other segment is left empty for cus-
tomer to program. Once the customer segment is pro-
grammed, it can be locked to prevent further reprogram-
ming.
Two-cycle Protection Program Command is used to pro-
gram protection register bits.The 64-bit register is pro-
grammed 16-bits at a time. First write C0H protection
program setup.The next write to the device will latch in
address and data and program the specified location.
The allowable address are also show inTable 7.Refer to
Figure 6 for the Protection Register Programming Flow-
chart.
5.1 Protection Register Read & Programming
Any attempt to address Protection Program command
onto undefined protection register address space will
result in a Status Register error (SR.4 set to "1"). In
addition, attempting to program or to previously locked
protection register segment will result in a status regis-
ter error (SR.4=1, SR.1=1).
The protection register is read in the configuration read
mode, which follows the stated Command Bus Defini-
tions.
The device is switched to this read mode by writing the
Read Configuration command (90H). Once this mode,
Table 7. Word-Wide Protection Register Addressing
Word
User
A7
1
A6
0
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
Lock
Both
0
1
2
3
4
5
6
7
Factory
Factory
Factory
Factory
Customer
Customer
Customer
Customer
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
Table 8. Protection Register Memory Map
5.2 Protection Register Locking
The user-programmable segment of the protection reg-
ister is lockable by programming Bit 1 of the PR-Lock
location to 0. Bit 0 of this location is programmed to 0 at
MXIC to protect the unique device number. This bit is
set using the unique device number.This bit is set using
the protection program command to program "FFFD" to
PR-LOCK location. After these bits have been pro-
grammed, no further changes can be made to the value
stored in the protection register.Protection program com-
mand to a locked section will result in a status register
error (Program Error bit SR.4 and Lock Error bit SR.1
will be set to 1). Protection register lockout state is not
reversible.
Protection Register Purpose
Bit Address
88H~85H
84H~87H
4 word user program Register
4 word factory program
Register
80H(Bit0 & Bit1)
Protection Register Lock
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MX28F160C3T/B
WARNING:Stressing the device beyond the "Absolute
Maximum Ratings" may cause permanent damage.
These are stress ratings only. Operation beyond the
"Operating Conditions" is not recommended and ex-
tended exposure beyond the "Operation Conditions" may
affect device reliability.
6 ELECTRICAL SPECIFICATIONS
6.1 ABSOLUTE MAXIMUM RATINGS
OperatingTemperature
During Read, Sector Erase, Word/Byte
Write . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Storage Temperature . . . . . . . . . . . . . .-65oC to +125oC
Voltage on Any Pin (except VCC and
VPP with respect to GND) ..... ......-0.5V to +5V(1)
VCC Supply Voltage . . . . . . . . . . . . .-0.2V to +4.6V(2)
VPP Supply Voltage (for sector erase and
VPP with respect to GND) . . . . . . . .-0.5V to +13.5V(1,2,4)
VCC andVCCQ SupplyVoltage
with respect to GND. . . . . . . . . . . . . . . . .-0.2V to +5.0V(1)
Output Short Circuit Voltage . . . . . . . . . . . . .100mA(3)
1. Minimum DC voltage is -0.5V on input pins. During
transitions, this level may undershoot to -2.0V for pe-
riods <20ns. Maximum DC voltage on input/output pins
toVCC+0.5V which during transition; may overshoot
to VCC+2.0V for periods <20ns.
2. Maximum DC voltage on VPP may overshoot to
+14.0V for periods <20ns.
3. Output shorted for no more than one second.No more
than one output shorted at a time.
4. VPP voltage is normally 1.65V~3.6V. Connection to
supply of 11.4~12.6V can only be done for 1000
cycles on the main sectors and 25000 cycles on the
parameter sectors during program/erase. VPP may
be connected to 12V for a total of 80 hours maximum.
6.2 Operating Conditions (Temperature andVCC Operating Conditions)
Symbol
TA
Parameter
Min.
-40
Max.
+85
3.6
Unit
oC
V
Notes
OperatingTemperature
VCC SupplyVoltage
I/O Supply Voltage
I/O Supply Voltage
I/O Supply Voltage
SupplyVoltage
VCC1
2.7
1
1
1
1
1
1
2
VCCQ1
VCCQ2
VCCQ3
VPP1
2.7
3.6
V
1.65
1.8
2.5
V
2.5
V
1.65
11.4
3.6
V
VPP2
SupplyVoltage
12.6
V
Cycling
Sector Erase Cycling
NOTE:
1.VCC and VCCQ must share the same supply when they are in the VCC1 range.
2.Applying VPP=11.4~12.6V during a program/erase can only be done for a maximum of 1000 cycles on the main
sectors and 2500 cycles on the parameter sectors.VPP may be connected to 12V for a total of 80 hours maximum.
6.2.1 Capacitance (1) (TA=+25oC, f=1MHz)
Symbol
CIN
Parameter
Typ.
6
Max.
8
Unit
pF
Test Condition
VIN=0.0V
Input Capacitance
Output Capacitance
COUT
10
12
pF
VOUT=0.0V
NOTE:
1.Sampled, not 100% tested.
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MX28F160C3T/B
6.2.2 AC Input/Output Test Conditions
VCCQ
VCCQ/2 Output
TEST POINTS
Input VCCQ/2
0.0
Note:AC test inputs are driven at VCCQ/2 for a Logic "1" and 0.0V for a Logic "0".
Figure 1.Transient Input/Output ReferenceWaveform
Figure 2. SWITCHINGTEST CIRCUITS
TEST SPECIFICATIONS
Test Condition
Output Load
70 90 120 Unit
1 TTL gate
DEVICE UNDER
TEST
2.7K ohm
3.3V
Output Load Capacitance, CL 30 100 100 pF
(including jig capacitance)
Input Rise and Fall Times
Input Pulse Levels
5
ns
V
0.0-3.0
1.5
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
Input timing measurement
reference levels
V
Output timing measurement
reference levels
1.5
V
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MX28F160C3T/B
6.2.3 AC Characteristic -- Read Only Operation (1)
-70
-90
Min.
-110
Min.
Sym.
Parameter
Notes
Min.
Max.
Max.
Max. Unit
tAVAV
tAVQV
tELQV
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
tOH
Read CycleTime
70
90
110
ns
Address to Output Delay
CE to Output Delay
OE to Output Delay
RP to Output Delay
CE to Output in Low Z
OE to Output in Low Z
CE to Output in High Z
OE to Output in High Z
Output Hold from Address,
CE, or OE Change,
Whichever Occurs First
70
70
90
90
110
110
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
20
30
150
150
150
3
3
3
3
3
0
0
0
0
0
0
20
20
20
20
20
20
0
0
0
Notes:
1. See ACWaveform:Read Operations.
2. OE may be delayed up to tELQV-tGLQV after the falling edge of CE without impact on tELQV.
3. Sampled, but not 100% tested.
4. See test Configuration.
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MX28F160C3T/B
Figure 3. READ-ONLY OPERATION AC WAVEFORM
Device and
Address Selection
Data
Valid
Standby
VIH
Addresses(A)
Address Stable
VIL
tAVAV
VIH
CE (E)
VIL
tEHQZ
tGHQZ
VIH
OE (G)
VIL
VIH
WE (W)
tGLQV
VIL
tOH
tGLQX
tELQV
tELQX
VOH
DATA
(D/Q)
High Z
High Z
Valid Output
VOL
tAVQV
VIH
tPHQV
RP (P)
VIL
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MX28F160C3T/B
6.2.5 AC Characteristic -- Write Operation
-70
Min.
150
0
-90
Min.
150
0
-110
Min.
150
0
Sym.
tPHWL/tPHEL RP High Recovery toWE(CE) Going Low
tELWL/tWLEL CE(WE) Setup toWE(CE) Going Low
Parameter
Note
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tELEH/tWLWH WE(CE) Pulse Width
4
2
2
45
40
50
0
50
50
50
0
70
60
70
0
tDVWH/tDVEH Data Setup to WE(CE) Going High
tAVWH/tAVEH Address Setup to WE(CE) Going High
tWHEH/tEHWH CE(WE) HoldTime fromWE(CE) High
tWHDX/tEHDX Data HoldTime fromWE(CE) High
tWHAX/tEHAX Address Hold Time fromWE(CE) High
tWHWL/tEHEL WE(CE) Pulse Width High
2
2
4
3
3
3
3
3
0
0
0
0
0
0
25
200
0
30
200
0
30
200
0
tVPWH/tVPEH VPP Setup to WE(CE) Going High
tQVVL
VPP Hold from Valid SRD
tBHWH/tBHEH WP Setup to WE(CE)Going High
0
0
0
tQVBL
tWHGL
WP Hold fromValid SRD
WE High to OE Going Low
0
0
0
30
30
30
Notes:
1. Write timing characteristics during erase suspend are the same as during write-only operations.
2. Refer to Table 5 for valid AIN or DIN.
3. Sampled, not 100% tested.
4. Write pulse width (tWP) is defined from CE or WE going low (whichever goes low last) to CE or WE going high
(whichever goes high first). Hence, tWP=tWLWH=tELEH=tELWH. Similarly, Write pulse width high (tWPH) is
defined from CE or WE going high (whichever goes high first) to CE or WE going low (whichever goes low first).
Hence, tWPH=tWHWL=tEHEL=tEHWL.
5. SeeTest Configuration.
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MX28F160C3T/B
Figure 4. WRITE AND ERASE OPERATION AC WAVEFORM
A
B
C
D
E
F
VIH
VIL
Address (A)
AIN
AIN
tAVWH
(tAVEH)
tWHAX
(tEHAX)
(Note 1)
VIH
VIL
CE(WE)[E(W)]
tELWL
(tWLEL)
tWHEH
(tEHWH)
VIH
VIL
OE(G)
Disable
tWHWL
(tEHEL)
tWHGL
(Note 1)
VIH
VIL
WE,(CE)[W(E)]
Enable
tELEH
(tWLWH)
tDVWH
(tEVEH)
tWHDX
(tEHDX)
VIH
VIL
High Z
Valid
SRD
DATA[D/Q]
RP[P]
DIN
DIN
DIN
tPHWL
(tPHEL)
VOH
VOL
tQVBL
tQVVL
tBHWH
(tBHEH)
VIH
VIL
WP
tVPWH
(tVPEH)
VPPH2
VPPH1
VPP[V]
VPPLK
VIL
Notes:
1. CE must be toggled low when reading Status Register Data. WE must be inactive (high) when reading Status
Register Data.
A.VCC Power-Up and Standby.
B.Write Program or Erase Setup Command.
C.WriteValid Address and Data (for Program) or Erase Confirm Command.
D.Automated Program or Erase Delay.
E.Read Status Register Data (SRD): reflects completed program/erase operation.
F.Write Read Array Command.
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MX28F160C3T/B
6.2.5 Erase and Program Timing (1)
Vpp
Note
2,3
1.65V-3.6V
11.4V-12.6V
Symbol
Parameter
Typ(1)
Max
Typ(1)
Max
Unit
tBWPB
4-KW Parameter Sector
Word ProgramTime(Word)
32-KW Main Sector
Word ProgramTime
Word ProgramTime
0.10
0.30
0.03
0.24
8
0.12
s
tBWMB
2,3
2,3
2,3
2,3
3
0.8
12
0.5
1
2.4
200
4
1
185
4.0
5
s
us
s
tWHQV1/
tEHQV1
tWHQV2/
tEHQV2
tWHQV3/
tEHQV3
tWHRH1/
tEHRH1
tWHRH2/
tEHRH2
4-KW Parameter Sector
Erase Time (Byte)
0.4
0.6
15
32-KW Main Sector
Erase Time (Byte)
5
s
Program Suspend Latency
15
15
20
20
20
20
us
us
Erase Suspend Latency
3
15
Notes:
1. Typical values measured at TA=+25°C and nominal voltage.
2. Excludes external system-level overhead.
3. Sampled, but not 100% tested.
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MX28F160C3T/B
Figure 5. RESET WAVEFORM
VIH
VIL
RP (P)
tPHQV
tPHWL
tPHEL
tPLPH
tPLRH
(A) Reset during Read Mode
tPHQV
Abort
Complete
tPHWL
tPHEL
VIH
RP (P)
VIL
tPLPH
(B) Reset during Program or Sector Erase, tPLPH < tPLRH
Abort
Deep
Power-
Down
tPHQV
tPHWL
tPHEL
Complete
tPLRH
VIH
VIL
RP (P)
tPLPH
(C) Reset Program or Sector Erase, tPLPH > tPLRH
AC Characteristic -- Under Reset Operation
Sym.
Parameter
VCC=2.7V~3.6V
Unit
Notes
Min.
Max.
tPLPH
RP Low to Reset during Read
100
ns
2,4
(If RP is tied to VCC, this specification is applicable)
tPLRH1 RP Low to Reset during Sector Erase
tPLRH2 RP Low to Reset during Program
22
12
us
us
3,4
3,4
Notes:
1. See Section 3.4 for a full description of these conditions.
2. If tPLPH is < 100ns the device may still reset but this is not guaranteed.
3. If RP is asserted while a sector erase or word program operation is not executing, the reset will complete within
100ns.
4. Sampled, but not 100% tested.
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MX28F160C3T/B
6.2.6 DC Characteristics
Sym. Parameter
VCC
VCCQ
Note
1,2
2.7V-3.6V
2.7V-3.6V
2.7V-2.85V
1.65V-2.5V
2.7V-3.0V
1.8V-2.5V Unit Test Conditions
Typ. Max. Typ. Max.
Typ.
Max.
ILI
Input Load Current
± 1
± 10
15
± 1
± 10
50
± 1 uA VCC=VCC Max.
VCCQ=VCCQ Max.
VIN=VCCQ or GND
± 10 uA VCC=VCC Max.
VCCQ=VCCQ Max.
VIN=VCCQ or GND
250 uA VCC=VCC Max.
CE=RP=VCCQ
ILO
Output Leakage
Current
1,2
1
0.2
7
0.2
20
0.2
ICCS VCC Standby Current
150
or during Program/
Erase Suspend
WP=VCCQ or GND
20 uA VCC=VCC Max
VCCQ=VCCQ Max
VIN=VCCQ or GND
RP=GND±0.2V
ICCD VCC Power-Down
Current
1,2
7
9
15
18
7
8
20
15
7
9
ICCR VCC Read Current
1,2,3
15 mA VCC=VCC Max
VCCQ=VCCQ Max
OE=VIH, CE=VIL
f=5MHz, IOUT=0mA
Inputs=VIL or VIH
IPPD VPP Deep Power-
Down Current
1
0.2
5
0.2
5
0.2
5
uA RP=GND±0.2V
VPP < VCC
IPPR VPP Read Current
1,4
1,4
2
±15
200
0.1
2
±15
200
55
2
±15 uA VPP < VCC
200 uA
50
50
18
50
18
0.05
55 mA VPP=VPP1,
ICCW+ VCC+VPP Program
IPPW Current
Program in Progress
8
22
0.1
22
10
21
16
21
30
45
45
45
10
21
16
21
30 mA VPP=VPP2(12V)
Program in Progress
45 mA VPP=VPP1
Erase in Progress
1,4
1,4
0.05
8
ICCE+ VCC+VPP Erase
IPPE Current
45 mA VPP=VPP2(12V)
Erase in Progress
0.05
0.1
45 mA VPP=VPP1
Program or Erase
IPPES VCC+VPP Program
+
or Erase Suspend
Suspend in Progress
200 mA VPP=VPP2(12V)
Program or Erase
IPPWS Current
50
200
50
200
50
Suspend in Progress
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MX28F160C3T/B
VCC
VCCQ
Note
2.7V-3.6V
2.7V-3.6V
2.7V-2.85V
1.65V-2.5V
2.7V-3.0V
1.8V-2.5V
SYM. Parameter
Unit Test Conditions
Typ. Max. Typ. Max.
Typ.
Max.
0.4
VIL
Input LowVoltage
-0.4 VCC* -0.4
0.22V
0.4
-0.4
V
VIH
VOL
Input HighVoltage
Output LowVoltage
2.0 VCCQ VCCQ VCCQ VCCQ VCCQ V
+0.3V -0.4V +0.3V -0.4V +0.3V
-0.1
0.1
-0.1
0.1
-0.1
0.1
1.0
V
V
V
VCC=VCC Min
VCC=VCCQ Min
IOL=100uA
VOH
Output HighVoltage
VCCQ
-0.1V
VCCQ
-0.1V
VCCQ
-0.1V
VCC=VCC Min
VCC=VCCQ Min
IOH=-100uA
VPPLK VPP Lock-Out Voltage
6
1.0
3.6
1.0
CompleteWrite
Protection
VPP1 VPP during Program/
VPP2 Erase Operations
VLKO VCC Prog/Erase
LockVoltage
6
1.65
1.5
V
V
V
6,7
11.4 12.6
1.5
1.5
1.2
VLKO2 VCCQ Prog/Erase
LockVoltage
1.2
1.2
V
Notes:
1. All currents are in RMS unless otherwise noted.Typical values at nominal VCC, TA=+25°C.
2. The test conditions VCC Max, VCCQ Max, VCC Min, and VCCQ Min refer to the maximum or minimum VCC or
VCCQ voltage listed at the top of each column.VCC Max=3.3V for 0.25um 32-Mbit devices.
3. Power Savings (Mode) reduces ICCR to approximately standby levels in static operation (CMOS inputs).
4. Sampled, but not 100% tested.
5. ICCES and ICCWS are specified with device de-selected. If device is read while in erase suspend, current draw is
sum of ICCES and ICCR. If the device is read while in program suspend, current draw is the sum of ICCWS and
ICCR.
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MX28F160C3T/B
Figure 6. Automated Word Programming Flowchart
Bus
Command Comments
Start
Operation
Write
Program
Setup
Data=40H
Write 40H
Write
Read
Program
Data=Data to Program
Addr=Location to Program
Status Register DataToggle
CE or OE to Update Status
Register Data
Program Address/Data
Read Status Register
Standby
Check SR.7
1=WSM Ready
0=WSM Busy
No
SR.7=1 ?
Repeat for subsequent programming operations.
SR full status check can be done after each program
or after a sequence of program operations.
Write FFH after the last program operation to reset
device to read array mode.
Yes
Full Status
Check if Desired
Program Ccomplete
Bus
Command
Comments
FULL STATUS CHECK PROCEDURE
Operation
Standby
Check SR.3
Read Status Register
Data(See Above)
1=VPP Low Detect
Check SR.4
Standby
Standby
1=VPP Program Detect
Check SR.11
1
VPP Range Error
Programming Error
SR.3=
1=Attempted Program to
Locked Sector-Program
Aborted
0
1
1
SR.4=
0
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by theWrite
State Machine.
SR.4, SR.3, and SR.1 are only cleared by the Clear
Status Register Command, in cases where multiple
programmed before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
Attempted Program to
Locked Block- Aborted
SR.1=
0
Program Successful
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MX28F160C3T/B
Figure 7. Program Suspend/Resume Flowchart
Start
Bus
Command Comments
Operation
Write
Program
Suspend
Data=B0H
Addr=X
Write B0H
Write 70H
Write
Read
Read Status Data=70H
Addr=X
Status Register DataToggle
Read
Status Register
CE or OE to Update Status
Register Data
Addr=X
0
Standby
Stanby
Check SR.7
SR.7=
1=WSM Ready
0=WSM Busy
1
Check SR.2
0
1=Program Suspended
0=Program Completed
SR.2=
Program Completed
1
Write
Read
Read Array Data=FFH
Addr=X
Write FFH
Read array data from
sector other than the one
being programmed.
Data=D0H
Read Array Data
Done Reading
Write
Program
Resume
Addr=X
No
Yes
Write D0H
Write FFH
Program Write Resumed
Read Array Data
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MX28F160C3T/B
Figure 8. Automated Sector Erase Flowchart
Bus
Command Comments
Start
Operation
Write
Erase Setup Data=20H
Addr=Within Sector to Be
Write 20H
Erased
Write
Erase
Data=D0H
Write D0H and
Block Address
Confirm
Addr=Within Sector to Be
Erased
Read
Status Register
Suspend
Erase Loop
Read
Status Register DataToggle
CE or OE to Update Status
Register Data
No
Yes
0
Standby
Check SR.7
SR.7=
Suspend Erase
1=WSM Ready
0=WSM Busy
1
Repeat for subsequent block erasures.
Full status check can be done after each sector erase
or after a sequence of sector erasures.
Write FFH after the last write operation to reset device
to read array mode.
Full Status Check if Desired
Sector Erase Complete
Bus
Command
Comments
FULL STATUS CHECK PROCEDURE
Operation
Standby
Read Status Register
Data(See Above)
Check SR.3
1=VPP Low Detect
Check SR.4, 5
Both 1=Command
Sequence Error
Check SR.5
Standby
1
VPP Range Error
SR.3=
Standby
Standby
0
1=Sector Erase Error
Check SR.1
1
SR.4,5=
Command Sequence Error
1=Attempted Erase of
Locked Sector- Erase
Aborted
0
SR.1 and SR.3 MUST be cleared, if set during an erase
attempt, before further attempts are allowed by the
Write State Machine.
1
SR.5=
Sector Erase Error
0
SR.1,3,4,5 are only cleared by the Clear Status Reg-
ister Command, in cases where multiple bytes are
erased before full status is checked.
Attempted Erase of Locked
Sector - Aborted
1
SR.1=
If an error is detected, clear the status register before
attempting retry or other error recovery.
0
Sector Erase Successful
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MX28F160C3T/B
Figure 9. Erase Suspend/Resume Flowchart
Bus
Command Comments
Start
Operation
Write
Erase
Data=B0H
Addr=X
Write B0H
Write 70H
Suspend
Write
Read
Read Status Data=70H
Addr=X
Status Register DataToggle
Read
Status Register
CE or OE to Update Status
Register Data
Addr=X
0
Standby
Stanby
Check SR.7
SR.7=
1=WSM Ready
0=WSM Busy
1
Check SR.6
0
1=Erase Suspended
0=Erase Completed
SR.6=
Erase Completed
Write
Read
Read Array Data=FFH
1
Addr=X
Write FFH
Read array data from
sector other than the one
being erased.
Data=D0H
Read Array Data
Done Reading
Write
Erase
Resume
Addr=X
No
Yes
Write D0H
Write FFH
Erase Write Resumed
Read Array Data
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MX28F160C3T/B
Figure 10. Locking Operations Flowchart
Bus
Command
Comments
Operation
Write
Start
Config. Setup Data=60H
Addr=X
Write
Lock, unlock Data=01H (Sector Lock)
Write 60H
(Configuration Setup)
or Lockdown
D0H(Sector Unlock)
2FH(Sector Lockdown)
Addr=Within sector to lock
Write
01H, D0H, or 2FH
Write
Read Status Data=70H
(Optional) Register
Read
(Optional)
Stanby
Addr=X
Status Register Register
Addr=X
Check Status Register
80H=no error
Write 70H
(Read Status Register)
Lock Command
Read Status Register
Sequence Error
(Optional)
30H=Lock Command
Sequence Error
Data=90H
1,1
SR.4, SR.5=
Write
Read
(Optional) Configuration Addr=X
0,0
Read
Sector Lock Sector Lock Status Data
Write 90H
(Read Configuration)
(Optional)
Status
Addr=Second addr of
sector
Stanby
Confirm Locking Change
on DQ1, DQ0 (See Sector
Locking State Table for
valid combinations.)
Read Sector Lock Status
No
Locking Change
Confirmed ?
Yes
Locking Change
Complete
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MX28F160C3T/B
Figure 11. Protection Register Programming Flowchart
Bus
Command Comments
Start
Operation
Write
Protection
Program
Setup
Data=C0H
Write C0H
(Protection Reg. Program Setup)
Write
Read
Protection
Program
Data=Data to Program
Addr=Location to Program
Status Register DataToggle
CE or OE to Update Status
Register Data
Write Protect. Register
Address/Data
Read Status Register
Standby
Check SR.7
1=WSM Ready
No
SR.7=1 ?
Yes
0=WSM Busy
Protection Program operations can only be addressed
within the protection register address space. Addresses
outside the defined space will return an error.
Repeat for subsequent programming operations.
SR Full Status Check can be done after each program
or after a sequence of program operations.
Write FFH after the last operation to reset device to
read array mode.
Full Status
Check if Desired
Program Ccomplete
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Bus
Command
Comments
Operation
Standby
SR.1, SR.3, SR.4
0
0
1
0
1 VPP Low
1 Prot. Reg.
Prog. Error
1 Register
Locked:
1,1
VPP Range Error
SR.3, SR.4=
Standby
Stanby
1
0
Protection Register
programming Error
0,1
SR.1, SR.4=
Aborted
SR.3 MUST be cleared, if set during a program at-
tempt, before further attempts are allowed by theWrite
State Machine.
Attempted Program to
Locked Register Aborted
1,1
SR.1,3,4 are only cleared by the Clear Status Regis-
ter Command, in cases of multiple protection register
program operations before full status is checked.
If an error is detected, clear the status register before
attempting retry or other error recovery.
SR.1, SR.4=
Program Successful
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MX28F160C3T/B
7 VPP Program and Erase Voltage
MX28F160C3T/B product provide in-system writes in ad-
dition a VPP pin for 12V production programming and
complete write protection.
7.1 VPP Fast manufacturing Programming
WhenVPP is between 1.65V and 3.6V, all program and
erase current is drawn through the VCC pin. If VPP is
driven by a logic signal, VIH=1.65V. That is, VPP must
remain above 1.65V to perform in-system flash update/
modifications. When VPP is connected to a 12V power
supply, the device draws program and erase current di-
rectly from the VPP pin.
7.2 Protection Under VPP<VPPLK
VPP can off additional hardware write protection. The
VPP programming voltage can be kept low for the abso-
lute hardware protection of all sector in the flash device.
As VPP is below VPPLK, any program or erase opera-
tion will result in a error, prompting the corresponding
status register bit (SR.3) to be set.
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MX28F160C3T/B
The single cycle Query command is valid only when the
device is in the Read mode, including Erase Suspend,
Program Suspend, Standby mode, and Read ID mode;
however, it is ignored otherwise.
8. QUERY COMMAND AND COMMON FLASH
INTERFACE (CFI) MODE
MX28F160C3T/B is capable of operating in the CFI mode.
This mode all the host system to determine the manu-
facturer of the device such as operating parameters and
configuration.Two commands are required in CFI mode.
Query command of CFI mode is placed first, then the
Reset command exits CFI mode. These are described
in Table X.
The Reset command exits from the CFI mode to the
Read mode, or Erase Suspend mode, Program Suspend
or read ID mode. The command is valid only when the
device is in the CFI mode.
Table 9-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Description
Addressh
Datah
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Query-unique ASCII string "QRY"
10
11
12
13
14
15
16
17
18
19
1A
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code (none)
Address for secondary algorithm extended query table (none)
Table 9-2. CFI Mode: System Interface Data Values
Description
Addressh
Datah
0027
0036
00B4
00C6
0005
0000
000A
0004
0004
0000
0003
0000
VCC supply, minimum (2.7V)
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
VCC supply, maximum (3.6V)
VPP supply, minimum (none)
VPP supply, maximum (none)
Typical timeout for single word/byte write (2N us)
Typical timeout for maximum size buffer write (2N us)
Typical timeout for individual block erase (2N ms)
Typical timeout for full chip erase (2N ms)
Maximum timeout for single word/byte write times (2N X Typ)
Maximum timeout for maximum size buffer write times (2N X Typ)
Maximum timeout for individual block erase times (2N X Typ)
Maximum timeout for full chip erase times (not supported)
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MX28F160C3T/B
Table 9-3. CFI Mode: Device Geometry Data Values
Description
Addressh
Datah
0001
0002
0000
0000
0000
0001
0004
0000
0000
0002
Device size (2N bytes)
27
28
29
2A
2B
2C
2D
2E
2F
30
Flash device interface code (02=asynchronous x8/x16)
Maximum number of bytes in multi-byte write (not supported)
Number of erase block regions
Erase block region 1 information
[2E,2D] = # of blocks in region -1
[30, 2F] = size in multiples of 256-bytes
Table 9-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Description
Addressh
Datah
0050
0052
0049
0031
0030
06
Query-unique ASCII string "PRI"
35
36
37
38
39
3A
3B
3C
3D
Major version number, ASCII
Minor version number, ASCII
OptionalFeature&CommandSupport
bit 0 Chip Erase Supported (1=yes, 0=no)
bit 1 Suspend Erase Supported (1=yes, 0=no)
bit 2 Suspend Program Supported (1=yes, 0=no)
bit 3 Lock/Unlock Supported (1=yes, 0=no)
bit 4 Queued Erase Supported (1=yes, 0=no)
bits 5-31 revered for future use; undefined bits are "0"
Sector Lock Status
00
00
00
3F
40
03
00
Define which bits in the sector status Register section of the Query are
implemented.
bit 0 sector Lock Status Register Lock/Unlock bit (bit 0) active; (1=yes, 0=no)
bit 1 sector Lock Status Register Lock/Unlock bit (bit 1) active; (1=yes, 0=no)
Bits 2-15 reserved for future use. Undefined bits are 0.
VCC Logic Supply Optimum Program/Erase Voltage (highest performance)
bits 7-4 BCD value in volts
41
42
27
bits 3-0 BCD value in 100mV
VPP(Programming)SupplyOptimumProgram/EraseVoltage
bits 7-4 HEX value in volts
C0
bits 3-0 BCD value in 100mV
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MX28F160C3T/B
ORDER INFORMATION
PART NO.
ACCESS TIME
OPERATING
STANDBY
PACKAGE
(ns)
70
Current MAX.(mA)
Current MAX.(uA)
MX28F160C3TTC-70
MX28F160C3BTC-70
MX28F160C3TTC-90
MX28F160C3BTC-90
MX28F160C3TTC-12
MX28F160C3BTC-12
MX28F160C3TTI-70
MX28F160C3BTI-70
MX28F160C3TTI-90
MX28F160C3BTI-90
MX28F160C3TTI-12
MX28F160C3BTI-12
MX28F160C3TXAC-70
MX28F160C3BXAC-70
MX28F160C3TXAC-90
MX28F160C3BXAC-90
MX28F160C3TXAC-12
MX28F160C3BXAC-12
MX28F160C3TXAI-70
MX28F160C3BXAI-70
MX28F160C3TXAI-90
MX28F160C3BXAI-90
MX28F160C3TXAI-12
MX28F160C3BXAI-12
MX28F160C3TTC-70G
MX28F160C3BTC-70G
MX28F160C3TTC-90G
MX28F160C3BTC-90G
MX28F160C3TTC-12G
MX28F160C3BTC-12G
MX28F160C3TTI-70G
MX28F160C3BTI-70G
MX28F160C3TTI-90G
MX28F160C3BTI-90G
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
30
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
48 Pin TSOP
70
90
90
120
120
70
70
90
90
120
120
70
70
90
90
120
120
70
70
90
90
120
120
70
70
90
90
120
120
70
70
90
90
REV. 0.5, JUN. 24, 2002
P/N:PM0867
38
MX28F160C3T/B
PART NO.
ACCESS TIME
OPERATING
STANDBY
PACKAGE
(ns)
120
120
Current MAX.(mA)
Current MAX.(uA)
MX28F160C3TTI-12G
MX28F160C3BTI-12G
30
30
30
30
30
30
30
30
30
30
30
30
30
30
5
5
5
5
5
5
5
5
5
5
5
5
5
5
48 Pin TSOP
48 Pin TSOP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
48 Ball CSP
MX28F160C3TXAC-70G
MX28F160C3BXAC-70G
MX28F160C3TXAC-90G
MX28F160C3BXAC-90G
MX28F160C3TXAC-12G
MX28F160C3BXAC-12G
MX28F160C3TXAI-70G
MX28F160C3BXAI-70G
MX28F160C3TXAI-90G
MX28F160C3BXAI-90G
MX28F160C3TXAI-12G
MX28F160C3BXAI-12G
70
70
90
90
120
120
70
70
90
90
120
120
REV. 0.5, JUN. 24, 2002
P/N:PM0867
39
MX28F160C3T/B
PACKAGE INFORMATION
48-PIN TSOP
REV. 0.5, JUN. 24, 2002
P/N:PM0867
40
MX28F160C3T/B
48-Ball CSP
REV. 0.5, JUN. 24, 2002
P/N:PM0867
41
MX28F160C3T/B
REVISION HISTORY
Revision No. Description
Page
P10
P25
P25
P4
Date
JAN/16/2002
JAN/24/2002
0.1
0.2
Revise Table 2. Bus Operation; delete columns of address & VPP
Revise Program suspend latency from 5/10 to 15/20
Revise erase suspend latency from 5/20 t0 15/20
Revise CSP from 6x8 to 8x6
0.3
0.4
FEB/01/2002
FEB/07/2002
Add Order Information
P38
Add Package Information
P39,40
P17
P22
0.5
1. To modify the status registet definition table
2. To modify the testing load circuit & capacitance loading value
3. To added Pb free part no.
JUN/24/2002
P38,39
REV. 0.5, JUN. 24, 2002
P/N:PM0867
42
MX28F160C3T/B
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