MX28F2100BTC-90_技术文档

PRELIMINARY

MX28F2100B

2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY

FEATURES

• 262,144x8/131,072x16 switchable

• Fast access time: 70/90/120ns

• Low power consumption

• Status Register feature for Device status detection

• Auto Erase (chip & block) and Auto Program

– Status Registers

– 50mA maximum active current

– 100uA maximum standby current

• Programming and erasing voltage 12V ±7%

• Command register architecture

– Byte/Word Programming (50 us typical)

– Auto chip erase 5 sec typical

• 10,000 minimum erase/program cycles

• Latch-up protected to 100mA from -1 to VCC+1V

• Package type:

– 44-pin SOP

– 48-pin TSOP (Type 1)

(including preprogramming time)

– Block Erase (Any one from 5 blocks:16K-Byte x1,

8K-Byte x2, 96K-Byte x1, and 128K-Byte x1)

– Auto Erase with Erase Suspend capability

GENERAL DESCRIPTION

perform the High Reliability Erase and auto Program/

Erase algorithms.

The MX28F2100B is a 2-mega bit Flash memory or-

ganized as 256K bytes of 8 bits or 128K words of 16

bits switchable. MXIC's Flash memories offer the

most cost-effective and reliable read/write non-

volatile random access memory. The MX28F2100B

is packaged in 44-pin SOP and 48-pin TSOP(I). It is

designed to be reprogrammed and erased in-system

or in-standard EPROM programmers.

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to 100

milliamps on address and data pin from -1V to VCC

+ 1V.

The standard MX28F2100B offers access times as

fast as 70ns, allowing operation of high-speed

microprocessors without wait states. To eliminate

bus contention, the MX28F2100B has separate chip

enable (CE) and output enable (OE ) controls.

BLOCK STRUCTURE

A 1 6 ~ A 0

1 F F F F H

1 2 8 K - B Y T E B L O C K

MXIC's Flash memories augment EPROM function-

ality with in-circuit electrical erasure and

programming. The MX28F2100B uses a command

register to manage this functionality. The command

register allows for 100% TTL level control inputs and

fixed power supply levels during erase and

programming, while maintaining maximum EPROM

compatibility.

1 0 0 0 0 H

0 F F F F H

9 6 K - B Y T E B L O C K

0 4 0 0 0 H

0 3 F F F H

8

K - B Y T E B L O C K

0 3 0 0 0 H

0 2 F F F H

0 2 0 0 0 H

0 1 F F F H

MXIC Flash technology reliably stores memory con-

tents even after 10,000 erase and program cycles.

The MXIC cell is designed to optimize the erase and

programming mechanisms. In addition, the combi-

nation of advanced tunnel oxide processing and low

internal electric fields for erase and programming

1 6 K - B Y T E B L O C K

0 0 0 0 0 H

Word Mode (x16) Memory Map

*Byte Mode operation should include

A-1(LSB) for addressing

operations produces reliable cycling.

The

MX28F2100B uses a 12.0V ± 7% VPP supply to

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MX28F2100B

PIN CONFIGURATIONS

44 SOP(500 mil)

TSOP (TYPE 1) (12mm x 20mm)

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2

Q9

Q1

Q8

Q0

OE

GND

CE

A0

RP

WE

A8

A9

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

VPP

NC

A7

A6

A5

A4

A3

A2

A1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

A10

A11

A12

A13

A14

A15

A16

BYTE

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

A8

9

NC

WE

RP

VPP

NC

A7

A6

A5

A4

A3

A2

A1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A0

MX28F2100B

CE

GND

OE

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

(NORMAL TYPE)

PIN DESCRIPTION:

SYMBOL

A0~A16

Q0~Q14

Q15/A-1

CE

PIN NAME

Address Input

Data Input/Output

Q15(Word mode)/LSB addr(Byte mode)

Chip Enable Input

WE

Write Enable Input

BYTE

RP

Word/Byte Selction input

Reset/Deep Power Down

Output Enable Input

OE

VPP

Power supply for Program and Erase

Power Supply Pin (+5V)

Ground Pin

VCC

GND

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MX28F2100B

BLOCK DIAGRAM

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

CE

OE

WE

BYTE

RP

MACHINE

(WSM)

LOGIC

STATE

MX28F2100B

REGISTER

ADDRESS

LATCH

FLASH

ARRAY

SOURCE

HV

Q15/A-1

A0-A16

AND

COMMAND

DATA

BUFFER

Y-PASS GATE

DECODER

PGM

DATA

HV

SENSE

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

I/O BUFFER

Q0-Q15/A-1

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MX28F2100B

AUTOMATIC PROGRAMMING

AUTOMATIC ERASE ALGORITHM

The MX28F2100B is byte/word programmable using

the Automatic Programming algorithm. The Automatic

Programming algorithm does not require the system to

time out or verify the data programmed. The typical

room temperature chip programming time of the

MX28F2100B is less than 5 seconds.

MXIC's Automatic Erase algorithm requires the user to

only write an Erase Set-up command and an Erase

command. The device will automatically pre-program

and verify the entire array. Then the device automati-

cally times the erase pulse width, provides the erase

verify, and counts the number of sequences. A status

register provides feedback to the user as to the status

of the erase operation. It is noted that after an Erase

Set-up command, if the next command is not an Erase

command, then the state-machine will set both the

program status and Erase Status bits of the Status

Register to a "1", place the device into the read Status

Register state, and wait for another command.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase

pulses according to MXIC's High Reliability Chip Erase

algorithm. Typical erasure at room temperature is

accomplished in less than five seconds. The device

may also be erased using the Automatic Erase

algorithm. The Automatic Erase algorithm automati-

cally programs the entire array prior to electrical erase.

The timing and verification of electrical erase are

controlled internally.

Commands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as inputs to an internal state-machine

which controls the erase and programming circuitry.

During write cycles, the command register internally

latches address and data needed for the programming

and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data is

latched on the rising edge of WE .

AUTOMATIC BLOCK ERASE

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX28F2100B electri-

cally erases all bits within a sector or chip simultaneously

using Fowler-Nordheim tunneling. The array is pro-

grammed one byte/word at a time using the EPROM

programming mechanism of hot electron injection.

The MX28F2100B is block(s) erasable using MXIC's

Auto Block Erase algorithm. Block erase modes allow

one of 5 blocks of the array to be erased in one erase

cycle. The Automatic Block Erase algorithm automati-

cally programs the specified block(s) prior to electrical

erase. The timing and verification of electrical erase

are controlled internal to the device.

Duringaprogramcycle, thestate-machinewillcontrolthe

program sequences and command register will not re-

spond to any command set. During a Sector/Chip Erase

cycle, the command register will respond to Erase Sus-

pend command. After Erase Suspend completed, the

device stays at status register Read state. After the state

machinehascompleteditstask, itwillallowthecommand

register to respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires

the user to only write a program set-up command and

a program command (program data and address). The

device automatically times the programming pulse

width, provides the program verify, and counts the

number of sequences. A status register scheme pro-

vides feedback to the user as to the status of the

programming operation.

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MX28F2100B

TABLE 1. SOFTWARE COMMAND DEFINITIONS

COMMAND

BUS

FIRST BUS CYCLE

SECOND BUS CYCLE

CYCLE

Mode

Address

Data

Mode Address

Data

X8

X16

X8

X16

Read Memory Array

Setup Auto program/

Auto Program

1

2

Write

X

FFH

10H

XXFFH

XX10H

---

Write

Program Program Program

or 40H or XX40H

Address

X

Data

20H

60H

Data

Setup Erase/Erase(Chip)

Setup Erase/Erase(Block)

2

Write

X

20H

60H

XX20H

XX60H

Write

XX20H

XX60H

Block

Address

X

Setup Auto Erase/

Auto Erase(Chip)

Setup Auto Erase/

Auto Erase(Block)

Erase Verify

2

Write

X

30H

20H

A0H

XX30H

XX20H

XXA0H

Write

Read

30H

D0H

XX30H

XXD0H

Block

Address

X

Verify

Data

DDI

---

Verify

Data

DDI

---

Address

Read device identifier code

Erase Suspend

2

1

2

1

Write

X

90H

B0H

D0H

70H

50H

XX90H

XXB0H

XXD0H

XX70H

XX50H

Read

---

ADI

---

X

Erase Resume

---

Read Status Register

Clear Status Register

Read

---

SRD

---

SRD

---

Note:

1. Write and Read mode are defined in mode selection table.

2. ADI = Address of Device identifier; A0 = 0 for manufacture code, A0 = 1 for device code.

DDI = Data of Device identifier : C2H for manufacture code, 2BH for device code(Byte = VIL) ; 00C2H for

manufacture code, 002BH for device code(Byte =VIH)

X = X can be VIL or VIH

SRD = Status Register Data

COMMAND DEFINITIONS

Placing high voltage on the VPP pin enables read/write

operations. Device operations are selected by writing

specific data patterns into the command register. Ta-

ble 1 defines these MX28F2100B register commands.

Table 2 defines the bus operations of MX28F2100B.

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MX28F2100B

TABLE 2. MX28F2100B BUS OPERATION

Pins

A0

A9

CE OE WE VPP

Data I/O

D8~D14

Hi-Z

Mode

D0~D7

A9 VIL VIL VIH VPPL Data Out

D15/A-1

A-1

Read

A0

X

Output Disable

X

VIL VIH VIH VPPL

VIH VPPL

Hi-Z

X

Byte

Mode

BYTE

= L

Read-Only Standby

Read Silicon ID(Mfr)(2)

Read Silicon ID(Device)(2) VIH VID(3) VIL VIL VIH VPPL Data=2BH

X

Hi-Z

X

VIL VID(3) VIL VIL VIH VPPL Data=C2H

Hi-Z

VIL

Hi-Z

VIL

Read

Read/Write Output Disable

Standby(5)

A0

X

A9 VIL VIL VIH VPPH Data Out(4)

Hi-Z

A-1

X

VIL VIH VIH VPPH

VIH VPPH

Hi-Z

X

Hi-Z

X

Write

A0

X

A9 VIL VIH VIL VPPH Data In(6)

A9 VIL VIL VIH VPPL Data Out

X

A-1

Read

Data Out

Hi-Z

Data Out

Hi-Z

0B

Read-Only Output Disable

Standby

X

VIL VIH VIH VPPL

VIH VPPL

Hi-Z

Word

Mode

BYTE

= H

X

Hi-Z

Read Silicon ID(Mfr)(2)

VIL VID(3) VIL VIL VIH VPPL Data=C2H Data=00H(8)

Read Silicon ID(Device)(2) VIH VID(3) VIL VIL VIH VPPL Data=2BH Data=00H(8)

0B

Read

Read/Write Output Disable

Standby(5)

A0

X

A9 VIL VIL VIH VPPH Data Out(4) Data Out

Data Out

Hi-Z

X

VIL VIH VIH VPPH

VIH VPPH

Hi-Z

X

Write

A0

A9 VIL VIH VIL VPPH Data In(6) Data In(6) Data In(6)

NOTES:

1. VPPL may be grounded, a no-connect with a resistor tied

to ground, or < VCC + 2.0V. VPPH is the programming

voltage specified for the device. When VPP = VPPL,

memory contents can be read but not written or erased.

2. Manufacturer and device codes may also be accessed

via a command register write sequence. Refer to Table

1. All other addresses are low.

3. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.

4. Read operations with VPP = VPPH may access array

data or Silicon ID codes.

5. With VPP at high voltage, the standby current equals ICC

+ IPP (standby).

6. Refer to Table 1 for valid Data-In during a write operation.

7. X can be VIL or VIH.

8. Includes D15

TABLE 3. SILICON ID CODE

Pins A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Code(Hex)

Code

BYTE

= L

Manufacture code VIL VIL --- --- ---

Device code VIH VIL --- --- ---

Manufacture code VIL

Device code VIH

---

0

--- --- ---

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

C2H

2BH

BYTE

= H

0

00C2H

002BH

0

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MX28F2100B

READ COMMAND

ERASE-VERIFY COMMAND

After each erase operation, all bytes must be verified.

The Erase Verify operation is initiated by writing

XXA0H into the command register. The address for

the byte to be verified must be supplied as it is latched

on the falling edge of the WE pulse.

While V

is high, for erasure and programming,

PP

memory contents can also be accessed via the Read

command. The read operation is initiated by writing

XXFFH into the command register. Microprocessor

read cycles retrieve array data. The device remains

enabled for reads until the command register contents

are altered.

The MX28F2100B applies an internally generated

margin voltage to the addressed byte. Reading

FFFFH from the addressed byte indicates that all bits

in the byte are erased.

RESET COMMAND

The Erase-Verify command must be written to the

command register prior to each byte verification to

latch its address. The process continues for each byte

in the array until a byte does not return FFFFH data, or

the last address is accessed.

A Reset command is provided as a means to safely

abort the erase- or program-command sequences.

Following Set-up command with two consecutive

writes of XXFFH for ERS (or one write of XXFFH for

PGM) will safely abort the operation. Memory contents

will not be altered. A valid command must then be

written to place the device in the desired state.

In the case where the data read is not FFFFH, another

erase operation needs to be performed. (Refer to Set-

up Erase/Erase). Verification then resumes from the

address of the last-verified byte. Once all bytes in the

array have been verified, the erase step is complete.

The device can be programmed. At this point, the

verify operation is terminated by writing a valid

command (e.g. Program Set-up) to the command

register. The High Reliability Erase algorithm

illustrates how commands and bus operations are

combined to perform electrical erasure of the

MX28F2100B.

SILICON-ID-READ COMMAND

Flash-memories are intended for use in applications

where the local CPU alters memory contents. As such,

manufacturer- and device-codes must be accessible

while the device resides in the target system. PROM

programmers typically access signature codes by rais-

ing A9 to a high voltage. However, multiplexing high

voltage onto address lines is not a desired system-

design practice.

The MX28F2100B contains a Silicon-ID-Read

operation to supplement traditional PROM-

programming methodology. The operation is initiated

by writing XX90H into the command register.

Following the command write, a read cycle with

A0=VIL retrieves the manufacturer code of

C2H(BYTE=VIL, 00C2H(BYTE=VIH). A read cycle

with A0=VIH returns the device code of 2BH(BYTE =

VIL), 002BH(BYTE = VIH).

SET-UP AUTOMATIC CHIP ERASE/ERASE

COMMANDS

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to excuting the

Automatic Set-up Erase command and Automatic Chip

Erase command. Upon executing the Automatic Chip

Erase command, the device automatically will

program and verify the entire memory for an all-zero

data pattern. When the device is automatically verified

to contain an all-zero pattern, a self-timed chip erase

and verify begin. The erase and verify operations are

completed by the feed back of the status register. The

system is not required to provide any control or timing

during these operations.

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MX28F2100B

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array(no erase verify command is required).

The margin voltages are internally generated in the

same manner as when the standard Erase Verify

command is used.

When using the Automatic Block Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verify command is required). The margin

voltages are internally generated in the same manner

as when the standard Erase Verify command is used.

The Automatic Set-up Block Erase command is a com-

mand only operation that stages the device for auto-

matic electrical erasure of selected blocks in the array.

Automatic Set-up Block Erase is performed by writing

XX20H to the command register. To enter Automatic

Block Erase, the user must write the command D0H to

the command register. Block addresses selected are

loaded into internal register on the second falling edge

of WE. Each successive block load cycle started by the

falling edge of WE must begin within 30us from the

rising edge of the preceding WE. Otherwise, the

loading period ends and internal auto block erase cycle

starts.

If the Erase operation was unsuccessful, bit 5 of the

Status Register will be set to a "1", indicating an Erase

Failure. If Vpp was not within acceptable limits after

the Erase command is issued, the state machine will

not execute an erase sequence; in stead, bit 5 of the

Status Register is set to a "1" to indicate an Erase

Failure, and bit 3 is set to a "1" to indentify that Vpp

supply voltage was not within acceptable limits.

The Automatic Set-up Erase command is a command

only operation that stages the device for automatic

electrical erasure of all bytes in the array. Automatic

set-up erase is performed by writing XX30H to the

command register.

ERASE SUSPEND

To commence Automatic Chip Erase, the command

XX30H must be written again to the command register.

This command only has meaning while the state ma-

chine is executing Automatic Chip/Block Erase opera-

tion, and therefore will only be responded to during

Automatic Chip/Block Erase operation. It is noted that

Erase Suspend is meaningful for block erase only after

block addresses load are finished (100 us after the last

address is loaded). After this command has been ex-

ecuted, the command register will initiate erase sus-

pend mode. The state machine will set DQ7, DQ6 as 1,

1, after suspend is ready. At this time, state machine

only allows the command register to respond to the

Read Memory Array, Erase Resume and Read Status

Register.

SET-UP AUTOMATIC BLOCK ERASE/ERASE

COMMANDS

The Automatic Block Erase does not require the device

to be entirely pre-programmed prior to executing the

Automatic Set-up Block Erase command and

Automatic Block Erase command. Upon executing the

Automatic Block Erase command, the device

automatically will program and verify the block(s)

memory for an all-zero data pattern. The system is not

required to provide any controls or timing during these

operations.

When the block(s) is automatically verified to contain

an all-zero pattern, a self-timed block erase and verify

begin. The system is not required to provide any

control or timing during these operations.

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MX28F2100B

ERASE RESUME

The Status Register bits are output on DQ[0:7],

whether the device is in the byte-wide (x8) or word-

wide (x16) mode. In the word-wide mode the upper

byte, DQ[8:15], is set to 00H during a Read Status

command. In the byte-wide mode, DQ[8:14] are tri-

stated and DQ15/A-1 retains the low order address

function.

This command will cause the command register to clear

the suspend state and set DQ6, DQ7, back to 0, 0, but

only if an Erase Suspend command was previously

issued. EraseResumewillnothaveanyeffectinallother

conditions.

The contents of the Status Register are latched on the

falling edge of OE or CE, whichever occurs last in the

read cycle. This prevents possible bus errors which

might occur if the contents of the Status Register

change while reading the Status Register. CE or OE

must be toggled with each subsequent status read, or

the completion of a Program or Erase operation will not

be evident from the Status Register.

SET-UP AUTOMATIC PROGRAM/PROGRAM

COMMANDS

The Automatic Set-up Program is a command only

operation that stages the device for automatic pro-

gramming. Automatic Set-up Program is performed by

writing XX10H/XX40H to the command register.

Program command is the command for byte-program

or word-program.

When the state machine is active, this register will

indicate the status of the state machine, and will also

hold the bits indicating whether or not the state

machine was successful in performing the desired

operation.

Once the Automatic Set-up Program operation is per-

formed, the next WE pulse causes a transition to an

active programming operation. Addresses are latched

on the falling edge, and data are internally latched on

the rising edge of the WE pulse. The rising edge of WE

also begins the programming operation. The system is

not required to provide further controls or timings. The

device will automatically provide an adequate

internally generated program pulse and verify margin.

CLEARING THE STATUS REGISTER

The state machine sets status bits "3" through "7" to

"1", and clears bits "6" and "7" to "0", but cannot clear

status bits "3" through "5" to "0". Bits 3 through 5 can

only be cleared by the controlling CPU through the use

of the Clear Status Register command. These bits can

indicate various error conditions. By allowing the

system software to control the resetting of these bits,

several operations may be performed (such as

cumulatively programming several bytes or erasing

multiple blocks in sequence). The Status Register may

then be read to determine if an error occurred during

that programming or erasure series. This adds

flexibility to the way the device may be programmed or

erased. Once an error occured, the command

Interface Only responds to clear Status Register, Read

Status Register and Read Array. To clear the Status

Register, the Clear Status Register command is written

to the command interface. Then, any other command

may be issued to the command interface. Note, again,

that before read cycle can be initiated, a Read Array

command must be written to the command interface to

specify whether the read data is to come from the

Memory Array, Status Register, or Sili-con -ID.

If the program opetation was unsuccessful, bit 4 of the

Status Register will be set to a "1", indicating a

program failure. If Vpp was not within acceptable limits

after the program command is issued, the state

machine will not execute a program sequence; in

stead, bit 4 of the Status Register is set to a "1" to

indicate a Program Failure, and bit 3 is set to a "1" to

identify that Vpp supply voltage was not within

acceptable limits.

STATUS REGISTER

The device contains a Status Register which may be

read to determine when a Program or Erase operation

is complete, and whether that operation completed

successfully. The Status Register may be read at any

time by writing the Read Status command to the

command interface. After writing this command, all

subsequent Read operations output data from the

Status Register until another command is written to the

command interface. A Read Array command must be

written to the command interface to return to the read

array mode.

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MX28F2100B

Status Register Bit Definition

WSMS

7

ESS

6

ES

5

PS

4

VPPS

3

SR.7 = WRITE STATE MACHINE STATUS(WSMS)

NOTE :

1 = Ready

0 = Busy

State machine bit must first be checked to determine

Byte/Word program or Block Erase completion, before

theProgramorEraseStatusbitsarecheckedforsuccess.

When Erase Suspend is issued, state machine halts

execution and sets both WSMS and ESS bits to "1," ESS

bit remains set to "1" until an Erase Resume command is

issued.

SR.6 = ERASE-SUSPEND STATUS (ESS)

1 = Erase Suspended

0 = Erase in Progress/Completed

SR.5 = ERASE STATUS

1 = Error in Erase

When this bit set to "1," state machine has applied the

maximumnumberoferasepulsestothe deviceandisstill

unable to successfully verify erasure.

0 = Successful Erasure

SR.4 = PROGRAM STATUS

1 = Error in Byte/Word Program

0 = Successful Byte/Word Program

When this bit is set to "1," state machine has attempted

but failed to program a byte or word.

SR.3 = Vpp STATUS

1 = Vpp Low Detect, Operation Abort

0 = Vpp OK

The Vpp status bit, unlike an A/D converter, does not

provide continuous indication of Vpp level. The state

machine interrogates Vpp level only after the Byte Write

or Erase command sequences have been entered, and

informs the system if Vpp has not been switched on.

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REV. 1.5, MAR. 24, 1998

10

MX28F2100B

DATA PROTECTION

POWER SUPPLY DECOUPLING

The MX28F2100B is designed to offer protection against

accidental erasure or programming caused by spurious

systemlevelsignalsthatmayexistduringpowertransition.

Duringpowerupthedeviceautomaticallyresetsthestate

machine in the Read mode. In addition, with its control

register architecture, alteration of the memory contents

only occurs after successful completion of specific

command sequences. The device also incorporates

several features to prevent inadvertent write cycles

resulting from VCC power-up and power-down transition

or system noise.

In order to reduced power switching effect, each device

should havea0.1uFceramiccapacitorconnectedbetween

its VCC and GND, and between its VPP and GND.

VPP TRACE ON PRINTED CIRCUIT BOARD

Programming flash memories, while they reside in the

target system, requires that the printed circuit board

designer pay attention to the Vpp power supply trace.

The Vpp pin supplies the memory cell current for

programming. Use similar trace widths and layout

considerations given to the Vcc power bus. Adequate

Vpp supply traces and decoupling will decrease Vpp

voltage spikes and overshoots.

LOW VPP WRITE INHIBIT

To avoid initiation of a write cycle during V power-up

PP

and power-down a write cycle is locked out for V less

PP

DEEP POWER DOWN MODE

than V

(typically 9V). If V < V

, the command

PPLK

PP

PPLK

register is disabled and all internal program/erase circuits

are disabled. Subsequent writes will be ignored until the

Thismodeisenabledby RPpin. DuringReadmodes,RP

going low deselects the memory and place the output

drivers in a high-Z state.

V

levelisgreaterthanV

. Itistheuser'sresponsibility

PP

PPLK

to ensure that the control pins are logically correct to

prevent unintentional write when V is above V

.

PPLK

In erase or program modes, RP low will abort erase or

program operations, but the memory contents are no

longer valid as the data has been corrupted by RP

function. RP transition to VIL, or turning power off to the

device will clear up Status Register and automatically

defaults to the read array mode.

PP

WRITE PULSE "GLITCH" PROTECTION

Noisepulsesoflessthan5ns(typical)onCEorWEwillnot

initiate a write cycle.

POWER-UP SEQUENCE

LOGICAL INHIBIT

The MX28F2100B powers up in the Read only mode. In

addition, the memory contents may only be altered after

successfulcompletionofatwo-stepcommandsequence.

Vpp and Vcc power up sequence is not required.

Writing is inhibited by holding any one of OE = VIL, CE =

VIHorWE=VIH. ToinitiateawritecycleCEandWEmust

be a logical zero while OE is a logical one.

P/N: PM0382

REV. 1.5, MAR. 24, 1998

11

MX28F2100B

NOTICE:

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under ABSOLUTE MAXI-

MUM RATINGS may cause permanent damage to the de-

vice. This is a stress rating only and functional operational

sections of this specification is not implied. Exposure to ab-

solute maximum rating conditions for extended period may

affect reliability.

RATING

VALUE

Ambient Operating Temperature 0^oC to 70^oC

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9 & VPP & RP

-65^oC to 125^oC

-0.5V to 7.0V

-0.5V to 13.5V

NOTICE:

Specifications contained within the following tables are sub-

ject to change.

SWITCHING VCC VOLTAGES

VCC SUPPLY SWITCHING TIMING

SYMBOL

PARAMETER

MIN.

MAX.

UNIT

T5VPH

VCC at 4.5V (minimum) to RP High

3

ms

NOTICE:

The T5VPH time must be strictly followed to guarantee all


型号：	MX28F2100BTC-90
厂家：	MACRONIX INTERNATIONAL
描述：	2M-BIT [256K x 8/128K x 16] CMOS FLASH MEMORY 2M- BIT [ 256K ×8 / 128K ×16 ]的CMOS FLASH MEMORY 闪存存储内存集成电路光电二极管
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中文：	中文翻译
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