MX29F001TTC-12 [Macronix]
1M-BIT [128K x 8] CMOS FLASH MEMORY; 1M - BIT [ 128K ×8 ] CMOS FLASH MEMORY
| 型号： | MX29F001TTC-12 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 1M-BIT [128K x 8] CMOS FLASH MEMORY |
| 文件： | 总43页 (文件大小：876K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX29F001T/B
1M-BIT [128K x 8] CMOS FLASH MEMORY
FEATURES
• Status Reply
• 5.0V ±10% for read, erase and write operation
• 131072x8 only organization
• Fast access time: 55/70/90/120ns
• Low power consumption
– 30mA maximum active current(5MHz)
– 1uA typical standby current
• Command register architecture
– Data polling & Toggle bit for detection of program
and erase cycle completion.
• Chip protect/unprotect for 5V only system or 5V/12V
system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
– T = Top Boot Sector
– Byte Programming (7us typical)
– Sector Erase (8K-Byte x1,4K-Byte x 2, 8K Bytex2,
32K-Bytex1, and 64K-Byte x1)
– B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
• Auto Erase (chip & sector) and Auto Program
– Automatically erase any combination of sectors
with Erase Suspend capability.
– 32-pin PLCC
– 32-pin TSOP
– 32-pin PDIP
– Automatically programs and verifies data at speci
fied address
• Boot Code Sector Architecture
– T=Top Boot Sector
– B=Bottom Boot Sector
• 20 years data retention
• Erase Suspend/Erase Resume
– Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation.
GENERAL DESCRIPTION
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's Flash
memories offer the most cost-effective and reliable
read/write non-volatile random access memory. The
MX29F001T/B is packaged in 32-pin PLCC, TSOP,
PDIP. It is designed to be reprogrammed and
erased in-system or in-standard EPROM program-
mers.
operations produces reliable cycling.
The
MX29F001T/B uses a 5.0V ± 10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The standard MX29F001T/B offers access time as
fast as 55ns, allowing operation of high-speed micro-
processors without wait states. To eliminate bus
contention, the MX29F001T/B has separate chip
enable (CE) and output enable (OE) controls.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs and
fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
REV. 2.1, JUN. 14, 2001
P/N: PM0515
1
MX29F001T/B
PIN CONFIGURATIONS
32 PDIP
PIN DESCRIPTION:
32PLCC
VCC
WE
NC
A14
A13
A8
NC
A16
A15
A12
A7
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
SYMBOL
A0~A16
Q0~Q7
CE
PIN NAME
2
3
4
5
1
32
Address Input
30
29
A7
A6
A5
A4
A3
A2
A1
A0
Q0
A14
A13
A8
4
5
Data Input/Output
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply Pin (+5V)
Ground Pin
A6
6
A9
A5
7
A9
A11
OE
A10
CE
Q7
A4
8
A3
WE
9
9
MX29F001T/B
25
A11
OE
A10
CE
Q7
A2
10
11
12
13
14
15
16
OE
A1
A0
VCC
Q6
Q0
Q5
Q1
13
14
21
GND
Q4
Q2
17
20
Q3
GND
TSOP (TYPE 1)
SECTOR STRUCTURE
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE
Q7
Q6
Q5
Q4
Q3
GND
Q2
Q1
Q0
A0
A8
3
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
4
A 1 6 ~ A 0
1 F F F F H
5
6
7
8
4
K - B Y T E
K - B Y T E
8
MX29F001T/B
1 D F F F H
9
10
11
12
13
14
15
16
1 C F F F H
1 B F F F H
4
8
8
K - B Y T E
K - B Y T E
K - B Y T E
A6
A1
A5
A2
1 9 F F F H
1 7 F F F H
A4
A3
3 2 K - B Y T E
6 4 K - B Y T E
(NORMAL TYPE)
0 F F F F H
0 0 0 0 0 H
MX29F001T Sector Architecture
A 1 6 ~ A 0
1 F F F F H
0 F F F F H
6 4 K - B Y T E
3 2 K - B Y T E
0 7 F F F H
0 5 F F F H
8
8
4
K - B Y T E
K - B Y T E
K - B Y T E
0 3 F F F H
0 2 F F F H
4
8
K - B Y T E
K - B Y T E
0 1 F F F H
0 0 0 0 0 H
MX29F001B Sector Architecture
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MX29F001T/B
BLOCK DIAGRAM
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
CE
OE
WE
MACHINE
(WSM)
LOGIC
STATE
MX29F001T/B
FLASH
ADDRESS
LATCH
REGISTER
ARRAY
ARRAY
A0-A16
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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MX29F001T/B
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F001T/B is byte programmable using the
Automatic Programming algorithm. The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical
chip programming time of the MX29F001T/B at room
temperature is less than 3.5 seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will
automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, provides the erase verification, and counts the
number of sequences. A status bit toggling between
consecutive read cycles provides feedback to the user
as to the status of the programming operation.
AUTOMATIC CHIP ERASE
Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches addresses and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .
The entire chip is bulk erased using 10 ms erase
pulses according to MXIC's Automatic Chip Erase
algorithm. Typical erasure at room temperature is
accomplished in less than 3 second. The Automatic
Erase algorithm automatically programs the entire
array prior to electrical erase. The timing and
verification of electrical erase are internally controlled
within the device.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX29F001T/B electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed by using the
EPROM programming mechanism of hot electron
injection.
AUTOMATIC SECTOR ERASE
The MX29F001T/B is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes allow
sectors of the array to be erased in one erase cycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter-
nally con trolled by the device.
Duringaprogramcycle, thestate-machinewillcontrolthe
program sequences and command register will not re-
spond to any command set. During a Sector Erase cycle,
thecommandregisterwillonlyrespondtoEraseSuspend
command. After Erase Suspend is completed, the device
stays in read mode. After the state machine has com-
pleted its task, it will allow the command register to
respond to its full command set.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires
the user to only write program set-up commands
(include 2 unlock write cycle and A0H) and a program
command (program data and address). The device
automatically times the programming pulse width,
provides the program verification, and counts the
number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive
read cycles, provides feedback to the user as to the
status of the programming operation.
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MX29F001T/B
TABLE1. SOFTWARE COMMAND DEFINITIONS
First Bus
Cycle
Second Bus
Cycle
Third Bus
Cycle
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Command
Bus
Cycle Addr Data
XXXH F0H
RD RD
Addr Data
Addr Data
Addr Data
Addr Data Addr Data
Reset
1
Read
1
Read Silicon ID
Chip Protect Verify
4
4
555H AAH 2AAH 55H
555H AAH 2AAH 55H
555H 90H
555H 90H
ADI DDI
(SA) 00H
X02H 01H
Porgram
4
6
6
1
1
6
555H AAH 2AAH 55H
555H AAH 2AAH 55H
555H AAH 2AAH 55H
XXXH B0H
555H A0H
555H 80H
555H 80H
PA
555H AAH 2AAH 55H 555H 10H
555H AAH 2AAH 55H SA 30H
PD
Chip Erase
Sector Erase
Sector Erase Suspend
Sector Erase Resume
Unlock for chip
protect/unprotect
Note:
XXXH 30H
555H AAH 2AAH 55H
555H 80H
555H AAH
2AAH 55H 555H 20H
1. ADI = Address of Device identifier;A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to
Table 3)
DDI = Data of Device identifier : C2H for manufacture code, 18H/19H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A16 in either state.
4.For chip protect verify operation : If read out data is 01H, it means the chip has been protected. If read out data is
00H, it means the chip is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register com-
mand sequences. Note that the Erase Suspend (B0H)
and Erase Resume (30H) commands are valid only
while the Sector Erase operation is in progress. Either
of the two reset command sequences will reset the
device(when applicable).
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MX29F001T/B
TABLE 2. MX29F001T/B BUS OPERATION
Pins
CE
OE
WE
H
A0
L
A1
L
A6
X
A9
Q0 ~ Q7
C2H
Mode
Read Silicon ID
Manfacturer Code(1)
Read Silicon ID
Device Code(1)
Read
L
L
VID(2)
L
L
H
H
L
X
VID(2)
18H/19H
L
H
L
L
L
L
X
H
X
H
L
A0
X
A1
X
A6
X
A9
X
DOUT
HIGH Z
HIGH Z
DIN(3)
X
Standby
Output Disable
Write
H
X
X
X
X
H
A0
X
A1
X
A6
L
A9
Chip Protect with 12V
system(6)
VID(2)
L
VID(2)
Chip Unprotect with 12V
system(6)
L
L
L
L
L
X
VID(2)
L
H
L
X
X
X
X
X
X
X
H
X
X
H
X
H
X
L
VID(2)
VID(2)
H
X
Code(5)
X
Verify Chip Protect
with 12V system
L
H
H
L
Chip Protect without 12V
system (6)
Chip Unprotect without 12V
system (6)
L
H
X
X
H
X
Verify Chip Protect/Unprotect
without 12V system (7)
Reset
H
X
H
Code(5)
HIGH Z
X
X
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.
Code=01H means protected.
6. Refer to chip protect/unprotect algorithm and waveform.
Must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12V system" command.
7. The "verify chip protect/unprotect without 12V sysytem" is only following "Chip protect/unprotect without 12V system"
command.
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REV. 2.1, JUN. 14, 2001
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MX29F001T/B
READ/RESET COMMAND
SET-UP AUTOMATIC CHIP ERASE COM-
MANDS
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array
data. The device remains enabled for reads until the
command register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing
the "set-up" command 80H. Two more "unlock" write
cycles are then followed by the chip erase command
10H.
If program-fail or erase-fail happen, the write of F0H
will reset the device to abort the operation. A valid
command must then be written to place the device in
the desired state.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and
verification begin. The erase and verification
operations are completed when the data on Q7 is "1"
at which time the device returns to the Read mode.
The system does not require to provide any control or
timing during these operations.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access siganature codes by
raising A9 to a high voltage. However, multiplexing
high voltage onto address lines is not generally desired
system design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array(no erase verify command is required).
The MX29F001T/B contains a Silicon-ID-Read opera-
tion to supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Following the command write, a read cycle
with A1=VIL,A0=VIL retrieves the manufacturer code
of C2H. A read cycle with A1=VIL, A0=VIH returns the
device code of 18H for MX29F001T,19H for
MX29F001B.
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating an erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and
terminates when the data on Q7 is "1" and the data on
Q6 stops toggling for two consecutive read cycles, at
which time the device returns to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code
Device code
VIL VIL
VIH VIL
1
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
C2H
18H
for MX29F001T
Device code
VIH VIL
0
0
0
1
1
0
0
1
19H
for MX29F001B
Chip Protection Verification
X
X
VIH
VIH
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
01H (Protected)
00H (Unprotected)
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MX29F001T/B
SECTOR ERASE COMMANDS
ERASE SUSPEND
The Automatic Sector Erase does not require the
device to be entirely pre-programmed prior to
executing the Automatic Set-up Sector Erase
command and Automatic Sector Erase command.
Upon executing the Automatic Sector Erase command,
the device will automatically program and verify the
sector(s) memory for an all-zero data pattern. The
system does not require to provide any control or
timing during these operations.
This command only has meaning while the state ma-
chine is executing Automatic Sector Erase operation,
and therefore will only be responded during Automatic
Sector Erase operation. Writing the Erase Suspend
command during the Sector Erase time-out immediately
terminates the time-out immediately terminates the
time-out period and suspends the erase operation.
After this command has been executed, the command
register will initiate erase suspend mode. The state
machine will return to read mode automatically after
suspend is ready. At this time, state machine only
allows the command register to respond to the Read
Memory Array, Erase Resume and Program com-
mands.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and
verification begin. The erase and verification
operations are complete when the data on Q7 is "1"
and the data on Q6 stops toggling for two consecutive
read cycles, at which time the device returns to the
Read mode. The system does not require to provide
any control or timing during these operations.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended sectors.
WhenusingtheAutomaticSectorErasealgorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required). Sector
erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
set-up command 80H. Two more "unlock" write cycles
are then followed by the sector erase command 30H.
The sector address is latched on the falling edge of WE,
while the command(data) is latched on the rising edge
of WE. Sector addresses selected are loaded into
internal register on the sixth falling edge of WE. Each
successive sector load cycle started by the falling edge
of WE must begin within 30us from the rising edge of
the preceding WE. Otherwise, the loading period ends
and internal auto sector erase cycle starts. (Monitor Q3
to determine if the sector erase timer window is still
open, see section Q3, Sector Erase Timer.) Any
command other than Sector Erase (30H) or Erase
Suspend (B0H) during the time-out period resets the
derice to read mode.
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MX29F001T/B
Table 4. Write Operation Status
Status
Q7
Q7 Toggle
Toggle
Q6
Q5
0
Q3
N/A
1
Byte Program in Auto Program Algorithm
In Progress Auto Erase Algorithm
Erase Suspended Mode
0
0
Erase Suspend Read
Data Data Data Data
Erase Suspend Program
(Non-Erase Suspended Sector)
Q7 Toggle
(Note1)
0
N/A
Byte Program in Auto Program Algorithm
Q7 Toggle
1
1
1
N/A
1
Exceeded Erase in Auto Erase Algorithm
Time Limits Erase Suspended Mode
0
Toggle
Erase Suspend Program
Q7 Toggle
N/A
(Non-Erase Suspended Sector)
Note:
1. Performing successive read operations from any address will cause Q6 to toggle.
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MX29F001T/B
ERASE RESUME
read. The toggle bit is valid after the rising edge of the
sixth WE pulse of the six write pulse sequences for chip/
sector erase.
This command will cause the command register to clear
the suspend state and return back to Sector Erase mode
but only if an Erase Suspend command was previously
issued. EraseResumewillnothaveanyeffectinallother
conditions.Another Erase Suspend command can be
written after the chip has resumed erasing.
TheToggleBitfeatureisactiveduringAutomaticProgram/
Erase algorithms or sector erase time-out.(see section
Q3 Sector Erase Timer)
DATA POLLING-Q7
SET-UP AUTOMATIC PROGRAM COMMANDS
TheMX29F001T/BalsofeaturesDataPollingasamethod
to indicate to the host system that the Automatic Program
or Erase algorithms are either in progress or completed.
To initiate Automatic Program mode, A three-cycle
command sequence is required. There are two "un-
lock" write cycles. These are followed by writing the
Automatic Program command A0H.
WhiletheAutomaticProgrammingalgorithmisinoperation,
anattempttoreadthedevicewillproducethecomplement
data of the data last written to Q7. Upon completion of the
Automatic Program Algorithm an attempt to read the
device will produce the true data last written to Q7. The
Data Polling feature is valid after the rising edge of the
fourth WE pulse of the four write pulse sequences for
automatic program.
Once the Automatic Program command is initiated,
the next WE pulse causes a transition to an active
programming operation. Addresses are latched on the
falling edge, and data are internally latched on the
rising edge of the WE pulse. The rising edge of WE
also begins the programming operation. The system
does not require to provide further controls or timings.
The device will automatically provide an adequate
internally generated program pulse and verify margin.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completionoftheeraseoperation,thedataonQ7willread
"1". The Data Polling feature is valid after the rising edge
of the sixth WE pulse of six write pulse sequences for
automatic chip/sector erase.
If the program opetation was unsuccessful, the data
on Q5 is "1"(see Table 4), indicating the program
operation exceed internal timing limit. The automatic
programming operation is completed when the data
read on Q6 stops toggling for two consecutive read
cycles and the data on Q7 and Q6 are equivalent to
data written to these two bits, at which time the device
returns to the Read mode(no program verify command
is required).
The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)
WRITE OPERATION STATUS
TOGGLE BIT-Q6
The MX29F001T/B features a "Toggle Bit" as a method
to indicate to the host system that the Auto Program/
Erase algorithms are either in progress or complete.
While the Automatic Program or Erase algorithm is in
progress, successive attempts to read data from the
device will result in Q6 toggling between one and zero.
Once the Automatic Program or Erase algorithm is
completed, Q6 will stop toggling and valid data will be
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MX29F001T/B
Q5
Q3
Exceeded Timing Limits
Sector Erase Timer
Q5willindicateiftheprogramorerasetimehasexceeded
the specified limits(internal pulse count). Under these
conditions Q5 will produce a "1". This time-out condition
indicates that the program or erase cycle was not
successfully completed. Data Polling and Toggle Bit are
the only operating functions of the device under this
condition.
After the completion of the initial sector erase command
sequence th sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
used to determine if the sector erase timer window is still
open. If Q3 is high ("1") the internally controlled erase
cyclehasbegun;attemptstowritesubsequentcommands
to the device will be ignored until the erase operation is
completed as indicated by Data Polling or Toggle Bit. If
Q3 is low ("0"), the device will accept additional sector
erase commands. To insure the command has been
accepted, thesystemsoftwareshouldcheckthestatusof
Q3 prior to and following each subsequent sector erase
command. If Q3 were high on the second status check,
the command may not have been accepted.
If this time-out condition occurs during sector erase
operation, it is specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. Thedevicemustberesettouseothersectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence.
This allows the system to continue to use the other active
sectors in the device.
If this time-out condition occures during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
DATA PROTECTION
If this time-out condition occurs during the byte
programming operation, it specifies that the entire sector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
reused).
TheMX29F001T/B isdesignedtoofferprotectionagainst
accidental erasure or programming caused by spurious
systemlevelsignalsthatmayexistduringpowertransition.
Duringpowerupthedeviceautomaticallyresetsthestate
machine in the Read mode. In addition, with its control
register architecture, alteration of the memory contents
only occurs after successful completion of specific
command sequences. The device also incorporates
several features to prevent inadvertent write cycles
resulting from VCC power-up and power-down transition
or system noise.
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
AutomaticAlgorithmoperation. Hence,thesystemnever
reads a valid data on Q7 bit and Q6 never stops toggling.
Once the Device has exceeded timing limits, the Q5 bit
will indicate a "1". Please note that this is not a device
failure condition since the device was incorrectly used.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
11
MX29F001T/B
WRITE PULSE "GLITCH" PROTECTION
CHIP UNPROTECT WITH 12V SYSTEM
Noisepulsesoflessthan5ns(typical)onCEorWEwillnot
initiate a write cycle.
The MX29F001T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect completion to incorporate any changes in the
code.
LOGICAL INHIBIT
To activate this mode, the programming equipment must
force VID on control pin OE and address pin A9. The CE
pins must be set at VIL. Pins A6 must be set to VIH.(see
Table 2) Refer to chip unprotect algorithm and waveform
for the chip unprotect algorithm. The unprotection
mechanism begins on the falling edge of the WE pulse
and is terminated with the rising edge of the same.
Writing is inhibited by holding any one of OE = VIL, CE =
VIHorWE=VIH. ToinitiateawritecycleCEandWEmust
be a logical zero while OE is a logical one.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND. (Using a 10uF bulk capacitor
connected for high current condition is available if
necessary.)
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
00H at data outputs (Q0-Q7) for an unprotected sector. It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
CHIP PROTECTION WITH 12V SYSTEM
The MX29F001T/B features hardware chip protection.
whichwilldisablebothprogramanderaseoperations. To
activate this mode, the programming equipment must
force VID on address pin A9 and control pin OE, (suggest
VID=12V)A6=VILandCE=VIL.(seeTable2) Programming
of the protection circuitry begins on the falling edge of the
WE pulse and is terminated with the rising edge of the
same.Pleaserefertochipprotectalgorithmandwaveform.
CHIP PROTECTION WITHOUT 12V SYSTEM
TheMX29F001T/Balsofeatureahardwarechipprotection
method in a system without 12V power suppply. The
programmingequipmentdonotneedtosupply12voltsto
protect all sectors. The details are shown in chip protect
algorithm and waveform.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE and OE at VIL and WE at VIH. When A1=1,
itwillproducealogical"1"codeatdeviceoutputQ0forthe
protected status. Otherwise the device will produce 00H
fortheunprotectedstatus. Inthismode,theaddress,except
forA1, aredon'tcare. AddresslocationswithA1=VILare
reserved to read manufacturer and device codes.(Read
Silicon ID)
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F001T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.
POWER-UP SEQUENCE
It is also possible to determine if the chip is protected in
the system by writing a Read Silicon ID command.
Performing a read operation with A1=VIH, it will produce
a logical "1" at Q0 for the protected status.
The MX29F001T/B powers up in the Read only mode. In
addition, the memory contents may only be altered after
successful completion of the predefined command
sequences.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
12
MX29F001T/B
ABSOLUTE MAXIMUM RATINGS
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to ab-
solute maximum rating conditions for extended period may
affect reliability.
RATING
VALUE
Ambient Operating Temperature 0oC to 70oC
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9&OE
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are sub-
ject to change.
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
CIN1
PARAMETER
MIN.
TYP
MAX.
8
UNIT
pF
CONDITIONS
VIN = 0V
Input Capacitance
Control Pin Capacitance
Output Capacitance
CIN2
12
pF
VIN = 0V
COUT
12
pF
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS TA = 0oC TO 70oC, VCC = 5V ±10%(VCC = 5V ±5% for 29F001T/B-55)
SYMBOL
ILI
PARAMETER
MIN.
TYP
MAX.
UNIT
uA
uA
mA
uA
mA
mA
V
CONDITIONS
Input Leakage Current
Output Leakage Current
Standby VCC current
1
VIN = GND to VCC
VOUT = GND to VCC
CE = VIH
ILO
10
ISB1
ISB2
ICC1
ICC2
VIL
1
1
5
CE = VCC + 0.3V
IOUT = 0mA, f=5MHz
IOUT = 0mA, f=10MHz
Operating VCC current
30
50
Input Low Voltage
-0.3(NOTE 1)
2.0
0.8
VIH
Input High Voltage
VCC + 0.3
0.45
V
VOL
Output Low Voltage
V
IOL = 2.1mA
IOH = -2mA
VOH1
VOH2
Output High Voltage(TTL)
Output High Voltage(CMOS)
2.4
V
VCC-0.4
V
IOH = -100uA
VCC=VCC MIN
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
13
MX29F001T/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ±10%(TA=0oC to 70oC, 5V ±5% for MX29F001T/B-55)
29F001T/B-70 29F001T/B-90 29F001T/B-12
SYMBOL PARAMETER
MIN.
MAX.
70
MIN. MAX.
MIN. MAX. UNIT CONDITIONS
tACC
tCE
tOE
tDF
Address to Output Delay
90
90
40
120
120
50
ns
ns
ns
ns
ns
CE=OE=VIL
OE=VIL
CE to Output Delay
70
OE to Output Delay
40
CE=VIL
OE High to Output Float (Note1)
Address to Output hold
0
0
20
0
0
30
0
0
30
CE=VIL
tOH
CE=OE=VIL
29F001T/B-55
SYMBOL PARAMETER
MIN. MAX.
UNIT CONDITIONS
tACC
tCE
tOE
tDF
Address to Output Delay
55
55
30
ns
ns
ns
ns
ns
CE=OE=VIL
OE=VIL
CE to Output Delay
OE to Output Delay
CE=VIL
OE High to Output Float (Note1)
Address to Output hold
0
0
20
CE=VIL
tOH
CE=OE=VIL
TEST CONDITIONS:
NOTE:
•
Input pulse levels: 0.45V/2.4V for 70ns max. ; 0V/3.0V for
55ns
1. tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
•
•
Input rise and fall times: <10ns for 70ns max; < 5ns for 55ns
Output load: 1 TTL gate + 100pF (Including scope and jig) for
70ns max. ; 1 TTL gate + 30pF (Including scope and jig) for
55ns max.
•
Reference levels for measuring timing : 0.8V & 2.0V for 70ns
max.; 1.5V for 55ns
P/N: PM0515
REV. 2.1, JUN. 14, 2001
14
MX29F001T/B
READ TIMING WAVEFORMS
VIH
ADD Valid
A0~16
VIL
tCE
VIH
CE
VIL
VIH
WE
tDF
VIL
tOE
VIH
OE
tACC
VIL
tOH
HIGH Z
HIGH Z
VOH
VOL
DATA
Q0~7
DATA Valid
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ±10%(VCC = 5V ±5% for 29F001T/B-55)
SYMBOL
PARAMETER
MIN.
TYP
MAX.
UNIT CONDITIONS
ICC1 (Read)
ICC2
Operating VCC Current
30
mA
mA
mA
mA
mA
IOUT=0mA, f=5MHz
50
IOUT=0mA, F=10MHz
In Programming
ICC3 (Program)
ICC4 (Erase)
ICCES
50
50
In Erase
VCC Erase Suspend Current
2
CE=VIH, Erase Suspended
NOTES:
1. VIL min. = -0.6V for pulse width < 20ns.
2. If VIH is over the specified maximum value, programming
operation cannot be guranteed.
3. ICCES is specified with the device de-selected. If the device
is read during erase suspend mode, current draw is the sum
of ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
15
MX29F001T/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ±10%(VCC = 5V ±5% for 29F001T/B-55)
29F001T/B-70 29F001T/B-90 29F001T/B-12
SYMBOL PARAMETER
MIN.
0
MAX. MIN.
MAX. MIN.
MAX. UNIT CONDITIONS
tOES
tCWC
tCEP
tCEPH1
tCEPH2
tAS
OE setup time
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Command programming cycle
WE programming pulse width
WE programming pluse width High
WE programming pluse width High
Address setup time
70
45
20
20
0
90
120
45
50
20
20
20
20
0
0
tAH
Address hold time
45
30
0
45
50
tDS
Data setup time
45
50
tDH
Data hold time
0
0
tCESC
tDF
CE setup time before command write
Output disable time (Note 1)
Total erase time in auto chip erase
Total erase time in auto sector erase
Total programming time in auto verify
Sector address load time
CE Hold Time
0
0
0
30
40
40
3(TYP.) 24
ns
s
tAETC
tAETB
tAVT
tBAL
3(TYP.) 24
1(TYP.) 8
3(TYP.) 24
1(TYP.)
8
1(TYP.)
8
s
7
210
7
210
7
210
us
us
ns
ns
us
us
us
ms
100
0
100
0
100
0
tCH
tCS
CE setup to WE going low
Voltge Transition Time
0
0
0
tVLHT
tOESP
tWPP
tWPP2
4
4
4
OE Setup Time to WE Active
Write pulse width for chip protect
Write pulse width for chip unprotect
4
4
4
10
12
10
12
10
12
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
16
MX29F001T/B
AC CHARACTERISTICS TA = 0oC to 70oC, VCC = 5V ±5% for MX29F001T/B-55
29F001T/B-55
SYMBOL PARAMETER
MIN.
0
MAX.
UNIT CONDITIONS
tOES
tCWC
tCEP
tCEPH1
tCEPH2
tAS
OE setup time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Command programming cycle
WE programming pulse width
WE programming pluse width High
WE programming pluse width High
Address setup time
70
45
20
20
0
tAH
Address hold time
45
20
0
tDS
Data setup time
tDH
Data hold time
tCESC
tDF
CE setup time before command write
Output disable time (Note 1)
Total erase time in auto chip erase
Total erase time in auto sector erase
Total programming time in auto verify
Sector address load time
CE Hold Time
0
20
tAETC
tAETB
tAVT
tBAL
3(TYP.) 24
1(TYP.)
8
s
7
210
us
us
ns
ns
us
us
us
ms
100
0
tCH
tCS
CE setup to WE going low
Voltge Transition Time
0
tVLHT
tOESP
tWPP
tWPP2
4
OE Setup Time to WE Active
Write pulse width for chip protect
Write pulse width for chip unprotect
4
10
12
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
17
MX29F001T/B
SWITCHING TEST CIRCUITS
DEVICE UNDER
TEST
1.6K ohm
+5V
CL
1.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance for 29F001T/B-70, 29F001T/B-90, 29F001T/B-12
30pF Including jig capacitance for 29F001T/B-55
SWITCHING TEST WAVEFORMS(I) for 29F001T/B-70, 29F001T/B-90, 29F001T/B-12
2.4 V
2.0V
0.8V
2.0V
0.8V
TEST POINTS
0.45 V
OUTPUT
INPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are < 10ns.
SWITCHING TEST WAVEFORMS(II) for 29F001T/B-55
3.0 V
1.5V
1.5V
TEST POINTS
0 V
OUTPUT
INPUT
AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".
Input pulse rise and fall times are < 5ns.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
18
MX29F001T/B
COMMAND WRITE TIMING WAVEFORM
VCC
5V
VIH
ADD
ADD Valid
A0~16
VIL
tAH
tAS
VIH
WE
VIL
tOES
tCEPH1
tCEP
tCWC
VIH
VIL
CE
OE
tCS
tCH
tDH
VIH
VIL
tDS
VIH
VIL
DATA
Q0-7
DIN
P/N: PM0515
REV. 2.1, JUN. 14, 2001
19
MX29F001T/B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verification in fast algo-
rithm and additional programming by external control are
not required because these operations are executed
automatically by internal control circuit. Programming
completion can be verified by DATA polling and toggle bit
checking after automatic verify starts. Device outputs
DATAduringprogrammingandDATAafterprogramming
on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,
timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Vcc 5V
A11~A16
ADD Valid
ADD Valid
2AAH
555H
A0~A10
WE
555H
tAS
tCWC
tCEPH1
tAH
tCESC
tAVT
CE
OE
tCEP
tDF
tDS tDH
DATA
Q0~Q2
Command In
Command In
Command In
Data In
Data In
DATA polling
,Q4(Note 1)
DATA
DATA
Command In
Command In
Command In
Q7
Command #A0H
Command #AAH
Command #55H
tOE
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
P/N: PM0515
REV. 2.1, JUN. 14, 2001
20
MX29F001T/B
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
NO
Toggle Bit Checking
Q6 not Toggled
YES
NO
Invalid
Verify Byte Ok
Command
YES
.
NO
Q5 = 1
YES
Auto Program Completed
Reset
Auto Program Exceed
Timing Limit
P/N: PM0515
REV. 2.1, JUN. 14, 2001
21
MX29F001T/B
TOGGLE BIT ALGORITHM
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
NO
Toggle Bit Q6
=Toggle?
YES
NO
Q5=1?
YES
(Note 1,2)
Read Q7~Q0 Twice
NO
Toggle Bit Q6=
Toggle?
YES
Program/Erase Operation Not
Program/Erase Operation Complete
Complete, Write Reset Command
Notes:
1.Read toggle bit Q6 twice to determine whether or not it is toggle. See text.
2.Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See text.
P/N: PM0515
REV. 2.1, JUN. 14, 2001
22
MX29F001T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internalcontrolcircuit. Erasurecompletioncanbeverified
by DATA polling and toggle bit checking after auto matic
erase starts. Device outputs 0 during erasure and 1 after
erasure 0n Q7.(Q6 is for toggle bit; see toggle bit, DATA
polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A16
555H
2AAH
555H
2AAH
555H
A0~A10
WE
555H
tAS
tCWC
tAH
tCEPH1
tAETC
CE
OE
tCEP
tDS tDH
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
DATA polling
Command In
Command In
Command In
Command In
Command In
Q7
Command #80H
Command #AAH
Command #55H
Command #10H
Command #AAH
Command #55H
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N: PM0515
REV. 2.1, JUN. 14, 2001
23
MX29F001T/B
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
NO
Toggle Bit Checking
Q6 not Toggled
YES
NO
Invalid
DATA Polling
Q7 = 1
Command
YES
NO
.
Q5 = 1
Auto Chip Erase Completed
YES
Reset
Auto Chip Erase Exceed
Timing Limit
P/N: PM0515
REV. 2.1, JUN. 14, 2001
24
MX29F001T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector data indicated by A13 to A16 are erased. External
erase verify is not required because data are erased
automatically by internal control circuit. Erasure comple-
tioncanbeverifiedbyDATApollingandtogglebitchecking
after automatic erase starts. Device outputs 0 during
erasureand1aftererasureonQ7.(Q6isfortogglebit;see
toggle bit, DATA polling, timing waveform)
AUTOMATICSECTORERASETIMINGWAVEFORM
Vcc 5V
Sector
Addressn
Sector
Address0
Sector
Address1
A13~A16
555H
555H
555H
tAS
2AAH
2AAH
A0~A10
tCWC
tAH
WE
CE
tCEPH1
tBAL
tAETB
tCEP
tDS
OE
tDH
Command
In
Command
In
Q0,Q1,
Command
In
Command
Command
In
Command
In
Command
Command
In
In
In
Q4(Note 1)
DATA polling
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Q7
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H
(Q0~Q7)
Command #30H
Command #30H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N: PM0515
REV. 2.1, JUN. 14, 2001
25
MX29F001T/B
AUTOMATICSECTORERASEALGORITHMFLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Toggle Bit Checking
Invalid Command
Q6 Toggled ?
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Sector
to Erase
YES
NO
NO
Time-out Bit
Checking Q3=1 ?
YES
Toggle Bit Checking
Q6 not Toggled
YES
.
NO
Q5 = 1
DATA Polling
Q7 = 1
YES
Reset
Auto Sector Erase Completed
Auto Sector Erase
Exceed Timing
P/N: PM0515
REV. 2.1, JUN. 14, 2001
26
MX29F001T/B
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
Continue Erase
Another
.
NO
Erase Suspend ?
YES
P/N: PM0515
REV. 2.1, JUN. 14, 2001
27
MX29F001T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
tVLHT
Verify
12V
5V
OE
tVLHT
tWPP 1
WE
CE
tOESP
Data
01H
F0H
tOE
P/N: PM0515
REV. 2.1, JUN. 14, 2001
28
MX29F001T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
A6
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
WE
CE
tOESP
Data
00H
F0H
tOE
P/N: PM0515
REV. 2.1, JUN. 14, 2001
29
MX29F001T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 10us
Device Failed
Set WE=VIH, CE=OE=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
No
Data=01H?
PLSCNT=32?
Yes
Remove VID from A9
Write Reset Command
Device Failed
Chip Protection
Complete
P/N: PM0515
REV. 2.1, JUN. 14, 2001
30
MX29F001T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment
PLSCNT
Set OE=CE=VIL
A9=VID,A1=1
Read Data from Device
No
No
Data=00H?
PLSCNT=1000?
Yes
Yes
Remove VID from A9
Write Reset Command
Device Failed
Chip Unprotect
Complete
P/N: PM0515
REV. 2.1, JUN. 14, 2001
31
MX29F001T/B
TIMING WAVEFORM FOR CHIP PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Don't care
(Note 2)
Data
01H
F0H
tOE
Note: 1. Must issue "unlock for sector protect/unprotect" command
before chip protection for a system without 12V provided.
2. Except F0H
P/N: PM0515
REV. 2.1, JUN. 14, 2001
32
MX29F001T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE
tCEP
WE
* See the following Note!
CE
Don't care
(Note 2)
Data
F0H
00H
tOE
Note: 1. Must issue "unlock for sector protect/unprotect" command
before chip unprotection for a system without 12V provided.
2. Except F0H
P/N: PM0515
REV. 2.1, JUN. 14, 2001
33
MX29F001T/B
CHIP PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect"
Command(Table1)
OE=VIH,A9=VIH
CE=VIL,A6=VIL
Activate WE Pulse to start
Data don't care
.
Toggle bit checking
DQ6 not Toggled
No
Yes
Increment PLSCNT
Set CE=OE=VIL
A9=VIH
Raed from Sector
Addr=SA, A1=1
No
No
Data=01H?
PLSCNT=32?
Yes
Yes
Write Reset Command
Device Failed
Chip Protection
Complete
P/N: PM0515
REV. 2.1, JUN. 14, 2001
34
MX29F001T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for chip protect/unprotect"
Command (Table 1)
Set OE=A9=VIH
CE=VIL,A6=1
Activate WE Pulse to start
Data don't care
No
Toggle bit checking
DQ6 not Toggled
Increment
PLSCNT
Yes
Set OE=CE=VIL
A9=VIH,A1=1
Read Data from Device
No
No
Data=00H?
PLSCNT=1000?
Yes
Yes
Device Failed
Write Reset Command
Chip Unprotect
Complete
P/N: PM0515
REV. 2.1, JUN. 14, 2001
35
MX29F001T/B
ID CODE READ TIMING WAVEFORM
VCC
5V
VID
ADD
A9
VIH
VIL
tACC
tACC
A1 VIH
VIL
ADD
A2-A8
VIH
A10-A16 VIL
CE
VIH
VIL
VIH
VIL
tCE
WE
OE
tOE
VIH
VIL
tDF
tOH
tOH
VIH
VIL
DATA
Q0-Q7
DATA OUT
C2H
DATA OUT
18H/19H
P/N: PM0515
REV. 2.1, JUN. 14, 2001
36
MX29F001T/B
ORDERING INFORMATION
PLASTIC PACKAGE (Top Boot Sector as an sample For Bottom Boot Sector ones,MX29F001Txx will change
toMX29F001Bxx)
PART NO.
ACCESS TIME
OPERATING CURRENT STANDBY CURRENT
PACKAGE
(ns)
55
MAX.(mA)
MAX.(uA)
MX29F001TQC-55
MX29F001TQC-70
MX29F001TQC-90
MX29F001TQC-12
MX29F001TTC-55
30
30
30
30
30
5
5
5
5
5
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin PLCC
32 Pin TSOP
(Normal Type)
32 Pin TSOP
(Normal Type)
32 Pin TSOP
(Normal Type)
32 Pin TSOP
(Normal Type)
32 Pin PDIP
32 Pin PDIP
32 Pin PDIP
32 Pin PDIP
70
90
120
55
MX29F001TTC-70
MX29F001TTC-90
MX29F001TTC-12
70
30
30
30
5
5
5
90
120
MX29F001TPC-55
MX29F001TPC-70
MX29F001TPC-90
MX29F001TPC-12
55
30
30
30
30
5
5
5
5
70
90
120
P/N: PM0515
REV. 2.1, JUN. 14, 2001
37
MX29F001T/B
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
PARAMETER
MIN.
TYP.(2)
MAX.(3)
UNITS
Sector Erase Time
1
3
8
s
s
Chip Erase Time
24
Byte Programming Time
Chip Programming Time
Erase/Program Cycles
7
210
10.5
us
3.5
sec
Cycles
100,000
Note: 1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C,5V.
3.Maxi,um values measured at 25°C,4.5V.
LATCHUP CHARACTERISTICS
MIN.
-1.0V
MAX.
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
13.5V
Vcc + 1.0V
+100mA
-1.0V
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
PARAMETER
MIN.
UNIT
DataRetentionTime
20
Years
P/N: PM0515
REV. 2.1, JUN. 14, 2001
38
MX29F001T/B
PACKAGE INFORMATION
32-PIN PLASTIC DIP
P/N: PM0515
REV. 2.1, JUN. 14, 2001
39
MX29F001T/B
32-PIN PLASTIC LEADED CHIP CARRIER (PLCC)
P/N: PM0515
REV. 2.1, JUN. 14, 2001
40
MX29F001T/B
32-PIN PLASTIC TSOP
P/N: PM0515
REV. 2.1, JUN. 14, 2001
41
MX29F001T/B
REVISION HISTORY
Revision
Description
Page
Date
2.0
1.To remove "Advanced Information" datasheet marking and
contain information on products in full production
2.The modification summary from Revision 0.0 to Revision 1.0:
2-1.Program/erase cycle times:10K cycles-->100K cycles
2-2.To add data retention 20 years
P1
DEC/21/1999
P1,38
P1,38
P32,33
2-3.To remove A9 from the timing waveform of protection/
unprotection without 12V
2-4.Multi-sector erase timeout:80ms-->30us
2-5.tBAL:80us-->100us
To modify "Package Information"
P8
P16,17
P39~41
2.1
JUN/14/2001
P/N: PM0515
REV. 2.1, JUN. 14, 2001
42
MX29F001T/B
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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
43
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