MX29F002BPI-70G_技术文档

MX29F002/002N T/B

2M-BIT [256K x 8] CMOS FLASH MEMORY

FEATURES

•

262,144x 8 only

-Datapolling&Togglebitfordetectionofprogramand

erase cycle completion.

Fast access time: 55/70/90/120ns

Lowpowerconsumption

•

Sectorprotection

- 30mA maximum active current(5MHz)

- 1uA typical standby current

- Hardware method to disable any combination of

sectors from program or erase operations

-Sectorprotect/unprotectfor5Vonlysystemor5V/12V

system

•

Programming and erasing voltage 5V ± 10%

Commandregisterarchitecture

- Byte Programming (7us typical)

- Sector Erase (16K-Byte x1, 8K-Byte x 2, 32K-Byte

x1, and 64K-Byte x 3)

•

100,000minimumerase/programcycles

Latch-up protected to 100mA from -1 to VCC+1V

Boot Code Sector Architecture

- T = Top Boot Sector

•

Auto Erase (chip & sector) and Auto Program

-Automaticallyeraseanycombinationofsectorsorthe

whole chip with Erase Suspend capability.

-Automaticallyprogramsandverifiesdataatspecified

address

- B = Bottom Boot Sector

•

HardwareRESETpin(onlyfor29F002T/B)

- Resets internal state machine to read mode

Low VCC write inhibit is equal to or less than 3.2V

Package type:

•

EraseSuspend/EraseResume

- Suspends an erase operation to read data from, or

programdatato,asectorthatisnotbeingerased,then

resumestheeraseoperation.

- 32-pin PDIP

-32-pinPLCC

- 32-pin TSOP (Type 1)

Status Reply

•

20 years data retention

GENERAL DESCRIPTION

MXIC'sFlashtechnologyreliablystoresmemorycontents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and programming

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields for

erase and programming operations produces reliable

cycling. The MX29F002T/B uses a 5.0V ± 10% VCC

supply to perform the High Reliability Erase and auto

Program/Erasealgorithms.

The MX29F002T/B is a 2-mega bit Flash memory organ-

ized as 256K bytes of 8 bits only. MXIC's Flash memories

offer the most cost-effective and reliable read/write non-

volatile random access memory. The MX29F002T/B is

packaged in 32-pin PDIP,PLCC and 32-pin TSOP(I). It is

designedtobereprogrammedanderasedin-systemorin-

standardEPROMprogrammers.

ThestandardMX29F002T/Boffersaccesstimeasfastas

55ns, allowing operation of high-speed microprocessors

without wait states. To eliminate bus contention, the

MX29F002T/B has separate chip enable (CE) and output

enable(OE)controls.

Thehighestdegreeoflatch-upprotectionisachievedwith

MXIC'sproprietarynon-epiprocess. Latch-upprotectionis

proved for stresses up to 100 milliamps on address and

data pin from -1V to VCC + 1V.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F002T/B uses a command register to manage this

functionality. Thecommandregisterallowsfor100%TTL

level control inputs and fixed power supply levels during

erase and programming, while maintaining maximum

EPROM compatibility.

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MX29F002/002N T/B

PIN CONFIGURATIONS

32 PDIP

32 TSOP (TYPE 1)

NC on MX29F002NT/B

VCC

WE

A17

A14

A13

A8

RESET

A16

A15

A12

A7

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1

A11

A9

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

OE

A10

CE

Q7

Q6

Q5

Q4

Q3

GND

Q2

Q1

Q0

A0

2

3

A8

3

A13

A14

A17

WE

4

5

6

7

A6

6

VCC

RESET

A16

A15

A12

A7

8

MX29F002T/B

A9

A5

7

(NC on MX29F002NT/B)

9

10

11

12

13

14

15

16

A11

OE

A10

CE

A4

8

A3

9

A2

10

11

12

13

14

15

16

A6

A1

A5

A2

Q7

A4

A3

A0

Q6

Q0

Q5

Q1

Q4

Q2

(NORMAL TYPE)

Q3

GND

32 PLCC

SECTOR STRUCTURE

NC on MX29F002NT/B

A 1 7 ~ A 0

3 F F F F H

1 6 K - B Y T E

( B O O T S E C T O R )

3 B F F F H

3 9 F F F H

4

5

1

32

30

29

A7

A6

A5

A4

A3

A2

A1

A0

Q0

A14

A13

A8

8

K - B Y T E

3 7 F F F H

2 F F F F H

1 F F F F H

A9

3 2 K - B Y T E

6 4 K - B Y T E

9

MX29F002T/B

25

A11

OE

A10

CE

Q7

0 F F F F H

0 0 0 0 0 H

13

14

21

17

20

MX29F002T Sector Architecture

A 1 7 ~ A 0

PIN DESCRIPTION

3 F F F F H

2 F F F F H

1 F F F F H

0 F F F F H

6 4 K - B Y T E

SYMBOL

A0~A17

Q0~Q7

CE

PIN NAME

Address Input

6 4 K - B Y T E

3 2 K - B Y T E

Data Input/Output

Chip Enable Input

Write Enable Input

0 7 F F F H

0 5 F F F H

0 3 F F F H

0 0 0 0 0 H

WE

8

K - B Y T E

RESET

OE

Hardware Reset Pin/Sector Protect Unlock

Output Enable Input

1 6 K - B Y T E

( B O O T S E C T O R )

VCC

Power Supply Pin (+5V)

Ground Pin

GND

MX29F002B Sector Architecture

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MX29F002/002N T/B

BLOCK DIAGRAM

WRITE

CONTROL

INPUT

PROGRAM/ERASE

STATE

WE

OE

HIGH VOLTAGE

MACHINE

(WSM)

LOGIC

WP

RESET

STATE

MX29F002

FLASH

REGISTER

ADDRESS

LATCH

ARRAY

A0~A17

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

DATA

HV

SENSE

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

I/O BUFFER

Q0-Q7

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MX29F002/002N T/B

AUTOMATIC PROGRAMMING

cally pre-program and verify the entire array. Then the

device automatically times the erase pulse width, verifies

theerase, andcountsthenumberofsequences. Astatus

bit similar to DATA polling and status bit toggling between

consecutive read cycles provides feedback to the user as

to the status of the programming operation.

The MX29F002T/B is byte programmable using the

Automatic Programming algorithm. The Automatic

Programming algorithm does not require the system to

time out or verify the data programmed. The typical chip

programmingtimeoftheMX29F002T/Batroomtemperature

is less than 3.5 seconds.

Commands are written to the command register using

standardmicroprocessorwritetimings. Registercontents

serveasinputstoaninternalstate-machinewhichcontrols

theeraseandprogrammingcircuitry. Duringwritecycles,

thecommandregisterinternallylatchesaddressanddata

neededfortheprogramminganderaseoperations. During

a system write cycle, addresses are latched on the falling

edge, and data are latched on the rising edge of WE .

AUTOMATIC CHIP ERASE

Typical erasure at room temperature is accomplished in

less than 3 seconds. The device is erased using the

AutomaticErasealgorithm. TheAutomaticErasealgorithm

automatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

internally controlled by the device.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX29F002T/B electri-

cally erases all bits simultaneously using Fowler-Nord-

heim tunneling. The bytes are programmed one byte at a

time using the EPROM programming mechanism of hot

electroninjection.

AUTOMATIC SECTOR ERASE

The MX29F002T/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

AutomaticSectorErasealgorithmautomaticallyprograms

thespecifiedsector(s)priortoelectricalerase. Thetiming

andverificationofelectricaleraseareinternallycontrolled

by the device.

Duringaprogramcycle, thestate-machinewillcontrolthe

program sequences and command register will not re-

spond to any command set. During a Sector Erase cycle,

thecommandregisterwillonlyrespondtoEraseSuspend

command. After Erase Suspend is completed, the device

stays in read mode. After the state machine has com-

pleted its task, it will allow the command register to

respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write a program set-up commands include 2

unlock write cycle and A0H and a program command

(program data and address). The device automatically

times the programming pulse width, verifies the program,

and counts the number of sequences. A status bit similar

to DATA polling and a status bit toggling between

consecutivereadcycles,providesfeedbacktotheuseras

to the status of the programming operation.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using standard

microprocessor write timings. The device will automati-

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MX29F002/002N T/B

TABLE 1. SOFTWARE COMMAND DEFINITIONS

First Bus

Cycle

Second Bus

Cycle

Third Bus

Cycle

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Bus

Cycle Addr Data

XXXH F0H

RA RD

Addr Data

Addr Data Addr Data

Reset

1

Read

1

Read Silicon ID

Sector Protect

Verification

4

555H AAH 2AAH 55H

555H 90H

ADI DDI

(SA) 00H

(X02H) 01H

Program

4

6

1

6

555H AAH 2AAH 55H

XXXH B0H

555H A0H

555H 80H

PA

PD

Chip Erase

555H AAH 2AAH

55H 555H 10H

55H SA 30H

Sector Erase

Sector Erase Suspend

Sector Erase Resume

Unlock for sector

protect/unprotect

XXXH 30H

555H AAH 2AAH 55H

555H 80H

555H AAH

2AAH 55H 555H 20H

Note:

1. ADI = Address of Device identifier; A1=0,A0 =0 for manufacture code,A1=0, A0 =1 for device code (Refer to Table 3).

DDI = Data of Device identifier : C2H for manufacture code, 00B0h/0034h for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3.The system should generate the following address patterns: 555H or 2AAH to Address A0~A10. Address bit A11~A17=X=Don't

care for all address commands except for Program Address (PA) and Sector Address (SA). Write Sequence may be initiated

with A11~A17 in either state.

4.For Sector Protect Verification Operation : If read out data is 01H, it means the sector has been protected. If read out data is 00H,

it means the sector is still not being protected.

COMMAND DEFINITIONS

Deviceoperationsareselectedbywritingspecificaddress

and data sequences into the command register. Writing

incorrect address and data values or writing them in the

impropersequencewillreset thedevicetothereadmode.

Table 1 defines the valid register command sequences.

Note that the Erase Suspend (B0H) and Erase Resume

(30H) commands are valid only while the Sector Erase

operationisinprogress. Eitherofthetworesetcommand

sequences will reset the device(when applicable).

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MX29F002/002N T/B

TABLE 2. MX29F002T/B BUS OPERATION

Pins

CE

OE

WE

A0

A1

A6

A9

Q0~Q7

Mode

Read Silicon ID

Manufacturer Code(1)

Read Silicon ID

Device Code(1)

Read

L

H

L

X

V_ID(2)

C2H

L

H

L

X

V_ID(2)

B0h/34h

L

H

L

X

H

X

H

L

A0

X

A1

X

A6

X

A9

X

D_OUT

HIGH Z

D_IN(3)

X

Standby

Output Disable

Write

H

X

H

A0

X

A1

X

A6

L

A9

Sector Protect with 12V

system(6)

V_ID(2)

L

V_ID(2)

Chip Unprotect with 12V

system(6)

L

X

V_ID(2)

L

H

L

X

H

X

H

X

H

X

L

V_ID(2)

H

X

Code(5)

X

Verify Sector Protect

with 12V system

L

H

L

Sector Protect without 12V

system (6)

Chip Unprotect without 12V

system (6)

L

H

X

H

X

Verify Sector Protect/Unprotect

without 12V system (7)

Reset

H

X

H

Code(5)

HIGH Z

X

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer to Table 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H means unprotected.

Code=01H means protected.

A17~A13=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system" command.

7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V system" com-

mand.

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MX29F002/002N T/B

READ/RESET COMMAND

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

The read or reset operation is initiated by writing the read/

reset command sequence into the command register.

Microprocessor read cycles retrieve array data. The

device remains enabled for reads until the command

register contents are altered.

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid command

must then be written to place the device in the desired

state.

The Automatic Chip Erase does not require the device to

beentirelypre-programmedpriortoexecutingtheAutomatic

Chip Erase. Upon executing the Automatic Chip Erase,

thedevicewillautomatically program and verify the entire

memory for an all-zero data pattern. When the device is

automaticallyverifiedtocontainanall-zeropattern,aself-

timed chip erase and verify begin. The erase and verify

operations are completed when the data on Q7 is "1" at

which time the device returns to the Read mode. The

system is not required to provide any control or timing

duringtheseoperations.

SILICON-ID-READ COMMAND

Flashmemoriesareintendedforuseinapplicationswhere

the local CPU alters memory contents. As such,

manufacturer and device codes must be accessible while

thedeviceresidesinthetargetsystem. PROMprogrammers

typically access signature codes by raising A9 to a high

voltage. However,multiplexinghighvoltageontoaddress

lines is not generally desired system design practice.

WhenusingtheAutomaticChipErasealgorithm,notethat

the erase automatically terminates when adequate erase

marginhasbeenachievedforthememoryarray(noerase

verify command is required).

The MX29F002T/B contains a Silicon-ID-Read operation

tosupplementtraditionalPROMprogrammingmethodology.

The operation is initiated by writing the read silicon ID

commandsequence intothecommandregister. Following

the command write, a read cycle with A1=VIL, A0=VIL

retrievesthemanufacturercodeofC2H. Areadcyclewith

A1=VIL, A0=VIH returns the device code of B0h for

MX29F002T, 34hforMX29F002B.

If the Erase operation was unsuccessful, the data on Q5

is"1"(seeTable4), indicatingtheeraseoperationexceed

internal timing limit.

The automatic erase begins on the rising edge of the last

WEpulseinthecommandsequenceandterminateswhen

the data on Q7 is "1" and the data on Q6 stops toggling for

two consecutive read cycles, at which time the device

returns to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins

A0

A1

Q7

Q6

Q5

Q4

Q3

Q2

Q1

Q0

Code(Hex)

Code

Manufacturecode

Device code

forMX29F002T

Device code

forMX29F002B

Sector Protection

Verification

VIL VIL

VIH VIL

1

0

1

0

1

0

1

0

C2H

B0h

VIH VIL

0

1

0

1

0

34h

X

VIH

0

1

0

01H(Protected)

00H(Unprotected)

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MX29F002/002N T/B

the Sector Erase time-out immediately terminates the

time-out period and suspends the erase operation. After

this command has been executed, the command register

will initiate erase suspend mode. The state machine will

return to read mode automatically after suspend is ready.

At this time, state machine only allows the command

register to respond to the Read Memory Array, Erase

Resume and Program commands. The system can

determinethestatusoftheprogramoperationusingtheQ7

orQ6statusbits,justasinthestandardprogramoperation.

Afteranerase-suspendedprogramoperationiscomplete,

the system can once again read array data within non-

suspendedsectors.

SET-UP AUTOMATIC SECTOR ERASE

COMMANDS

The Automatic Sector Erase does not require the device

to be entirely pre-programmed prior to executing the

AutomaticSet-upSectorErasecommandandAutomatic

Sector Erase command. Upon executing the Automatic

Sector Erase command, the device will automatically

program and verify the sector(s) memory for an all-zero

datapattern. Thesystemdoesnotrequire toprovideany

control or timing during these operations.

When the sector(s) is automatically verified to contain an

all-zeropattern,aself-timedsectorerase and verification

begin. Theeraseandverificationoperationsarecomplete

when the data on Q7 is "1" and the data on Q6 stops

togglingfortwoconsecutivereadcycles,atwhichtimethe

device returns to the Read mode. The system does not

required to provide any control or timing during these

operations.

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

erasemarginhasbeenachievedforthememoryarray(no

erase verify command is required). Sector erase is a six-

bus cycle operation. There are two "unlock" write cycles.

These are followed by writing the set-up command-80H.

Two more "unlock" write cycles are then followed by the

sector erase command-30H. The sector address is

latchedonthefallingedgeof WE,whilethecommand(data)

is latched on the rising edge of WE. Sector addresses

selectedare loadedintointernalregisteronthesixthfalling

edge of WE. Each successive sector load cycle started

bythefallingedgeofWE mustbeginwithin30usfromthe

rising edge of the preceding WE. Otherwise, the loading

period ends and internal auto sector erase cycle starts.

(MonitorQ3todetermineifthesectorerasetimerwindow

is still open, see section Q3, Sector Erase Timer.) Any

commandotherthanSectorErase(30H)orEraseSuspend

(BOH)duringthetime-outperiodresetsthedevicetoread

mode.

ERASE SUSPEND

This command is only valid while the state machine is

executingAutomaticSectorEraseoperation,andtherefore

will only be responded during Automatic Sector Erase

operation. Writing the Erase Suspend command during

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MX29F002/002N T/B

TABLE 4. WRITE OPERATION STATUS

Status

Q7

Q6

Q5

Q3

Q2

Note1

Note2

Byte Program in Auto Program Algorithm

Auto Erase Algorithm

Q7 Toggle

0

N/A No Toggle

0

1

Toggle

No

1

Toggle

Erase Suspend Read

N/A

In Progress

(Erase Suspended Sector)

Erase Suspend Read

Toggle

Erase Suspended Mode

Data Data Data Data

Data

N/A

(Non-Erase Suspended Sector)

Erase Suspend Program

Q7 Toggle

0

1

N/A

Byte Program in Auto Program Algorithm

N/A No Toggle

Exceeded Auto Erase Algorithm

0

Toggle

1

Toggle

N/A

Time Limits Erase Suspend Program

Q7 Toggle

N/A

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

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MX29F002/002N T/B

fourth WE pulse of the four write pulse sequences for

automaticprogram.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. EraseResumewillnothaveanyeffectinallother

conditions. Another Erase Suspend command can be

written after the chip has resumed erasing.

WhiletheAutomaticErasealgorithmisinoperation,Q7will

read "0" until the erase operation is competed. Upon

completionoftheeraseoperation,thedataonQ7willread

"1". The Data Polling feature is valid after the rising edge

of the sixth WE pulse of six write pulse sequences for

automatic chip/sector erase.

TheDataPollingfeatureisactiveduringAutomaticProgram/

Erase algorithm or sector erase time-out.(see section Q3

Sector Erase Timer)

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, a three-cycle

command sequence is required. There are two "unlock"

write cycles. These are followed by writing the Automatic

ProgramcommandA0H.

Q6:Toggle BIT I

The MX29F002T/B features a "Toggle Bit" as a method to

indicate to the host system that the Auto Program/Erase

algorithms are either in progress or completed.

Once the Automatic Program command is initiated, the

nextWEpulsecausesatransitiontoanactiveprogramming

operation. Addressesarelatchedonthefallingedge,and

data are internally latched on the rising edge of the WE

pulse. TherisingedgeofWEalsobeginstheprogramming

operation. Thesystemdoesnotrequiretoprovidefurther

controls or timings. The device will automatically provide

anadequateinternallygeneratedprogrampulseandverify

margin.

DuringanAutomaticProgramorErasealgorithmoperation,

successivereadcyclestoanyaddresscauseQ6totoggle.

The system may use either OE or CE to control the read

cycles.Whentheoperationiscomplete,Q6stopstoggling.

After an erase command sequence is written, if all sectors

selectedforerasingareprotected,Q6togglesand returns

to reading array data. If not all selected sectors are

protected, the Automatic Erase algorithm erases the

unprotectedsectors,andignorestheselectedsectorsthat

areprotected.

Iftheprogramoperationwasunsuccessful,thedataonQ5

is "1", indicating the program operation exceed internal

timing limit. The automatic programming operation is

completedwhenthedatareadonQ6stopstogglingfortwo

consecutive read cycles and the data on Q7 and Q6 are

equivalent to data written to these two bits, at which time

the device returns to the Read mode(no program verify

commandisrequired).

The system can use Q6 and Q2 together to determine

whetherasectorisactivelyerasingoriserasesuspended.

When the device is actively erasing (that is, the Automatic

Erase algorithm is in progress), Q6 toggling. When the

deviceenterstheEraseSuspendmode,Q6stopstoggling.

However,thesystemmustalsouseQ2todeterminewhich

sectorsareerasingorerase-suspended.Alternatively,the

systemcanuseQ7(seethesubsectiononQ7:DataPolling).

WRITE OPERATION STATUS

DATA POLLING-Q7

If a program address falls within a protected sector, Q6

toggles forapproximately2us aftertheprogramcommand

sequence is written, then returns to reading array data.

TheMX29F002T/BalsofeaturesDataPollingasamethod

toindicatetothehostsystemthattheAutomaticProgram

or Erase algorithms are either in progress or completed.

Q6alsotogglesduringtheerase-suspend-programmode,

andstopstogglingoncetheAutomaticProgramalgorithm

is complete.

WhiletheAutomaticProgrammingalgorithmisinoperation,

anattempttoreadthedevicewillproducethecomplement

dataofthedatalastwrittentoQ7. Uponcompletionofthe

Automatic Program Algorithm an attempt to read the

device will produce the true data last written to Q7. The

Data Polling feature is valid after the rising edge of the

The Write Operation Status table shows the outputs for

Toggle Bit I on Q6. Refer to the toggle bit algorithm.

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MX29F002/002N T/B

system must start at the beginning of the algorithm when

itreturnstodeterminethestatusoftheoperation(topofthe

toggle bit algorithm flow chart).

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is, the

Automatic Erase algorithm is in process), or whether that

sector is erase-suspended. Toggle Bit I is valid after the

risingedgeofthefinalWEpulseinthecommandsequence.

Q5

Exceeded Timing Limits

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

cycles.) But Q2 cannot distinguish whether the sector is

activelyerasingoriserase-suspended. Q6,bycomparison,

indicates whether the device is actively erasing, or is in

Erase Suspend, but cannot distinguish which sectors are

selectedforerasure. Thus,bothstatusbitsarerequiredfor

sectorsandmodeinformation. RefertoTable4tocompare

outputs for Q2 and Q6.

Q5willindicateiftheprogramorerasetimehasexceeded

the specified limits(internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

which indicates that the program or erase cycle was not

successfully completed. Data Polling and Toggle Bit are

the only operating functions of the device under this

condition.

If this time-out condition occurs during sector erase

operation, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still

functional and may be used for the program or erase

operation. Thedevicemustberesettouseothersectors.

Write the Reset command sequence to the device, and

thenexecuteprogramorerasecommandsequence. This

allows the system to continue to use the other active

sectors in the device.

Reading Toggle Bits Q6/ Q2

Refertothetogglebitalgorithmforthefollowingdiscussion.

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

systemwouldnoteandstorethevalueofthetogglebitafter

the first read. After the second read, the system would

comparethenewvalueofthetogglebitwiththefirst. Ifthe

toggle bit is not toggling, the device has completed the

program or erase operation. The system can read array

data on Q7-Q0 on the following read cycle.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or

combination of sectors are bad.

Ifthistime-outconditionoccursduringthebyteprogramming

operation,itspecifiesthattheentiresectorcontainingthat

byte is bad and this sector maynot be reused, (other

sectors are still functional and can be reused).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the system

also should note whether the value of Q5 is high (see the

section on Q5). If it is, the system should then determine

againwhetherthetogglebitistoggling,sincethetogglebit

may have stopped toggling just as Q5 went high. If the

togglebitisnolongertoggling,thedevicehassuccessfully

completed the program or erase operation. If it is still

toggling, the device did not complete the operation

successfully,andthesystemmustwritetheresetcommand

to return to reading array data.

The Q5 time-out condition may also appear if a user tries

to program a non blank location without erasing. In this

case the device locks out and never completes the

AutomaticAlgorithmoperation. Hence,thesystemnever

reads a valid data on Q7 bit and Q6 never stops toggling.

OncetheDevicehasexceededtiminglimits, theQ5bitwill

indicate a "1". Please note that this is not a device failure

condition since the device was incorrectly used.

Theremainingscenarioisthatsysteminitiallydetermines

thatthetogglebitistogglingandQ5hasnotgonehigh. The

system may continue to monitor the toggle bit and Q5

throughsuccessivereadcycles,determiningthestatusas

describedinthepreviousparagraph. Alternatively, itmay

choose to perform other system tasks. In this case, the

REV. 1.5, MAR. 28, 2005

P/N: PM0547

11

MX29F002/002N T/B

Q3

LOGICAL INHIBIT

Sector Erase Timer

Writing is inhibited by holding any one of OE = VIL, CE =

VIHorWE=VIH. ToinitiateawritecycleCEandWEmust

be a logical zero while OE is a logical one.

After the completion of the initial sector erase command

sequence the sector erase time-out will begin. Q3 will

remainlowuntilthetime-outiscomplete. DataPollingand

ToggleBitarevalidaftertheinitialsectorerasecommand

sequence.

POWER SUPPLY DECOUPLING

If Data Polling or the Toggle Bit indicates the device has

beenwrittenwithavaliderasecommand,Q3maybeused

to determine if the sector erase timer window is still open.

If Q3 is high ("1") the internally controlled erase cycle has

begun; attempts to write subsequent commands to the

devicewillbeignoreduntiltheeraseoperationiscompleted

asindicatedbyDataPollingorToggleBit. IfQ3islow("0"),

the device will accept additional sector erase commands.

To insure the command has been accepted, the system

software should check the status of Q3 prior to and

followingeachsubsequentsectorerasecommand. If Q3

werehighonthesecondstatuscheck, thecommandmay

not have been accepted.

In order to reduce power switching effect, each device

should havea0.1uFceramiccapacitorconnectedbetween

its VCC and GND.

SECTOR PROTECTION WITH 12V SYSTEM

The MX29F002T/B features hardware sector protection.

Thisfeaturewilldisablebothprogramanderaseoperations

for these sectors protected. To activate this mode, the

programmingequipmentmustforceVIDonaddresspinA9

and control pin OE, (suggest VID = 12V) A6 = VIL and CE

= VIL.(see Table 2) Programming of the protection

circuitry begins on the falling edge of the WE pulse and is

terminated on the rising edge. Please refer to sector

protectalgorithmandwaveform.

DATA PROTECTION

TheMX29F002T/B isdesignedtoofferprotectionagainst

accidental erasure or programming caused by spurious

system levelsignalsthatmayexistduringpowertransition.

Duringpowerupthedeviceautomaticallyresetsthestate

machine in the Read mode. In addition, with its control

register architecture, alteration of the memory contents

only occurs after successful completion of specific

command sequences. The device also incorporates

severalfeaturestopreventinadvertentwritecyclesresulting

fromVCCpower-upandpower-downtransitionorsystem

noise.

To verify programming of the protection circuitry, the

programmingequipmentmustforceVIDonaddresspinA9

(withCEandOEatVILandWEatVIH. WhenA1=1, itwill

produce a logical "1" code at device output Q0 for a

protected sector. Otherwise the device will produce 00H

for the unprotected sector. In this mode, the addresses,

except for A1, are in "don't care" state. Address locations

withA1=VILarereservedtoreadmanufactureranddevice

codes.(Read Silicon ID)

It is also possible to determine if the sector is protected

in the system by writing a Read Silicon ID command.

PerformingareadoperationwithA1=VIH,itwillproducea

logical "1" at Q0 for the protected sector.

WRITE PULSE "GLITCH" PROTECTION

Noisepulsesoflessthan5ns(typical)onCEorWEwillnot

initiate a write cycle.

REV. 1.5, MAR. 28, 2005

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12

MX29F002/002N T/B

Temporary Sector Unprotect Operation (For 29F002T/B only)

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

2. All previously protected sectors are protected again.

REV. 1.5, MAR. 28, 2005

P/N: PM0547

13

MX29F002/002N T/B

TEMPORARY SECTOR UNPROTECT

ParameterStd. Description

TestSetup All Speed Options Unit

tVIDR

tRSP

VID Rise and Fall Time (See Note)

RESET Setup Time for Temporary Sector Unprotect

Min

500

4

ns

us

Note:

Not 100% tested

Temporary Sector Unprotect Timing Diagram (For 29F002T/B only)

12V

RESET

0 or 5V

Program or Erase Command Sequence

tVIDR

CE

WE

tRSP

REV. 1.5, MAR. 28, 2005

P/N: PM0547

14

MX29F002/002N T/B

AC CHARACTERISTICS

ParameterStd Description

TestSetup All Speed Options Unit

tREADY

RESET PIN Low (Not During Automatic Algorithms)

MAX

500

ns

to Read or Write (See Note)

tRP1

tRP2

tRH

RESET Pulse Width (During Automatic Algorithms)

MIN

10

500

0

us

ns

RESET Pulse Width (NOT During Automatic Algorithms) MIN

RESET High Time Before Read(See Note) MIN

Note:

Not 100% tested

RESET TIMING WAVEFORM (For 29F002T/B only)

CE, OE

tRH

RESET

tRP2

tReady

Reset Timing NOT during Automatic Algorithms

RESET

tRP1

Reset Timing during Automatic Algorithms

REV. 1.5, MAR. 28, 2005

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15

MX29F002/002N T/B

CHIP UNPROTECT WITH 12V SYSTEM

ABSOLUTE MAXIMUM RATINGS

TheMX29F002T/Balsofeaturesthechipunprotectmode,

so that all sectors are unprotected after chip unprotect is

completed to incorporate any changes in the code. It is

recommendedtoprotectallsectorsbeforeactivatingchip

unprotectmode.

RATING

VALUE

Ambient Operating Temperature 0^oC to 70^oC

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

A9

-65^oC to 125^oC

-0.5V to 7.0V

-0.5V to 13.5V

To activate this mode, the programming equipment must

force VID on control pin OE and address pin A9. The CE

pins must be set at VIL. Pins A6 must be set to VIH.(see

Table 2) Refer to chip unprotect algorithm and waveform

for the chip unprotect algorithm. The unprotection

mechanismbeginsonthefallingedgeoftheWEpulseand

is terminated on the rising edge.

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stressratingonlyandfunctionaloperationalsectionsofthisspecification

is not implied. Exposure to absolute maximum rating conditions for

extended period may affect reliability.

It is also possible to determine if the chip is unprotected in

the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00Hatdataoutputs(Q0-Q7)foranunprotectedsector.Itis

noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

NOTICE:

Specifications contained within the following tables are subject to

change.

SECTOR PROTECTION WITHOUT 12V SYSTEM

TheMX29F002T/Balsofeatureahardwaresectorprotection

method in a system without 12V power supply. The

programmingequipmentdonotneedtosupply12voltsto

protect sectors. The details are shown in sector protect

algorithmandwaveform.

CHIP UNPROTECT WITHOUT 12V SYSTEM

TheMX29F002T/Balsofeatureahardwarechipunprotection

method in a system without 12V power supply. The

programmingequipmentdonotneedtosupply12voltsto

unprotect all sectors. The details are shown in chip

unprotectalgorithmandwaveform.

POWER-UP SEQUENCE

The MX29F002T/B powers up in the Read only mode. In

addition, the memory contents may only be altered after

successfulcompletionofatwo-stepcommandsequence.

Vpp and Vcc power up sequence is not required.

REV. 1.5, MAR. 28, 2005

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16

MX29F002/002N T/B

DC/AC Operating Conditions for Read/Programming/Erase Operation

MX29F002/002N

-70 -90

0^oC to 70^oC 0^oC to 70^oC 0^oC to 70^oC

-55

-12

0^oC to 70^oC

OperatingTemperature

Vcc Power Supply

Commercial

Industrial

-40^oCto85^oC -40^oCto85^oC -40^oCto85^oC

5V±5%

5V±10%

CAPACITANCE TA = 25^oC, f = 1.0 MHz

SYMBOL

CIN1

PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Control Pin Capacitance

Output Capacitance

CIN2

12

pF

VIN = 0V

COUT

12

pF

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS

SYMBOL

ILI

PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

Input Leakage Current

Output Leakage Current

Standby VCC current

1(Note 3) uA

VIN = GND to VCC

VOUT = GND to VCC

CE = VIH

ILO

10

1

uA

mA

uA

ISB1

ISB2

ICC1

ICC2

VIL

1

5

CE = VCC + 0.3V

IOUT = 0mA, f=5MHz

IOUT = 0mA, f=10MHz

Operating VCC current

30(Note 4) mA

50

mA

V

Input Low Voltage

-0.3(NOTE 1)

2.0

0.8

VIH

Input High Voltage

VCC + 0.3

0.45

V

VOL

Output Low Voltage

V

IOL = 2.1mA

IOH = -2mA

VOH1

VOH2

Output High Voltage(TTL)

Output High Voltage(CMOS)

2.4

V

VCC-0.4

V

IOH = -100uA,

VCC=VCC MIN

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns.

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. ILI=10uA for Industrial grade.

4. ICC1=45mA for Industrial grade.

REV. 1.5, MAR. 28, 2005

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17

MX29F002/002N T/B

AC CHARACTERISTICS

29F002T/B-55

29F002T/B-70

SYMBOL PARAMETER

MIN.

MAX.

55

MIN.

MAX.

70

UNIT CONDITION

tACC

tCE

tOE

tDF

Address to Output Delay

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

55

70

OE to Output Delay

25

30

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

20

0

20

CE=VIL

tOH

CE=OE=VIL

29F002T/B-90

29F002T/B-12

SYMBOL PARAMETER

MIN.

MAX.

90

MIN.

MAX.

120

50

UNIT CONDITIONS

tACC

tCE

tOE

tDF

Address to Output Delay

ns

CE=OE=VIL

OE=VIL

CE to Output Delay

90

OE to Output Delay

40

CE=VIL

OE High to Output Float (Note1)

Address to Output hold

0

30

0

30

CE=VIL

tOH

CE=OE=VIL

TEST CONDITIONS:

NOTE:

1. tDF is defined as the time at which the output achieves the

open circuit condition and data is no longer driven.

•

Input pulse levels: 0.45V/2.4V for 70ns max., 0V/3V for 55ns

Input rise and fall times: < 10ns for 70ns max.

< 5ns for 55ns

•

Output load:

1 TTL gate + 100pF (Including scope and jig) for 70ns max.

1 TTL gate + 50pF (Including scope and jig) for 55ns speed

grade

•

Reference levels for measuring timing: 0.8V, 2.0V for 70ns

max.

: 1.5V for 55ns

READ TIMING WAVEFORMS

VIH

ADD Valid

A0~17

VIL

tCE

VIH

CE

VIL

VIH

WE

tDF

VIL

tOE

VIH

OE

tACC

VIL

tOH

HIGH Z

VOH

VOL

DATA

Q0~7

DATA Valid

REV. 1.5, MAR. 28, 2005

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18

MX29F002/002N T/B

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS

SYMBOL

PARAMETER

MIN.

TYP

MAX.

UNIT CONDITIONS

ICC1 (Read)

ICC2

Operating VCC Current

30(Note 5) mA

IOUT=0mA, f=5MHz

IOUT=0mA, F=10MHz

In Programming

50

mA

ICC3 (Program)

ICC4 (Erase)

ICCES

In Erase

VCC Erase Suspend Current

2

CE=VIH, Erase Suspended

NOTES:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of ICCES

and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

5. ICC1(Read)=45mA for Industrial Grade.

REV. 1.5, MAR. 28, 2005

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19

MX29F002/002N T/B

AC CHARACTERISTICS

29F002T/B-55(NOTE 2)

SYMBOL PARAMETER

MIN.

0

MAX.

UNIT

ns

s

tOES

tCWC

tCEP

tCEPH1

tCEPH2

tAS

OE setup time

Command programming cycle

WE programming pulse width

WE programming pulse width High

Address setup time

70

45

20

0

tAH

Address hold time

45

20

0

tDS

Data setup time

tDH

Data hold time

tCESC

tDF

CE setup time before command write

Output disable time (Note 1)

Total erase time in auto chip erase

Total erase time in auto sector erase

Total programming time in auto verify

(Byte Program time)

0

20

24

8

tAETC

tAETB

tAVT

3(TYP.)

1(TYP.)

7

s

210

us

tBAL

Sector address load time

CE Hold Time

100

0

us

ns

us

ms

tCH

tCS

CE setup to WE going low

Voltage Transition Time

0

tVLHT

tOESP

tWPP1

tWPP2

4

OE Setup Time to WE Active

Write pulse width for sector protect

Write pulse width for sector unprotect

4

10

12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2. The test conditin of MX29F002T/B-55 : VCC=5V ± 5%,CL=50pf,VIH/VIL=3.0V/0V

VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=-2mA

TA= 0^oC TO 70^oC

REV. 1.5, MAR. 28, 2005

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20

MX29F002/002N T/B

AC CHARACTERISTICS

29F002T/B-70 29F002T/B-90 29F002T/B-12

SYMBOL PARAMETER

MIN.

0

MAX. MIN.

MAX.

UNIT

ns

s

tOES

tCWC

tCEP

tCEPH1

tCEPH2

tAS

OE setup time

0

Command programming cycle

WE programming pulse width

WE programming pulse width High

Address setup time

70

45

20

0

90

120

45

50

20

0

tAH

Address hold time

45

30

0

45

50

tDS

Data setup time

45

50

tDH

Data hold time

0

tCESC

tDF

CE setup time before command write

Output disable time (Note 1)

Total erase time in auto chip erase

Total erase time in auto sector erase

Total programming time in auto verify

(Byte Program time)

0

30

40

tAETC

tAETB

tAVT

3(TYP.) 24

1(TYP.) 8

3(TYP.) 24

1(TYP.)

7

8

1(TYP.)

7

8

s

7

210

us

tBAL

Sector address load time

CE Hold Time

100

0

100

0

100

0

us

ns

us

ms

tCH

tCS

CE setup to WE going low

Voltage Transition Time

0

tVLHT

tOESP

tWPP1

tWPP2

4

OE Setup Time to WE Active

Write pulse width for sector protect

Write pulse width for sector unprotect

4

10

12

10

12

10

12

NOTES:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

REV. 1.5, MAR. 28, 2005

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21

MX29F002/002N T/B

SWITCHING TEST CIRCUITS

DEVICE UNDER

TEST

1.6K ohm

+5V

CL

1.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=100pF Including jig capacitance

CL=50pF for MX29F002T/B-55

SWITCHING TEST WAVEFORMS(I) for speed grade 70ns max.

2.4V

2.0V

TEST POINTS

0.8V

0.45V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are equal to or less than 20ns.

SWITCHING TEST WAVEFORMS(II) for speed grade 55ns(MX29F002T/B-55)

3.0V

TEST POINTS

1.5V

0V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 3.0V for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

REV. 1.5, MAR. 28, 2005

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22

MX29F002/002N T/B

COMMAND WRITE TIMING WAVEFORM

VCC

5V

VIH

ADD

ADD Valid

A0~17

VIL

tAH

tAS

VIH

VIL

WE

tOES

tCEPH1

tCEP

tCWC

VIH

VIL

CE

OE

tCS

tCH

tDH

VIH

VIL

tDS

VIH

VIL

DATA

Q0-7

DIN

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P/N: PM0547

23

MX29F002/002N T/B

AUTOMATIC PROGRAMMING TIMING WAVEFORM

verified by DATA polling and toggle bit checking after

automaticverificationstarts. DeviceoutputsDATAduring

programming and DATA after programming on Q7.(Q6 is

fortogglebit;seetogglebit,DATApolling,timingwaveform)

Onebytedataisprogrammed. Verifyinfastalgorithmand

additionalprogrammingbyexternalcontrolarenotrequired

because these operations are executed automatically by

internal control circuit. Programming completion can be

AUTOMATIC PROGRAMMING TIMING WAVEFORM

Vcc 5V

A11~A17

ADD Valid

2AAH

555H

ADD Valid

tAVT

A0~A10

WE

555H

tAS

tCWC

tCEPH1

tAH

tCESC

CE

OE

tCEP

tDS tDH

tDF

DATA

Q0~Q1,Q2

,Q4(Note 1)

Command In

Data In

DATA polling

DATA

Command In

Q7

Command #A0H

Command #AAH

Command #55H

tOE

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Tin=Timing-limit bit, Q3: Time-out bit

REV. 1.5, MAR. 28, 2005

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MX29F002/002N T/B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

Verify Byte Ok

Command

YES

NO

.

Q5 = 1

Reset

Auto Program Completed

YES

Auto Program Exceed

Timing Limit

REV. 1.5, MAR. 28, 2005

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25

MX29F002/002N T/B

TOGGLE BIT ALGORITHM

START

Read Q7~Q0

(Note 1)

NO

Toggle Bit Q6

=Toggle?

YES

NO

Q5=1?

YES

(Note 1,2)

Read Q7~Q0 Twice

Toggle Bit Q6

=Toggle?

YES

Program/Erase Operation Not

Program/Erase Operation Complete

Complete, Write Reset Command

Note:

1. Read toggle bit Q6 twice to determine whether or not it is toggle. See test.

2. Recheck toggle bit Q6 because it may stop toggling as Q5 changes to "1". See test.

REV. 1.5, MAR. 28, 2005

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26

MX29F002/002N T/B

AUTOMATIC CHIPE RASETIMING WAVEFORM

All data in chip are erased. External erase verify is not

requiredbecausedatais erasedautomaticallybyinternal

control circuit. Erasure completion can be verified by

DATApollingandtogglebitcheckingafterautomaticerase

starts. Deviceoutputs0duringerasureand1aftererasure

on Q7.(Q6 is for toggle bit; see toggle bit, DATA polling,

timingwaveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM

Vcc 5V

A11~A17

555H

2AAH

555H

2AAH

555H

A0~A10

WE

555H

tAS

tCWC

tAH

tCEPH1

tAETC

CE

OE

tCEP

tDS tDH

Q0,Q1,

Command In

Q4(Note 1)

DATA polling

Command In

Q7

Command #80H

Command #AAH

Command #55H

Command #10H

Command #AAH

Command #55H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

REV. 1.5, MAR. 28, 2005

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27

MX29F002/002N T/B

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

DATA Polling

Command

Q7 = 1

YES

NO

.

Q5 = 1

Auto Chip Erase Completed

YES

Reset

Auto Chip Erase Exceed

Timing Limit

REV. 1.5, MAR. 28, 2005

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28

MX29F002/002N T/B

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

after automatic erase starts. Device outputs 0 during

erasureand1aftererasureonQ7.(Q6isfortogglebit;see

toggle bit, DATA polling, timing waveform)

SectordataindicatedbyA13toA17 areerased. External

eraseverificationisnotrequiredbecausedataareerased

automatically by internal control circuit. Erasure comple-

tioncanbeverifiedbyDATApollingandtogglebitchecking

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Vcc 5V

Sector

Addressn

Sector

Address0

Sector

Address1

A13~A17

555H

tAS

2AAH

A0~A10

tCWC

tAH

WE

CE

tCEPH1

tBAL

tAETB

tCEP

tDS

OE

tDH

Command

In

Command

In

Q0,Q1,

Command

In

Command

In

Command

In

Command

In

Q4(Note 1)

DATA polling

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Q7

Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H

(Q0~Q7)

Command #30H

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

REV. 1.5, MAR. 28, 2005

P/N: PM0547

29

MX29F002/002N T/B

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Toggle Bit Checking

Q6 Toggled ?

Invalid Command

YES

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

NO

Last Sector

to Erase

YES

NO

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

NO

Q5 = 1

DATA Polling

Q7 = 1

YES

Reset

Auto Sector Erase Completed

Auto Sector Erase Exceed

Timing Limit

REV. 1.5, MAR. 28, 2005

P/N: PM0547

30

MX29F002/002N T/B

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Continue Erase

.

Another

NO

Erase Suspend ?

YES

REV. 1.5, MAR. 28, 2005

P/N: PM0547

31

MX29F002/002N T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V

A1

A6

12V

5V

A9

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 1

WE

CE

tOESP

Data

01H

F0H

tOE

A17-A13

Sector Address

REV. 1.5, MAR. 28, 2005

P/N: PM0547

32

MX29F002/002N T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V

A1

12V

5V

A9

A6

tVLHT

Verify

12V

5V

OE

tVLHT

tWPP 2

WE

CE

tOESP

Data

00H

F0H

tOE

REV. 1.5, MAR. 28, 2005

P/N: PM0547

33

MX29F002/002N T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Set Up Sector Addr

(A17,A16,A15,A14,A13)

PLSCNT=1

OE=VID,A9=VID,CE=VIL

A6=VIL

Activate WE Pulse

Time Out 10us

Set WE=VIH, CE=OE=VIL

A9 should remain VID

Read from Sector

Addr=SA, A1=1

No

Data=01H?

PLSCNT=32?

.

Yes

Device Failed

Yes

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Sector Protection

Complete

REV. 1.5, MAR. 28, 2005

P/N: PM0547

34

MX29F002/002N T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V

START

Protect All Sectors

PLSCNT=1

Set OE=A9=VID

CE=VIL,A6=1

Activate WE Pulse

Time Out 12ms

Increment

PLSCNT

Set OE=CE=VIL

A9=VID,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

PLSCNT=1000?

Increment

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

REV. 1.5, MAR. 28, 2005

P/N: PM0547

35

MX29F002/002N T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE

tCEP

WE

* See the following Note!

CE

Don't care

(Note 2)

Data

01H

F0H

tOE

A17-A13

Sector Address

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection

for a system without 12V provided.

Note2: Except F0H

REV. 1.5, MAR. 28, 2005

P/N: PM0547

36

MX29F002/002N T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE

tCEP

WE

* See the following Note!

CE

Don't care

(Note 2)

Data

F0H

00H

tOE

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection

for a system without 12V provided.

Note2: Except F0H

REV. 1.5, MAR. 28, 2005

P/N: PM0547

37

MX29F002/002N T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command(Table1)

Set Up Sector Addr

(A17,A16,A15,A14,A13)

OE=VIH,A9=VIH

CE=VIL,A6=VIL

Activate WE Pulse to start

Data don't care

Toggle bit checking

Q6 not Toggled

No

Yes

Increment PLSCNT

Set CE=OE=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

No

Data=01H?

Yes

PLSCNT=32?

Yes

.

Device Failed

Yes

Protect Another

Sector?

No

Write Reset Command

Sector Protection

Complete

REV. 1.5, MAR. 28, 2005

P/N: PM0547

38

MX29F002/002N T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command (Table 1)

Set OE=A9=VIH

CE=VIL,A6=1

Activate WE Pulse to start

Data don't care

No

Toggle bit checking

Q6 not Toggled

Increment

PLSCNT

Yes

Set OE=CE=VIL

A9=VIH,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

Increment

PLSCNT=1000?

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect the whole chip, all sectors should be protected in advance.

REV. 1.5, MAR. 28, 2005

P/N: PM0547

39

MX29F002/002N T/B

ID CODE READ TIMING WAVEFORM MODE

VCC

5V

VID

ADD

A9

VIH

VIL

ADD

AD

tACC

A1 VIH

VIL

ADD

A2-A8

VIH

A10-A17 ^VIL

CE

VIH

VIL

VIH

VIL

tCE

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q7

DATA OUT

C2H

DATA OUT

B0h/34h

REV. 1.5, MAR. 28, 2005

P/N: PM0547

40

MX29F002/002N T/B

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

Access Time Operating Current Standby Current

Temperature

Range

PACKAGE

(ns)

55

(mA)

30

MAX.(uA)

MX29F002TPC-55

MX29F002TPC-70

MX29F002TPC-90

MX29F002TPC-12

MX29F002TTC-55

5

0^oC~70^oC

32 Pin PDIP

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

32 Pin PDIP

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

32 Pin PDIP

32 Pin TSOP

(Normal Type)

70

30

90

30

120

55

30

MX29F002TTC-70

MX29F002TTC-90

MX29F002TTC-12

70

90

30

5

0^oC~70^oC

120

MX29F002TQC-55

MX29F002TQC-70

MX29F002TQC-90

MX29F002TQC-12

MX29F002BPC-55

MX29F002BPC-70

MX29F002BPC-90

MX29F002BPC-12

MX29F002BTC-55

55

70

30

5

0^oC~70^oC

90

120

55

70

90

120

55

MX29F002BTC-70

MX29F002BTC-90

MX29F002BTC-12

70

90

30

5

0^oC~70^oC

120

MX29F002BQC-55

MX29F002BQC-70

MX29F002BQC-90

MX29F002BQC-12

MX29F002NTPC-55

MX29F002NTPC-70

MX29F002NTPC-90

MX29F002NTPC-12

MX29F002NTTC-55

55

70

30

5

0^oC~70^oC

90

120

55

70

90

120

55

REV. 1.5, MAR. 28, 2005

P/N: PM0547

41

MX29F002/002N T/B

PART NO.

Access Time Operating Current Standby Current

Temperature

Range

PACKAGE

(ns)

(mA)

MAX.(uA)

MX29F002NTTC-70

MX29F002NTTC-90

MX29F002NTTC-12

70

30

5

0^oC~70^oC

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

32 Pin PDIP

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

32 Pin PDIP

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

32 Pin PDIP

90

30

5

0^oC~70^oC

120

MX29F002NTQC-55

MX29F002NTQC-70

MX29F002NTQC-90

MX29F002NTQC-12

MX29F002NBPC-55

MX29F002NBPC-70

MX29F002NBPC-90

MX29F002NBPC-12

MX29F002NBTC-55

55

70

30

5

0^oC~70^oC

90

120

55

70

90

120

55

MX29F002NBTC-70

MX29F002NBTC-90

MX29F002NBTC-12

70

90

30

5

0^oC~70^oC

120

MX29F002NBQC-55

MX29F002NBQC-70

MX29F002NBQC-90

MX29F002NBQC-12

MX29F002TPI-70

MX29F002TPI-90

MX29F002TPI-12

MX29F002TTI-70

55

70

30

45

5

0^oC~70^oC

90

120

70

0^oC~70^oC

-40^oC~85^oC

90

120

70

MX29F002TTI-90

MX29F002TTI-12

90

45

5

-40^oC~85^oC

120

IMX29F002TQI-70

MX29F002TQI-90

MX29F002TQI-12

IMX29F002BPI-70

MX29F002BPI-90

MX29F002BPI-12

70

90

45

5

-40^oC~85^oC

120

70

90

120

REV. 1.5, MAR. 28, 2005

P/N: PM0547

42

MX29F002/002N T/B

PART NO.

Access Time Operating Current Standby Current

Temperature

Range

PACKAGE

(ns)

(mA)

MAX.(uA)

IMX29F002BTI-70

MX29F002BTI-90

MX29F002BTI-12

70

45

5

-40^oC~85^oC

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

32 Pin PDIP

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

32 Pin PDIP

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin TSOP

(Normal Type)

32 Pin PLCC

90

45

5

-40^oC~85^oC

120

MX29F002BQI-70

MX29F002BQI-90

MX29F002BQI-12

MX29F002NTPI-70

MX29F002NTPI-90

MX29F002NTPI-12

MX29F002NTTI-70

70

90

45

5

-40^oC~85^oC

120

70

90

120

70

MX29F002NTTI-90

MX29F002NTTI-12

90

45

5

-40^oC~85^oC

120

MX29F002NTQI-70

MX29F002NTQI-90

MX29F002NTQI-12

MX29F002NBPI-70

MX29F002NBPI-90

MX29F002NBPI-12

MX29F002NBTI-70

70

90

45

5

-40^oC~85^oC

120

70

90

120

70

MX29F002NBTI-90

MX29F002NBTI-12

90

45

5

-40^oC~85^oC

120

MX29F002NBQI-70

MX29F002NBQI-90

MX29F002NBQI-12

70

90

45

5

-40^oC~85^oC

120

REV. 1.5, MAR. 28, 2005

P/N: PM0547

43

MX29F002/002N T/B

PART NO.

Access Time Operating Current Standby Current

Temperature

Range

PACKAGE

(ns)

(mA)

MAX.(uA)

MX29F002TTC-70G

MX29F002TTC-90G

MX29F002BTC-70G

MX29F002BTC-90G

MX29F002TQC-70G

MX29F002TQC-90G

MX29F002BQC-70G

MX29F002BQC-90G

MX29F002TPC-70G

MX29F002TPC-90G

MX29F002BPC-70G

MX29F002BPC-90G

MX29F002TPI-70G

MX29F002TPI-90G

MX29F002BPI-70G

MX29F002BPI-90G

70

30

5

0^oC~70^oC

32 Pin TSOP

(Pb-free)

90

70

90

70

90

70

90

70

90

70

90

70

90

70

90

30

45

5

0^oC~70^oC

-40^oC~85^oC

32 Pin TSOP

(Pb-free)

32 Pin TSOP

(Pb-free)

32 Pin TSOP

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

REV. 1.5, MAR. 28, 2005

P/N: PM0547

44

MX29F002/002N T/B

PART NO.

Access Time Operating Current Standby Current

Temperature

Range

PACKAGE

(ns)

(mA)

MAX.(uA)

MX29F002NTTC-70G

MX29F002NTTC-90G

MX29F002NBTC-70G

MX29F002NBTC-90G

MX29F002NTQC-70G

MX29F002NTQC-90G

MX29F002NBQC-70G

MX29F002NBQC-90G

MX29F002NTPC-70G

MX29F002NTPC-90G

MX29F002NBPC-70G

MX29F002NBPC-90G

70

30

5

0^oC~70^oC

32 Pin TSOP

(Pb-free)

90

70

90

70

90

70

90

70

90

70

90

30

5

0^oC~70^oC

32 Pin TSOP

(Pb-free)

32 Pin TSOP

(Pb-free)

32 Pin TSOP

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PLCC

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

32 Pin PDIP

(Pb-free)

REV. 1.5, MAR. 28, 2005

P/N: PM0547

45

MX29F002/002N T/B

ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

TYP.(2)

PARAMETER

MIN.

MAX.(3)

UNITS

Sector Erase Time

1

3

8

s

Chip Erase Time

24

Byte Programming Time

Chip Programming Time

Erase/Program Cycles

7

210

10.5

us

3.5

sec

Cycles

100,000

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25° C, 5V.

3.Maximum values measured at 25°C, 4.5V.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

13.5V

Vcc + 1.0V

+100mA

-1.0V

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

DATA RETENTION

PARAMETER

MIN.

UNIT

DataRetentionTime

20

Years

REV. 1.5, MAR. 28, 2005

P/N: PM0547

46

MX29F002/002N T/B

PACKAGE INFORMATION

REV. 1.5, MAR. 28, 2005

P/N: PM0547

47

MX29F002/002N T/B

REV. 1.5, MAR. 28, 2005

P/N: PM0547

48

MX29F002/002N T/B

REV. 1.5, MAR. 28, 2005

P/N: PM0547

49

MX29F002/002N T/B

REVISION HISTORY

Revision Description

Page

Date

1.0

1.Removed "Advanced Information" datasheet marking and

P1

DEC/27/1999

contain information on products in full production

2.The modification summary of Revision 0.9.8 to Revision 1.0:

2-1.Program/erase cycle times:10K cycles-->100K cycles

2-2.To add data retention 20 years

P1,46

2-3.To add industrial grade range from "Read Mode" to "Full Range"

2-4.To remove A9 from "timing waveform for sector protection for

system without 12V"

P17,19,21,41-43

P36

To remove A9 from "timing waveform for chip unprotection for

system without 12V"

P37

2-5.Multi-sectorerasetime-out:30ms-->30us,tBAL:80us-->100us

Modified "Package Information"

1. Correctedtypingerror

1. Changedpartno. fromMX29F002/002NtoMX29F002/002NT/B

1. Added Pb-free option for PDIP package

1. Added Pb-free option for all commercial-grade package with 70ns & 90ns P44,45

P8,20,21

P45~47

All

P43

1.1

1.2

1.3

1.4

1.5

JUN/14/2001

JUN/11/2002

NOV/11/2002

NOV/08/2004

MAR/28/2005

REV. 1.5, MAR. 28, 2005

P/N: PM0547

50

MX29F002/002N T/B

M

ACRONIX

INTERNATIONAL

CO.,

LTD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX29F002BPI-70G
厂家：	MACRONIX INTERNATIONAL
描述：	2M-BIT [256K x 8] CMOS FLASH MEMORY 2M- BIT [ 256K ×8 ] CMOS FLASH MEMORY
文件：	总51页 (文件大小：609K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29F002BPI-70G [Macronix]

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