MX29F016T4C-90 [Macronix]
16M-BIT [2M X 8] CMOS EQUAL SECTOR FLASH MEMORY; 16M - BIT [2M ×8 ] CMOS EQUAL部门FLASH MEMORY
| 型号： | MX29F016T4C-90 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 16M-BIT [2M X 8] CMOS EQUAL SECTOR FLASH MEMORY |
| 文件： | 总37页 (文件大小：848K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX29F016
16M-BIT[2MX8]CMOSEQUALSECTORFLASHMEMORY
FEATURES
• Single power supply 5V operation for read, erase and
program
• Fast access time: 90/120ns
• Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
• Low power consumption
- 30mA maximum active current
• Group Sector protect/unprotect for 5V/12V system.
• Group Sector protection
- 0.2uA typical standby current
- Hardware sector protect/unprotect method for each
group which consists of two adjacent sectors
- Temporary group sector unprotect allows code
changes in previously locked sectors
• 100,000minimumerase/programcycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 40-pin TSOP, 44-pin SOP, 48-pin TSOP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase:32 equal sector with of 64KByte each
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically program and verify data at specified
address
• Erase suspend/Erase Resume
- Suspends an erase operation to read data from,
or program data to, another sector that is not being
erased, then resumes the erase.
GENERAL DESCRIPTION
TheMX29F016isa16-megabitFlashmemoryorganized
as 2M bytes of 8 bits. MXIC's Flash memories offer the
most cost-effective and reliable read/write non-volatile
randomaccessmemory. TheMX29F016ispackagedin
40-pinTSOPor44-pinSOP,48-pinTSOP. Itisdesigned
tobereprogrammedanderasedinsystemorinstandard
EPROM programmers.
during erase and programming, while maintaining
maximum EPROM compatibility.
MXIC Flash technology reliably stores memory
contents even after 100,000 erase and program
cycles. The MXIC cell is designed to optimize the
erase and program mechanisms. In addition, the
combination of advanced tunnel oxide processing
and low internal electric fields for erase and
programming operations produces reliable cycling.
The MX29F016 uses a 5.0V±10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The standard MX29F016 offers access time as fast as
90ns,allowingoperationofhigh-speedmicroprocessors
without wait states. To eliminate bus contention, the
MX29F016 has separate chip enable (CE) and output
enable (OE ) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F016 uses a command register to manage this
functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to
100 milliamps on address and data pin from -1V to
VCC + 1V.
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1
MX29F016
PIN CONFIGURATIONS
40 TSOP (Standard Type) (10mm x 20mm)
48 TSOP (Standard Type) (12mm x 20mm)
1
2
3
4
5
6
7
8
1
NC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
A20
NC
WE
OE
RY/BY
Q7
Q6
Q5
Q4
VCC
VSS
VSS
Q3
Q2
Q1
Q0
A0
A1
A2
A3
NC
NC
A20
NC
WE
OE
RY/BY
Q7
A19
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
2
A18
A19
A18
A17
A16
A15
A14
A13
A12
CE
VCC
NC
RESET
A11
A10
A9
A8
A7
A6
A5
A4
NC
NC
3
A17
4
A16
5
A15
6
A14
7
Q6
A13
9
8
Q5
A12
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
9
Q4
CE
10
VCC
VSS
VSS
Q3
VCC
MX29F016
MX29F016
11
NC
12
RESET
13
A11
14
Q2
A10
15
A9
16
A8
17
A7
18
A6
19
A5
20
A4
Q1
Q0
A0
A1
A2
A3
44 SOP
PIN DESCRIPTION
VCC
CE
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
RESET
A11
A10
A9
SYMBOL
A0~A20
Q0~Q7
CE
PIN NAME
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A12
A13
A14
A15
A16
A17
A18
A19
NC
NC
A20
NC
WE
OE
RY/BY
Q7
Address Input
8 Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
A8
A7
A6
A5
WE
A4
NC
NC
A3
A2
A1
A0
Q0
Q1
Q2
OE
RESET
RY/BY
VCC
Hardware Reset Pin, Active Low
Read/BusyOutput
+5.0V single power supply
DeviceGround
Q6
Q5
Q4
VCC
VSS
Q3
VSS
VSS
NC
Pin Not Connected Internally
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MX29F016
MX29F016SECTORADDRESSTABLE
LOGICSYMBOL
Group Sector A20 A19 A18 A17 A16 Address Range
Sector
21
8
A0-A20
SGA0 SA0
SGA0 SA1
SGA0 SA2
SGA0 SA3
SGA1 SA4
SGA1 SA5
SGA1 SA6
SGA1 SA7
SGA2 SA8
SGA2 SA9
SGA2 SA10
SGA2 SA11
SGA3 SA12
SGA3 SA13
SGA3 SA14
SGA3 SA15
SGA4 SA16
SGA4 SA17
SGA4 SA18
SGA4 SA19
SGA5 SA20
SGA5 SA21
SGA5 SA22
SGA5 SA23
SGA6 SA24
SGA6 SA25
SGA6 SA26
SGA6 SA27
SGA7 SA28
SGA7 SA29
SGA7 SA30
SGA7 SA31
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
Q0-Q7
CE
OE
WE
RY/BY
RESET
Legend:SA=Sector Address ; SGA=Sector Group Address
Note:All sectors are 64 Kbytes in size.
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MX29F016
BLOCK DIAGRAM
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
CE
OE
WE
MACHINE
(WSM)
LOGIC
STATE
MX29F016
FLASH
ADDRESS
LATCH
REGISTER
ARRAY
ARRAY
A0-A20
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q7
I/O BUFFER
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MX29F016
automatically pre-program and verify the entire array.
Then the device automatically times the erase pulse
width, provides the erase verification, and counts the
number of sequences. A status bit toggling between
consecutive read cycles provides feedback to the user
as to the status of the programming operation.
AUTOMATIC PROGRAMMING
TheMX29F016isbyteprogrammableusingtheAutomatic
Programming algorithm. The Automatic Programming
algorithmmakestheexternalsystemdonotneedtohave
time out sequence nor to verify the data programmed.
Thetypicalchipprogrammingtimeatroomtemperature
of the MX29F016 is less than 15 seconds.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches address and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE .
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typicalerasureatroomtemperatureisaccomplishedin
less than 19 seconds. The Automatic Erase algorithm
automaticallyprogramstheentirearraypriortoelectrical
erase. Thetimingandverificationofelectricaleraseare
controlled internally within the device.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F016
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.
AUTOMATIC SECTOR ERASE
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspendcommand.AfterEraseSuspendiscompleted,
the device stays in read mode. After the state machine
hascompleteditstask,itwillallowthecommandregister
to respond to its full command set.
The MX29F016 is sector(s) erasable using MXIC's
Auto Sector Erase algorithm. Sector erase modes
allow sectors of the array to be erased in one erase
cycle. The Automatic Sector Erase algorithm
automatically programs the specified sector(s) prior to
electrical erase. The timing and verification of
electrical erase are controlled internally within the
device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm require the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
timestheprogrammingpulsewidth,providestheprogram
verification, and counts the number of sequences. A
statusbitsimilartoDATApollingandastatusbittoggling
between consecutive read cycles, provide feedback to
the user as to the status of the programming operation.
AUTOMATIC ERASE ALGORITHM
MXIC's Automatic Erase algorithm requires the user to
writecommandstothecommandregisterusingstandard
microprocessor write timings. The device will
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MX29F016
TABLE1. SOFTWARE COMMAND DEFINITIONS
First Bus
Cycle
Second Bus Third Bus
Cycle Cycle
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Command
Bus
Cycle
Addr
Data Addr Data Addr Data Addr Data Addr Data Addr Data
Reset
1
1
4
4
XXXH F0H
RA RD
555H AAH 2AAH 55H 555H 90H ADI
Read
Read Silicon ID
Sector Group Protect
Verify
DDI
555H AAH 2AAH 55H 555H 90H SGA 00H
X02H 01H
Porgram
4
6
6
1
1
555H AAH 2AAH 55H 555H A0H PA
PD
Chip Erase
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
555H 10H
SA 30H
Sector Erase
Sector Erase Suspend
Sector Erase Resume
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
XXXH B0H
XXXH 30H
Note:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code.
(Refer to Table 3)
DDI = Data of Device identifier : C2H for manufacture code, ADH for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2.PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address of the sector to be erased.
SGA = Address of the Sector Group Address bits A18-A20 select a uniqul sector group.
3.The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 .
Address bit A11~A20=X=Don't care for all address commands except for Program Address (PA) and Sector
Address (SA). Write Sequence may be initiated with A11~A20 in either state.
4.For Sector Group Protect Verify Operation : If read out data is 01H, it means the sector has been protected.If read
out data is 00H,it means the sector is still not being protected.
COMMAND DEFINITIONS
Device operations are selected by writing specific address
and data sequences into the command register. Writing
incorrect address and data values or writing them in the
improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.
Note that the Erase Suspend (B0H) and Erase Resume
(30H) commands are valid only while the Sector Erase
operation is in progress.
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MX29F016
TABLE 2. MX29F016 BUS OPERATION
Mode
Pins
CE
L
OE
L
WE
H
A0
L
A1
L
A6
X
A9
Q0 ~ Q7
C2H
Read Silicon ID
Manfacturer Code(1)
Read Silicon ID
Device Code(1)
Read
VID(2)
L
L
H
H
L
X
VID(2)
ADH
L
H
L
L
L
L
H
X
H
L
A0
X
A1
X
A6
X
A9
X
DOUT
Standby
X
HIGH Z
HIGH Z
DIN(3)
X
Output Disable
Write
H
X
X
X
X
H
A0
X
A1
X
A6
L
A9
VID(2)
Sector Protect with 12V
system(6)
VID(2)
L
Chip Unprotect with 12V
system(6)
L
L
X
VID(2)
L
X
X
X
X
H
X
H
X
X
VID(2)
VID(2)
X
X
Verify Sector Group Protect
with 12V system
Reset
L
H
X
Code(5)
HIGH Z
X
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 13V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5. Code=00H means unprotected.
Code=01H means protected.
A20~A18=Sector Group address for protect.
6. Refer to sector protect/unprotect algorithm and waveform.
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MX29F016
READ/RESET COMMAND
SET-UP AUTOMATIC CHIP/SECTOR ERASE
The read or reset operation is initiated by writing the
read/reset command sequence into the command
register. Microprocessor read cycles retrieve array
data. The device remains enabled for reads until the
command register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up"command80H. Twomore "unlock"writecycles
are then followed by the chip erase command 10H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zeropattern,aself-timedchiperaseandverifybegin.
Theeraseandverifyoperationsarecompletedwhenthe
data on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
If program-fail or erase-fail happen, the write of F0H will
resetthedevicetoaborttheoperation. Avalidcommand
must then be written to place the device in the desired
state.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmerstypicallyaccesssignaturecodesbyraising
A9toahighvoltage. However,multiplexinghighvoltage
onto address lines is not generally desired system
design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erasemarginhasbeenachievedforthememoryarray(no
erase verification command is required).
TheMX29F016containsaSilicon-ID-Readoperationto
supplement traditional PROM programming
methodology. The operation is initiated by writing the
read silicon ID command sequence into the command
register. Followingthecommandwrite,areadcyclewith
A1=VIL,A0=VILretrievesthemanufacturercodeofC2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of ADH for MX29F016.
IftheEraseoperationwasunsuccessful, thedataonQ5
is"1"(seeTable4),indicatingtheeraseoperationexceed
internal timing limit.
Theautomaticerasebeginsontherisingedgeofthelast
WE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. SILICON ID CODE
Pins
A0
A1
Q7
1
Q6
1
Q5
0
Q4
0
Q3
0
Q2
0
Q1
1
Q0
0
Code(Hex)
C2H
Manufacture code
Device code for MX29F016
VIL
VIL
VIH VIL
1
0
1
0
1
1
0
1
ADH
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MX29F016
SECTOR ERASE COMMANDS
The Automatic Sector Erase does not require the
device to be entirely pre-programmed prior to
executing the Automatic Set-up Sector Erase
command and Automatic Sector Erase command.
Upon executing the Automatic Sector Erase
command, the device will automatically program and
verify the sector(s) memory for an all-zero data
pattern. The system is not required to provide any
control or timing during these operations.
When using the Automatic Sector Erase algorithm,
note that the erase automatically terminates when
adequate erase margin has been achieved for the
memory array (no erase verification command is
required). Sector erase is a six-bus cycle operation.
There are two "unlock" write cycles. These are
followed by writing the set-up command 80H. Two
more "unlock" write cycles are then followed by the
sector erase command 30H. The sector address is
latched on the falling edge of WE, while the
command(data) is latched on the rising edge of WE.
Sector addresses selected are loaded into internal
register on the sixth falling edge of WE. Each
successive sector load cycle started by the falling
edge of WE must begin within 80ms from the rising
edge of the preceding WE. Otherwise, the loading
period ends and internal auto sector erase cycle
starts. (Monitor Q3 to determine if the sector erase
timer window is still open, see section Q3, Sector
Erase Timer.) Any command other than Sector
Erase(30H) or Erase Suspend(B0H) during the time-
out period resets the device to read mode.
When the sector(s) is automatically verified to contain
an all-zero pattern, a self-timed sector erase and
verify begin. The erase and verify operations are
complete when the data on Q7 is "1" and the data on
Q6 stops toggling for two consecutive read cycles, at
which time the device returns to the Read mode. The
system is not required to provide any control or timing
during these operations.
Table 4. Write Operation Status
Status
Q7
Q6
Q5
0
Q3
0
Q2
1
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Q7 Toggle
0
1
Toggle
1
0
1
Toggle
Toggle
(Note1)
Data
Erase Suspend Read
0
0
In Progress
(Erase Suspended Sector)
Erase Suspend Read
Erase Suspended Mode
Data Data Data Data
(Non-Erase Suspended Sector)
Erase Suspend Program
Q7 Toggle
(Note2)
0
0
1
(Note3)
1
(Non-Erase Suspended Sector)
Byte Program in Auto Program Algorithm
Program/Erase in Auto Erase Algorithm
Q7 Toggle
1
1
1
0
1
0
Exceeded
0
Toggle
N/A
N/A
Time Limits Erase Suspended Mode
Erase Suspend Program
Q7 Toggle
(Non-Erase Suspended Sector)
Notes:
1.Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.
2.Performing successive read operations from any address will cause Q6 to toggle.
3.Reading the byte address being programmed while in the erase-suspend program mode will indicate logic "1" at the Q2 bit.
However, successive reads from the erase-suspended sector will cause Q2 to toggle.
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MX29F016
If the program opetation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceedinternaltiminglimit.Theautomaticprogramming
operation is completed when the data read on Q6 stops
togglingfortwoconsecutivereadcyclesandthedataon
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(no program verify command is required).
ERASE SUSPEND
Thiscommandonlyhasmeaningwhilethestatemachine
is executing Automatic Sector Erase operation, and
thereforewillonlyberespondedduringAutomaticSector
Erase operation. However, When the Erase Suspend
commandiswrittenduringthesectorerasetime-out,the
device immediately terminates the time-out period and
suspends the erase operation. After this command has
been executed, the command register will initiate erase
suspend mode. The state machine will return to read
mode automatically after suspend is ready. At this time,
state machine only allows the command register to
respondtotheReadMemoryArray, EraseResumeand
program commands.
DATA POLLING-Q7
The MX29F016 also features Data Polling as a method
toindicatetothehostsystemthattheAutomaticProgram
orErasealgorithmsareeitherinprogressorcompleted.
While the Automatic Programming algorithm is in
operation, anattempttoreadthedevicewillproducethe
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an
attempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
risingedgeofthefourth WEpulseofthefourwritepulse
sequences for automatic program.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended blocks.
ERASE RESUME
While the Automatic Erase algorithm is in operation, Q7
willread"0"untiltheeraseoperationiscompeted. Upon
completion of the erase operation, the data on Q7 will
read"1". TheDataPollingfeatureisvalidaftertherising
edge of the sixth WE pulse of six write pulse sequences
for automatic chip/sector erase.
This command will cause the command register to clear
thesuspendstateandreturnbacktoSectorErasemode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
otherconditions.AnotherEraseSuspendcommandcan
be written after the chip has resumed erasing.
The Data Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)
SET-UP AUTOMATIC PROGRAM
COMMANDS
To initiate Automatic Program mode, A three-cycle
commandsequenceisrequired. Therearetwo"unlock"
writecycles. ThesearefollowedbywritingtheAutomatic
Program command A0H.
Once the Automatic Program command is initiated, the
next WE pulse causes a transition to an active
programming operation. Addresses are latched on the
fallingedge,and dataareinternally latchedon therising
edgeoftheWEpulse. TherisingedgeofWEalsobegins
the programming operation. The system is not required
to provide further controls or timings. The device will
automatically provide an adequate internally generated
program pulse and verify margin.
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MX29F016
Q6:Toggle BIT I
Q2 toggles when the system reads at addresses within
thosesectorsthathavebeenselectedforerasure. (The
system may use either OE or CE to control the read
cycles.) ButQ2cannotdistinguishwhetherthesectoris
actively erasing or is erase-suspended. Q6, by
comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
statusbitsarerequiredforsectorsandmodeinformation.
Refer to Table 4 to compare outputs for Q2 and Q6.
Toggle Bit I on Q6 indicates whether an Automatic
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE pulse in the
command sequence(prior to the program or erase
operation), and during the sector time-out.
During an Automatic Program or Erase algorithm
operation,successivereadcyclestoanyaddresscause
Q6 to toggle. The system may use either OE or CE to
controlthereadcycles.Whentheoperationiscomplete,
Q6 stops toggling.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determinewhetheratogglebitistoggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completedtheprogramoreraseoperation. Thesystem
can read array data on Q7-Q0 on the following read
cycle.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Q6 toggles
and returns to reading array data. If not all selected
sectors are protected, the Automatic Erase algorithm
erasestheunprotectedsectors,andignorestheselected
sectors that are protected.
The system can use Q6 and Q2 together to determine
whetherasectorisactivelyerasingoriserasesuspended.
Whenthedeviceisactivelyerasing(thatis,theAutomatic
Erase algorithm is in progress), Q6 toggling. When the
device enters the Erase Suspend mode, Q6 stops
toggling. However, the system must also use Q2 to
determinewhichsectorsareerasingorerase-suspended.
Alternatively, the system can use Q7.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
alsoshould notewhetherthevalueofQ5ishigh(seethe
sectiononQ5). Ifitis,thesystemshouldthendetermine
again whether the toggle bit is toggling, since the toggle
bit may have stopped toggling just as Q5 went high. If
the toggle bit is no longer toggling, the device has
successfuly completed the program or erase operation.
If it is still toggling, the device did not complete the
operation successfully, and the system must write the
reset command to return to reading array data.
If a program address falls within a protected sector, Q6
togglesforapproximately2usaftertheprogramcommand
sequence is written, then returns to reading array data.
Q6 also toggles during the erase-suspend-program
mode, and stops toggling once the Automatic Program
algorithm is complete.
Theremainingscenarioisthatsysteminitiallydetermines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks. Inthiscase,thesystemmuststartatthebeginning
of the algorithm when it returns to determine the status
of the operation.
Table 4 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether a particular sector is actively eraseing (that is,
the Automatic Erase alorithm is in process), or whether
thatsectoriserase-suspended. ToggleBitIisvalidafter
the rising edge of the final WE pulse in the command
sequence.
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MX29F016
cycles resulting from VCC power-up and power-down
transition or system noise.
Q5
Exceeded Timing Limits
Q5willindicateiftheprogramorerasetimehasexceeded
the specified limits(internal pulse count). Under these
conditionsQ5willproducea"1". Thistime-outcondition
indicates that the program or erase cycle was not
successfullycompleted. DataPollingandToggleBitare
the only operating functions of the device under this
condition.
TEMPORARYSECTORUNPROTECT
Thisfeatureallowstemporaryunprotectionofpreviously
protectedsectortochangedatain-system.TheTemporary
SectorUnprotectmodeisactivatedbysettingtheRESET
pin to VID(11.5V-12.5V). During this mode, formerly
protected sectors can be programmed or erased as un-
protected sector. Once VID is remove from the RESET
pin,all the previously protected sectors are protected
again.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other
sectors. Write the Reset command sequence to the
device, and then execute program or erase command
sequence. Thisallowsthesystemtocontinuetousethe
other active sectors in the device.
Q3
Sector Erase Timer
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data Polling
and Toggle Bit are valid after the initial sector erase
command sequence.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
If this time-out condition occurs during the byte
programmingoperation,itspecifiesthattheentiresector
containing that byte is bad and this sector maynot be
reused, (other sectors are still functional and can be
reused).
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, Q3 may be
usedtodetermineifthesectorerasetimerwindowisstill
open. If Q3 is high ("1") the internally controlled erase
cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If Q3 is low ("0"), the device will accept
additional sector erase commands. To insure the
command has been accepted, the system software
shouldcheckthestatusofQ3priortoandfollowingeach
subsequent sector erase command. If Q3 were high on
the second status check, the command may not have
been accepted.
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
adevicefailureconditionsincethedevicewasincorrectly
used.
WRITE PULSE "GLITCH" PROTECTION
DATA PROTECTION
Noise pulses of less than 5ns(typical) on CE or WE will
not initiate a write cycle.
The MX29F016 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power
transition. During power up the device automatically
resets the state machine in the Read mode. In addition,
with its control register architecture, alteration of the
memorycontentsonlyoccursaftersuccessfulcompletion
of specific command sequences. The device also
incorporatesseveralfeaturestopreventinadvertentwrite
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or WE = VIH. To initiate a write cycle CE and WE
must be a logical zero while OE is a logical one.
P/N:PM0590
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12
MX29F016
in the system by writing the Read Silicon ID command.
PerformingareadoperationwithA1=VIH,itwillproduce
00H at data outputs(Q0-Q7) for an unprotected sector.
It is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
POWER SUPPLY DECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND.
SECTOR PROTECTION WITH 12V SYSTEM
POWER-UP SEQUENCE
TheMX29F016featureshardwaregroupsectorprotection.
Thisfeaturewilldisablebothprogramanderaseoperations
forthesegroupsectorprotected. Toactivatethismode,
theprogrammingequipmentmustforceVIDonaddress
pin A9 and control pin OE, (suggest VID = 12V) A6 = VIL
andCE=VIL.(seeTable2) Programmingoftheprotection
circuitry begins on the falling edge of the WE pulse and
is terminated on the rising edge. Please refer to group
sector protect algorithm and waveform.
The MX29F016 powers up in the Read only mode. In
addition, thememorycontentsmayonlybealteredafter
successful completion of the predefined command
sequences.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9(withCEandOEatVILandWEatVIH). WhenA1=1,
it will produce a logical "1" code at device output Q0 for
a protected sector. Otherwise the device will produce
00H for the unprotected sector. In this mode, the
addresses, except for A1, are don't care. Address
locationswithA1=VILarereservedtoreadmanufacturer
and device codes.(Read Silicon ID)
It is also possible to determine if the group is protected
in the system by writing a Read Silicon ID command.
PerformingareadoperationwithA1=VIH,itwillproduce
a logical "1" at Q0 for the protected sector.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F016 also features the chip unprotect mode,
so that all sectors are unprotected after chip unprotect
is completed to incorporate any changes in the code. It
is recommended to protect all sectors before activating
chip unprotect mode.
To activate this mode, the programming equipment
must force VID on control pin OE and address pin A9.
The CE pins must be set at VIL. Pins A6 must be set to
VIH.(seeTable2) Refertochipunprotect algorithmand
waveform for the chip unprotect algorithm. The
unprotection mechanism begins on the falling edge of
the WE pulse and is terminated on the rising edge.
It is also possible to determine if the chip is unprotected
P/N:PM0590
REV. 1.3, JUN. 13, 2001
13
MX29F016
CAPACITANCE (TA = 25oC, f = 1.0 MHz)
SYMBOL
CIN
PARAMETER
MIN.
TYP
MAX.
8
UNIT
pF
CONDITIONS
VIN = 0V
Input Capacitance
Output Capacitance
COUT
12
pF
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS (TA = -40°C TO 85°C, VCC = 5V±10%)
SYMBOL PARAMETER
MIN.
TYP
MAX.
1
UNIT
uA
uA
mA
uA
mA
mA
V
CONDITIONS
ILI
ILO
Input Leakage Current
VIN = GND to VCC
VOUT = GND to VCC
CE = VIH
Output Leakage Current
Standby VCC current
±1
1
ISB1
ISB2
ICC1
ICC2
VIL
0.2
5
CE = VCC + 0.3V
IOUT = 0mA, f=1MHz
IOUT = 0mA, f=10MHz
Operating VCC current
30
50
0.8
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-0.3(NOTE 1)
2.0
VIH
VCC + 0.3
0.45
V
VOL
V
IOL = 2.1mA
IOH = -2mA
VOH
2.4
V
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less
than 20 ns
IfVIHisoverthespecifiedmaximumvalue, readoperation
cannot be guaranteed.
AC CHARACTERISTICS (TA = -40oC to 85oC, VCC = 5V±10%)
Read Operations
29F016-90
29F016-12
SYMBOL PARAMETER
MIN. MAX. MIN. MAX.
UNIT
ns
CONDITIONS
CE=OE=VIL
OE=VIL
tACC
tCE
tOE
tDF
Address to Output Delay
90
90
40
30
120
120
50
CE to Output Delay
ns
OE to Output Delay
ns
CE=VIL
OE High to Output Float (Note1)
Address to Output hold
0
0
0
0
30
ns
CE=VIL
tOH
ns
CE=OE=VIL
TEST CONDITIONS:
NOTE:
•
•
•
•
Input pulse levels: 0.45V/2.4V*
1. tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
Input rise and fall times is equal to or less than 20ns
Output load: 1 TTL gate + 100pF *(Including scope and jig)
Reference levels for measuring timing*: 0.8V, 2.0V
P/N:PM0590
REV. 1.3, JUN. 13, 2001
14
MX29F016
NOTICE:
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to
the device. This is a stress rating only and functional
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended period may affect reliability.
RATING
VALUE
Ambient Operating Temperature -40oC to 85oC
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9 & OE
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are
subject to change.
READ TIMING WAVEFORMS
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE
VIL
VIH
WE
tDF
VIL
tOE
VIH
OE
tACC
VIL
tOH
HIGH Z
HIGH Z
VOH
VOL
Outputs
DATA Valid
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS (TA = -40oC to 85oC, VCC = 5V±10%)
SYMBOL
ICC1 (Read)
ICC2
PARAMETER
MIN.
TYP
MAX.
30
UNIT
mA
mA
mA
mA
mA
CONDITIONS
Operating VCC Current
IOUT=0mA, f=1MHz
IOUT=0mA, F=10MHz
In Programming
50
ICC3 (Program)
ICC4 (Erase)
ICCES
50
50
In Erase
VCC Erase Suspend Current
2
CE=VIH, Erase Suspended
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than
20ns.
3. ICCES is specified with the device de-selected. If the
device is read during erase suspend mode, current draw is
the sum of ICCES and ICC1 or ICC2.
2. If VIH is over the specified maximum value, programming
operation cannot be guranteed.
4. All current are in RMS unless otherwise noted.
P/N:PM0590
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15
MX29F016
AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 5V ±10%
Erase/Program Operations
29F016-90
29F016-12
SYMBOL PARAMETER
MIN.
50
90
45
20
20
0
MAX. MIN.
MAX.
UNIT CONDITIONS
tOES
tCWC
tCEP
tCEPH1
tCEPH2
tAS
OE setup time
50
120
50
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Command programming cycle
WE programming pulse width
WE programming pluse width High
WE programming pluse width High
Address setup time
tAH
Address hold time
45
45
0
50
50
0
tDS
Data setup time
tDH
Data hold time
tCESC
tDF
CE setup time before command write
Output disable time (Note 1)
Total erase time in auto chip erase(Note2,3)
0
0
30
32(TYP.) 256
30
tAETC
tAETB
tAVT
32(TYP.)256
Total erase time in auto sector erase(Note2,3) 4(TYP.) 30
Byte programming time in auto verify(Note2,3) 7(TYP.) 300
4(TYP.) 30
s
7(TYP.) 300
us
us
ns
ns
us
us
us
ms
tBAL
Block address load time
80
0
80
0
tCH
CE Hold Time
tCS
CE setup to WE going low
Voltge Transition Time
0
0
tVLHT
tOESP
tWPP1
tWPP2
4
4
OE Setup Time to WE Active
Write pulse width for sector protect
Write pulse width for sector unprotect
4
4
10
12
10
12
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
2. Numbers are sampled, not 100% tested.
3. Typical values are measured at 25oC,VCC=5.0V.
P/N:PM0590
REV. 1.3, JUN. 13, 2001
16
MX29F016
SWITCHING TEST CIRCUITS
DEVICE UNDER
TEST
1.6K ohm
+5V
CL
1.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V
2.0V
TEST POINTS
0.8V
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.
COMMAND WRITE TIMING WAVEFORM
VCC
5V
VIH
VIL
Addresses
ADD Valid
tAH
tAS
VIH
VIL
WE
CE
tOES
tCEPH1
tCEP
tCWC
VIH
VIL
tCS
tCH
tDH
VIH
VIL
OE
tDS
VIH
VIL
Data
DIN
P/N:PM0590
REV. 1.3, JUN. 13, 2001
17
MX29F016
AUTOMATIC PROGRAMMING TIMING WAVEFORM
bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after
programming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform)
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed
automatically by internal control circuit. Programming
completion can be verified by DATA polling and toggle
AUTOMATIC PROGRAMMING TIMING WAVEFORM
Vcc 5V
A11~A20
ADD Valid
2AAH
555H
ADD Valid
tAVT
A0~A10
WE
555H
tAS
tCWC
tCEPH1
tAH
tCESC
CE
OE
tCEP
tDS tDH
tDF
Q0,Q1,
DATA
DATA
Command In
Command In
Command In
Data In
Data In
DATA polling
Q4(Note 1)
DATA
Command In
Command In
Command In
Q7
Command #A0H
Command #55H
Command #AAH
(Q0~Q7)
tOE
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0590
REV. 1.3, JUN. 13, 2001
18
MX29F016
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
NO
Toggle Bit Checking
Q6 not Toggled
YES
.
NO
Invalid
Verify Byte Ok
Command
YES
NO
Q5 = 1
Reset
Auto Program Completed
YES
Auto Program Exceed
Timing Limit
P/N:PM0590
REV. 1.3, JUN. 13, 2001
19
MX29F016
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automaticerasestarts. Deviceoutputs0duringerasure
and1aftererasureonQ7.(Q6isfortogglebit;seetoggle
bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM
Vcc 5V
A11~A20
2AAH
555H
555H
2AAH
555H
A0~A10
WE
555H
tAS
tCWC
tAH
tCEPH1
tCESC
tAETC
CE
OE
tCEP
tDF
tDS tDH
Command In
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
DATA polling
Command In
Command In
Command In
Command In
Command In
Command In
Q7
Command #80H
Command #AAH
Command #55H
Command #10H
Command #AAH
(Q0~Q7)
Command #55H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0590
REV. 1.3, JUN. 13, 2001
20
MX29F016
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
NO
Toggle Bit Checking
Q6 not Toggled
YES
.
NO
Invalid
DATA Polling
Q7 = 1
Command
YES
NO
Q5 = 1
Auto Chip Erase Completed
YES
Reset
Auto Chip Erase Exceed
Timing Limit
P/N:PM0590
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21
MX29F016
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
checking after automatic erase starts. Device outputs 0
during erasure and 1 after erasure on Q7.(Q6 is for
togglebit;seetogglebit,DATApolling,timingwaveform)
BlockdataindicatedbyA16toA20 areerased. External
erase verify is not required because data are erased
automatically by internal control circuit. Erasure com-
pletion can be verified by DATA polling and toggle bit
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Vcc 5V
Sector
Sector
Sector
A16~A20
Address 0
Address 1
Address N
2AAH
555H
555H
2AAH
A0~A10
WE
555H
tAS
tCWC
tAH
tBAL
tCESC
tCEPH1
tCEPH2
tAETB
CE
OE
tCEP
tDF
tDS tDH
Command In
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
DATA polling
tDPA
Command In
Command In
Command In
Command In
Command In
Command In
Command In
Q7
Command #30H
Command #80H
Command #AAH
Command #55H
Command #30H
Command #30H
Command #AAH
(Q0~Q7)
Command #55H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
P/N:PM0590
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22
MX29F016
AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Toggle Bit Checking
Invalid Command
Q6 Toggled ?
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Sector
to Erase
YES
NO
NO
Time-out Bit
Checking Q3=1 ?
YES
Toggle Bit Checking
Q6 not Toggled
YES
.
Q5 = 1
Reset
DATA Polling
Q7 = 1
Auto Sector Erase Completed
Auto Sector Erase Exceed
Timing Limit
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23
MX29F016
ERASE SUSPEND/ERASE RESUME FLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
.
Write Data 30H
Continue Erase
Another
NO
Erase Suspend ?
YES
P/N:PM0590
REV. 1.3, JUN. 13, 2001
24
MX29F016
TIMING WAVEFORM FOR GROUP SECTOR PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
tVLHT
Verify
12V
5V
OE
tVLHT
tWPP 1
WE
CE
tOESP
Data
01H
tOE
Group Sector Address
A20-A16
P/N:PM0590
REV. 1.3, JUN. 13, 2001
25
MX29F016
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
A6
tVLHT
Verify
12V
5V
OE
tVLHT
tVLHT
tWPP 2
WE
CE
tOESP
Data
00H
tOE
A20-A16
Sector Address
P/N:PM0590
REV. 1.3, JUN. 13, 2001
26
MX29F016
SECTOR GROUP PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Set Up Sector Group Addr
(A20, A19, A18)
PLSCNT=1
OE=VID,A9=VID,CE=VIL
A6=VIL
Activate WE Pulse
Time Out 10us
Set WE=VIH, CE=OE=VIL
A9 should remain VID
.
Read from Sector Group
No
Addr=SGA, A1=1
No
Data=01H?
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Group Sector?
Remove VID from A9
Write Reset Command
Sector Group Protection
Complete
P/N:PM0590
REV. 1.3, JUN. 13, 2001
27
MX29F016
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Protect All Sectors
PLSCNT=1
Set OE=A9=VID
CE=VIL,A6=1
Activate WE Pulse
Time Out 12ms
Increment
PLSCNT
Set OE=CE=VIL
A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Increment
PLSCNT=1000?
Sector Addr
Yes
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect the whole chip, all sectors should be protected in advance.
P/N:PM0590
REV. 1.3, JUN. 13, 2001
28
MX29F016
TEMPORARYSECTORUNPROTECTALGORITHM
Start
RESET = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET = VIH
Temporary Sector Unprotect Completed(Note 2)
Note :
1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
P/N:PM0590
REV. 1.3, JUN. 13, 2001
29
MX29F016
ID CODE READ TIMING WAVEFORM
VCC
5V
VID
VIH
VIL
ADD
A9
VIH
VIL
ADD
A0
tACC
tACC
VIH
VIL
A1
ADD
A2-A8
VIH
A10-A20 VIL
CE
VIH
VIL
VIH
VIL
tCE
WE
OE
tOE
VIH
VIL
tDF
tOH
tOH
VIH
VIL
DATA
Q0-Q7
DATA OUT
C2H
DATA OUT
ADH
P/N:PM0590
REV. 1.3, JUN. 13, 2001
30
MX29F016
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
TYP.(2)
PARAMETER
MIN.
MAX.(3)
UNITS
Sector Erase Time
4
32
7
30
256
300
45
sec
sec
Chip Erase Time
Byte Programming Time
Chip Programming Time
Erase/Program Cycles
us
15
sec
100,000
Cycles
Note: 1.Not 100% Tested, Excludes external system level over head.
2.Typical values measured at 25°C,5V.
3.Maximum values measured at 25°C,4.5V.
LATCHUP CHARACTERISTICS
MIN.
-1.0V
MAX.
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
13.5V
Vcc + 1.0V
+100mA
-1.0V
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
P/N:PM0590
REV. 1.3, JUN. 13, 2001
31
MX29F016
ORDERING INFORMATION
PLASTICPACKAGE
PART NO.
ACCESS TIME(ns) OPERATING
STANDBY
OPERATING
TEMPERATURE
0°C ~70°C
PACKAGE
CURRENT MAX.(mA)
CURRENT MAX.(uA)
100
MX29F016T4C-90 90
MX29F016T4C-12 120
50
40 Pin TSOP
(Normal Type)
40 Pin TSOP
(Normal Type)
44 Pin SOP
50
100
0°C ~70°C
MX29F016MC-90 90
MX29F016MC-12 120
MX29F016TC-90 90
50
50
50
100
100
100
0°C ~70°C
0°C ~70°C
0°C ~70°C
44 Pin SOP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
40 Pin TSOP
(Normal Type)
40 Pin TSOP
(Normal Type)
44 Pin SOP
MX29F016TC-12 120
MX29F016T4I-90 90
MX29F016T4I-12 120
50
50
50
100
100
100
0°C ~70°C
-40°C ~85°C
-40°C ~85°C
MX29F016MI-90
MX29F016MI-12
MX29F016TI-90
90
50
50
50
100
100
100
-40°C ~85°C
-40°C ~85°C
-40°C ~85°C
120
90
44 Pin SOP
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
MX29F016TI-12
120
50
100
-40°C ~85°C
P/N:PM0590
REV. 1.3, JUN. 13, 2001
32
MX29F016
PACKAGE INFORMATION
40-PIN PLASTIC TSOP
P/N:PM0590
REV. 1.3, JUN. 13, 2001
33
MX29F016
48-PINPLASTICTSOP(NORMALTYPE)
P/N:PM0590
REV. 1.3, JUN. 13, 2001
34
MX29F016
44-PIN PLASTIC SOP
P/N:PM0590
REV. 1.3, JUN. 13, 2001
35
MX29F016
Revision History
RevisionNo. Description
Page
Date
1.1
1.2
DelPreliminary
Correcttypingerror
CorrectErase/ProgramOperationstDF:40(MAX.)-->30(MAX.)
P1
P14
P16
OCT/23/2000
JAN/08/2001
1.3
To modify the "chip unprotection algorithm for system with 12V" P28
flowchart
JUN/13/2001
Add temporary sector unprotect algorithm
To modify the "Package Information"
P29
P33~35
P/N:PM0590
REV. 1.3, JUN. 13, 2001
36
MX29F016
MACRONIX INTERNATIONAL CO., LTD.
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
37
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