MX29F200CBTC-70 [Macronix]
Flash, 128KX16, 70ns, PDSO48,;型号: | MX29F200CBTC-70 |
厂家: | MACRONIX INTERNATIONAL |
描述: | Flash, 128KX16, 70ns, PDSO48, 光电二极管 内存集成电路 |
文件: | 总49页 (文件大小:447K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX29F200C T/B
2M-BIT [256Kx8/128Kx16] CMOS FLASH MEMORY
FEATURES
• 5.0V±10% for read, erase and write operation
• 131072x16/262144x8 switchable
• Fast access time: 70/90ns
• CompatiblewithMX29F200T/Bdevice
• Lowpowerconsumption
- 40mA maximum active current@5MHz
- 1uA typical standby current
• Command register architecture
- Byte/Word Programming (9us/11us typical)
-SectorErase(16K-Bytex1,8K-Bytex2,32K-Bytex1,
and 64K-Byte x3)
- Superiorinadvertentwriteprotection
• Sector protection
- Hardware method to disable any combination of
sectors from program or erase operations
- Sector protect/unprotect for 5V only system or 5V/
12V system
• 100,000minimumerase/programcycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors or
the whole chip with Erase Suspend capability.
- Automatically program and verify data at specified
address
• Low VCC write inhibit is equal to or less than 3.2V
• Erase suspend/ Erase Resume
- Suspends an erase operation to read data from, or
programdatatoasectorthatisnotbeingerased,then
resume the erase operation.
• Status Reply
• HardwareRESET#pin
- Data# Polling & Toggle bit for detection of program
and erase cycle completion.
- Resets internal state mechine to the read mode
• 20 years data retention
• Ready/Busy#pin(RY/BY#)
• Package type:
- Provides a hardware method or detecting program
or erase cycle completion
- 44-pin SOP
- 48-pin TSOP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
- All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
TheMX29F200CT/Bisa2-megabit, single5VoltFlash
memoryorganizedas1Mwordx16or2Mbytex8MXIC's
Flash memories offer the most cost-effective and reli-
able read/write non-volatile random access memory.
TheMX29F200CT/Bispackagedin44-pinSOPand48-
pin TSOP. It is designed to be reprogrammed and
erasedin-systemorin-standardEPROMprogrammers.
TTL level control inputs and fixed power supply levels
duringeraseandprogramming,whilemaintainingmaxi-
mum EPROM compatibility.
MXICFlashtechnologyreliablystoresmemorycontents
evenafter100,000eraseandprogramcycles. TheMXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunneloxideprocessingandlowinternalelectricfieldsfor
erase and programming operations produces reliable
cycling. The MX29F200C T/B uses a 5.0V ±10% VCC
supply to perform the High Reliability Erase and auto
Program/Erasealgorithms.
ThestandardMX29F200CT/Boffersaccesstimeasfast
as70ns, allowingoperationofhigh-speedmicroproces-
sorswithoutwaitstates. Toeliminatebuscontention,the
MX29F200C T/B has separate chip enable (CE#) and
output enable (OE# ) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX29F200C T/B uses a command register to manage
thisfunctionality. Thecommandregisterallowsfor100%
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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MX29F200C T/B
PIN CONFIGURATIONS
44SOP(500mil)
PIN DESCRIPTION
SYMBOL PIN NAME
A0-A16
Q0-Q14
Q15/A-1
CE#
Address Input
RESET#
WE#
A8
A9
A10
A11
A12
A13
A14
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
RY/BY#
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Data Input/Output
A7
A6
A5
A4
A3
A2
A1
A0
CE#
GND
OE#
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
Q15(Wordmode)/LSBaddr.(Bytemode)
Chip Enable Input
OE#
Output Enable Input
A15
A16
RESET#
WE#
Hardware Reset Pin, Active low
Write Enable Input
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
RY/BY#
BYTE#
VCC
Read/BusyOutput
Word/Byte Selection Input
Power Supply Pin (+5V)
Ground Pin
GND
NC
Pin Not Connected Internally
VCC
48 TSOP(TYPE I) (12mm x 20mm)
1
2
3
4
5
6
7
8
48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE#
RESET#
NC
NC
RY/BY#
NC
NC
A7
A6
A5
A16
A15
A14
A13
A12
A11
A10
A9
A8
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
NC
WE#
RESET#
NC
NC
RY/BY#
NC
MX29F200C T/B
MX29F200C T/B
(NORMAL TYPE)
(REVERSE TYPE)
NC
A7
A6
A5
A4
A3
A2
A1
A4
A3
A2
A1
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MX29F200C T/B
SECTOR STRUCTURE
MX29F200CTTopBootSectorAddressesTables
Sector Size Address Range (in hexadecimal)
(Kbytes/
A16
0
A15
0
A14
X
A13
X
A12
X
Kwords)
64/32
64/32
64/32
32/16
8/4
(x8)Address Range
00000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-37FFFh
38000h-39FFFh
3A000h-3BFFFh
3C000h-3FFFFh
(x16) Address Range
00000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1BFFFh
1C000h-1CFFFh
1D000h-1DFFFh
1E000h-1FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
1
X
X
X
1
0
X
X
X
1
1
0
X
X
1
1
1
0
0
1
1
1
0
1
8/4
1
1
1
1
X
16/8
MX29F200CBBottomBootSectorAddressesTables
Sector Size Address Range (in hexadecimal)
(Kbytes/
A16
0
A15
0
A14
0
A13
0
A12
X
0
Kwords)
16/8
(x8)Address Range
00000h-03FFFh
04000h-05FFFh
06000h-07FFFh
08000h-0FFFFh
10000h-1FFFFh
20000h-2FFFFh
30000h-3FFFFh
(x16) Address Range
00000h-01FFFh
02000h-02FFFh
03000h-03FFFh
04000h-07FFFh
08000h-0FFFFh
10000h-17FFFh
18000h-1FFFFh
SA0
SA1
SA2
SA3
SA4
SA5
SA6
0
0
0
1
8/4
0
0
0
1
1
8/4
0
0
1
X
X
32/16
64/32
64/32
64/32
0
1
X
X
X
1
0
X
X
X
1
1
X
X
X
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MX29F200C T/B
BLOCK DIAGRAM
WRITE
CONTROL
INPUT
CE#
OE#
WE#
PROGRAM/ERASE
STATE
MACHINE
(WSM)
HIGH VOLTAGE
LOGIC
STATE
FLASH
ARRAY
ADDRESS
LATCH
REGISTER
ARRAY
A0-A16
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
A-1/Q15
DATA LATCH
PROGRAM
DATA LATCH
I/O BUFFER
Q0-Q14
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MX29F200C T/B
AUTOMATICPROGRAMMING
AUTOMATICERASEALGORITHM
The MX29F200C T/B is byte programmable using the
AutomaticProgrammingalgorithm. TheAutomaticPro-
grammingalgorithmdoesnotrequirethesystemtotime
out sequence or verify the data programmed. The
typicalchipprogrammingtimeoftheMX29F200CT/Bat
room temperature is less than 4.5 seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stand-
ard microprocessor write timings. The device will auto-
matically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
verifiestheerase andcountsthenumberofsequences.
A status bit toggling between consecutive read cycles
provides feedback to the user as to the status of the
programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typicalerasureatroomtemperatureisaccomplishedin
less than two second. The Automatic Erase algorithm
automaticallyprogramstheentirearraypriortoelectrical
erase. Thetimingandverificationofelectricaleraseare
internally controlled by the device.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming
circuitry. During write cycles, the command register
internally latches addresses and data needed for the
programming and erase operations. During a system
write cycle, addresses are latched on the falling edge,
and data are latched on the rising edge of WE#.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality,
reliability, and cost effectiveness. The MX29F200C T/B
electrically erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by
using the EPROM programming mechanism of hot
electron injection.
AUTOMATICSECTORERASE
The MX29F200CT/B issector(s)erasableusingMXIC's
AutoSectorErasealgorithm. Sectorerasemodesallow
sectorsofthearraytobeerasedinoneerasecycle. The
Automatic Sector Erase algorithm automatically pro-
grams the specified sector(s) prior to electrical erase.
The timing and verification of electrical erase are inter-
nally controlled by the device.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set. During a Sector Erase
cycle, the command register will only respond to Erase
Suspend command. After Erase Suspend is complete,
the device stays in read mode. After the state machine
hascompleteditstask,itwillallowthecommandregister
to respond to its full command set.
AUTOMATICPROGRAMMINGALGORITHM
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (include 2
unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, verifies the pro-
gram, andcountsthenumberofsequences. Astatusbit
similartoData#Pollingandastatusbittogglingbetween
consecutive read cycles, provides feedback to the user
as to the status of the programming operation.
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MX29F200C T/B
COMMAND DEFINITIONS
Device operations are selected by writing specific ad-
dress and data sequences into the command register.
Writing incorrect address and data values or writing
them in the improper sequence will reset the device to
the read mode. Table 1 defines the valid register
command sequences. Note that the Erase Suspend
(B0H) and Erase Resume (30H) commands are valid
only while the Sector Erase operation is in progress.
Either of the two reset command sequences will reset
the device(when applicable).
TABLE1.SOFTWARECOMMANDDEFINITIONS
First Bus
Cycle
Second Bus Third Bus
Cycle Cycle
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Command
Bus
Cycle Addr Data
Addr Data Addr Data Addr
Data
Addr Data
Addr Data
Reset
1
1
4
4
4
XXXH F0H
RA RD
Read
Read Silicon ID
Word
Byte
555H AAH
AAAH AAH
555H AAH
2AAH 55H 555H 90H ADI
555H 55H AAAH 90H ADI
2AAH 55H 555H 90H (SA)
DDI
DDI
Sector Protect
Verify
Word
XX00H
X02H XX01H
Byte
4
AAAH AAH
555H 55H AAAH 90H (SA)
00
X04H 01
Program
Word
Byte
Word
Byte
Word
Byte
4
4
6
6
6
6
1
1
6
555H AAH
AAAH AAH
555H AAH
AAAH AAH
555H AAH
AAAH AAH
XXXH B0H
XXXH 30H
555H AAH
2AAH 55H 555H A0H PA
555H 55H AAAH A0H PA
PD
PD
Chip Erase
Sector Erase
2AAH 55H 555H 80H 555H AAH
555H 55H AAAH 80H AAAH AAH
2AAH 55H 555H 80H 555H AAH
555H 55H AAAH 80H AAAH AAH
2AAH 55H
555H 55H
2AAH 55H
555H 55H
555H 10H
AAAH 10H
SA
SA
30H
30H
Sector Erase Suspend
Sector Erase Resume
Unlock for sector
2AAH 55H 555H 80H 555H AAH
2AAH 55H
555H 20H
protect/unprotect
NOTES:
1. ADI = Address of Device identifier; A1=0, A0 =0 for manufacture code, A1=0, A0 =1 for device code.(Refer to Table 3)
DDI = Data of Device identifier : C2H for manufacture code,51H/57H(x8) and 2251H/2257H(x16) for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
2. PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
SA = Address to the sector to be erased.
3. The system should generate the following address patterns: 555H or 2AAH to Address A0~A10.
Address bit A11~A16=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).
Write Sequence may be initiated with A11~A16 in either state.
4. For Sector Protection Verify Operation : If read out data is 01H, it means the sector has been protected. If read out data is
00H, it means the sector is still not being protected.
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MX29F200C T/B
TABLE 2. MX29F200C T/B BUS OPERATIONS
Pins
CE#
L
OE# WE# A0
A1
L
A6
X
A9
Q0 ~ Q15
Mode
Read Silicon ID
L
L
H
H
L
VID(2) C2H(Bytemode)
00C2H(Wordmode)
ManufacturerCode(1)
Read Silicon ID
DeviceCode(1)
Read
L
H
L
X
VID(2) 51H/57H(Bytemode)
2251H/2257H(Wordmode)
L
H
L
L
L
L
H
X
H
L
A0
X
A1
X
A6
X
A9
X
DOUT
Standby
X
HIGH Z
HIGH Z
DIN(3)
X
OutputDisable
Write
H
X
X
X
X
H
A0
X
A1
X
A6
L
A9
VID(2)
Sector Protect with 12V
system(6)
VID(2)
L
Chip Unprotect with 12V
system(6)
L
L
L
VID(2)
L
X
X
X
X
X
X
H
X
X
H
H
X
L
VID(2)
X
Verify Sector Protect
with 12V system
Sector Protect without 12V
system (6)
L
H
L
VID(2) Code(5)
H
H
L
H
H
H
X
Chip Unprotect without 12V L
system (6)
L
H
X
X
Verify Sector Protect/
Unprotectwithout12V
system (7)
L
H
Code(5)
Reset
X
X
X
X
X
X
X
HIGH Z
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
5.Code=00H/0000Hmeansunprotected.
Code=01H/0001H means protected.
A16~A12=Sector address for sector protect.
6. Refer to sector protect/unprotect algorithm and waveform.
Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system"
command.
7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V
system" command.
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MX29F200C T/B
READ/RESETCOMMAND
SET-UP AUTOMATIC CHIP/SECTOR ERASE COM-
MANDS
Thereadorresetoperationisinitiatedbywritingtheread/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data. The
device remains enabled for reads until the command
register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up"command80H. Twomore "unlock"writecycles
are then followed by the chip erase command 10H.
If program-fail or erase-fail happen, the write of F0H will
resetthedevicetoaborttheoperation. Avalidcommand
must then be written to place the device in the desired
state.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zeropattern,aself-timedchiperaseandverifybegin.
Theeraseandverifyoperationsarecompletedwhenthe
data on Q7 is "1" at which time the device returns to the
Read mode. The system does not require to provide
any control or timing during these operations.
SILICON-ID-READCOMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible
while the device resides in the target system. PROM
programmers typically access signature codes by rais-
ing A9 to a high voltage. However, multiplexing high
voltage onto address lines is not generally desired
system design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erasemarginhasbeenachievedforthememoryarray(no
erase-verified command is required).
TheMX29F200CT/BcontainsaSilicon-ID-Readopera-
tiontosupplementtraditionalPROMprogrammingmeth-
odology. The operation is initiated by writing the read
silicon ID command sequence into the command regis-
ter. Following the command write, a read cycle with
A1=VIL,A0=VILretrievesthemanufacturercodeofC2H/
00C2H. A read cycle with A1=VIL, A0=VIH returns the
devicecodeof51H/2251HforMX29F200CT,57H/2257H
forMX29F200CB.
IftheEraseoperationwasunsuccessful, thedataonQ5
is"1"(seeTable4),indicatinganeraseoperationexceed
internal timing limit.
Theautomaticerasebeginsontherisingedgeofthelast
WE# pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
A0
A1
Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)
Code
Manufacturecode
Word VIL VIL
Byte VIL VIL
Word VIH VIL
Byte VIH VIL
Word VIH VIL
Byte VIH VIL
00H
X
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
1
0
00C2H
C2H
Device code
22H
X
2251H
forMX29F200CT
Device code
51H
22H
X
2257H
forMX29F200CB
Sector Portection
Verification
57H
X
X
VIH
VIH
X
01H(Protected)
00H(Unprotected)
X
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MX29F200C T/B
SECTORERASECOMMANDS
ERASESUSPEND
TheAutomaticSectorErasedoesnotrequirethedevice
to be entirely pre-programmed prior to executing the
AutomaticSet-upSectorErasecommandandAutomatic
SectorErasecommand. UponexecutingtheAutomatic
Sector Erase command, the device will automatically
program and verify the sector(s) memory for an all-zero
data pattern. The system does not require to provide
any control or timing during these operations.
This command is only valid while the state machine is
executing Automatic Sector Erase operation, and
thereforewillonlyberespondedtoperiodduringAutomatic
Sector Erase operation. Writing the Erase Suspend
commandduringtheSectorErasetime-outimmediately
terminates the time-out period and suspends the erase
operation. After this command has been executed, the
commandregisterwillinitiateerasesuspendmode. The
statemachinewillreturntoreadmodeautomaticallyafter
suspendisready. Atthistime,statemachineonlyallows
the command register to respond to the Read Memory
Array, Erase Resume and Program commands.
Whenthesector(s)isautomaticallyverifiedtocontainan
all-zeropattern,aself-timedsectoreraseandverification
begin. Theeraseandverificationoperationsarecomplete
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode. The system does
not require to provide any control or timing during these
operations.
The system can determine the status of the program
operation using the Q7 or Q6 status bits, just as in the
standard program operation. After an erase-suspend
program operation is complete, the system can once
again read array data within non-suspended sectors.
WhenusingtheAutomaticSectorErasealgorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase-verified command is required). Sector erase
isasix-buscycleoperation. Therearetwo"unlock"write
cycles. Thesearefollowedbywritingtheset-upcommand
80H. Two more "unlock" write cycles are then followed
by the sector erase command 30H. The sector address
is latched on the falling edge of WE#, while the
command(data) is latched on the rising edge of WE#.
Sectoraddressesselectedareloadedintointernalregister
onthesixthfallingedgeofWE#. Eachsuccessivesector
loadcyclestartedbythefallingedgeofWE# mustbegin
within 30us from the rising edge of the preceding WE#.
Otherwise, the loading period ends and internal auto
sectorerasecyclestarts. (MonitorQ3todetermineifthe
sector erase timer window is still open, see section Q3,
Sector Erase Timer.) Any command other than Sector
Erase (30H) or Erase Suspend (B0H) during the time-
out period resets the derice to read mode.
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MX29F200C T/B
Table 4. Write Operation Status
Status
Q7
Q6
Q5
Q3
Q2 RY/BY#
Note1
Note2
Byte Program in Auto Program Algorithm
Q7# Toggle
0
N/A
1
No
0
Toggle
Auto Erase Algorithm
0
1
Toggle
0
0
Toggle
0
1
Erase Suspend Read
(Erase Suspended Sector)
No
Toggle
N/A Toggle
In Progress
Erase Suspended Mode
Erase Suspend Read
Data
Data Data Data Data
1
0
0
(Non-Erase Suspended Sector)
Erase Suspend Program
Q7# Toggle
Q7# Toggle
0
1
N/A N/A
Byte Program in Auto Program Algorithm
N/A
1
No
Toggle
Exceeded
Time Limits Auto Erase Algorithm
0
Toggle
1
1
Toggle
0
0
Erase Suspend Program
Q7# Toggle
N/A N/A
Notes:
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.
See "Q5:Exceeded Timing Limits " for more information.
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MX29F200C T/B
ERASERESUME
sequences for automatic program.
This command will cause the command register to clear
thesuspendstateandreturnbacktoSectorErasemode
but only if an Erase Suspend command was previously
issued. Erase Resume will not have any effect in all
otherconditions.AnotherEraseSuspendcommandcan
be written after the chip has resumed erasing.
While the Automatic Erase algorithm is in operation, Q7
willread"0"untiltheeraseoperationiscompeted. Upon
completion of the erase operation, the data on Q7 will
read"1". TheData#Pollingfeatureisvalidaftertherising
edgeofthesixthWE#pulseofsix writepulsesequences
for automatic chip/sector erase.
The Data# Polling feature is active during Automatic
Program/Erase algorithm or sector erase time-out.(see
section Q3 Sector Erase Timer)
SET-UPAUTOMATICPROGRAM COMMANDS
To initiate Automatic Program mode, A three-cycle
commandsequenceisrequired. Therearetwo"unlock"
writecycles. ThesearefollowedbywritingtheAutomatic
Program command A0H.
RY/BY#:Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Automatic Erase/Program algo-
rithm is in progress or complete. The RY/BY# status is
valid after the rising edge of the final WE# pulse in the
command sequence. Since RY/BY# is an open-drain
output, several RY/BY# pins can be tied together in
parallel with a pull-up resistor to Vcc.
Once the Automatic Program command is initiated, the
nextWE#pulsecausesatransitiontoanactiveprogram-
ming operation. Addresses are latched on the falling
edge, and dataareinternally latchedon therisingedge
of the WE# pulse. The rising edge of WE# also begins
theprogrammingoperation. Thesystemdoesnotrequire
to provide further controls or timings. The device will
automatically provide an adequate internally generated
program pulse and verify margin.
Iftheoutputsislow(Busy), thedeviceisactivelyerasing
or programming. (This includes programming in the
EraseSuspendmode.) Iftheoutputishigh(Ready), the
device is ready to read array data (including during the
Erase Suspend mode), or is in the standby mode.
If the program operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the program operation
exceedinternaltiminglimit.Theautomaticprogramming
operation is completed when the data read on Q6 stops
togglingfortwoconsecutivereadcyclesandthedataon
Q7 and Q6 are equivalent to data written to these two
bits, at which time the device returns to the Read
mode(noprogramverifycommandisrequired).
Q6:Toggle BIT I
Toggle Bit I on Q6 indicates whether an Automatic
ProgramorErasealgorithmisinprogressorcomplete,or
whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
commandsequence(priortotheprogramoreraseopera-
tion), and during the sector time-out.
WRITEOPERATIONSTATUSDATA#POLLING-Q7
The MX29F200C T/B also features Data# Polling as a
methodtoindicatetothehostsystemthattheAutomatic
Program or Erase algorithms are either in progress or
completed.
DuringanAutomaticProgramorErasealgorithmopera-
tion, successivereadcyclestoanyaddresscauseQ6to
toggle.ThesystemmayuseeitherOE#orCE#tocontrol
the read cycles. When the operation is complete, Q6
stops toggling.
WhiletheAutomaticProgrammingalgorithmisinopera-
tion, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at-
tempt to read the device will produce the true data last
writtentoQ7. TheData#Pollingfeatureisvalidafterthe
risingedgeofthefourth WE#pulseofthefourwritepulse
After an erase command sequence is written, if all
sectors selected for erasing are protected, Q6 toggles
and returns to reading array data. If not all selected
sectors are protected, the Automatic Erase algorithm
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MX29F200C T/B
erasestheunprotectedsectors,andignorestheselected
sectors that are protected.
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has
completedtheprogramoreraseoperation. Thesystem
canreadarraydataonQ7-Q0onthefollowingreadcycle.
The system can use Q6 and Q2 together to determine
whether a sector is actively erasing or is erase sus-
pended. When the device is actively erasing (that is, the
Automatic Erase algorithm is in progress), Q6 toggling.
When the device enters the Erase Suspend mode, Q6
stops toggling. However, the system must also use Q2
to determine which sectors are erasing or erase-sus-
pended. Alternatively, the system can use Q7.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system
alsoshould notewhetherthevalueofQ5ishigh(seethe
sectiononQ5). Ifitis,thesystemshouldthendetermine
again whether the toggle bit is toggling, since the toggle
bitmayhavestoppedtogglingjustasQ5wenthigh. Ifthe
togglebitisnolongertoggling,thedevicehassuccessfully
completed the program or erase operation. If it is still
toggling, the device did not complete the operation
successfully, and the system must write the reset
command to return to reading array data.
If a program address falls within a protected sector, Q6
toggles for approximately 2us after the program com-
mand sequence is written, then returns to reading array
data.
Q6alsotogglesduringtheerase-suspend-programmode,
and stops toggling once the Automatic Program algo-
rithm is complete.
Theremainingscenarioisthatsysteminitiallydetermines
that the toggle bit is toggling and Q5 has not gone high.
The system may continue to monitor the toggle bit and
Q5 through successive read cycles, determining the
status as described in the previous paragraph.
Alternatively, it may choose to perform other system
tasks.Inthiscase,thesystemmuststartatthebeginning
ofthealgorithmwhenitreturnstodeterminethestatusof
theoperation.
Table 4 shows the outputs for Toggle Bit I on Q6.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whetheraparticularsectorisactivelyerasing(thatis,the
AutomaticErasealgorithmisinprocess),orwhetherthat
sector is erase-suspended. Toggle Bit I is valid after the
rising edge of the final WE# pulse in the command
sequence.
Q5
Exceeded Timing Limits
Q2 toggles when the system reads at addresses within
thosesectorsthathavebeenselectedforerasure. (The
system may use either OE# or CE# to control the read
cycles.) ButQ2cannotdistinguishwhetherthesectoris
activelyerasingoriserase-suspended. Q6,bycompari-
son, indicates whether the device is actively erasing, or
is in Erase Suspend, but cannot distinguish which sec-
tors are selected for erasure. Thus, both status bits are
requiredforsectorsandmodeinformation. RefertoTable
4 to compare outputs for Q2 and Q6.
Q5willindicateiftheprogramorerasetimehasexceeded
the specified limits(internal pulse count). Under these
conditionsQ5willproducea"1". Thistime-outcondition
which indicates that the program or erase cycle was not
successfully completed. Data# Polling and Toggle Bit
are the only operating functions of the device under this
condition.
If this time-out condition occurs during sector erase
operation, it specifies that a particular sector is bad and
it may not be reused. However, other sectors are still
functional and may be used for the program or erase
operation. Thedevicemustberesettouseothersectors.
Write the Reset command sequence to the device, and
then execute program or erase command sequence.
Thisallowsthesystemtocontinuetousetheotheractive
sectors in the device.
Reading Toggle Bits Q6/ Q2
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determinewhetheratogglebitistoggling. Typically, the
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MX29F200C T/B
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad or
combination of sectors are bad.
cally resets the state machine in the Read mode. In
addition, with its control register architecture, alteration
of the memory contents only occurs after successful
completionofspecificcommandsequences. Thedevice
alsoincorporatesseveralfeaturestopreventinadvertent
write cycles resulting from VCC power-up and power-
down transition or system noise.
Ifthistime-outconditionoccursduringthebyte program-
mingoperation, itspecifiesthattheentiresectorcontain-
ing that byte is bad and this sector maynot be reused,
(other sectors are still functional and can be reused).
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the
Automatic Algorithm operation. Hence, the system
never reads a valid data on Q7 bit and Q6 never stops
toggling. Once the Device has exceeded timing limits,
the Q5 bit will indicate a "1". Please note that this is not
a device failure condition since the device was incor-
rectly used.
TEMPORARYSECTORUNPROTECT
Thisfeatureallowstemporaryunprotectionofpreviously
protectedsectortochangedatain-system. TheTempo-
rary Sector Unprotect mode is activated by setting the
RESET# pin to VID(11.5V-12.5V). During this mode,
formerlyprotectedsectorscanbeprogrammedorerased
as un-protected sector. Once VID is remove from the
RESET# pin,all the previously protected sectors are
protectedagain.
Q3
Sector Erase Timer
WRITEPULSE"GLITCH"PROTECTION
After the completion of the initial sector erase command
sequence, the sector erase time-out will begin. Q3 will
remain low until the time-out is complete. Data# Polling
and Toggle Bit are valid after the initial sector erase
commandsequence.
Noisepulsesoflessthan5ns(typical)onCE#orWE#will
not initiate a write cycle.
LOGICALINHIBIT
IfData#PollingortheToggleBitindicatesthedevicehas
been written with a valid erase command, Q3 may be
usedtodetermineifthesectorerasetimerwindowisstill
open. If Q3 is high ("1") the internally controlled erase
cyclehasbegun;attemptstowritesubsequentcommands
to the device will be ignored until the erase operation is
completedasindicatedbyData#PollingorToggleBit. If
Q3 is low ("0"), the device will accept additional sector
erase commands. To insure the command has been
accepted, the system software should check the status
ofQ3priortoandfollowingeachsubsequentsectorerase
command. If Q3 were high on the second status check,
the command may not have been accepted.
WritingisinhibitedbyholdinganyoneofOE#=VIL,CE#
= VIH or WE# = VIH. To initiate a write cycle CE# and
WE# must be a logical zero while OE# is a logical one.
POWERSUPPLYDECOUPLING
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected
between its VCC and GND.
SECTOR PROTECTION WITH 12V SYSTEM
The MX29F200C T/B features hardware sector protec-
tion. This feature will disable both program and erase
operations for these sectors protected. To activate this
mode, the programming equipment must force VID on
addresspinA9andcontrolpinOE#,(suggestVID=12V)
A6 = VIL and CE# = VIL.(see Table 2) Programming of
the protection circuitry begins on the falling edge of the
DATAPROTECTION
The MX29F200C T/B is designed to offer protection
against accidental erasure or programming caused by
spurious system level signals that may exist during
power transition. During power up the device automati-
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MX29F200C T/B
WE# pulse and is terminated on the rising edge. Please
refer to sector protect algorithm and waveform.
CHIP UNPROTECT WITHOUT 12V SYSTEM
The MX29F200C T/B also feature a hardware chip
unprotection method in a system without 12V power
supply. The programming equipment do not need to
supply 12 volts to unprotect all sectors. The details are
shown in chip unprotect algorithm and waveform.
To verify programming of the protection circuitry, the
programming equipment must force VID on address pin
A9 ( with CE# and OE# at VIL and WE# at VIH. When
A1=1, it will produce a logical "1" code at device output
Q0 for a protected sector. Otherwise the device will
produce00Hfortheunprotectedsector. Inthismode,the
addresses, except for A1, are in "don't care" state.
Address locations with A1 = VIL are reserved to read
manufacturer and device codes.(Read Silicon ID)
POWER-UPSEQUENCE
TheMX29F200CT/BpowersupintheReadonlymode.
In addition, the memory contents may only be altered
aftersuccessfulcompletionofthepredefinedcommand
sequences.
It is also possible to determine if the sector is protected
in the system by writing a Read Silicon ID command.
PerformingareadoperationwithA1=VIH,itwillproduce
a logical "1" at Q0 for the protected sector.
CHIP UNPROTECT WITH 12V SYSTEM
The MX29F200C T/B also features the chip unprotect
mode, so that all sectors are unprotected after chip
unprotect iscompleted toincorporateanychangesinthe
code. It is recommended to protect all sectors before
activating chip unprotect mode.
Toactivatethismode,theprogrammingequipmentmust
force VID on control pin OE# and address pin A9. The
CE# pins must be set at VIL. Pins A6 must be set to
VIH.(seeTable2) Refertochipunprotect algorithmand
waveform for the chip unprotect algorithm. The
unprotectionmechanismbeginsonthefallingedgeofthe
WE# pulse and is terminated on the rising edge .
It is also possible to determine if the chip is unprotected
in the system by writing the Read Silicon ID command.
PerformingareadoperationwithA1=VIH,itwillproduce
00Hatdataoutputs(Q0-Q7)foranunprotectedsector.It
is noted that all sectors are unprotected after the chip
unprotect algorithm is completed.
SECTOR PROTECTION WITHOUT 12V SYSTEM
The MX29F200C T/B also feature a hardware sector
protectionmethodinasystemwithout12Vpowersuppply.
The programming equipment do not need to supply 12
volts to protect sectors. The details are shown in sector
protectalgorithmandwaveform.
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MX29F200C T/B
TEMPORARY SECTOR UNPROTECT OPERATION
Start
RESET# = VID (Note 1)
Perform Erase or Program Operation
Operation Completed
RESET# = VIH
Temporary Sector Unprotect Completed(Note 2)
Notes :
1. All protected sectors are temporary unprotected.
VID=11.5V~12.5V
2. All previously protected sectors are protected again.
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MX29F200C T/B
TEMPORARYSECTORUNPROTECT
ParameterStd. Description
TestSetup AllSpeedOptions Unit
tVIDR
tRSP
VID Rise and Fall Time (See Note)
RESET# Setup Time for Temporary Sector Unprotect
Min
Min
500
4
ns
us
Note:
Not 100% tested
TEMPORARYSECTORUNPROTECTTIMINGDIAGRAM
12V
RESET#
0 or 5V
0 or 5V
Program or Erase Command Sequence
tVIDR
tVIDR
CE#
WE#
tRSP
RY/BY#
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MX29F200C T/B
ParameterStd Description
TestSetup All Speed Options Unit
tREADY1
RESET# PIN Low (During Automatic Algorithms)
MAX
MAX
MIN
20
us
to Read or Write (See Note)
tREADY2
RESET# PIN Low (NOT During Automatic
Algorithms) to Read or Write (See Note)
RESET# Pulse Width (During Automatic Algorithms)
500
ns
tRP1
tRP2
tRH
10
500
0
us
ns
ns
ns
ns
RESET# Pulse Width (NOT During Automatic Algorithms) MIN
RESET# High Time Before Read(See Note)
RY/BY# Recovery Time(to CE#, OE# go low)
RY/BY# Recovery Time(to WE# go low)
MIN
MIN
MIN
tRB1
tRB2
0
50
Note:Not 100% tested
RESET# TIMING WAVEFORM
RY/BY#
CE#, OE#
RESET#
tRH
tRP
tReady
Reset Timing NOT during Automatic Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Reset Timing during Automatic Algorithms
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MX29F200C T/B
NOTICE:
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under ABSOLUTE
MAXIMUMRATINGSmaycausepermanentdamageto
the device. This is a stress rating only and functional
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended period may affect reliability.
RATING
VALUE
AmbientOperatingTemperature -40oCto85oC
AmbientTemperaturewithPower -55oCto125oC
Applied
StorageTemperature
Applied Input Voltage
AppliedOutputVoltage
VCC to Ground Potential
A9&OE#
-65oCto125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
NOTICE:
Specifications contained within the following tables are
subject to change.
DC/AC Operating Conditions for Read Operation
MX29F200CT/B
-70
-90
OperatingTemperature
Vcc Power Supply
Commercial
Industrial
0oC to 70oC
-40oCto85oC
5V ± 10%
0oC to 70oC
-40oCto85oC
5V ± 10%
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL PARAMETER
MIN.
TYP
MAX.
UNIT
pF
CONDITIONS
CIN1
CIN2
COUT
InputCapacitance
8
VIN = 0V
VIN = 0V
VOUT = 0V
ControlPinCapacitance
OutputCapacitance
12
12
pF
pF
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MX29F200C T/B
READ OPERATION
DCCHARACTERISTICS
Symbol PARAMETER
MIN.
TYP
MAX.
UNIT CONDITIONS
ILI
InputLeakageCurrent
1(Note3)
uA
uA
mA
uA
mA
mA
V
VIN = GND to VCC
ILO
OutputLeakageCurrent
Standby VCC current
10
VOUT = GND to VCC
CE# = VIH
ISB1
ISB2
ICC1
ICC2
VIL
1
1
5
CE# = VCC + 0.3V
IOUT = 0mA, f=5MHz
IOUT = 0mA, f=10MHz
OperatingVCCcurrent
40
50
Input Low Voltage
-0.3(Note1)
0.7xVCC
0.8
VIH
Input High Voltage
VCC+0.3
0.45
V
VOL
VOH1
VOH2
OutputLowVoltage
OutputHighVoltage(TTL)
V
IOL = 2.1mA,VCC=VCC MIN
IOH = -2mA,VCC=VCC MIN
IOH = -100uA,VCC=VCC MIN
2.4
V
OutputHighVoltage(CMOS) VCC-0.4
V
NOTES:
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to ot less than 20 ns.
2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
3. ILI=10uA for Industrial Grade.
AC CHARACTERISTICS
29F200C-70
29F200C-90
SYMBOL PARAMETER
MIN.
MAX.
MIN. MAX.
UNIT
ns
CONDITIONS
CE#=OE#=VIL
OE#=VIL
tACC
tCE
tOE
tDF
Address to Output Delay
70
70
30
20
0
90
90
35
CE# to Output Delay
ns
OE# to Output Delay
ns
CE#=VIL
OE# High to Output Float (Note1)
Address to Output hold
0
0
20
0
ns
CE#=VIL
tOH
ns
CE#=OE#=VIL
TESTCONDITIONS:
NOTE:
• Input pulse levels: 0.45V/0.7xVCC
• Input rise and fall times: is equal to or less than 10ns
1.tDFisdefinedasthetimeatwhichtheoutputachieves
theopencircuitconditionanddataisnolongerdriven.
• Outputload:1TTLgate+100pF(Includingscopeand
jig)
• Reference levels for measuring input timing: 0.8V,
2.0V
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MX29F200C T/B
READTIMINGWAVEFORMS
VIH
ADD Valid
A0~16
VIL
tCE
VIH
CE#
VIL
VIH
WE#
tDF
VIL
tOE
VIH
OE#
tACC
VIL
tOH
HIGH Z
HIGH Z
VOH
VOL
DATA
Q0~7
DATA Valid
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MX29F200C T/B
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC/ACOperatingConditionsforProgramming/EraseOperation
MX29F200CT/B
-70
-90
OperatingTemperature
Vcc Power Supply
Commercial
Industrial
0oC to 70oC
-40oCto85oC
5V±10%
0oC to 70oC
-40oCto85oC
5V±10%
DCCHARACTERISTICS
SYMBOL
PARAMETER
Operating VCC Current
MIN.
TYP
MAX.
UNIT CONDITIONS
ICC1 (Read)
ICC2
40
50
50
50
mA
mA
mA
mA
mA
IOUT=0mA, f=5MHz
IOUT=0mA, F=10MHz
In Programming
ICC3 (Program)
ICC4 (Erase)
ICCES
In Erase
VCC Erase Suspend Current
2
CE#=VIH, Erase Suspended
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is
the sum of ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
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MX29F200C T/B
ACCHARACTERISTICS
SYMBOL PARAMETER
TA=-40°C to 85°C, VCC=5V ±10%
29F200C T/B-70
29F200C T/B-90
MIN.
0
MAX.
MIN.
0
MAX. UNIT
tOES
tCWC
tCEP
OE# setup time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
Commandprogrammingcycle
WE#programmingpulsewidth
70
35
20
20
0
90
45
20
20
0
tCEPH1 WE#programmingpulsewidthHigh
tCEPH2 WE#programmingpulsewidthHigh
tAS
Address setup time
tAH
Address hold time
45
35
0
45
45
0
tDS
Data setup time
tDH
Data hold time
tCESC
tDF
CE# setup time before command write
Output disable time (Note 1)
Erase time in auto chip erase
Erase time in auto sector erase
Programming time in auto verify
(Byte/Wordprogramtime)
Sector address load time
CE# Hold Time
0
0
20
32
15
20
32
tAETC
tAETB
tAVT
4(TYP.)
4(TYP.)
0.7(TYP.)
9/11(TYP.)
0.7(TYP.) 15
s
300/360 9/11(TYP.) 300/360 us
tBAL
50
0
50
0
us
ns
ns
us
us
us
ms
tCH
tCS
CE# setup to WE# going low
Voltage Transition Time
0
0
tVLHT
tOESP
tWPP
tWPP2
4
4
OE# Setup Time to WE# Active
Write pulse width for sector protect
Write pulse width for sector unprotect
4
4
10
12
10
12
NOTES:
1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.
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MX29F200C T/B
SWITCHINGTESTCIRCUITS
DEVICE UNDER
2.7K ohm
+5V
TEST
CL
6.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance
SWITCHINGTESTWAVEFORMS
0.7xVCC
0.45V
2.0V
2.0V
0.8V
TEST POINTS
0.8V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 0.7xVCC for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are < 20ns.
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MX29F200C T/B
COMMANDWRITETIMINGWAVEFORM
VCC
5V
VIH
ADDRESS
ADD Valid
A0~16
VIL
tAH
tAS
VIH
VIL
WE#
tOES
tCEPH1
tCEP
tCWC
VIH
VIL
CE#
OE#
tCS
tCH
tDH
VIH
VIL
tDS
VIH
VIL
DATA
Q0-7
DIN
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MX29F200C T/B
AUTOMATIC PROGRAMMING TIMING WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed auto-
matically by internal control circuit. Programming com-
pletion can be verified by Data# Polling and toggle bit
checking after automatic verification starts. Device
outputs DATA# during programming and DATA# after
programming on Q7.(Q6 is for toggle bit; see toggle bit,
Data# Polling, timing waveform).
AUTOMATICPROGRAMMINGTIMINGWAVEFORM(WORDMODE)
VCC 5V
A11~A16
ADD Valid
ADD Valid
2AAH
555H
A0~A10
WE#
555H
tAS
tCWC
tCEPH1
tAH
tCESC
tAVT
CE#
OE#
tCEP
tDS tDH
tDF
DATA
DATA
Q0~Q2,
Command In
Command In
Command In
Data In
Data In
DATA# Polling
Q4(Note 1)
DATA#
Command In
Command In
Command In
Q7
Command #A0H
Command #AAH
Command #55H
tOE
(Q0~Q7)
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
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MX29F200C T/B
AUTOMATICPROGRAMMINGALGORITHMFLOWCHART(WORDMODE)
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
NO
Toggle Bit Checking
Q6 not Toggled
YES
NO
Invalid
Verify Byte OK
Command
YES
NO
Q5 = 1
Reset
Auto Program Completed
YES
Auto Program Exceed
Timing Limit
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26
MX29F200C T/B
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification is
not required because data is erased automatically by
internal control circuit. Erasure completion can be
verified by Data# Polling and toggle bit checking after
automaticerasestarts. Deviceoutputs0duringerasure
and1aftererasure0nQ7.(Q6isfortogglebit;seetoggle
bit, Data# Polling, timing waveform)
AUTOMATICCHIPERASETIMINGWAVEFORM(WORDMODE)
VCC 5V
A11~A16
2AAH
555H
555H
2AAH
A0~A10
WE#
555H
tAS
555H
tCWC
tCEPH1
tAH
tCESC
tAETC
CE#
OE#
tCEP
tDF
tDS tDH
Command In
Q0~Q2
Command In
Command In
Command In
Command In
Command In
Data# Polling
,Q4(Note 1)
Command In
Command In
Command In
Command In
Command In
Command In
Q7
Command #80H
Command #AAH
Command #55H
Command #10H
Command #AAH
(Q0~Q7)
Command #55H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit
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MX29F200C T/B
AUTOMATICCHIPERASEALGORITHMFLOWCHART(WORDMODE)
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
NO
Toggle Bit Checking
Q6 not Toggled
YES
NO
Invalid
Data# Polling
Command
Q7 = 1
YES
NO
Q5 = 1
Auto Chip Erase Completed
YES
Reset
Auto Chip Erase Exceed
Timing Limit
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MX29F200C T/B
AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Sector dataindicatedbyA12toA16areerased. External
erase verification is not required because data are
erased automatically by internal control circuit. Erasure
completioncanbeverifiedbyData#Pollingandtogglebit
checking after automatic erase starts. Device outputs 0
duringerasureand1aftererasureonQ7.(Q6isfortoggle
bit; see toggle bit, Data# Polling, timing waveform)
AUTOMATICSECTORERASETIMINGWAVEFORM(WORDMODE)
Vcc 5V
Sector
Addressn
Sector
Address0
Sector
Address1
A12~A16
555H
555H
555H
tAS
2AAH
2AAH
A0~A10
tCWC
tAH
WE#
CE#
tCEPH1
tBAL
tAETB
tCEP
tDS
OE#
tDH
Command
In
Command
In
Q0,Q1,
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Q4(Note 1)
Data# Polling
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Command
In
Q7
Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H
(Q0~Q7)
Command #30H
Command #30H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit
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MX29F200C T/B
AUTOMATICSECTORERASEALGORITHMFLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Toggle Bit Checking
Invalid Command
Q6 Toggled ?
YES
Load Other Sector Addrss If Necessary
(Load Other Sector Address)
NO
Last Sector
to Erase
YES
NO
NO
Time-out Bit
Checking Q3=1 ?
YES
Toggle Bit Checking
Q6 not Toggled
YES
NO
Q5 = 1
Data# Polling
Q7 = 1
YES
Reset
Auto Sector Erase Completed
Auto Sector Erase Exceed
Timing Limit
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MX29F200C T/B
ERASESUSPEND/ERASERESUMEFLOWCHART
START
Write Data B0H
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
Continue Erase
Another
NO
Erase Suspend ?
YES
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MX29F200C T/B
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITH 12V
A1
A6
12V
5V
A9
tVLHT
tVLHT
Verify
12V
5V
OE#
tVLHT
tWPP 1
WE#
CE#
tOESP
Data
01H
tOE
A16-A12
Sector Address
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32
MX29F200C T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITH 12V
A1
12V
5V
A9
A6
tVLHT
Verify
12V
5V
OE#
tVLHT
tVLHT
tWPP 2
WE#
CE#
tOESP
Data
00H
tOE
A16-A12
Sector Address
P/N:PM1250
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MX29F200C T/B
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Set Up Sector Addr
(A16,A15,A14,A13,A12)
PLSCNT=1
OE#=VID, A9=VID, CE#=VIL
A6=VIL
Activate WE# Pulse
Time Out 10us
Set WE#=VIH, CE#=OE#=VIL
A9 should remain VID
Read from Sector
Addr=SA, A1=1
No
No
Data=01H?
Yes
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
No
Remove VID from A9
Write Reset Command
Sector Protection
Complete
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MX29F200C T/B
CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITH 12V
START
Protect All Sectors
PLSCNT=1
Set OE#=A9=VID
CE#=VIL,A6=1
Activate WE# Pulse
Time Out 12ms
Increment
PLSCNT
Set OE#=CE#=VIL
A9=VID,A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Yes
PLSCNT=1000?
Increment
Sector Addr
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove VID from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect the whole chip, all sectors should be protected in advance.
P/N:PM1250
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MX29F200C T/B
TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE#
tCEP
WE#
* See the following Note!
CE#
Data
Don't care
(Note 2)
01H
F0H
tOE
A16-A12
Sector Address
Note1: Must issue "unlock for sector protect/unprotect" command before sector protection
for a system without 12V provided.
Note2: Except F0H
P/N:PM1250
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36
MX29F200C T/B
TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V
A1
A6
Toggle bit polling
Verify
5V
OE#
tCEP
WE#
* See the following Note!
CE#
Data
Don't care
(Note 2)
F0H
00H
tOE
Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection
for a system without 12V provided.
Note2: Except F0H
P/N:PM1250
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MX29F200C T/B
SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V
START
PLSCNT=1
Write "unlock for sector protect/unprotect"
Command (Table1)
Set Up Sector Addr
(A16,A15,A14,A13,A12)
OE#=VIH, A9=VIH
CE#=VIL, A6=VIL
Activate WE# Pulse to start
Data don't care
No
Toggle bit checking
Q6 not Toggled
Yes
Increment PLSCNT
Set CE#=OE#=VIL
A9=VIH
Read from Sector
Addr=SA, A1=1
No
No
Data=01H?
Yes
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
No
Write Reset Command
Sector Protection
Complete
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MX29F200C T/B
SECTORUNPROTECTIONALGORITHMFORSYSTEMWITHOUT12V
START
Protect All Sectors
PLSCNT=1
Write "unlock for sector protect/unprotect"
Command (Table 1)
Set OE#=A9=VIH
CE#=VIL,A6=1
Activate WE# Pulse to start
Data don't care
No
Toggle bit checking
DQ6 not Toggled
Increment
PLSCNT
Yes
Set OE#=CE#=VIL
A9=VIH,A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Yes
Increment
PLSCNT=1000?
Sector Addr
Yes
Device Failed
No
All sectors have
been verified?
Yes
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect the whole chip, all sectors should be protected in advance.
P/N:PM1250
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MX29F200C T/B
ID CODE READ TIMING WAVEFORM
VCC
5V
VID
ADD
A9
VIH
VIL
tACC
tACC
A1 VIH
VIL
ADD
A2-A8
VIH
A10-A17 VIL
CE#
VIH
VIL
VIH
VIL
tCE
WE#
OE#
tOE
VIH
VIL
tDF
tOH
tOH
VIH
VIL
DATA
Q0-Q15
DATA OUT
DATA OUT
C2H/00C2H
51H/57H (Byte mode)
2251H/2257H (Word mode)
P/N:PM1250
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MX29F200C T/B
RECOMMENDED OPERATING CONDITIONS
AtDevicePower-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.
If the timing in the figure is ignored, the device may not operate correctly.
VCC(min)
VCC
GND
tVR
tACC
tR or tF
tR or tF
VIH
VIL
Valid
ADDRESS
CE#
Address
tF
tCE
tR
VIH
VIL
VIH
VIL
WE#
tF
tOE
tR
VIH
VIL
OE#
VOH
VOL
High Z
Valid
Ouput
DATA
Figure A. AC Timing at Device Power-Up
Notes
Symbol
Parameter
Min.
Max.
Unit
tVR
tR
VCC Rise Time
1
20
500000
20
us/V
us/V
us/V
Inptut Signal Rise Time
Inptut Signal Fall Time
1,2
1,2
tF
20
Notes :
1. Sampled, not 100% tested.
2. This specification is applied for not only the device power-up but also the normal operations.
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MX29F200C T/B
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
PARAMETER
MIN.
TYP.(2)
0.7
4
MAX.(3)
15
UNITS
sec
Sector Erase Time
Chip Erase Time
32
sec
Byte Programming Time
WordProgrammingTime
ChipProgrammingTime Byte Mode
WordMode
9
300
360
6.8
us
11
us
2.3
1.5
sec
4.5
sec
Erase/ProgramCycles
100,000
Cycles
Note: 1. Not 100% Tested, Excludes external system level over head.
2. Typical values measured at 25° C,5V.
3. Maximum values measured at worst condition: 90° C, 4.5V, 100K cycles.
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
13.5V
VCC + 1.0V
+100mA
-1.0V
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
DATA RETENTION
PARAMETER
MIN.
UNIT
DataRetentionTime
20
Years
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MX29F200C T/B
ORDERING INFORMATION
PARTNO.
ACCESS
OPERATING
STANDBY
PACKAGE
Remark
TIME (ns) CurrentMAX. (mA) CurrentMAX.(uA)
MX29F200CTMC-70
MX29F200CTMC-90
MX29F200CTTC-70
70
90
70
40
40
40
5
5
5
44 Pin SOP
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
44 Pin SOP
MX29F200CTTC-90
90
40
5
MX29F200CBMC-70
MX29F200CBMC-90
MX29F200CBTC-70
70
90
70
40
40
40
5
5
5
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
44 Pin SOP
MX29F200CBTC-90
90
40
5
MX29F200CTMI-70
MX29F200CTMI-90
MX29F200CTTI-70
70
90
70
40
40
40
5
5
5
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
44 Pin SOP
MX29F200CTTI-90
90
40
5
MX29F200CBMI-70
MX29F200CBMI-90
MX29F200CBTI-70
70
90
70
40
40
40
5
5
5
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
MX29F200CBTI-90
90
40
5
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43
MX29F200C T/B
PARTNO.
ACCESS
OPERATING
STANDBY
PACKAGE
Remark
TIME (ns) CurrentMAX. (mA) CurrentMAX.(uA)
MX29F200CTMC-70G
MX29F200CTMC-90G
MX29F200CTTC-70G
70
90
70
40
40
40
5
5
5
44 Pin SOP
Pb-free
Pb-free
Pb-free
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
44 Pin SOP
MX29F200CTTC-90G
90
40
5
Pb-free
MX29F200CBMC-70G
MX29F200CBMC-90G
MX29F200CBTC-70G
70
90
70
40
40
40
5
5
5
Pb-free
Pb-free
Pb-free
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
44 Pin SOP
MX29F200CBTC-90G
90
40
5
Pb-free
MX29F200CTMI-70G
MX29F200CTMI-90G
MX29F200CTTI-70G
70
90
70
40
40
40
5
5
5
Pb-free
Pb-free
Pb-free
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
44 Pin SOP
MX29F200CTTI-90G
90
40
5
Pb-free
MX29F200CBMI-70G
MX29F200CBMI-90G
MX29F200CBTI-70G
70
90
70
40
40
40
5
5
5
Pb-free
Pb-free
Pb-free
44 Pin SOP
48 Pin TSOP
(NormalType)
48 Pin TSOP
(NormalType)
MX29F200CBTI-90G
90
40
5
Pb-free
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MX29F200C T/B
PART NAME DESCRIPTION
MX 29 F 200 C T T C 70 G
OPTION:
G: Lead-free package
SPEED:
70:70ns
90: 90ns
TEMPERATURE RANGE:
C: Commercial (0˚C to 70˚C)
I: Industrial (-40˚C to 85˚C)
PACKAGE:
M:SOP
T: TSOP
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
C
DENSITY & MODE:
200: 2M, x8/x16 Boot Sector
TYPE:
F: 5V
DEVICE:
29: Flash
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MX29F200C T/B
PACKAGE INFORMATION
P/N:PM1250
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MX29F200C T/B
P/N:PM1250
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MX29F200C T/B
REVISION HISTORY
RevisionNo. Description
Page
Date
0.01
1. Added"RecommendedOperatingConditions"
P41
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MX29F200C T/B
MACRONIX INTERNATIONALCO., LTD.
Headquarters:
TEL:+886-3-578-6688
FAX:+886-3-563-2888
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http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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