MX29F805PC-90 [Macronix]
Flash, 512KX16, 90ns, PDIP42, 0.600 INCH, PLASTIC, DIP-42;
| 型号： | MX29F805PC-90 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 512KX16, 90ns, PDIP42, 0.600 INCH, PLASTIC, DIP-42 光电二极管 内存集成电路 |
| 文件： | 总29页 (文件大小：146K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX29F805
8M-BIT [1Mx8/512Kx16] CMOS FLASH MEMORY
FEATURES
• 1,048,576 x 8/524,288 x 16 switchable
• Auto Erase and Auto Program
- Automatically program and verify data at specified
address
• Dual power supply operation
- 5.0V only operation for read, 10.0V for erase and
program operations
• Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
• Fast access time: 90/120ns
• Low power consumption
- 30mA maximum active current
- 1uA typical standby current
• 100 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Low VCC write inhibit is equal to or less than 3.2V
• Command register architecture
- Word Programming (14us typical)
• Package type:
- 42-pin PDIP
GENERAL DESCRIPTION
The MX29F805 is a 8-mega bit Flash memory orga-
nized as 1M bytes of 8 bits or 512K words of 16 bits.
MXIC's Flash memories offer the most cost-effective and
reliable read/write non-volatile random access memory.
The MX29F805 is packaged in 42-pin PDIP. It is de-
signed to be reprogrammed and erased in system or in
standard EPROM programmers.
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 100 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX29F805 needs 10V power supply to per-
form the High Reliability Erase and auto Program/Erase
algorithms.
The standard MX29F805 offers access time as fast as
90ns, allowing operation of high-speed microprocessors
without wait states. To eliminate bus contention, the
MX29F805 has separate chip enable (CE) and output
enable (OE) controls.
MXIC's Flash memories augment EPROM functionality
with electrical erasure and programming. The
MX29F805 uses a command register to manage this
functionality. The command register allows for 100%
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
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1
MX29F805
PIN CONFIGURATIONS
42 PDIP(600 mil)
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A18
Q0~Q14
Q15/A-1
Address Input
Data Input/Output
Q15(Word mode)/LSB addr(Byte mode, for
read operation only)
DU
A18
A17
A7
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
1
A8
2
A9
3
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
A6
4
CE
Chip Enable Input
A5
5
A4
6
BYTE/VPP Word/Byte Selction input, for read operation
only.VPP=VHH for Erase/Program operation.
A3
7
A2
8
A1
9
OE
Output Enable Input
Power Supply Pin (+5V)
Ground Pin
A0
10
11
12
13
14
15
16
17
18
19
20
21
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
VCC
GND
DU
Q14
Q6
Do Not Use
Q13
Q5
Q12
Q4
VCC
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MX29F805
BLOCK DIAGRAM
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
CE
OE
BYTE/VPP
MACHINE
(WSM)
LOGIC
STATE
MX29F805
FLASH
REGISTER
ADDRESS
LATCH
ARRAY
ARRAY
SOURCE
HV
A0-A18
AND
COMMAND
DATA
DECODER
BUFFER
Y-PASS GATE
PGM
DATA
HV
SENSE
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
I/O BUFFER
Q0-Q15/A-1
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MX29F805
AUTOMATIC PROGRAMMING
AUTOMATIC ERASE ALGORITHM
The MX29F805 is word programmable using the Auto-
matic Programming algorithm. The Automatic Program-
ming algorithm makes the external system do not need
to have time out sequence nor to verify the data pro-
grammed. The typical chip programming time at room
temperature of the MX29F805 is less than 4 seconds.
MXIC's Automatic Erase algorithm requires the user to
write commands to the command register using stan-
dard microprocessor write timings. The device will au-
tomatically pre-program and verify the entire array. Then
the device automatically times the erase pulse width,
provides the erase verification, and counts the number
of sequences. A status bit toggling between consecu-
tive read cycles provides feedback to the user as to the
status of the programming operation.
AUTOMATIC CHIP ERASE
The entire chip is bulk erased using 10 ms erase pulses
according to MXIC's Automatic Chip Erase algorithm.
Typical erasure at room temperature is accomplished
in less than 4 second. The Automatic Erase algorithm
automatically programs the entire array prior to electri-
cal erase. The timing and verification of electrical erase
are controlled internally within the device.
Register contents serve as inputs to an internal state-
machine which controls the erase and programming cir-
cuitry. During write cycles, the command register inter-
nally latches address and data needed for the program-
ming and erase operations. During a system write cycle,
addresses are latched on the falling edge, and data are
latched on the rising edge of CE .
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, reli-
ability, and cost effectiveness. The MX29F805 electri-
cally erases all bits simultaneously using Fowler-
Nordheim tunneling. The bytes are programmed by us-
ing the EPROM programming mechanism of hot elec-
tron injection.
MXIC's Automatic Programming algorithm requires the
user to only write program set-up commands (including
2 unlock write cycle and A0H) and a program command
(program data and address). The device automatically
times the programming pulse width, provides the pro-
gram verification, and counts the number of sequences.
A status bit similar to DATA polling and a status bit tog-
gling between consecutive read cycles, provide feed-
back to the user as to the status of the programming
operation.
During a program cycle, the state-machine will control
the program sequences and command register will not
respond to any command set.
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MX29F805
TABLE1. SOFTWARE COMMAND DEFINITIONS(BYTE/VPP=VHH)
First Bus
Bus Cycle
Second Bus Third Bus
Cycle Cycle
Fourth Bus
Cycle
Fifth Bus
Cycle
Sixth Bus
Cycle
Command
Cycle Addr Data Addr Data Addr
Data Addr Data Addr
Data Addr Data
Reset
1
1
4
4
6
XXXH F0H
RA RD
Read
Read Silicon ID Word
555H AAH 2AAH 55H 555H 90H ADI
555H AAH 2AAH 55H 555H A0H PA
DDI
PD
Porgram
Word
Word
Chip Erase
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H
555H 10H
Legend:
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code. A2 to A18=Do not care.
(Refer to table 3)
DDI = Data of Device identifier : C2H for manufacture code, B4H for device code.
X = X can be VIL or VIH
RA=Address of memory location to be read.
RD=Data to be read at location RA.
PA = Address of memory location to be programmed.
PD = Data to be programmed at location PA.
Note:
1. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode.
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA). Write Sequence may be
initiated with A11~A18 in either state.
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MX29F805
COMMAND DEFINITIONS
Device operations are selected by writing specific address and data sequences into the command register. Writing
incorrect address and data values or writing them in the improper sequence will reset the device to the read mode.
Table 1 defines the valid register command sequences.
TABLE 2. MX29F805 BUS OPERATION
Pins
CE OE BYTE/VPP A0
A1
L
A6
X
A9
Q0 ~ Q15
Mode
Read Silicon ID
L
L
L
L
H/L
H/L
L
VID(2)
VID(2)
C2H (Byte mode)
00C2H (Word mode)
B4H (Byte mode)
22B4H (Word mode)
DOUT
Manfacturer Code(1)
Read Silicon ID
Device Code(1)
Read
H
L
X
L
H
L
L
H/L
X
A0
X
A1
X
A6
X
A9
X
Standby
X
H
H
X
HIGH Z
Output Disable
Write(6)
H/L
VHH
X
X
X
X
X
HIGH Z
L
A0
X
A1
X
A6
X
A9
X
DIN(3)
Reset
X
HIGH Z
NOTES:
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 1.
2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.
3. Refer to Table 1 for valid Data-In during a write operation.
4. X can be VIL or VIH.
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MX29F805
SET-UP AUTOMATIC CHIP ERASE
READ/RESET COMMAND
COMMANDS
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the com-
mand register contents are altered.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cy-
cles are then followed by the chip erase command 10H.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the
Automatic Chip Erase. Upon executing the Automatic
Chip Erase, the device will automatically program and
verify the entire memory for an all-zero data pattern.
When the device is automatically verified to contain an
all-zero pattern, a self-timed chip erase and verify be-
gin. The erase and verify operations are completed when
the data on Q7 is "1" at which time the device returns to
the Read mode. The system is not required to provide
any control or timing during these operations.
SILICON-ID-READ COMMAND
Flash memories are intended for use in applications
where the local CPU alters memory contents. As such,
manufacturer and device codes must be accessible while
the device resides in the target system. PROM pro-
grammers typically access signature codes by raising
A9 to a high voltage(VID). However, multiplexing high
voltage onto address lines is not generally desired sys-
tem design practice.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory
array(no erase verification command is required).
The MX29F805 contains a Silicon-ID-Read operation
to supplement traditional PROM programming method-
ology. The operation is initiated by writing the read sili-
con ID command sequence into the command register.
Following the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H/00C2H.
A read cycle with A1=VIL, A0=VIH returns the device
code of for MX29F805.
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 4), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last CE pulse in the command sequence and terminates
when the data on Q7 is "1" and the data on Q6 stops
toggling for two consecutive read cycles, at which time
the device returns to the Read mode.
TABLE 3. EXPANDED SILICON ID CODE
Pins
A0
A1
Q15~Q8 Q7 Q6 Q5
Q4 Q3 Q2 Q1 Q0 Code(Hex)
Manufacture code Word VIL
Byte VIL
VIL 00H
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
00C2H
C2H
VIL
X
Device code
Word VIH VIL 22H
Byte VIH VIL
22B4H
B4H
for MX29F805
X
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MX29F805
Table 4.Write Operation Status
Status
Operation
Q7
Q7
0
Q6
Q5
0
Q3
N/A No Toggle
Toggle
N/A No Toggle
Toggle
Q2
Byte Program in Auto Program Algorithm
Auto Erase Algorithm
Toggle
Toggle
Toggle
Toggle
In Progress
Exceeded
0
1
Byte Program in Auto Program Algorithm
Q7
0
1
Time Limits Program/Erase in Auto Erase Algorithm
1
1
Notes:
1.Performing successive read operations from any address will cause Q6 to toggle while in program/erase mode.
2.Reading the byte address being programmed will indicate No Toggle at the Q2 bit.
SET-UP AUTOMATIC PROGRAM COMMANDS
DATA POLLING-Q7
To initiate Automatic Program mode, A three-cycle com-
mand sequence is required. There are two "unlock" write
cycles. These are followed by writing the Automatic Pro-
gram command A0H.
The MX29F805 also features Data Polling as a method
to indicate to the host system that the Automatic Pro-
gram or Erase algorithms are either in progress or com-
pleted.
Once the Automatic Program command is initiated, the
next CE pulse causes a transition to an active program-
ming operation. Addresses are latched on the falling
edge, and data are internally latched on the rising
edge of the CE pulse. The rising edge of CE also be-
gins the programming operation. The system is not re-
quired to provide further controls or timings. The device
will automatically provide an adequate internally gener-
ated program pulse and verify margin.
While the Automatic Programming algorithm is in op-
eration, an attempt to read the device will produce the
complement data of the data last written to Q7. Upon
completion of the Automatic Program Algorithm an at-
tempt to read the device will produce the true data last
written to Q7. The Data Polling feature is valid after the
rising edge of the fourth CE pulse of the four write pulse
sequences for automatic program.
While the Automatic Erase algorithm is in operation, Q7
will read "0" until the erase operation is competed. Upon
completion of the erase operation, the data on Q7 will
read "1". The Data Polling feature is valid after the ris-
ing edge of the sixth CE pulse of six write pulse se-
quences for automatic chip/sector erase.
If the program opetation was unsuccessful, the data on
Q5 is "1"(seeTable 4), indicating the program operation
exceed internal timing limit.The automatic programming
operation is completed when the data read on Q6 stops
toggling for two consecutive read cycles and the data
on Q7 and Q6 are equivalent to data written to these
two bits, at which time the device returns to the Read
mode(no program verify command is required).
The Data Polling feature is active during Automatic Pro-
gram/Erase algorithm
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8
MX29F805
Q6:Toggle BIT I
Reading Toggle Bits Q6/ Q2
Toggle Bit I on Q6 indicates whether an Automatic Pro-
gram or Erase algorithm is in progress or complete.
Toggle Bit I may be read at any address, and is valid
after the rising edge of the final CE pulse in the com-
mand sequence(prior to the program or erase opera-
tion).
Whenever the system initially begins reading toggle bit
status, it must read Q7-Q0 at least twice in a row to
determine whether a toggle bit is toggling. Typically, the
system would note and store the value of the toggle bit
after the first read. After the second read, the system
would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on Q7-Q0 on the following read cycle.
During an Automatic Program or Erase algorithm op-
eration, successive read cycles to any address cause
Q6 to toggle. The system may use either OE or CE to
control the read cycles.When the operation is complete,
Q6 stops toggling.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of Q5 is high
(see the section on Q5). If it is, the system should then
determine again whether the toggle bit is toggling, since
the toggle bit may have stopped toggling just as Q5 went
high. If the toggle bit is no longer toggling, the device
has successfuly completed the program or erase op-
eration. If it is still toggling, the device did not complete
the operation successfully, and the system must write
the reset command to return to reading array data.
Q2:Toggle Bit II
The "Toggle Bit II" on Q2, when used with Q6, indicates
whether the device is actively eraseing (that is, the Au-
tomatic Erase alorithm is in process), or whether that
sector is erase-suspended. Toggle Bit I is valid after the
rising edge of the final CE pulse in the command se-
quence.
The remaining scenario is that system initially deter-
mines that the toggle bit is toggling and Q5 has not gone
high. The system may continue to monitor the toggle bit
and Q5 through successive read cycles, determining
the status as described in the previous paragraph. Al-
ternatively, it may choose to perform other system tasks.
In this case, the system must start at the beginning of
the algorithm when it returns to determine the status of
the operation.
Q2 toggles when the device is in erase operation. (The
system may use either OE or CE to control the read
cycles.) Refer toTable 4 to compare outputs for Q2 and
Q6.
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MX29F805
Q5
Exceeded Timing Limits
WRITE PULSE "GLITCH" PROTECTION
Q5 will indicate if the program or erase time has ex-
ceeded the specified limits(internal pulse count). Un-
der these conditions Q5 will produce a "1". This time-
out condition indicates that the program or erase cycle
was not successfully completed. Data Polling andToggle
Bit are the only operating functions of the device under
this condition.
Noise pulses of less than 5ns(typical) on CE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL, CE
= VIH or BYTE/VPP=VIH/VIL To initiate a write cycle
CE and WE must be a logical zero while OE is a logical
one.
If this time-out condition occurs during the chip erase
operation, it specifies that the entire chip is bad.
POWER SUPPLY DECOUPLING
If this time-out condition occurs during the byte program-
ming operation, it specifies that byte is bad and maynot
be reused, (other sectors are still functional and can be
reused).
In order to reduce power switching effect, each device
should have a 0.1uF ceramic capacitor connected be-
tween its VCC and GND.
The time-out condition may also appear if a user tries to
program a non blank location without erasing. In this
case the device locks out and never completes the Au-
tomatic Algorithm operation. Hence, the system never
reads a valid data on Q7 bit and Q6 never stops tog-
gling. Once the Device has exceeded timing limits, the
Q5 bit will indicate a "1". Please note that this is not a
device failure condition since the device was incorrectly
used.
POWER-UP SEQUENCE
The MX29F805 powers up in the Read only mode. In
addition, the memory contents may only be altered af-
ter successful completion of the predefined command
sequences.
ABSOLUTE MAXIMUM RATINGS
DATA PROTECTION
RATING
VALUE
The MX29F805 is designed to offer protection against
accidental erasure or programming caused by spurious
system level signals that may exist during power transi-
tion. During power up the device automatically resets
the state machine in the Read mode. In addition, with
its control register architecture, alteration of the memory
contents only occurs after successful completion of spe-
cific command sequences. The device also incorpo-
rates several features to prevent inadvertent write cycles
resulting from VCC power-up and power-down transi-
tion or system noise.
Ambient OperatingTemperature
StorageTemperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9,OE
0oC to 70oC
-65oC to 125oC
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 7.0V
-0.5V to 13.5V
-0.5V to 10.5V
BYTE/VPP
NOTICE:
Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the de-
vice. This is a stress rating only and functional operational
sections of this specification is not implied. Exposure to ab-
solute maximum rating conditions for extended period may
affect reliability.
NOTICE:
Specifications contained within the following tables are sub-
ject to change.
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10
MX29F805
CAPACITANCE TA = 25oC, f = 1.0 MHz
SYMBOL
CIN
PARAMETER
MIN.
TYP
MAX.
8
UNIT
pF
CONDITIONS
VIN = 0V
Input Capacitance
Output Capacitance
COUT
12
pF
VOUT = 0V
READ OPERATION
DC CHARACTERISTICS TA = 0oCTO 70oC, VCC = 5V±10%
SYMBOL
ILI
PARAMETER
MIN.
TYP
MAX.
UNIT
uA
uA
mA
uA
mA
mA
V
CONDITIONS
Input Leakage Current
Output Leakage Current
Standby VCC current
1
VIN = GND to VCC
VOUT = GND to VCC
CE = VIH
ILO
±1
ISB1
ISB2
ICC1
ICC2
VIL
1
0.2
5
CE = VCC + 0.3V
IOUT = 0mA, f=1MHz
IOUT= 0mA, f=10MHz
Operating VCC current
30
50
Input Low Voltage
-0.3(NOTE 1)
2.0
0.8
VIH
Input High Voltage
VCC + 0.3
0.45
V
VOL
Output Low Voltage
Output High Voltage(TTL)
V
IOL = 2.1mA
IOH = -2mA
VOH1
VOH2
2.4
V
Output High Voltage(CMOS) VCC-0.4
V
IOH = -100uA,
VCC=VCC MIN.
NOTES:
1.VIL min. = -1.0V for pulse width is equal to or less than 50 ns.
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.
2.VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
AC CHARACTERISTICS TA = 0oC to 70oC,VCC = 5V ±10%
29F805-90
29F805-12
SYMBOL PARAMETER
MIN. MAX.
MIN. MAX. UNIT CONDITIONS
tACC
tCE
tOE
tDF
Address to Output Delay
90
90
40
120
120
50
ns
ns
ns
ns
ns
CE=OE=VIL
OE=VIL
CE to Output Delay
OE to Output Delay
CE=VIL
OE High to Output Float (Note1)
Address to Output hold
0
0
20
0
0
30
CE=VIL
tOH
CE=OE=VIL
NOTE:
TEST CONDITIONS:
1. tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times is equal to or less than 10ns
• Outputload:1TTLgate+100pF(Includingscopeand
jig)
• Reference levels for measuring timing: 0.8V, 2.0V
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11
MX29F805
READ TIMING WAVEFORMS
VIH
ADD Valid
Addresses
VIL
tCE
VIH
CE
VIL
VIH/VIL
BYTE/VPP
tDF
tOE
VIH
OE
tACC
VIL
tOH
HIGH Z
HIGH Z
VOH
VOL
Outputs
DATA Valid
COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION
DC CHARACTERISTICS TA = 0oC to 70oC,VCC = 5V ±10%
SYMBOL
ICC1 (Read)
ICC2
PARAMETER
MIN.
TYP
MAX. UNIT CONDITIONS
Operating VCC Current
30
50
50
50
mA
mA
mA
mA
mA
IOUT=0mA, f=1MHz
IOUT=0mA, F=10MHz
In Programming
ICC3 (Program)
ICC4 (Erase)
ICCES
In Erase
VCC Erase Suspend Current
2
CE=VIH, Erase Suspended
NOTES:
1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.
2. If VIH is over the specified maximum value, programming operation cannot be guranteed.
3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is the sum of
ICCES and ICC1 or ICC2.
4. All current are in RMS unless otherwise noted.
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MX29F805
AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE/VPP)
Speed Options
SYMBOL
tELFL/tELFH
tFLQZ
Description
90
5
120
5
unit
ns
CE to BYTE/VPP Switching Low or High
MAX
BYTE/VPP Switching Low to Output HIHG Z Max
BYTE/VPP Switching High to Output Active Min
30
90
30
ns
tFHQV
120
ns
Figure 6. BYTE/VPP TIMING WAVEFORMS
CE
OE
VIH
BYTE/VPP
VIL
tELFL
BYTE/VPP
Q0~Q14
Data Output
(Q0~Q14)
Data Output
(Q0~Q7)
Switching
from word
to byte
mode read
Q15/A-1
Q15
Output
Address Input
tFLQZ
tELFL
VIH
BYTE/VPP VIL
Data Output
(Q0~Q7)
Data Output
(Q0~Q14)
BYTE/VPP
Switching
Q0~Q14
from byte
to word
Q15
Output
mode read
Address Input
tFHQV
Q15/A-1
P/N:PM0614
REV. 0.1, OCT. 06, 1999
13
MX29F805
AC CHARACTERISTICS TA = 0oC to 70oC,VCC = 5V ±10%
29F805-90
29F805-12
SYMBOL PARAMETER
MIN. MAX.
MIN. MAX. UNIT CONDITIONS
tOES
tCWC
tAS
OE setup time
50
50
ns
ns
ns
ns
us
us
ns
s
Command programming cycle
Address setup time
90
120
0
0
tAH
Address hold time
45
50
tVPS
tVPH
tCESC
tAETC
tAVT
BYTE/Vpp Setup Time
BYTE/Vpp Hold Time
2
2
2
2
CE setup time before command write
Total erase time in auto chip erase
Total programming time in auto verify
( word program time)
0
0
8(TYP.)
14(TYP.)
8(TYP.)
14(TYP.)
us
tCH
CE Hold Time
0
0
4
0
0
4
ns
ns
us
tCS
CE setup to WE going low
Voltge Transition Time
tVLHT
tOESP
OE Setup Time to BYTE/VPP Active
4
4
us
P/N:PM0614
REV. 0.1, OCT. 06, 1999
14
MX29F805
SWITCHINGTEST CIRCUITS
DEVICE UNDER
TEST
1.6K ohm
+5V
CL
1.2K ohm
DIODES=IN3064
OR EQUIVALENT
CL=100pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V
0.8V
2.0V
TEST POINTS
0.8V
0.45V
INPUT
OUTPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are <20ns.
P/N:PM0614
REV. 0.1, OCT. 06, 1999
15
MX29F805
COMMAND WRITE TIMING WAVEFORM
CE
tOES
OE
tVPH
tVPS
10V
BYTE/VPP
tAS
tAH
ADDRESSES
VALID
tDH
HIGH Z
DIN
DATA
VCC
tDS
tVCS
P/N:PM0614
REV. 0.1, OCT. 06, 1999
16
MX29F805
AUTOMATIC PROGRAMMING TIMING
WAVEFORM
One byte data is programmed. Verify in fast algorithm
and additional programming by external control are not
required because these operations are executed auto-
matically by internal control circuit. Programming
completion can be verified by DATA polling and toggle
bit checking after automatic verification starts. Device
outputs DATA during programming and DATA after pro-
gramming on Q7.(Q6 is for toggle bit; see toggle bit,
DATA polling, timing waveform)
AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A18
ADD Valid
ADD Valid
2AAH
555H
A0~A10
BYTE/VPP
CE
555H
tAS
10V
tVPH
tVPS
tCESC
tAVT
tCEP
OE
tDS tDH
tDF
Q0,Q1,
DATA
DATA
Command In
Command In
Command In
Data In
DATA polling
Q4(Note 1)
DATA
Command In
Command In
Command In
Data In
Q7
Command #A0H
Command #55H
Command #AAH
(Q0~Q7)
tOE
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q2: Toggle bit
(2). BYTE/VPP must not be VHH while reading status.
P/N:PM0614
REV. 0.1, OCT. 06, 1999
17
MX29F805
AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)
START
BYTE/VPP=VHH
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
BYTE/VPP=VIH/VIL
Increment
Address
Data Poll
from system
No
Verify Byte Ok ?
YES
No
Last Address ?
YES
Auto Program Completed
P/N:PM0614
REV. 0.1, OCT. 06, 1999
18
MX29F805
AUTOMATIC CHIP ERASE TIMING WAVEFORM
All data in chip are erased. External erase verification
is not required because data is erased automatically
by internal control circuit. Erasure completion can be
verified by DATA polling and toggle bit checking after
automatic erase starts. Device outputs 0 during era-
sure and 1 after erasure on Q7.(Q6 is for toggle bit; see
toggle bit, DATA polling, timing waveform)
AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)
Vcc 5V
A11~A18
2AAH
555H
555H
2AAH
A0~A10
BYTE/VPP
CE
555H
tAS
555H
10V
tVPS
tVPH
tCESC
tCEP
OE
tDS tDH
Command In
Q0,Q1,
Command In
Command In
Command In
Command In
Command In
Q4(Note 1)
DATA polling
Command In
Command In
Command In
Command In
Command In
Command In
Q7
Command #80H
Command #AAH
Command #55H
Command #10H
Command #AAH
(Q0~Q7)
Command #55H
Notes:
(1). Q6:Toggle bit, Q5:Timing-limit bit, Q2: Toggle bit
(2). BYTE/VPP must not be VHH while reading status.
P/N:PM0614
REV. 0.1, OCT. 06, 1999
19
MX29F805
AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)
START
BYTE/VPP=VHH
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
BYTE/VPP=VIH/VIL
Data Poll
from system
YES
DATA = FFh ?
YES
Auto Erase Completed
P/N:PM0614
REV. 0.1, OCT. 06, 1999
20
MX29F805
DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
VA
VA
Address
CE
tCE
tOE
OE
tDF
tOH
High Z
High Z
Complement
Status Data
Status Data
Status Data
True
True
Valid Data
Valid Data
Q7
Q0-Q6
NOTES:
VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.
P/N:PM0614
REV. 0.1, OCT. 06, 1999
21
MX29F805
Data Polling Algorithm
START
Read Q7~Q0
Add. = VA (1)
Yes
Q7 = Data ?
No
No
Q5 = 1 ?
Yes
Read Q7~Q0
Add. = VA
Yes
Q7 = Data ?
(2)
No
PASS
FAIL
Notes:
1. VA=valid address for programming.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
P/N:PM0614
REV. 0.1, OCT. 06, 1999
22
MX29F805
TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALOGRITHMS)
VA
VA
VA
VA
Address
CE
tCE
tOE
OE
tDF
tOH
Valid Status
(second read)
Valid Status
(first raed)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
NOTES:
VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and
array data read cycle.
P/N:PM0614
REV. 0.1, OCT. 06, 1999
23
MX29F805
Toggle Bit Algorithm
START
Read Q7~Q0
Read Q7~Q0
(Note 1)
NO
Toggle Bit Q6
=Toggle?
YES
NO
Q5=1?
YES
(Note 1,2)
Read Q7~Q0 Twice
Toggle Bit Q6=
Toggle?
YES
Program/Erase Operation Not
Program/Erase Operation Complete
Complete, Write Reset Command
Note:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
P/N:PM0614
REV. 0.1, OCT. 06, 1999
24
MX29F805
ID CODE READ TIMING WAVEFORM
VCC
5V
VID
ADD
A9
VIH
VIL
VIH
VIL
ADD
A0
tACC
tACC
ADD
A1-A8
VIH
A10-A18 VIL
CE
VIH
VIL
VIH
VIL
tCE
BYTE/VPP
OE
tOE
VIH
VIL
tDF
tOH
tOH
VIH
VIL
DATA
Q0-Q15
DATA OUT
DATA OUT
B4H (Byte)
C2H/00C2H
22B4H (Word)
P/N:PM0614
REV. 0.1, OCT. 06, 1999
25
MX29F805
ORDERING INFORMATION
PLASTIC PACKAGE
PART NO.
ACCESSTIME OPERATING CURRENT STANDBY CURRENT PACKAGE
(ns)
90
MAX.(mA, at10MHz)
MAX.(uA)
MX29F805PC-90
MX29F805PC-12
50
50
5
5
42 Pin PDIP
42 Pin PDIP
120
ERASE AND PROGRAMMING PERFORMANCE
LIMITS
TYP.
PARAMETER
MIN.
MAX.
UNITS
Chip Erase Time
16
14
7
128
21
sec
us
Word Programming Time
Chip Programming Time
Erase/Program Cycles
21
sec
100
Cycles
LATCHUP CHARACTERISTICS
MIN.
-1.0V
MAX.
13.5V
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
-1.0V
Vcc + 1.0V
+100mA
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.
P/N:PM0614
REV. 0.1, OCT. 06, 1999
26
MX29F805
PACKAGE INFORMATION
42-PIN PLASTIC DIP(600 mil)
ITEM
A
MILLIMETERS INCHES
42
22
52.54 max.
0.76 [REF]
2.54 [TP]
.46 [Typ.]
50.76
2.070 max.
.030 [REF]
.100 [TP]
B
C
D
E
.018 [Typ.]
2.000
1
21
F
1.27 [Typ.]
3.30 ±. 25
.51 [REF]
3.94 ±. 25
5.33 max.
15.22 ±.25
13.97± .25
.25 [Typ.]
.050 [Typ.]
.130 ±.010
.020 [REF]
.155 ±.010
.210 max.
.600 ±.010
.550 ±.010
.010 [Typ.]
A
G
H
I
K
L
I
J
J
K
H
G
L
F
B
M
0~15¡
C
M
D
NOTE: Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum material condition.
E
P/N:PM0614
REV. 0.1, OCT. 06, 1999
27
MX29F805
REVISION HISTORY
Revision
Description
Page
Date
0.1
Remove sector-related features of sector structure, sector
protect/unprotect, sector erase suspend/resume, and
top/bottom boot block
P1~10, 12~14 OCT/06/1999
P17, 20~30, 32
Add Data polling and toggle bit timing waveforms and
flowcharts
P21, 22
Change device ID to B4H
P5, 6, 7, 25
P/N:PM0614
REV. 0.1, OCT. 06, 1999
28
MX29F805
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
TEL:+886-3-578-8888
FAX:+886-3-578-8887
EUROPE OFFICE:
TEL:+32-2-456-8020
FAX:+32-2-456-8021
JAPAN OFFICE:
TEL:+81-44-246-9100
FAX:+81-44-246-9105
SINGAPORE OFFICE:
TEL:+65-747-2309
FAX:+65-748-4090
TAIPEI OFFICE:
TEL:+886-3-509-3300
FAX:+886-3-509-2200
MACRONIX AMERICA, INC.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
CHICAGO OFFICE:
TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice.
29
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