MX29GA129E_技术文档

MX29GA256/257E H/L

MX29GA128/129E H/L

MX29GA - E Series

DATASHEET

P/N:PM1484

REV. 0.02, MAR. 06, 2009

1

PRELIMINARY

MX29GA256/257E H/L

MX29GA128/129E H/L

SINGLE VOLTAGE 3V ONLY FLASH MEMORY

FEATURES

GENERAL FEATURES

•ꢀ PowerꢀSupplyꢀOperation

ꢀ -ꢀ2.7ꢀtoꢀ3.6ꢀvoltꢀforꢀread,ꢀerase,ꢀandꢀprogramꢀoperations

ꢀ -ꢀVꢀI/OꢀꢀvoltageꢀmustꢀtightꢀwithꢀVCC

ꢀ ꢀ

-ꢀVꢀI/O=VCC=2.7V~3.6V

•ꢀ Byte/Wordꢀmodeꢀswitchable

ꢀ -ꢀ33,554,432ꢀxꢀ8ꢀ/ꢀ16,777,216ꢀxꢀ16ꢀ(MX29GA256/257EꢀH/L)

ꢀ -ꢀ16,777,216ꢀxꢀ8ꢀ/ꢀ8,388,608ꢀxꢀ16ꢀ(MX29GA128/129EꢀH/L)

•ꢀ 64KW/128KBꢀuniformꢀsectorꢀarchitecture

ꢀ -ꢀMX29GA256/257EꢀH/L:ꢀ256ꢀequalꢀsectors

ꢀ -ꢀMX29GA128/129EꢀH/L:ꢀ128ꢀequalꢀsectors

•ꢀ 16-byte/8-wordꢀpageꢀreadꢀbuffer

•ꢀ 64-byte/32-wordꢀwriteꢀbuffer

•ꢀ Latch-upꢀprotectedꢀtoꢀ100mAꢀfromꢀ-1Vꢀtoꢀ1.5xVcc

•ꢀ LowꢀVccꢀwriteꢀinhibitꢀ:ꢀVccꢀ≤ꢀVLKO

•ꢀ CompatibleꢀwithꢀJEDECꢀstandard

ꢀ -ꢀPinoutꢀandꢀsoftwareꢀcompatibleꢀtoꢀsingleꢀpowerꢀsupplyꢀFlash

•ꢀ Deepꢀpowerꢀdownꢀmode

PERFORMANCE

•ꢀ HighꢀPerformance

ꢀ -ꢀMX29GA256/257EꢀH/L:ꢀ90nsꢀ(Vcc=3.0~3.6V),ꢀ100nsꢀ(Vcc=2.7~3.6V)

-ꢀMX29GA128/129EꢀH/L:ꢀ90nsꢀ(Vcc=2.7~3.6V)

ꢀ -ꢀPageꢀaccessꢀtime:ꢀ25ns

ꢀ -ꢀFastꢀprogramꢀtime:ꢀ11us/word

ꢀ -ꢀFastꢀeraseꢀtime:ꢀ0.6s/sector

•ꢀ LowꢀPowerꢀConsumption

ꢀ -ꢀLowꢀactiveꢀreadꢀcurrent:ꢀ30mAꢀ(typical)ꢀatꢀ5MHz

ꢀ -ꢀLowꢀstandbyꢀcurrent:ꢀ30uAꢀ(typical)

•ꢀ Typicalꢀ100,000ꢀerase/programꢀcycle

•ꢀ 10ꢀyearsꢀdataꢀretention

SOFTWARE FEATURES

•ꢀ Program/EraseꢀSuspendꢀ&ꢀProgram/EraseꢀResume

ꢀ -ꢀSuspendsꢀsectorꢀeraseꢀoperationꢀtoꢀreadꢀdataꢀfromꢀorꢀprogramꢀdataꢀtoꢀanotherꢀsectorꢀwhichꢀisꢀnotꢀbeingꢀ

erased

ꢀ -ꢀSuspendsꢀsectorꢀprogramꢀoperationꢀtoꢀreadꢀdataꢀfromꢀanotherꢀsectorꢀwhichꢀisꢀnotꢀbeingꢀprogram

•ꢀ StatusꢀReply

ꢀ -ꢀData#ꢀPollingꢀ&ꢀToggleꢀbitsꢀprovideꢀdetectionꢀofꢀprogramꢀandꢀeraseꢀoperationꢀcompletion

•ꢀ SupportꢀCommonꢀFlashꢀInterfaceꢀ(CFI)

HARDWARE FEATURES

•ꢀ Ready/Busy#ꢀ(RY/BY#)ꢀOutput

ꢀ -ꢀProvidesꢀaꢀhardwareꢀmethodꢀofꢀdetectingꢀprogramꢀandꢀeraseꢀoperationꢀcompletion

•ꢀ HardwareꢀResetꢀ(RESET#)ꢀInput

ꢀ -ꢀProvidesꢀaꢀhardwareꢀmethodꢀtoꢀresetꢀtheꢀinternalꢀstateꢀmachineꢀtoꢀreadꢀmode

•ꢀ WP#/ACCꢀinputꢀpin

ꢀ -ꢀHardwareꢀwriteꢀprotectꢀpin/Providesꢀacceleratedꢀprogramꢀcapability

SECURITY

•ꢀ Extraꢀ128-wordꢀsectorꢀforꢀsecurity

ꢀ -ꢀFeaturesꢀfactoryꢀlockedꢀandꢀidentiﬁable,ꢀandꢀcustomerꢀlockable

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MX29GA256/257E H/L

MX29GA128/129E H/L

•ꢀ Advancedꢀsectorꢀprotection/unprotectionꢀfunctionꢀ(SolidꢀandꢀPasswordꢀProtect)

ꢀ -ꢀProvidesꢀsectorꢀprotect/unprotectꢀfunctionꢀtoꢀdisableꢀorꢀenableꢀprogramꢀorꢀeraseꢀoperationꢀinꢀtheꢀsector

PACKAGE

•ꢀ 64-BallꢀLFBGAꢀ(11mmꢀxꢀ13mm)

•ꢀ 64-BallꢀFBGAꢀ(10mmꢀxꢀ13mm)

•ꢀ All Pb-free devices are RoHS Compliant

PIN CONFIGURATION for MX29GA256E/128E H/L

Please contact Macronix sales for specific information regarding 64-FBGA/64-LFBGA package pin

conﬁguration.

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MX29GA256/257E H/L

MX29GA128/129E H/L

LOGIC SYMBOL for MX29GA256E/128E H/L

PIN DESCRIPTION for MX29GA256E/128E H/L

SYMBOL PIN NAME

24

AddressꢀInputꢀ

A0~A23 A0~A23ꢀforꢀ256Mb,ꢀ

A0~A22ꢀforꢀ128Mb

16 or 8

A0-A23

Q0-Q15

(A-1)

Q0~Q14 DataꢀInputs/Outputs

Q15/A-1 Q15(WordꢀMode)/LSBꢀaddr(ByteꢀMode)

CE#

WE#

OE#

ChipꢀEnableꢀInput

WriteꢀEnableꢀInput

OutputꢀEnableꢀInput

OE#

WE#

RESET# HardwareꢀResetꢀPin,ꢀActiveꢀLow

RESET#

WP#/ACC

BYTE#

VI/O

RY/BY#

HardwareꢀWriteꢀProtect/Programmingꢀ

Accelerationꢀinput

WP#/ACC*

RY/BY# Read/BusyꢀOutput

BYTE# Selectsꢀ8ꢀbitsꢀorꢀ16ꢀbitsꢀmode

VCC

GND

NC

+3.0Vꢀsingleꢀpowerꢀsupply

DeviceꢀGround

PinꢀNotꢀConnectedꢀInternally

PowerꢀSupplyꢀforꢀInput/Output

VI/O*

Notes:

1.ꢀWP#/ACCꢀhasꢀinternalꢀpullꢀup.

2.ꢀVI/OꢀvoltageꢀmustꢀbeꢀtiedꢀtoꢀVCC.

ꢀꢀꢀꢀVI/O=VCC=2.7V~3.6V

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MX29GA256/257E H/L

MX29GA128/129E H/L

PIN CONFIGURATION for MX29GA257E/129E H/L

Please contact Macronix sales for speciﬁc information regarding 64-FBGA package pin conﬁguration.

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MX29GA256/257E H/L

MX29GA128/129E H/L

PIN DESCRIPTION for MX29GA257E/129E H/L

LOGIC SYMBOL for MX29GA257E/129E H/L

SYMBOL PIN NAME

24

A0~A23/A-1 AddressꢀInput/LSBꢀaddrꢀ(ByteꢀMode)

16 or 8

A0-A23

(A-1)

Q0-Q15

(A-1)

Q0~Q14

DataꢀInputs/Outputs

Q15(Wordꢀ Mode)/LSBꢀ addr(Byteꢀ

Mode)

Q15

CE0#~CE2# ChipꢀEnableꢀInputꢀ(CEx#)

CEx#

WE#

OE#

WriteꢀEnableꢀInput

OE#

OutputꢀEnableꢀInput

WE#

RESET#

HardwareꢀResetꢀPin,ꢀActiveꢀLow

RESET#

WP#/ACC

BYTE#

VI/O

HardwareꢀWriteꢀProtect/Programmingꢀ

Accelerationꢀinput

WP#/ACC

RY/BY#

BYTE#

VCC

Read/BusyꢀOutput

Selectsꢀ8ꢀbitsꢀorꢀ16ꢀbitsꢀmode

+3.0Vꢀsingleꢀpowerꢀsupply

DeviceꢀGround

GND

NC

PinꢀNotꢀConnectedꢀInternally

PowerꢀSupplyꢀforꢀInput/Output,ꢀwhichꢀ

isꢀtiedꢀtoꢀVcc

VI/O

Chip Enable Truth table for MX29GA257E/129E H/L

DEVICE

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

CE0#

VIL

CE1#

VIL

CE2#

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

Note:ꢀForꢀSingle-chipꢀapplications,ꢀCE2#ꢀandꢀCE1#ꢀ

canꢀbeꢀstrappedꢀtoꢀGND.

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MX29GA256/257E H/L

MX29GA128/129E H/L

BLOCK DIAGRAM

CE#

OE#

WRITE

CONTROL

INPUT

PROGRAM/ERASE

STATE

WE#

RESET#

BYTE#

WP#/ACC

HIGH VOLTAGE

MACHINE

(WSM)

LOGIC

STATE

FLASH

ARRAY

ADDRESS

LATCH

REGISTER

ARRAY

A0-AM

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q15/A-1

I/O BUFFER

AM: MSB address

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MX29GA256/257E H/L

MX29GA128/129E H/L

BLOCK DIAGRAM DESCRIPTION

TheꢀblockꢀdiagramꢀonꢀPageꢀ7ꢀillustratesꢀaꢀsimpliﬁedꢀarchitectureꢀofꢀMX29GA256EꢀH/L.ꢀEachꢀblockꢀinꢀtheꢀblockꢀ

diagramꢀrepresentsꢀoneꢀorꢀmoreꢀcircuitꢀmodulesꢀinꢀtheꢀrealꢀchipꢀusedꢀtoꢀaccess,ꢀerase,ꢀprogram,ꢀandꢀreadꢀtheꢀ

memoryꢀarray.

Theꢀ"CONTROLꢀINPUTꢀLOGIC"ꢀblockꢀreceivesꢀinputꢀpinsꢀCE#,ꢀOE#,ꢀWE#,ꢀRESET#,ꢀBYTE#,ꢀandꢀWP#/ACC.ꢀ

Itꢀcreatesꢀinternalꢀtimingꢀcontrolꢀsignalsꢀaccordingꢀtoꢀtheꢀinputꢀpinsꢀandꢀoutputsꢀtoꢀtheꢀ"ADDRESSꢀLATCHꢀANDꢀ

BUFFER"ꢀtoꢀlatchꢀtheꢀexternalꢀaddressꢀpinsꢀA0-AM(A23).ꢀTheꢀinternalꢀaddressesꢀareꢀoutputꢀfromꢀthisꢀblockꢀtoꢀ

theꢀmainꢀarrayꢀandꢀdecodersꢀcomposedꢀofꢀ"X-DECODER",ꢀ"Y-DECODER",ꢀ"Y-PASSꢀGATE",ꢀANDꢀ"FLASHꢀAR-

RAY".ꢀTheꢀX-DECODERꢀdecodesꢀtheꢀword-linesꢀofꢀtheꢀﬂashꢀarray,ꢀwhileꢀtheꢀY-DECODERꢀdecodesꢀtheꢀbit-linesꢀ

ofꢀtheꢀﬂashꢀarray.ꢀTheꢀbitꢀlinesꢀareꢀelectricallyꢀconnectedꢀtoꢀtheꢀ"SENSEꢀAMPLIFIER"ꢀandꢀ"PGMꢀDATAꢀHV"ꢀse-

lectivelyꢀthroughꢀtheꢀY-PASSꢀGATES.ꢀSENSEꢀAMPLIFIERSꢀareꢀusedꢀtoꢀreadꢀoutꢀtheꢀcontentsꢀofꢀtheꢀﬂashꢀmemo-

ry,ꢀwhileꢀtheꢀ"PGMꢀDATAꢀHV"ꢀblockꢀisꢀusedꢀtoꢀselectivelyꢀdeliverꢀhighꢀpowerꢀtoꢀbit-linesꢀduringꢀprogramming.ꢀTheꢀ

"I/OꢀBUFFER"ꢀcontrolsꢀtheꢀinputꢀandꢀoutputꢀonꢀtheꢀQ0-Q15/A-1ꢀpads.ꢀDuringꢀreadꢀoperation,ꢀtheꢀI/OꢀBUFFERꢀ

receivesꢀdataꢀfromꢀSENSEꢀAMPLIFIERSꢀandꢀdrivesꢀtheꢀoutputꢀpadsꢀaccordingly.ꢀInꢀtheꢀlastꢀcycleꢀofꢀprogramꢀ

command,ꢀtheꢀI/OꢀBUFFERꢀtransmitsꢀtheꢀdataꢀonꢀQ0-Q15/A-1ꢀtoꢀ"PROGRAMꢀDATAꢀLATCH",ꢀwhichꢀcontrolsꢀtheꢀ

highꢀpowerꢀdriversꢀinꢀ"PGMꢀDATAꢀHV"ꢀtoꢀselectivelyꢀprogramꢀtheꢀbitsꢀinꢀaꢀwordꢀorꢀbyteꢀaccordingꢀtoꢀtheꢀuserꢀin-

putꢀpattern.

Theꢀ"PROGRAM/ERASEꢀHIGHꢀVOLTAGE"ꢀblockꢀcomprisesꢀtheꢀcircuitsꢀtoꢀgenerateꢀandꢀdeliverꢀtheꢀnecessaryꢀ

highꢀvoltageꢀtoꢀtheꢀX-DECODER,ꢀFLASHꢀARRAY,ꢀandꢀ"PGMꢀDATAꢀHV"ꢀblocks.ꢀTheꢀlogicꢀcontrolꢀmoduleꢀcom-

prisesꢀofꢀtheꢀ"WRITEꢀSTATEꢀMACHINE,ꢀWSM",ꢀ"STATEꢀREGISTER",ꢀ"COMMANDꢀDATAꢀDECODER",ꢀandꢀ

"COMMANDꢀDATAꢀLATCH".ꢀWhenꢀtheꢀuserꢀissuesꢀaꢀcommandꢀbyꢀtogglingꢀWE#,ꢀtheꢀcommandꢀonꢀQ0-A15/A-1ꢀ

isꢀlatchedꢀinꢀtheꢀCOMMANDꢀDATAꢀLATCHꢀandꢀisꢀdecodedꢀbyꢀtheꢀCOMMANDꢀDATAꢀDECODER.ꢀTheꢀSTATEꢀ

REGISTERꢀreceivesꢀtheꢀcommandꢀandꢀrecordsꢀtheꢀcurrentꢀstateꢀofꢀtheꢀdevice.ꢀTheꢀWSMꢀimplementsꢀtheꢀin-

ternalꢀalgorithmsꢀforꢀprogramꢀorꢀeraseꢀaccordingꢀtoꢀtheꢀcurrentꢀcommandꢀstateꢀbyꢀcontrollingꢀeachꢀblockꢀinꢀtheꢀ

blockꢀdiagram.

ARRAY ARCHITECTURE

TheꢀmainꢀﬂashꢀmemoryꢀarrayꢀcanꢀbeꢀorganizedꢀasꢀByteꢀmodeꢀ(x8)ꢀorꢀWordꢀmodeꢀ(x16).ꢀꢀTheꢀdetailsꢀofꢀtheꢀad-

dressꢀrangesꢀandꢀtheꢀcorrespondingꢀsectorꢀaddressesꢀareꢀshownꢀinꢀTableꢀ1.ꢀ

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MX29GA256/257E H/L

MX29GA128/129E H/L

BLOCK STRUCTURE

Table 1-1: MX29GA256/257EH/L SECTOR ARCHITECTURE

Sector Size

Sector

Sector Address

A23-A16

(x16)

Address Range

Kbytes

128

Kwords

64

SA0

SA1

00000000

00000001

00000010

00000011

00000100

00000101

00000110

00000111

00001000

00001001

00001010

00001011

00001100

00001101

00001110

00001111

00010000

00010001

00010010

00010011

00010100

00010101

00010110

00010111

00011000

00011001

00011010

00011011

00011100

00011101

00011110

00011111

00100000

00100001

00100010

00100011

00100100

00100101

000000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A23-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

00100110

00100111

00101000

00101001

00101010

00101011

00101100

00101101

00101110

00101111

00110000

00110001

00110010

00110011

00110100

00110101

00110110

00110111

00111000

00111001

00111010

00111011

00111100

00111101

00111110

00111111

01000000

01000001

01000010

01000011

01000100

01000101

01000110

01000111

01001000

01001001

01001010

01001011

01001100

01001101

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

400000h-40FFFFh

410000h-41FFFFh

420000h-42FFFFh

430000h-43FFFFh

440000h-44FFFFh

450000h-45FFFFh

460000h-46FFFFh

470000h-47FFFFh

480000h-48FFFFh

490000h-49FFFFh

4A0000h-4AFFFFh

4B0000h-4BFFFFh

4C0000h-4CFFFFh

4D0000h-4DFFFFh

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A23-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

01001110

01001111

01010000

01010001

01010010

01010011

01010100

01010101

01010110

01010111

01011000

01011001

01011010

01011011

01011100

01011101

01011110

01011111

01100000

01100001

01100010

01100011

01100100

01100101

01100110

01100111

01101000

01101001

01101010

01101011

01101100

01101101

01101110

01101111

01110000

01110001

01110010

01110011

01110100

01110101

4E0000h-4EFFFFh

4F0000h-4FFFFFh

500000h-50FFFFh

510000h-51FFFFh

520000h-52FFFFh

530000h-53FFFFh

540000h-54FFFFh

550000h-55FFFFh

560000h-56FFFFh

570000h-57FFFFh

580000h-58FFFFh

590000h-59FFFFh

5A0000h-5AFFFFh

5B0000h-5BFFFFh

5C0000h-5CFFFFh

5D0000h-5DFFFFh

5E0000h-5EFFFFh

5F0000h-5FFFFFh

600000h-60FFFFh

610000h-61FFFFh

620000h-62FFFFh

630000h-63FFFFh

640000h-64FFFFh

650000h-65FFFFh

660000h-66FFFFh

670000h-67FFFFh

680000h-68FFFFh

690000h-69FFFFh

6A0000h-6AFFFFh

6B0000h-6BFFFFh

6C0000h-6CFFFFh

6D0000h-6DFFFFh

6E0000h-6EFFFFh

6F0000h-6FFFFFh

700000h-70FFFFh

710000h-71FFFFh

720000h-72FFFFh

730000h-73FFFFh

740000h-74FFFFh

750000h-75FFFFh

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A23-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

SA128

SA129

SA130

SA131

SA132

SA133

SA134

SA135

SA136

SA137

SA138

SA139

SA140

SA141

SA142

SA143

SA144

SA145

SA146

SA147

SA148

SA149

SA150

SA151

SA152

SA153

SA154

SA155

SA156

SA157

SA158

SA159

01110110

01110111

01111000

01111001

01111010

01111011

01111100

01111101

01111110

01111111

10000000

10000001

10000010

10000011

10000100

10000101

10000110

10000111

10001000

10001001

10001010

10001011

10001100

10001101

10001110

10001111

10010000

10010001

10010010

10010011

10010100

10010101

10010110

10010111

10011000

10011001

10011010

10011011

10011100

10011101

10011110

10011111

760000h-76FFFFh

770000h-77FFFFh

780000h-78FFFFh

790000h-79FFFFh

7A0000h-7AFFFFh

7B0000h-7BFFFFh

7C0000h-7CFFFFh

7D0000h-7DFFFFh

7E0000h-7EFFFFh

7F0000h-7FFFFFh

800000h-80FFFFh

810000h-81FFFFh

820000h-82FFFFh

830000h-83FFFFh

840000h-84FFFFh

850000h-85FFFFh

860000h-86FFFFh

870000h-87FFFFh

880000h-88FFFFh

890000h-89FFFFh

8A0000h-8AFFFFh

8B0000h-8BFFFFh

8C0000h-8CFFFFh

8D0000h-8DFFFFh

8E0000h-8EFFFFh

8F0000h-8FFFFFh

900000h-90FFFFh

910000h-91FFFFh

920000h-92FFFFh

930000h-93FFFFh

940000h-94FFFFh

950000h-95FFFFh

960000h-96FFFFh

970000h-97FFFFh

980000h-98FFFFh

990000h-99FFFFh

9A0000h-9AFFFFh

9B0000h-9BFFFFh

9C0000h-9CFFFFh

9D0000h-9DFFFFh

9E0000h-9EFFFFh

9F0000h-9FFFFFh

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A23-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA160

SA161

SA162

SA163

SA164

SA165

SA166

SA167

SA168

SA169

SA170

SA171

SA172

SA173

SA174

SA175

SA176

SA177

SA178

SA179

SA180

SA181

SA182

SA183

SA184

SA185

SA186

SA187

SA188

SA189

SA190

SA191

SA192

SA193

SA194

SA195

SA196

SA197

SA198

SA199

SA200

10100000

10100001

10100010

10100011

10100100

10100101

10100110

10100111

10101000

10101001

10101010

10101011

10101100

10101101

10101110

10101111

10110000

10110001

10110010

10110011

10110100

10110101

10110110

10110111

10111000

10111001

10111010

10111011

10111100

10111101

10111110

10111111

11000000

11000001

11000010

11000011

11000100

11000101

11000110

11000111

11001000

A00000h-A0FFFFh

A10000h-A1FFFFh

A20000h-A2FFFFh

A30000h-A3FFFFh

A40000h-A4FFFFh

A50000h-A5FFFFh

A60000h-A6FFFFh

A70000h-A7FFFFh

A80000h-A8FFFFh

A90000h-A9FFFFh

AA0000h-AAFFFFh

AB0000h-ABFFFFh

AC0000h-ACFFFFh

AD0000h-ADFFFFh

AE0000h-AEFFFFh

AF0000h-AFFFFFh

B00000h-B0FFFFh

B10000h-B1FFFFh

B20000h-B2FFFFh

B30000h-B3FFFFh

B40000h-B4FFFFh

B50000h-B5FFFFh

B60000h-B6FFFFh

B70000h-B7FFFFh

B80000h-B8FFFFh

B90000h-B9FFFFh

BA0000h-BAFFFFh

BB0000h-BBFFFFh

BC0000h-BCFFFFh

BD0000h-BDFFFFh

BE0000h-BEFFFFh

BF0000h-BFFFFFh

C00000h-C0FFFFh

C10000h-C1FFFFh

C20000h-C2FFFFh

C30000h-C3FFFFh

C40000h-C4FFFFh

C50000h-C5FFFFh

C60000h-C6FFFFh

C70000h-C7FFFFh

C80000h-C8FFFFh

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A23-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA201

SA202

SA203

SA204

SA205

SA206

SA207

SA208

SA209

SA210

SA211

SA212

SA213

SA214

SA215

SA216

SA217

SA218

SA219

SA220

SA221

SA222

SA223

SA224

SA225

SA226

SA227

SA228

SA229

SA230

SA231

SA232

SA233

SA234

SA235

SA236

SA237

SA238

SA239

SA240

11001001

11001010

11001011

11001100

11001101

11001110

11001111

11010000

11010001

11010010

11010011

11010100

11010101

11010110

11010111

11011000

11011001

11011010

11011011

11011100

11011101

11011110

11011111

11100000

11100001

11100010

11100011

11100100

11100101

11100110

11100111

11101000

11101001

11101010

11101011

11101100

11101101

11101110

11101111

11110000

C90000h-C9FFFFh

CA0000h-CAFFFFh

CB0000h-CBFFFFh

CC0000h-CCFFFFh

CD0000h-CDFFFFh

CE0000h-CEFFFFh

CF0000h-CFFFFFh

D00000h-D0FFFFh

D10000h-D1FFFFh

D20000h-D2FFFFh

D30000h-D3FFFFh

D40000h-D4FFFFh

D50000h-D5FFFFh

D60000h-D6FFFFh

D70000h-D7FFFFh

D80000h-D8FFFFh

D90000h-D9FFFFh

DA0000h-DAFFFFh

DB0000h-DBFFFFh

DC0000h-DCFFFFh

DD0000h-DDFFFFh

DE0000h-DEFFFFh

DF0000h-DFFFFFh

E00000h-E0FFFFh

E10000h-E1FFFFh

E20000h-E2FFFFh

E30000h-E3FFFFh

E40000h-E4FFFFh

E50000h-E5FFFFh

E60000h-E6FFFFh

E70000h-E7FFFFh

E80000h-E8FFFFh

E90000h-E9FFFFh

EA0000h-EAFFFFh

EB0000h-EBFFFFh

EC0000h-ECFFFFh

ED0000h-EDFFFFh

EE0000h-EEFFFFh

EF0000h-EFFFFFh

F00000h-F0FFFFh

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A23-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA241

SA242

SA243

SA244

SA245

SA246

SA247

SA248

SA249

SA250

SA251

SA252

SA253

SA254

SA255

11110001

11110010

11110011

11110100

11110101

11110110

11110111

11111000

11111001

11111010

11111011

11111100

11111101

11111110

11111111

F10000h-F1FFFFh

F20000h-F2FFFFh

F30000h-F3FFFFh

F40000h-F4FFFFh

F50000h-F5FFFFh

F60000h-F6FFFFh

F70000h-F7FFFFh

F80000h-F8FFFFh

F90000h-F9FFFFh

FA0000h-FAFFFFh

FB0000h-FBFFFFh

FC0000h-FCFFFFh

FD0000h-FDFFFFh

FE0000h-FEFFFFh

FF0000h-FFFFFFh

64

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MX29GA256/257E H/L

MX29GA128/129E H/L

Table 1-2: MX29GA128/129E H/L SECTOR ARCHITECTURE

Sector Size

Sector Address

A22-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA0

SA1

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0100000

0100001

0100010

0100011

0100100

0100101

000000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A22-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

0100110

0100111

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111110

0111111

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

400000h-40FFFFh

410000h-41FFFFh

420000h-42FFFFh

430000h-43FFFFh

440000h-44FFFFh

450000h-45FFFFh

460000h-46FFFFh

470000h-47FFFFh

480000h-48FFFFh

490000h-49FFFFh

4A0000h-4AFFFFh

4B0000h-4BFFFFh

4C0000h-4CFFFFh

4D0000h-4DFFFFh

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A22-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA78

SA79

SA80

SA81

SA82

SA83

SA84

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

4E0000h-4EFFFFh

4F0000h-4FFFFFh

500000h-50FFFFh

510000h-51FFFFh

520000h-52FFFFh

530000h-53FFFFh

540000h-54FFFFh

550000h-55FFFFh

560000h-56FFFFh

570000h-57FFFFh

580000h-58FFFFh

590000h-59FFFFh

5A0000h-5AFFFFh

5B0000h-5BFFFFh

5C0000h-5CFFFFh

5D0000h-5DFFFFh

5E0000h-5EFFFFh

5F0000h-5FFFFFh

600000h-60FFFFh

610000h-61FFFFh

620000h-62FFFFh

630000h-63FFFFh

640000h-64FFFFh

650000h-65FFFFh

660000h-66FFFFh

670000h-67FFFFh

680000h-68FFFFh

690000h-69FFFFh

6A0000h-6AFFFFh

6B0000h-6BFFFFh

6C0000h-6CFFFFh

6D0000h-6DFFFFh

6E0000h-6EFFFFh

6F0000h-6FFFFFh

700000h-70FFFFh

710000h-71FFFFh

720000h-72FFFFh

730000h-73FFFFh

740000h-74FFFFh

750000h-75FFFFh

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MX29GA256/257E H/L

MX29GA128/129E H/L

Sector Size

Sector Address

A22-A16

(x16)

Address Range

Sector

Kbytes

128

Kwords

64

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

760000h-76FFFFh

770000h-77FFFFh

780000h-78FFFFh

790000h-79FFFFh

7A0000h-7AFFFFh

7B0000h-7BFFFFh

7C0000h-7CFFFFh

7D0000h-7DFFFFh

7E0000h-7EFFFFh

7F0000h-7FFFFFh

64

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MX29GA256/257E H/L

MX29GA128/129E H/L

BUS OPERATION

Table 2-1. BUS OPERATION

Byte#

Data

RE-

Mode Select

SET#

Address

(Note4)

Vil

Vih

WP#/

ACC

CE# WE# OE#

I/O

Data (I/O)

Q8~Q15

Q0~Q7

DeviceꢀResetꢀ

StandbyꢀModeꢀ

Lꢀ

Xꢀ

X

Xꢀ

HighZꢀ HighZꢀ

HighZꢀ

L/H

H

Vccꢀ±ꢀ Vcc±ꢀ

0.3V

Hꢀ

Xꢀ

HighZꢀ

0.3V

Lꢀ

OutputꢀDisable

ReadꢀModeꢀ

Write

Hꢀ

Lꢀ

Hꢀ

Lꢀ

Xꢀ

HighZꢀ

DOUTꢀ

DINꢀ

L/H

Hꢀ

Lꢀ

AIN

DOUTꢀ

Q8-Q14=

Hꢀ

DINꢀ

HighZ,

Q15=A1

Note1,2

Vhv

AccelerateꢀProgramꢀ

Lꢀ

DINꢀ

Notes:

1.ꢀꢀTheꢀﬁrstꢀorꢀlastꢀsectorꢀwasꢀprotectedꢀifꢀWP#/ACC=Vil.

2.ꢀ WhenꢀWP#/ACCꢀ=ꢀVih,ꢀtheꢀprotectionꢀconditionsꢀofꢀtheꢀoutmostꢀsectorꢀdependsꢀonꢀpreviousꢀprotectionꢀcondi-

tions.ꢀReferꢀtoꢀtheꢀadvanedꢀprotectꢀfeature.

3.ꢀ Q0~Q15ꢀareꢀinputꢀ(DIN)ꢀorꢀoutputꢀ(DOUT)ꢀpinsꢀaccordingꢀtoꢀtheꢀrequestsꢀofꢀcommandꢀsequence,ꢀsectorꢀpro-

tection,ꢀorꢀdataꢀpollingꢀalgorithm.

4.ꢀ InꢀWordꢀModeꢀ(Byte#=Vih),ꢀtheꢀaddressesꢀareꢀAMꢀtoꢀA0,ꢀAM:ꢀMSBꢀofꢀaddress.

ꢀ

InꢀByteꢀModeꢀ(Byte#=Vil),ꢀtheꢀaddressesꢀareꢀAMꢀtoꢀA-1ꢀ(Q15),ꢀAM:ꢀMSBꢀofꢀaddress.

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MX29GA256/257E H/L

MX29GA128/129E H/L

Table 2-2. BUS OPERATION

Control Input

CE# WE# OE#

AM A11

to to A9 to A6 to

A12 A10

A8

A5 A3

to A1 A0 Q0 ~ Q7 Q8 ~ Q15

A4 A2

Item

A7

01hꢀorꢀ

00hꢀ

(Noteꢀ1)

SectorꢀLockꢀStatusꢀ

Veriﬁcation

L

H

L

SA

X

V_hv

X

L

X

L

H

L

X

ReadꢀSiliconꢀIDꢀ

Manufacturerꢀ

Codeꢀ

X

C2H

ReadꢀSiliconꢀIDꢀ--ꢀMX29GA256/257EꢀH/L

22H(Word),ꢀ

XXH(Byte)

22H(Word),ꢀ

XXH(Byte)

Cycleꢀ1

Cycleꢀ2

Cycleꢀ3

L

H

L

X

V_hv

X

L

X

L

H

L

H

L

7EH

38H

01H

22H(Word),ꢀ

XXH(Byte)

H

ReadꢀSiliconꢀIDꢀ--ꢀMX29GA128/129EꢀH/L

22H(Word),ꢀ

XXH(Byte)

Cycleꢀ1

Cycleꢀ2

Cycleꢀ3

L

H

L

X

V_hv

X

L

X

L

H

L

H

L

7EH

37H

01H

22H(Word),ꢀ

XXH(Byte)

22H(Word),ꢀ

XXH(Byte)

H

Notes:

1.ꢀSectorꢀunprotectedꢀcode:00h.ꢀSectorꢀprotectedꢀcode:01h.

2.ꢀFactoryꢀlockedꢀcode:ꢀꢀ WP#ꢀprotectsꢀhighꢀaddressꢀsector:ꢀ99h.ꢀ

WP#ꢀprotectsꢀlowꢀaddressꢀsector:ꢀ89h

ꢀꢀꢀꢀFactoryꢀunlockedꢀcode:ꢀꢀWP#ꢀprotectsꢀhighꢀaddressꢀsector:ꢀ19h.ꢀ

ꢀ

WP#ꢀprotectsꢀlowꢀaddressꢀsector:ꢀ09h

3.ꢀAM:ꢀMSBꢀofꢀaddress.

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MX29GA256/257E H/L

MX29GA128/129E H/L

FUNCTIONAL OPERATION DESCRIPTION

READ OPERATION

Toꢀperformꢀaꢀreadꢀoperation,ꢀtheꢀsystemꢀaddressesꢀtheꢀdesiredꢀmemoryꢀarrayꢀorꢀstatusꢀregisterꢀlocationꢀbyꢀpro-

vidingꢀitsꢀaddressꢀonꢀtheꢀaddressꢀpinsꢀandꢀsimultaneouslyꢀenablingꢀtheꢀchipꢀbyꢀdrivingꢀCE#ꢀ&ꢀOE#ꢀLOW,ꢀandꢀ

WE#ꢀHIGH.ꢀꢀAfterꢀtheꢀTceꢀandꢀToeꢀtimingꢀrequirementsꢀhaveꢀbeenꢀmet,ꢀtheꢀsystemꢀcanꢀreadꢀtheꢀcontentsꢀofꢀtheꢀ

addressedꢀlocationꢀbyꢀreadingꢀtheꢀDataꢀ(I/O)ꢀpins.ꢀꢀIfꢀeitherꢀtheꢀCE#ꢀorꢀOE#ꢀisꢀheldꢀHIGH,ꢀtheꢀoutputsꢀwillꢀremainꢀ

tri-statedꢀandꢀnoꢀdataꢀwillꢀappearꢀonꢀtheꢀoutputꢀpins.

PAGE READ

ThisꢀdeviceꢀisꢀableꢀtoꢀconductꢀMXICꢀMaskROMꢀcompatibleꢀhighꢀperformanceꢀpageꢀread.ꢀPageꢀsizeꢀisꢀ16ꢀbytesꢀ

orꢀ8ꢀwords.ꢀTheꢀhigherꢀaddressꢀAmaxꢀ~ꢀA3ꢀselectꢀtheꢀcertainꢀpage,ꢀwhileꢀA2~A0ꢀforꢀwordꢀmode,ꢀA2~A-1ꢀforꢀ

byteꢀmodeꢀselectꢀtheꢀparticularꢀwordꢀorꢀbyteꢀinꢀaꢀpage.ꢀTheꢀpageꢀaccessꢀtimeꢀisꢀTaaꢀorꢀTce,ꢀfollowingꢀbyꢀTpaꢀforꢀ

theꢀrestꢀofꢀtheꢀpageꢀreadꢀtime.ꢀWhenꢀCE#ꢀtoggles,ꢀaccessꢀtimeꢀisꢀTaaꢀorꢀTce.ꢀPageꢀmodeꢀcanꢀbeꢀturnedꢀonꢀbyꢀ

keepingꢀ"page-readꢀaddress"ꢀconstantꢀandꢀchangingꢀtheꢀ"intra-readꢀpage"ꢀaddresses.

WRITE OPERATION

Toꢀperformꢀaꢀwriteꢀoperation,ꢀtheꢀsystemꢀprovidesꢀtheꢀdesiredꢀaddressꢀonꢀtheꢀaddressꢀpins,ꢀenablesꢀtheꢀchipꢀbyꢀ

assertingꢀCE#ꢀLOW,ꢀandꢀdisablesꢀtheꢀDataꢀ(I/O)ꢀpinsꢀbyꢀholdingꢀOE#ꢀHIGH.ꢀꢀTheꢀsystemꢀthenꢀplacesꢀdataꢀtoꢀbeꢀ

writtenꢀonꢀtheꢀDataꢀ(I/O)ꢀpinsꢀandꢀpulsesꢀWE#ꢀLOW.ꢀꢀTheꢀdeviceꢀcapturesꢀtheꢀaddressꢀinformationꢀonꢀtheꢀfallingꢀ

edgeꢀofꢀWE#ꢀandꢀtheꢀdataꢀonꢀtheꢀrisingꢀedgeꢀofꢀWE#.ꢀꢀToꢀseeꢀanꢀexample,ꢀpleaseꢀreferꢀtoꢀtheꢀtimingꢀdiagramꢀ

inꢀFigureꢀ1ꢀonꢀPageꢀ53.ꢀꢀTheꢀsystemꢀisꢀnotꢀallowedꢀtoꢀwriteꢀinvalidꢀcommandsꢀ(commandsꢀnotꢀdeﬁnedꢀinꢀthisꢀ

datasheet)ꢀtoꢀtheꢀdevice.ꢀꢀꢀWritingꢀanꢀinvalidꢀcommandꢀmayꢀputꢀtheꢀdeviceꢀinꢀanꢀundeﬁnedꢀstate.

DEVICE RESET

DrivingꢀtheꢀRESET#ꢀpinꢀLOWꢀforꢀaꢀperiodꢀofꢀTrpꢀorꢀmoreꢀwillꢀreturnꢀtheꢀdeviceꢀtoꢀReadꢀmode.ꢀIfꢀtheꢀdeviceꢀisꢀinꢀ

theꢀmiddleꢀofꢀaꢀprogramꢀorꢀeraseꢀoperation,ꢀtheꢀresetꢀoperationꢀwillꢀtakeꢀatꢀmostꢀaꢀperiodꢀofꢀTready1ꢀbeforeꢀtheꢀ

deviceꢀreturnsꢀtoꢀReadꢀmode.ꢀUntilꢀtheꢀdeviceꢀdoesꢀreturnsꢀtoꢀReadꢀmode,ꢀtheꢀRY/BY#ꢀpinꢀwillꢀremainꢀLowꢀ(Busyꢀ

Status).

WhenꢀtheꢀRESET#ꢀpinꢀisꢀheldꢀatꢀGND±0.3V,ꢀtheꢀdeviceꢀonlyꢀconsumesꢀstandbyꢀ(Isbr)ꢀcurrent.ꢀHowever,ꢀtheꢀde-

viceꢀdrawsꢀlargerꢀcurrentꢀifꢀtheꢀRESET#ꢀpinꢀisꢀheldꢀatꢀaꢀvoltageꢀgreaterꢀthanꢀGND+0.3Vꢀandꢀlessꢀthanꢀorꢀequalꢀtoꢀ

Vil.

ItꢀisꢀrecommendedꢀtoꢀtieꢀtheꢀsystemꢀresetꢀsignalꢀtoꢀtheꢀRESET#ꢀpinꢀofꢀtheꢀﬂashꢀmemory.ꢀꢀThisꢀallowsꢀtheꢀdeviceꢀ

toꢀbeꢀresetꢀwithꢀtheꢀsystemꢀandꢀputsꢀitꢀinꢀaꢀstateꢀwhereꢀtheꢀsystemꢀcanꢀimmediatelyꢀbeginꢀreadingꢀbootꢀcodeꢀ

fromꢀit.

STANDBY MODE

TheꢀdeviceꢀentersꢀStandbyꢀmodeꢀwheneverꢀtheꢀRESET#ꢀandꢀCE#ꢀpinsꢀareꢀbothꢀheldꢀHighꢀexceptꢀinꢀtheꢀembed-

dedꢀmode.ꢀꢀWhileꢀinꢀthisꢀmode,ꢀWE#ꢀandꢀOE#ꢀwillꢀbeꢀignored,ꢀallꢀDataꢀOutputꢀpinsꢀwillꢀbeꢀinꢀaꢀhighꢀimpedanceꢀ

state,ꢀandꢀtheꢀdeviceꢀwillꢀdrawꢀminimalꢀ(Isb)ꢀcurrent.ꢀ

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FUNCTIONAL OPERATION DESCRIPTION (cont'd)

OUTPUT DISABLE

Whileꢀinꢀactiveꢀmodeꢀ(RESET#ꢀHIGHꢀandꢀCE#ꢀLOW),ꢀtheꢀOE#ꢀpinꢀcontrolsꢀtheꢀstateꢀofꢀtheꢀoutputꢀpins.ꢀꢀIfꢀOE#ꢀisꢀ

heldꢀHIGH,ꢀallꢀDataꢀ(I/O)ꢀpinsꢀwillꢀremainꢀtri-stated.ꢀꢀIfꢀheldꢀLOW,ꢀtheꢀByteꢀorꢀWordꢀDataꢀ(I/O)ꢀpinsꢀwillꢀdriveꢀdata.

BYTE/WORD SELECTION

TheꢀBYTE#ꢀinputꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀorganizationꢀofꢀtheꢀarrayꢀdataꢀandꢀhowꢀtheꢀdataꢀisꢀinput/outputꢀonꢀtheꢀ

Dataꢀ(I/O)ꢀpins.ꢀꢀIfꢀtheꢀBYTE#ꢀpinꢀisꢀheldꢀHIGH,ꢀWordꢀmodeꢀwillꢀbeꢀselectedꢀandꢀallꢀ16ꢀdataꢀlinesꢀ(Q0ꢀtoꢀQ15)ꢀwillꢀ

beꢀactive.

IfꢀBYTE#ꢀisꢀforcedꢀLOW,ꢀByteꢀmodeꢀwillꢀbeꢀactiveꢀandꢀonlyꢀdataꢀlinesꢀQ0ꢀtoꢀQ7ꢀwillꢀbeꢀactive.ꢀꢀDataꢀlinesꢀQ8ꢀtoꢀ

Q14ꢀwillꢀremainꢀinꢀaꢀhighꢀimpedanceꢀstateꢀandꢀQ15ꢀbecomesꢀtheꢀA-1ꢀaddressꢀinputꢀpin.

HARDWARE WRITE PROTECT

ByꢀdrivingꢀtheꢀWP#/ACCꢀpinꢀLOW.ꢀTheꢀhighestꢀorꢀlowestꢀwasꢀprotectedꢀfromꢀallꢀerase/programꢀoperations.ꢀꢀIfꢀ

WP#/ACCꢀisꢀheldꢀHIGHꢀ(VihꢀtoꢀVCC),ꢀtheseꢀsectorsꢀrevertꢀtoꢀtheirꢀpreviouslyꢀprotected/unprotectedꢀstatus.

ACCELERATED PROGRAMMING OPERATION

Byꢀapplyingꢀhighꢀvoltageꢀ(Vhv)ꢀtoꢀtheꢀWP#/ACCꢀpin,ꢀtheꢀdeviceꢀwillꢀenterꢀtheꢀAcceleratedꢀProgrammingꢀmode.ꢀ

Thisꢀmodeꢀpermitsꢀtheꢀsystemꢀtoꢀskipꢀtheꢀnormalꢀcommandꢀunlockꢀsequencesꢀandꢀprogramꢀbyte/wordꢀlocationsꢀ

directly.ꢀꢀDuringꢀacceleratedꢀprogramming,ꢀtheꢀcurrentꢀdrawnꢀfromꢀtheꢀWP#/ACCꢀpinꢀisꢀnoꢀmoreꢀthanꢀICP1.

WRITE BUFFER PROGRAMMING OPERATION

Programsꢀ64bytes/32wordsꢀinꢀaꢀprogrammingꢀoperation.ꢀToꢀtriggerꢀtheꢀWriteꢀBufferꢀProgramming,ꢀstartꢀbyꢀtheꢀ

ﬁrstꢀtwoꢀunlockꢀcycles,ꢀthenꢀthirdꢀcycleꢀwritesꢀtheꢀWriteꢀBufferꢀLoadꢀcommandꢀatꢀtheꢀdestinedꢀprogrammingꢀSec-

torꢀAddress.ꢀTheꢀforthꢀcycleꢀwritesꢀtheꢀ"wordꢀlocationsꢀsubtractꢀone"ꢀnumber.

Followingꢀaboveꢀoperations,ꢀsystemꢀstartsꢀtoꢀwriteꢀtheꢀminglingꢀofꢀaddressꢀandꢀdata.ꢀAfterꢀtheꢀprogrammingꢀofꢀ

theꢀﬁrstꢀaddressꢀorꢀdata,ꢀtheꢀ"write-buffer-page"ꢀisꢀselected.ꢀTheꢀfollowingꢀdataꢀshouldꢀbeꢀwithinꢀtheꢀaboveꢀmen-

tionedꢀpage.

Theꢀ"write-buffer-page"ꢀisꢀselectedꢀbyꢀchoosingꢀaddressꢀAmax-A5.

"Write-Buffer-Page"ꢀaddressꢀhasꢀtoꢀbeꢀtheꢀsameꢀforꢀallꢀaddress/ꢀdataꢀwriteꢀintoꢀtheꢀwriteꢀbuffer.ꢀIfꢀnot,ꢀoperationꢀ

willꢀABORT.

ToꢀprogramꢀtheꢀcontentꢀofꢀtheꢀwriteꢀbufferꢀpageꢀthisꢀcommandꢀmustꢀbeꢀfollowedꢀbyꢀaꢀwriteꢀtoꢀbufferꢀProgramꢀcon-

ﬁrmꢀcommand.

Theꢀoperationꢀofꢀwrite-bufferꢀcanꢀbeꢀsuspendedꢀorꢀresumedꢀbyꢀtheꢀstandardꢀcommands,ꢀonceꢀtheꢀwriteꢀbufferꢀ

programmingꢀoperationꢀisꢀﬁnished,ꢀit’llꢀreturnꢀtoꢀnormalꢀREADꢀmode.

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FUNCTIONAL OPERATION DESCRIPTION (cont'd)

WRITE BUFFER PROGRAMMING OPERATION (cont'd)

ABORTꢀwillꢀbeꢀexecutedꢀforꢀtheꢀWriteꢀBufferꢀProgrammingꢀSequenceꢀifꢀfollowingꢀconditionꢀoccurs:

•ꢀ Theꢀvalueꢀloadedꢀisꢀbiggerꢀthanꢀtheꢀpageꢀbufferꢀsizeꢀduringꢀ"NumberꢀofꢀLocationsꢀtoꢀProgram"

•ꢀ AddressꢀwrittenꢀinꢀaꢀsectorꢀisꢀnotꢀtheꢀsameꢀasꢀtheꢀoneꢀassignedꢀduringꢀtheꢀWrite-Buffer-Loadꢀcommand.

•ꢀ Address/ꢀDataꢀpairꢀwrittenꢀtoꢀaꢀdifferentꢀwrite-buffer-pageꢀthanꢀtheꢀoneꢀassignedꢀbyꢀtheꢀ"StartingꢀAddress"ꢀ

during

ꢀ

theꢀ"writeꢀbufferꢀdataꢀloading"ꢀoperation.

•ꢀ Writingꢀnotꢀ"ConﬁrmꢀCommand"ꢀafterꢀtheꢀassignedꢀnumberꢀofꢀ"dataꢀload"ꢀcycles.

TheꢀabortꢀisꢀtriggeredꢀbyꢀQ1=1,ꢀQ7=DATA#ꢀ(lastꢀaddressꢀwritten),ꢀQ6=toggle,ꢀQ5=0.ꢀAꢀWrite-to-Buffer-AbortꢀRe-

setꢀcommandꢀsequenceꢀhasꢀtoꢀbeꢀwrittenꢀtoꢀresetꢀtheꢀdeviceꢀforꢀtheꢀnextꢀoperation.

Writeꢀbufferꢀprogrammingꢀcanꢀbeꢀconductedꢀinꢀanyꢀsequence.ꢀHoweverꢀtheꢀCFIꢀfunctions,ꢀautoselect,ꢀSecuredꢀ

Siliconꢀsectorꢀareꢀnotꢀfunctionalꢀwhenꢀprogramꢀoperationꢀisꢀinꢀprogress.ꢀMultipleꢀwriteꢀbufferꢀprogrammingꢀopera-

tionsꢀonꢀtheꢀsameꢀwriteꢀbufferꢀaddressꢀrangeꢀwithoutꢀinterveningꢀerasesꢀisꢀavailable.ꢀAnyꢀbitꢀinꢀaꢀwriteꢀbufferꢀad-

dressꢀrangeꢀcan’tꢀbeꢀprogrammedꢀfromꢀ0ꢀbackꢀtoꢀ1.

SECTOR PROTECT OPERATION

Theꢀdeviceꢀprovidesꢀuserꢀprogrammableꢀprotectionꢀagainstꢀprogram/eraseꢀoperationsꢀforꢀselectedꢀsectors.ꢀ

PleaseꢀreferꢀtoꢀTableꢀ1ꢀwhichꢀshowꢀallꢀSectorꢀassignments.

Duringꢀtheꢀprotectionꢀoperation,ꢀtheꢀsectorꢀaddressꢀofꢀanyꢀsectorꢀwithinꢀaꢀSectorꢀmayꢀbeꢀusedꢀtoꢀspecifyꢀtheꢀ

Sectorꢀbeingꢀprotected.

AUTOMATIC SELECT BUS OPERATIONS

TheꢀfollowingꢀﬁveꢀbusꢀoperationsꢀrequireꢀA9ꢀtoꢀbeꢀraisedꢀtoꢀVhv.ꢀꢀPleaseꢀseeꢀAUTOMATICꢀSELECTꢀCOMMANDꢀ

SEQUENCEꢀinꢀtheꢀCOMMANDꢀOPERATIONSꢀsectionꢀforꢀdetailsꢀofꢀequivalentꢀcommandꢀoperationsꢀthatꢀdoꢀnotꢀ

requireꢀtheꢀuseꢀofꢀVhv.

SECTOR LOCK STATUS VERIFICATION

Toꢀdetermineꢀtheꢀprotectedꢀstateꢀofꢀanyꢀsectorꢀusingꢀbusꢀoperations,ꢀtheꢀsystemꢀperformsꢀaꢀREADꢀOPERATIONꢀ

withꢀA9ꢀraisedꢀtoꢀVhv,ꢀtheꢀsectorꢀaddressꢀappliedꢀtoꢀaddressꢀpinsꢀA22ꢀtoꢀA12,ꢀꢀaddressꢀpinsꢀA6,ꢀA3,ꢀA2ꢀ&ꢀA0ꢀheldꢀ

LOW,ꢀꢀandꢀaddressꢀpinꢀA1ꢀheldꢀHIGH.ꢀꢀIfꢀdataꢀbitꢀQ0ꢀisꢀLOW,ꢀtheꢀsectorꢀisꢀnotꢀprotected,ꢀandꢀifꢀQ0ꢀisꢀHIGH,ꢀtheꢀ

sectorꢀisꢀprotected.

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FUNCTIONAL OPERATION DESCRIPTION (cont'd)

READ SILICON ID MANUFACTURER CODE

ToꢀdetermineꢀtheꢀSiliconꢀIDꢀManufacturerꢀCode,ꢀtheꢀsystemꢀperformsꢀaꢀREADꢀOPERATIONꢀwithꢀA9ꢀraisedꢀtoꢀ

VhvꢀandꢀaddressꢀpinsꢀA6,ꢀA3,ꢀA2,ꢀA1,ꢀ&ꢀꢀA0ꢀheldꢀLOW.ꢀꢀTheꢀMacronixꢀIDꢀcodeꢀofꢀC2hꢀshouldꢀbeꢀpresentꢀonꢀdataꢀ

bitsꢀQ0ꢀtoꢀQ7.

READ INDICATOR BIT (Q7) FOR SECURITY SECTOR

ToꢀdetermineꢀifꢀtheꢀSecurityꢀSectorꢀhasꢀbeenꢀlockedꢀatꢀtheꢀfactory,ꢀtheꢀsystemꢀperformsꢀaꢀREADꢀOPERATIONꢀ

withꢀA9ꢀraisedꢀtoꢀVhv,ꢀaddressꢀpinꢀA6,ꢀA3ꢀ&ꢀA2ꢀheldꢀLOW,ꢀandꢀꢀaddressꢀpinsꢀA1ꢀ&ꢀA0ꢀheldꢀHIGH.ꢀꢀIfꢀtheꢀSecurityꢀ

Sectorꢀhasꢀbeenꢀlockedꢀatꢀtheꢀfactory,ꢀtheꢀcodeꢀ99h(H)/89h(L)ꢀwillꢀbeꢀpresentꢀonꢀdataꢀbitsꢀQ0ꢀtoꢀQ7.ꢀꢀOtherwise,ꢀ

theꢀfactoryꢀunlockedꢀcodeꢀofꢀ19h(H)/09h(L)ꢀwillꢀbeꢀpresent.

INHERENT DATA PROTECTION

Toꢀavoidꢀaccidentalꢀerasureꢀorꢀprogrammingꢀofꢀtheꢀdevice,ꢀtheꢀdeviceꢀisꢀautomaticallyꢀresetꢀtoꢀReadꢀmodeꢀduringꢀ

powerꢀup.ꢀꢀAdditionally,ꢀtheꢀfollowingꢀdesignꢀfeaturesꢀprotectꢀtheꢀdeviceꢀfromꢀunintendedꢀdataꢀcorruption.

COMMAND COMPLETION

Onlyꢀafterꢀtheꢀsuccessfulꢀcompletionꢀofꢀtheꢀspeciﬁedꢀcommandꢀsetsꢀwillꢀtheꢀdeviceꢀbeginꢀitsꢀeraseꢀorꢀprogramꢀ

operation.ꢀꢀTheꢀfailureꢀinꢀobservingꢀvalidꢀcommandꢀsetsꢀwillꢀresultꢀinꢀtheꢀmemoryꢀreturningꢀtoꢀreadꢀmode.

LOW VCC WRITE INHIBIT

TheꢀdeviceꢀrefusesꢀtoꢀacceptꢀanyꢀwriteꢀcommandꢀwhenꢀVccꢀisꢀlessꢀthanꢀVLKO.ꢀThisꢀpreventsꢀdataꢀfromꢀ

spuriouslyꢀbeingꢀalteredꢀduringꢀpower-up,ꢀpower-down,ꢀorꢀtemporaryꢀpowerꢀinterruptions.ꢀTheꢀdeviceꢀ

automaticallyꢀresetsꢀitselfꢀwhenꢀVccꢀisꢀlowerꢀthanꢀVLKOꢀandꢀwriteꢀcyclesꢀareꢀignoredꢀuntilꢀVccꢀisꢀgreaterꢀthanꢀ

VLKO.ꢀTheꢀsystemꢀmustꢀprovideꢀproperꢀsignalsꢀonꢀcontrolꢀpinsꢀafterꢀVccꢀrisesꢀaboveꢀVLKOꢀtoꢀavoidꢀunintentionalꢀ

programꢀorꢀeraseꢀoperations.

WRITE PULSE "GLITCH" PROTECTION

CE#,ꢀWE#,ꢀOE#ꢀpulsesꢀshorterꢀthanꢀ5nsꢀareꢀtreatedꢀasꢀglitchesꢀandꢀwillꢀnotꢀbeꢀregardedꢀasꢀanꢀeffectiveꢀwriteꢀ

cycle.

LOGICAL INHIBIT

AꢀvalidꢀwriteꢀcycleꢀrequiresꢀbothꢀCE#ꢀandꢀWE#ꢀatꢀVilꢀwithꢀOE#ꢀatꢀVih.ꢀWriteꢀcycleꢀisꢀignoredꢀwhenꢀeitherꢀCE#ꢀatꢀ

Vih,ꢀWE#ꢀatꢀVih,ꢀorꢀOE#ꢀatꢀVil.

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FUNCTIONAL OPERATION DESCRIPTION (cont'd)

POWER-UP SEQUENCE

Uponꢀpowerꢀup,ꢀtheꢀdeviceꢀisꢀplacedꢀinꢀReadꢀmode.ꢀFurthermore,ꢀprogramꢀorꢀeraseꢀoperationꢀwillꢀbeginꢀonlyꢀ

afterꢀsuccessfulꢀcompletionꢀofꢀspeciﬁedꢀcommandꢀsequences.

POWER-UP WRITE INHIBIT

WhenꢀWE#,ꢀCE#ꢀisꢀheldꢀatꢀVilꢀandꢀOE#ꢀisꢀheldꢀatꢀVihꢀduringꢀpowerꢀup,ꢀtheꢀdeviceꢀignoresꢀtheꢀﬁrstꢀcommandꢀonꢀ

theꢀrisingꢀedgeꢀofꢀWE#.

POWER SUPPLY DECOUPLING

Aꢀ0.1uFꢀcapacitorꢀshouldꢀbeꢀconnectedꢀbetweenꢀtheꢀVccꢀandꢀGNDꢀtoꢀreduceꢀtheꢀnoiseꢀeffect.

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COMMAND OPERATIONS

READING THE MEMORY ARRAY

Readꢀmodeꢀisꢀtheꢀdefaultꢀstateꢀafterꢀpowerꢀupꢀorꢀafterꢀaꢀresetꢀoperation.ꢀꢀToꢀperformꢀaꢀreadꢀoperation,ꢀpleaseꢀre-

ferꢀtoꢀREADꢀOPERATIONꢀinꢀtheꢀBUSꢀOPERATIONSꢀsectionꢀabove.

IfꢀtheꢀdeviceꢀreceivesꢀanꢀEraseꢀSuspendꢀcommandꢀwhileꢀinꢀtheꢀSectorꢀEraseꢀstate,ꢀtheꢀeraseꢀoperationꢀwillꢀ

pauseꢀ(afterꢀaꢀtimeꢀdelayꢀnotꢀexceedingꢀ20us)ꢀandꢀtheꢀdeviceꢀwillꢀenterꢀErase-SuspendedꢀReadꢀmode.ꢀꢀWhileꢀinꢀ

theꢀErase-SuspendedꢀReadꢀmode,ꢀdataꢀcanꢀbeꢀprogrammedꢀorꢀreadꢀfromꢀanyꢀsectorꢀnotꢀbeingꢀerased.ꢀꢀReadingꢀ

fromꢀaddressesꢀwithinꢀsector(s)ꢀbeingꢀerasedꢀwillꢀonlyꢀreturnꢀtheꢀcontentsꢀofꢀtheꢀstatusꢀregister,ꢀwhichꢀisꢀinꢀfactꢀ

howꢀtheꢀcurrentꢀstatusꢀofꢀtheꢀdeviceꢀcanꢀbeꢀdetermined.

Ifꢀaꢀprogramꢀcommandꢀisꢀissuedꢀtoꢀanyꢀinactiveꢀ(notꢀcurrentlyꢀbeingꢀerased)ꢀsectorꢀduringꢀErase-Suspendedꢀ

Readꢀmode,ꢀtheꢀdeviceꢀwillꢀperformꢀtheꢀprogramꢀoperationꢀandꢀautomaticallyꢀreturnꢀtoꢀErase-SuspendedꢀReadꢀ

modeꢀafterꢀtheꢀprogramꢀoperationꢀcompletesꢀsuccessfully.

WhileꢀinꢀErase-SuspendedꢀReadꢀmode,ꢀanꢀEraseꢀResumeꢀcommandꢀmustꢀbeꢀissuedꢀbyꢀtheꢀsystemꢀtoꢀreactivateꢀ

theꢀeraseꢀoperation.ꢀꢀTheꢀeraseꢀoperationꢀwillꢀresumeꢀfromꢀwhereꢀisꢀwasꢀsuspendedꢀandꢀwillꢀcontinueꢀuntilꢀitꢀ

completesꢀsuccessfullyꢀorꢀanotherꢀEraseꢀSuspendꢀcommandꢀisꢀreceived.

Afterꢀtheꢀmemoryꢀdeviceꢀcompletesꢀanꢀembeddedꢀoperationꢀ(automaticꢀChipꢀErase,ꢀSectorꢀErase,ꢀorꢀProgram)ꢀ

successfully,ꢀitꢀwillꢀautomaticallyꢀreturnꢀtoꢀReadꢀmodeꢀandꢀdataꢀcanꢀbeꢀreadꢀfromꢀanyꢀaddressꢀinꢀtheꢀarray.ꢀIfꢀtheꢀ

embeddedꢀoperationꢀfailsꢀtoꢀcomplete,ꢀasꢀindicatedꢀbyꢀstatusꢀregisterꢀbitꢀQ5ꢀ(exceedsꢀtimeꢀlimitꢀﬂag)ꢀgoingꢀHIGHꢀ

duringꢀtheꢀoperations,ꢀtheꢀsystemꢀmustꢀperformꢀaꢀresetꢀoperationꢀtoꢀreturnꢀtheꢀdeviceꢀtoꢀReadꢀmode.

ThereꢀareꢀseveralꢀstatesꢀthatꢀrequireꢀaꢀresetꢀoperationꢀtoꢀreturnꢀtoꢀReadꢀmode:

1.ꢀAꢀprogramꢀorꢀeraseꢀfailure--indicatedꢀbyꢀstatusꢀregisterꢀbitꢀQ5ꢀgoingꢀHIGHꢀduringꢀtheꢀoperation.ꢀꢀFailuresꢀdur-

ingꢀeitherꢀofꢀtheseꢀstatesꢀwillꢀpreventꢀtheꢀdeviceꢀfromꢀautomaticallyꢀreturningꢀtoꢀReadꢀmode.

2.ꢀTheꢀdeviceꢀisꢀinꢀAutoꢀSelectꢀmodeꢀorꢀCFIꢀmode.ꢀꢀTheseꢀtwoꢀstatesꢀremainꢀactiveꢀuntilꢀtheyꢀareꢀterminatedꢀbyꢀaꢀ

resetꢀoperation.

Inꢀtheꢀtwoꢀsituationsꢀabove,ꢀifꢀaꢀresetꢀoperationꢀ(eitherꢀhardwareꢀresetꢀorꢀsoftwareꢀresetꢀcommand)ꢀisꢀnotꢀper-

formed,ꢀtheꢀdeviceꢀwillꢀnotꢀreturnꢀtoꢀReadꢀmodeꢀandꢀtheꢀsystemꢀwillꢀnotꢀbeꢀableꢀtoꢀreadꢀarrayꢀdata.

AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY

TheꢀdeviceꢀprovidesꢀtheꢀuserꢀtheꢀabilityꢀtoꢀprogramꢀtheꢀmemoryꢀarrayꢀinꢀByteꢀmodeꢀorꢀWordꢀmode.ꢀAsꢀlongꢀasꢀ

theꢀusersꢀentersꢀtheꢀcorrectꢀcycleꢀdeﬁnedꢀinꢀtheꢀTableꢀ3ꢀ(includingꢀ2ꢀunlockꢀcyclesꢀandꢀtheꢀA0Hꢀprogramꢀcom-

mand),ꢀanyꢀbyteꢀorꢀwordꢀdataꢀprovidedꢀonꢀtheꢀdataꢀlinesꢀbyꢀtheꢀsystemꢀwillꢀautomaticallyꢀbeꢀprogrammedꢀintoꢀtheꢀ

arrayꢀatꢀtheꢀspeciﬁedꢀlocation.

Afterꢀtheꢀprogramꢀcommandꢀsequenceꢀhasꢀbeenꢀexecuted,ꢀtheꢀinternalꢀwriteꢀstateꢀmachineꢀ(WSM)ꢀautomaticallyꢀ

executesꢀtheꢀalgorithmsꢀandꢀtimingsꢀnecessaryꢀforꢀprogrammingꢀandꢀveriﬁcation,ꢀwhichꢀincludesꢀgeneratingꢀsuit-

ableꢀprogramꢀpulses,ꢀcheckingꢀcellꢀthresholdꢀvoltageꢀmargins,ꢀandꢀrepeatingꢀtheꢀprogramꢀpulseꢀifꢀanyꢀcellsꢀdoꢀ

notꢀpassꢀveriﬁcationꢀorꢀhaveꢀlowꢀmargins.ꢀTheꢀinternalꢀcontrollerꢀprotectsꢀcellsꢀthatꢀdoꢀpassꢀveriﬁcationꢀandꢀmar-

ginꢀtestsꢀfromꢀbeingꢀover-programmedꢀbyꢀinhibitingꢀfurtherꢀprogramꢀpulsesꢀtoꢀtheseꢀpassingꢀcellsꢀasꢀweakerꢀcellsꢀ

continueꢀtoꢀbeꢀprogrammed.

WithꢀtheꢀinternalꢀWSMꢀautomaticallyꢀcontrollingꢀtheꢀprogrammingꢀprocess,ꢀtheꢀuserꢀonlyꢀneedsꢀtoꢀenterꢀtheꢀpro-

gramꢀcommandꢀandꢀdataꢀonce.

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COMMAND OPERATIONS (cont'd)

AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY (cont'd)

Programmingꢀwillꢀonlyꢀchangeꢀtheꢀbitꢀstatusꢀfromꢀ"1"ꢀtoꢀ"0".ꢀꢀItꢀisꢀnotꢀpossibleꢀtoꢀchangeꢀtheꢀbitꢀstatusꢀfromꢀ"0"ꢀtoꢀ

"1"ꢀbyꢀprogramming.ꢀThisꢀcanꢀonlyꢀbeꢀdoneꢀbyꢀanꢀeraseꢀoperation.ꢀꢀFurthermore,ꢀtheꢀinternalꢀwriteꢀveriﬁcationꢀ

onlyꢀchecksꢀandꢀdetectsꢀerrorsꢀinꢀcasesꢀwhereꢀaꢀ"1"ꢀisꢀnotꢀsuccessfullyꢀprogrammedꢀtoꢀ"0".

Anyꢀcommandsꢀwrittenꢀtoꢀtheꢀdeviceꢀduringꢀprogrammingꢀwillꢀbeꢀignoredꢀexceptꢀhardwareꢀresetꢀorꢀprogramꢀsus-

pend.ꢀꢀHardꢀwareꢀresetꢀwillꢀterminateꢀtheꢀprogramꢀoperationꢀafterꢀaꢀperiodꢀofꢀtimeꢀnoꢀmoreꢀthanꢀ10us.ꢀWhenꢀtheꢀ

embeddedꢀprogramꢀalgorithmꢀisꢀcompleteꢀorꢀtheꢀprogramꢀoperationꢀisꢀterminatedꢀbyꢀaꢀhardwareꢀreset,ꢀtheꢀde-

viceꢀwillꢀreturnꢀtoꢀReadꢀmode.ꢀProgramꢀsuspendꢀready,ꢀtheꢀdeviceꢀwillꢀenterꢀprogramꢀsuspendꢀreadꢀmode.ꢀ

Afterꢀtheꢀembeddedꢀprogramꢀoperationꢀhasꢀbegun,ꢀtheꢀuserꢀcanꢀcheckꢀforꢀcompletionꢀbyꢀreadingꢀtheꢀfollowingꢀ

bitsꢀinꢀtheꢀstatusꢀregister:

Status

Q7^*1

Q7#

Q6^*1

Q5

0

Q1

0

RY/BY# (Note)

Inꢀprogress

Toggling

0

Exceedꢀtimeꢀlimit

1

N/A

Note:ꢀRY/BY#ꢀisꢀanꢀopenꢀdrainꢀoutputꢀpinꢀandꢀshouldꢀbeꢀconnectedꢀtoꢀVCCꢀthroughꢀaꢀhighꢀvalueꢀpull-upꢀresistor.

ERASING THE MEMORY ARRAY

Thereꢀareꢀtwoꢀtypesꢀofꢀeraseꢀoperationsꢀperformedꢀonꢀtheꢀmemoryꢀarrayꢀ--ꢀSectorꢀEraseꢀandꢀChipꢀErase.ꢀꢀInꢀ

theꢀSectorꢀEraseꢀoperation,ꢀoneꢀorꢀmoreꢀselectedꢀsectorsꢀmayꢀbeꢀerasedꢀsimultaneously.ꢀꢀInꢀtheꢀChipꢀEraseꢀ

operation,ꢀtheꢀcompleteꢀmemoryꢀarrayꢀisꢀerasedꢀexceptꢀforꢀanyꢀprotectedꢀsectors.ꢀꢀMoreꢀdetailsꢀofꢀtheꢀprotectedꢀ

sectorsꢀareꢀexplainedꢀinꢀsectionꢀ5.

SECTOR ERASE

Theꢀsectorꢀeraseꢀoperationꢀisꢀusedꢀtoꢀclearꢀdataꢀwithinꢀaꢀsectorꢀbyꢀreturningꢀallꢀofꢀitsꢀmemoryꢀlocationsꢀtoꢀtheꢀ

"1"ꢀstate.ꢀItꢀrequiresꢀsixꢀcommandꢀcyclesꢀtoꢀinitiateꢀtheꢀeraseꢀoperation.ꢀTheꢀﬁrstꢀtwoꢀcyclesꢀareꢀ"unlockꢀcycles",ꢀ

theꢀthirdꢀisꢀaꢀconﬁgurationꢀcycle,ꢀtheꢀfourthꢀandꢀﬁfthꢀareꢀalsoꢀ"unlockꢀcycles",ꢀandꢀtheꢀsixthꢀcycleꢀisꢀtheꢀSectorꢀ

Eraseꢀcommand.ꢀꢀAfterꢀtheꢀsectorꢀeraseꢀcommandꢀsequenceꢀhasꢀbeenꢀissued,ꢀanꢀinternalꢀ50usꢀtime-outꢀcounterꢀ

isꢀstarted.ꢀꢀUntilꢀthisꢀcounterꢀreachesꢀzero,ꢀadditionalꢀsectorꢀaddressesꢀandꢀSectorꢀEraseꢀcommandsꢀmayꢀbeꢀis-

suedꢀthusꢀallowingꢀmultipleꢀsectorsꢀtoꢀbeꢀselectedꢀandꢀerasedꢀsimultaneously.ꢀꢀAfterꢀtheꢀ50usꢀtime-outꢀcounterꢀ

hasꢀexpired,ꢀnoꢀnewꢀcommandsꢀwillꢀbeꢀacceptedꢀandꢀtheꢀembeddedꢀsectorꢀeraseꢀoperationꢀwillꢀbegin.ꢀꢀNoteꢀthatꢀ

theꢀ50usꢀtimer-outꢀcounterꢀisꢀrestartedꢀafterꢀeveryꢀeraseꢀcommandꢀsequence.ꢀꢀIfꢀtheꢀuserꢀentersꢀanyꢀcommandꢀ

otherꢀthanꢀSectorꢀEraseꢀorꢀEraseꢀSuspendꢀduringꢀtheꢀtime-outꢀperiod,ꢀtheꢀeraseꢀoperationꢀwillꢀabortꢀandꢀtheꢀde-

viceꢀwillꢀreturnꢀtoꢀReadꢀmode.

Afterꢀtheꢀembeddedꢀsectorꢀeraseꢀoperationꢀbegins,ꢀallꢀcommandsꢀexceptꢀEraseꢀSuspendꢀwillꢀbeꢀignored.ꢀꢀTheꢀ

onlyꢀwayꢀtoꢀinterruptꢀtheꢀoperationꢀisꢀwithꢀanꢀEraseꢀSuspendꢀcommandꢀorꢀwithꢀaꢀhardwareꢀreset.ꢀꢀTheꢀhardwareꢀ

resetꢀwillꢀcompletelyꢀabortꢀtheꢀoperationꢀandꢀreturnꢀtheꢀdeviceꢀtoꢀReadꢀmode.

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COMMAND OPERATIONS (cont'd)

SECTOR ERASE (cont'd)

Theꢀsystemꢀcanꢀdetermineꢀtheꢀstatusꢀofꢀtheꢀembeddedꢀsectorꢀeraseꢀoperationꢀbyꢀtheꢀfollowingꢀmethods:

Status

Q7

0

Q6

Q5

0

Q3^*1

0

Q2

RY/BY#^*2

Time-outꢀperiod

Inꢀprogress

Toggling

0

1

Exceededꢀtimeꢀlimit

0

1

Note:

1.ꢀTheꢀQ3ꢀstatusꢀbitꢀisꢀtheꢀ50usꢀtime-outꢀindicator.ꢀWhenꢀQ3=0,ꢀtheꢀ50usꢀtime-outꢀcounterꢀhasꢀnotꢀyetꢀreachedꢀ

zeroꢀandꢀaꢀnewꢀSectorꢀEraseꢀcommandꢀmayꢀbeꢀissuedꢀtoꢀspecifyꢀtheꢀaddressꢀofꢀanotherꢀsectorꢀtoꢀbeꢀerased.ꢀ

WhenꢀQ3=1,ꢀtheꢀ50usꢀtime-outꢀcounterꢀhasꢀexpiredꢀandꢀtheꢀSectorꢀEraseꢀoperationꢀhasꢀalreadyꢀbegun.ꢀꢀEraseꢀ

Suspendꢀisꢀtheꢀonlyꢀvalidꢀcommandꢀthatꢀmayꢀbeꢀissuedꢀonceꢀtheꢀembeddedꢀeraseꢀoperationꢀisꢀunderway.

2.ꢀRY/BY#ꢀisꢀopenꢀdrainꢀoutputꢀpinꢀandꢀshouldꢀbeꢀconnectedꢀtoꢀVCCꢀthroughꢀaꢀhighꢀvalueꢀpull-upꢀresistor.

3.ꢀWhenꢀanꢀattemptꢀisꢀmadeꢀtoꢀeraseꢀonlyꢀprotectedꢀsector(s),ꢀtheꢀeraseꢀoperationꢀwillꢀabortꢀthusꢀpreventingꢀanyꢀ

dataꢀchangesꢀinꢀtheꢀprotectedꢀsector(s).ꢀꢀQ7ꢀwillꢀoutputꢀ"0"ꢀandꢀQ6ꢀwillꢀtoggleꢀbrieﬂyꢀ(100usꢀorꢀless)ꢀbeforeꢀ

abortingꢀandꢀreturningꢀtheꢀdeviceꢀtoꢀReadꢀmode.ꢀꢀIfꢀunprotectedꢀsectorsꢀareꢀalsoꢀspeciﬁed,ꢀhowever,ꢀtheyꢀwillꢀ

beꢀerasedꢀnormallyꢀandꢀtheꢀprotectedꢀsector(s)ꢀwillꢀremainꢀunchanged.

4.ꢀ

Q2ꢀisꢀaꢀlocalizedꢀindicatorꢀshowingꢀaꢀspeciﬁedꢀsectorꢀisꢀundergoingꢀeraseꢀoperationꢀorꢀnot.ꢀQ2ꢀtogglesꢀwhenꢀ

userꢀreadsꢀatꢀaddressesꢀwhereꢀtheꢀsectorsꢀareꢀactivelyꢀbeingꢀerasedꢀ(inꢀeraseꢀmode)ꢀorꢀtoꢀbeꢀerasedꢀ(inꢀeraseꢀ

suspendꢀmode).ꢀ

CHIP ERASE

TheꢀChipꢀEraseꢀoperationꢀisꢀusedꢀeraseꢀallꢀtheꢀdataꢀwithinꢀtheꢀmemoryꢀarray.ꢀꢀAllꢀmemoryꢀcellsꢀcontainingꢀaꢀ"0"ꢀ

willꢀbeꢀreturnedꢀtoꢀtheꢀerasedꢀstateꢀofꢀ"1".ꢀꢀThisꢀoperationꢀrequiresꢀ6ꢀwriteꢀcyclesꢀtoꢀinitiateꢀtheꢀaction.ꢀꢀTheꢀﬁrstꢀ

twoꢀcyclesꢀareꢀ"unlock"ꢀcycles,ꢀtheꢀthirdꢀisꢀaꢀconﬁgurationꢀcycle,ꢀtheꢀfourthꢀandꢀﬁfthꢀareꢀalsoꢀ"unlock"ꢀcycles,ꢀandꢀ

theꢀsixthꢀcycleꢀinitiatesꢀtheꢀchipꢀeraseꢀoperation.ꢀ

Duringꢀtheꢀchipꢀeraseꢀoperation,ꢀnoꢀotherꢀsoftwareꢀcommandsꢀwillꢀbeꢀaccepted,ꢀbutꢀifꢀaꢀhardwareꢀresetꢀisꢀre-

ceivedꢀorꢀtheꢀworkingꢀvoltageꢀisꢀtooꢀlow,ꢀthatꢀchipꢀeraseꢀwillꢀbeꢀterminated.ꢀAfterꢀChipꢀErase,ꢀtheꢀchipꢀwillꢀauto-

maticallyꢀreturnꢀtoꢀReadꢀmode.

Theꢀsystemꢀcanꢀdetermineꢀtheꢀstatusꢀofꢀtheꢀembeddedꢀchipꢀeraseꢀoperationꢀbyꢀtheꢀfollowingꢀmethods:

Status

Q7

0

Q6

Q5

0

Q2

RY/BY#^*1

Inꢀprogress

Toggling

0

Exceedꢀtimeꢀlimit

0

1

*1:ꢀRY/BY#ꢀisꢀopenꢀdrainꢀoutputꢀpinꢀandꢀshouldꢀbeꢀconnectedꢀtoꢀVCCꢀthroughꢀaꢀhighꢀvalueꢀpull-upꢀresistor.

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COMMAND OPERATIONS (cont'd)

ERASE SUSPEND/RESUME

Afterꢀbeginningꢀaꢀsectorꢀeraseꢀoperation,ꢀEraseꢀSuspendꢀisꢀtheꢀonlyꢀvalidꢀcommandꢀthatꢀmayꢀbeꢀissued.ꢀIfꢀsys-

temꢀissuesꢀanꢀEraseꢀSuspendꢀcommandꢀduringꢀtheꢀ50usꢀtime-outꢀperiodꢀfollowingꢀaꢀSectorꢀEraseꢀcommand,ꢀtheꢀ

time-outꢀperiodꢀwillꢀterminateꢀimmediatelyꢀandꢀtheꢀdeviceꢀwillꢀenterꢀErase-SuspendedꢀReadꢀmode.ꢀꢀIfꢀtheꢀsystemꢀ

issuesꢀanꢀEraseꢀSuspendꢀcommandꢀafterꢀtheꢀsectorꢀeraseꢀoperationꢀhasꢀalreadyꢀbegun,ꢀtheꢀdeviceꢀwillꢀnotꢀenterꢀ

Erase-SuspendedꢀReadꢀmodeꢀuntilꢀ20usꢀtimeꢀhasꢀelapsed.ꢀꢀTheꢀsystemꢀcanꢀdetermineꢀifꢀtheꢀdeviceꢀhasꢀenteredꢀ

theꢀErase-SuspendedꢀReadꢀmodeꢀthroughꢀQ6,ꢀQ7,ꢀandꢀRY/BY#.

AfterꢀtheꢀdeviceꢀhasꢀenteredꢀErase-SuspendedꢀReadꢀmode,ꢀtheꢀsystemꢀcanꢀreadꢀorꢀprogramꢀanyꢀsector(s)ꢀex-

ceptꢀthoseꢀbeingꢀerasedꢀbyꢀtheꢀsuspendedꢀeraseꢀoperation.ꢀꢀReadingꢀanyꢀsectorꢀbeingꢀerasedꢀorꢀprogrammedꢀ

willꢀreturnꢀtheꢀcontentsꢀofꢀtheꢀstatusꢀregister.ꢀꢀWheneverꢀaꢀsuspendꢀcommandꢀisꢀissued,ꢀuserꢀmustꢀissueꢀaꢀre-

sumeꢀcommandꢀandꢀcheckꢀQ6ꢀtoggleꢀbitꢀstatus,ꢀbeforeꢀissueꢀanotherꢀeraseꢀcommand.ꢀTheꢀsystemꢀcanꢀuseꢀtheꢀ

statusꢀregisterꢀbitsꢀshownꢀinꢀtheꢀfollowingꢀtableꢀtoꢀdetermineꢀtheꢀcurrentꢀstateꢀofꢀtheꢀdevice:

Status

Q7

1

Q6

Noꢀtoggle

Data

Q5

Q3

Q2

Q1 RY/BY#

Eraseꢀsuspendꢀreadꢀinꢀeraseꢀsuspendedꢀsector

Eraseꢀsuspendꢀreadꢀinꢀnon-eraseꢀsuspendedꢀsector

Eraseꢀsuspendꢀprogramꢀinꢀnon-eraseꢀsuspendedꢀsector

0

N/A toggle N/A

1

0

Data

Q7#

Data Data Data Data

N/A N/A N/A

Toggle

0

Whenꢀtheꢀdeviceꢀhasꢀsuspendedꢀerasing,ꢀuserꢀcanꢀexecuteꢀtheꢀcommandꢀsetsꢀexceptꢀsectorꢀeraseꢀandꢀchipꢀ

erase,ꢀsuchꢀasꢀreadꢀsiliconꢀID,ꢀsectorꢀprotectꢀverify,ꢀprogram,ꢀCFIꢀqueryꢀandꢀeraseꢀresume.ꢀ

SECTOR ERASE RESUME

TheꢀsectorꢀEraseꢀResumeꢀcommandꢀisꢀvalidꢀonlyꢀwhenꢀtheꢀdeviceꢀisꢀinꢀErase-SuspendedꢀReadꢀmode.ꢀAfterꢀ

eraseꢀresumes,ꢀtheꢀuserꢀcanꢀissueꢀanotherꢀEaseꢀSuspendꢀcommand,ꢀbutꢀthereꢀshouldꢀbeꢀaꢀ400usꢀintervalꢀbe-

tweenꢀEaseꢀResumeꢀandꢀtheꢀnextꢀEraseꢀSuspendꢀcommand.

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COMMAND OPERATIONS (cont'd)

PROGRAM SUSPEND/RESUME

Afterꢀbeginningꢀaꢀprogramꢀoperation,ꢀProgramꢀSuspendꢀisꢀtheꢀonlyꢀvalidꢀcommandꢀthatꢀmayꢀbeꢀissued.ꢀꢀTheꢀsys-

temꢀcanꢀdetermineꢀifꢀtheꢀdeviceꢀhasꢀenteredꢀtheꢀProgram-SuspendedꢀReadꢀmodeꢀthroughꢀQ6,ꢀandꢀRY/BY#.

AfterꢀtheꢀdeviceꢀhasꢀenteredꢀProgram-Suspendedꢀmode,ꢀtheꢀsystemꢀcanꢀreadꢀanyꢀsector(s)ꢀexceptꢀthoseꢀbeingꢀ

programdꢀbyꢀtheꢀsuspendedꢀprogramꢀoperation.ꢀꢀReadingꢀtheꢀsectorꢀbeingꢀprogramꢀsuspendedꢀisꢀinvalid.ꢀꢀWhen-

everꢀaꢀsuspendꢀcommandꢀisꢀissued,ꢀuserꢀmustꢀissueꢀaꢀresumeꢀcommandꢀandꢀcheckꢀQ6ꢀtoggleꢀbitꢀstatus,ꢀbeforeꢀ

issueꢀanotherꢀprogramꢀcommand.ꢀTheꢀsystemꢀcanꢀuseꢀtheꢀstatusꢀregisterꢀbitsꢀshownꢀinꢀtheꢀfollowingꢀtableꢀtoꢀde-

termineꢀtheꢀcurrentꢀstateꢀofꢀtheꢀdevice:

Status

Q7

Q6

Q5

Q3

Q2

Q1 RY/BY#

Programꢀsuspendꢀreadꢀinꢀprogramꢀsuspendedꢀsector

Invalid

1

Programꢀsuspendꢀreadꢀinꢀnon-programꢀsuspendedꢀ

sector

Data Data Data Data Data Data

1

WhenꢀtheꢀdeviceꢀhasꢀProgram/Eraseꢀsuspended,ꢀuserꢀcanꢀexecuteꢀreadꢀarray,ꢀauto-select,ꢀreadꢀCFI,ꢀreadꢀsecu-

rityꢀsilicon.

PROGRAM RESUME

TheꢀProgramꢀResumeꢀcommandꢀisꢀvalidꢀonlyꢀwhenꢀtheꢀdeviceꢀisꢀinꢀProgram-Suspendedꢀmode.ꢀAfterꢀprogramꢀ

resumes,ꢀtheꢀuserꢀcanꢀissueꢀanotherꢀProgramꢀSuspendꢀcommand,ꢀbutꢀthereꢀshouldꢀbeꢀaꢀ5usꢀintervalꢀbetweenꢀ

ProgramꢀResumeꢀandꢀtheꢀnextꢀProgramꢀSuspendꢀcommand.ꢀ

BUFFER WRITE ABORT

Q1ꢀisꢀtheꢀindicatorꢀofꢀBufferꢀWriteꢀAbort.ꢀWhenꢀQ1=1,ꢀtheꢀdeviceꢀwillꢀabortꢀfromꢀbufferꢀwriteꢀandꢀgoꢀbackꢀtoꢀreadꢀ

statusꢀregisterꢀshownꢀasꢀfollowingꢀtable:

Status

Q7

Q6

Q5

0

Q3

N/A

Q2

N/A

Q1

0

RY/BY#

BufferꢀWriteꢀBusy

BufferꢀWriteꢀAbort

BufferꢀWriteꢀExceededꢀTimeꢀLimit

Q7#

Toggle

0

1

0

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COMMAND OPERATIONS (cont'd)

AUTOMATIC SELECT OPERATIONS

WhenꢀtheꢀdeviceꢀisꢀinꢀReadꢀmode,ꢀProgramꢀSuspendꢀReadꢀmode,ꢀErase-SuspendedꢀReadꢀmode,ꢀorꢀCFIꢀmode,ꢀ

theꢀuserꢀcanꢀissueꢀtheꢀAutomaticꢀSelectꢀcommandꢀshownꢀinꢀTableꢀ3ꢀ(twoꢀunlockꢀcyclesꢀfollowedꢀbyꢀtheꢀAutomaticꢀ

Selectꢀcommandꢀ90h)ꢀtoꢀenterꢀAutomaticꢀSelectꢀmode.ꢀAfterꢀenteringꢀAutomaticꢀSelectꢀmode,ꢀtheꢀuserꢀcanꢀqueryꢀ

theꢀManufacturerꢀID,ꢀDeviceꢀID,ꢀSecurityꢀSectorꢀlockedꢀstatus,ꢀorꢀSectorꢀprotectedꢀstatusꢀmultipleꢀtimesꢀwithoutꢀ

issuingꢀaꢀnewꢀAutomaticꢀSelectꢀcommand.

WhileꢀInꢀAutomaticꢀSelectꢀmode,ꢀissuingꢀaꢀResetꢀcommandꢀ(F0h)ꢀwillꢀreturnꢀtheꢀdeviceꢀtoꢀReadꢀmodeꢀ(orꢀEase-

SuspendedꢀReadꢀmodeꢀifꢀErase-SuspendꢀwasꢀactiveꢀorꢀProgramꢀSuspendꢀReadꢀmodeꢀifꢀProgramꢀSuspendꢀwasꢀ

active).

AnotherꢀwayꢀtoꢀenterꢀAutomaticꢀSelectꢀmodeꢀisꢀtoꢀuseꢀoneꢀofꢀtheꢀbusꢀoperationsꢀshownꢀinꢀTableꢀ2.ꢀBUSꢀ

OPERATION_2.ꢀꢀAfterꢀtheꢀhighꢀvoltageꢀ(Vhv)ꢀisꢀremovedꢀfromꢀtheꢀA9ꢀpin,ꢀtheꢀdeviceꢀwillꢀautomaticallyꢀreturnꢀtoꢀ

ReadꢀmodeꢀorꢀErase-SuspendedꢀReadꢀmode.

AUTOMATIC SELECT COMMAND SEQUENCE

AutomaticꢀSelectꢀmodeꢀisꢀusedꢀtoꢀaccessꢀtheꢀmanufacturerꢀID,ꢀdeviceꢀIDꢀandꢀtoꢀverifyꢀwhetherꢀorꢀnotꢀsecuredꢀ

siliconꢀisꢀlockedꢀandꢀwhetherꢀorꢀnotꢀaꢀsectorꢀisꢀprotected.ꢀTheꢀautomaticꢀselectꢀmodeꢀhasꢀfourꢀcommandꢀcycles.ꢀ

Theꢀﬁrstꢀtwoꢀareꢀunlockꢀcycles,ꢀandꢀfollowedꢀbyꢀaꢀspeciﬁcꢀcommand.ꢀTheꢀfourthꢀcycleꢀisꢀaꢀnormalꢀreadꢀcycle,ꢀ

andꢀuserꢀcanꢀreadꢀatꢀanyꢀaddressꢀanyꢀnumberꢀofꢀtimesꢀwithoutꢀenteringꢀanotherꢀcommandꢀsequence.ꢀTheꢀResetꢀ

commandꢀisꢀnecessaryꢀtoꢀexitꢀtheꢀAutomaticꢀSelectꢀmodeꢀandꢀbackꢀtoꢀreadꢀarray.ꢀꢀTheꢀfollowingꢀtableꢀshowsꢀtheꢀ

identiﬁcationꢀcodeꢀwithꢀcorrespondingꢀaddress.

Address

X00

Data (Hex)

Representation

Word

Byte

C2

ManufacturerꢀID

X00

Word

X01/0E/0F

227E/2238/2201

MX29GA256/

257E

Byte

Word

Byte

X02/1C/1E

X01/0E/0F

X02/1C/1E

ꢀ7E/38/01

227E/2237/2201

ꢀ7E/37/01

DeviceꢀID

MX29GA128/

129E

99/19ꢀ(H)ꢀ

89/09ꢀ(L)

99/19ꢀ(H)ꢀ

89/09ꢀ(L)

00/01

Word

Byte

X03

X06

Factoryꢀlocked/unlocked

SecuredꢀSilicon

Word (Sectorꢀaddress)ꢀXꢀ02

Byte (Sectorꢀaddress)ꢀXꢀ04

Unprotected/protected

SectorꢀProtectꢀVerify

00/01

Afterꢀenteringꢀautomaticꢀselectꢀmode,ꢀnoꢀotherꢀcommandsꢀareꢀallowedꢀexceptꢀtheꢀresetꢀcommand.

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COMMAND OPERATIONS (cont'd)

READ MANUFACTURER ID OR DEVICE ID

TheꢀManufacturerꢀIDꢀ(identiﬁcation)ꢀisꢀaꢀuniqueꢀhexadecimalꢀnumberꢀassignedꢀtoꢀeachꢀmanufacturerꢀbyꢀtheꢀJE-

DECꢀcommittee.ꢀꢀEachꢀcompanyꢀhasꢀitsꢀownꢀmanufacturerꢀID,ꢀwhichꢀisꢀdifferentꢀfromꢀtheꢀIDꢀofꢀallꢀotherꢀcompa-

nies.ꢀꢀTheꢀnumberꢀassignedꢀtoꢀMacronixꢀisꢀC2h.

AfterꢀenteringꢀAutomaticꢀSelectꢀmode,ꢀperformingꢀaꢀreadꢀoperationꢀwithꢀA1ꢀ&ꢀA0ꢀheldꢀLOWꢀwillꢀcauseꢀtheꢀdeviceꢀ

toꢀoutputꢀtheꢀManufacturerꢀIDꢀonꢀtheꢀDataꢀI/Oꢀ(Q7ꢀtoꢀQ0)ꢀpins.ꢀꢀ

RESET

Inꢀtheꢀfollowingꢀsituations,ꢀexecutingꢀresetꢀcommandꢀwillꢀresetꢀdeviceꢀꢀbackꢀtoꢀReadꢀmode:

•ꢀ Amongꢀeraseꢀcommandꢀsequenceꢀ(beforeꢀtheꢀfullꢀcommandꢀsetꢀisꢀcompleted)

•ꢀ Sectorꢀeraseꢀtime-outꢀperiod

•ꢀ Eraseꢀfailꢀ(whileꢀQ5ꢀisꢀhigh)

•ꢀ Amongꢀprogramꢀcommandꢀsequenceꢀ(beforeꢀtheꢀfullꢀcommandꢀsetꢀisꢀcompleted,ꢀerase-suspendedꢀprogramꢀ

included)

•ꢀ Programꢀfailꢀ(whileꢀQ5ꢀisꢀhigh,ꢀandꢀerase-suspendedꢀprogramꢀfailꢀisꢀincluded)

•ꢀ Auto-Selectꢀmode

•ꢀ CFIꢀmode

Whileꢀdeviceꢀisꢀatꢀtheꢀstatusꢀofꢀprogramꢀfailꢀorꢀeraseꢀfailꢀ(Q5ꢀisꢀhigh),ꢀuserꢀmustꢀissueꢀresetꢀcommandꢀtoꢀresetꢀ

deviceꢀꢀbackꢀtoꢀreadꢀarrayꢀmode.ꢀWhileꢀtheꢀdeviceꢀisꢀinꢀAuto-SelectꢀmodeꢀorꢀCFIꢀmode,ꢀuserꢀmustꢀissueꢀresetꢀ

commandꢀtoꢀresetꢀdeviceꢀꢀbackꢀtoꢀreadꢀarrayꢀmode.ꢀꢀꢀ

Whenꢀtheꢀdeviceꢀisꢀinꢀtheꢀprogressꢀofꢀprogrammingꢀ(notꢀprogramꢀfail)ꢀorꢀerasingꢀ(notꢀeraseꢀfail),ꢀdeviceꢀwillꢀꢀig-

noreꢀresetꢀcommand.

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SECURITY SECTOR FLASH MEMORY REGION

TheꢀSecurityꢀSectorꢀregionꢀisꢀanꢀextraꢀOTPꢀmemoryꢀspaceꢀofꢀ128ꢀwordsꢀinꢀlength.ꢀTheꢀsecurityꢀsectorꢀcanꢀbeꢀ

lockedꢀuponꢀshippingꢀfromꢀfactory,ꢀorꢀitꢀcanꢀbeꢀlockedꢀbyꢀcustomerꢀafterꢀshipping.ꢀCustomerꢀcanꢀissueꢀSecurityꢀ

SectorꢀFactoryꢀProtectꢀVerifyꢀand/orꢀSecurityꢀSectorꢀProtectꢀVerifyꢀtoꢀqueryꢀtheꢀlockꢀstatusꢀofꢀtheꢀdevice.ꢀ

Inꢀfactory-lockedꢀdevice,ꢀsecurityꢀsectorꢀregionꢀisꢀprotectedꢀwhenꢀshippedꢀfromꢀfactoryꢀandꢀtheꢀsecurityꢀsiliconꢀ

sectorꢀindicatorꢀbitꢀisꢀsetꢀtoꢀ"1".ꢀInꢀcustomerꢀlockableꢀdevice,ꢀsecurityꢀsectorꢀregionꢀisꢀunprotectedꢀwhenꢀshippedꢀ

fromꢀfactoryꢀandꢀtheꢀsecurityꢀsiliconꢀindicatorꢀbitꢀisꢀsetꢀtoꢀ"0".ꢀ

Factory Locked: Security Sector Programmed and Protected at the Factory

Inꢀaꢀfactoryꢀlockedꢀdevice,ꢀtheꢀSecurityꢀSectorꢀisꢀpermanentlyꢀlockedꢀbeforeꢀshippingꢀfromꢀtheꢀfactory.ꢀꢀTheꢀde-

viceꢀwillꢀhaveꢀaꢀ16-byteꢀ(8-word)ꢀESNꢀinꢀtheꢀsecurityꢀregion.ꢀTheꢀESNꢀoccupiesꢀaddressesꢀ00000hꢀtoꢀ0000Fhꢀinꢀ

byteꢀmodeꢀorꢀ00000hꢀtoꢀ00007hꢀinꢀwordꢀmode.

Secured Silicon Sector

Express Flash

Factory Locked

Standard Factory Locked

Customer Lockable

Address Range

ESNꢀorꢀDeterminedꢀbyꢀ

Customer

DeterminedꢀbyꢀCustomer

000000h-000007h

000008h-00007Fh

ESN

DeterminedꢀbyꢀCustomer

Unavailable

Customer Lockable: Security Sector NOT Programmed or Protected at the Factory

Whenꢀtheꢀsecurityꢀfeatureꢀisꢀnotꢀrequired,ꢀtheꢀsecurityꢀregionꢀcanꢀactꢀasꢀanꢀextraꢀmemoryꢀspace.ꢀ

Securityꢀsiliconꢀsectorꢀcanꢀalsoꢀbeꢀprotectedꢀbyꢀtwoꢀmethods.ꢀNoteꢀthatꢀonceꢀtheꢀsecurityꢀsiliconꢀsectorꢀisꢀpro-

tected,ꢀthereꢀisꢀnoꢀwayꢀtoꢀunprotectꢀtheꢀsecurityꢀsiliconꢀsectorꢀandꢀtheꢀcontentꢀofꢀitꢀcanꢀnoꢀlongerꢀbeꢀaltered.

Afterꢀtheꢀsecurityꢀsiliconꢀisꢀlockedꢀandꢀveriﬁed,ꢀsystemꢀmustꢀwriteꢀExitꢀSecurityꢀSectorꢀRegion,ꢀgoꢀthroughꢀaꢀpow-

erꢀcycle,ꢀorꢀissueꢀaꢀhardwareꢀresetꢀtoꢀreturnꢀtheꢀdeviceꢀtoꢀreadꢀnormalꢀarrayꢀmode.

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TABLE 3. COMMAND DEFINITIONS

AutomaticꢀSelect

Securityꢀ

Sectorꢀ

Region

ExitꢀSecurityꢀ

Sector

Program

Readꢀ Resetꢀ

Mode Mode

FactoryꢀProtectꢀ SectorꢀProtectꢀ

Commandꢀ

SiliconꢀID DeviceꢀID

Word Byte Word Byte

Addr Addr XXX 555 AAA 555 AAA

Verifyꢀ

Verify

Word Byte Word

Byte Word Byte Word Byte Word Byte

555

AAA

555

AAA

555 AAA 555 AAA 555 AAA

AA AA AA AA AA AA

2AA 555 2AA 555 2AA 555

55 55 55 55 55 55

555 AAA 555 AAA 555 AAA

88 88 90 90 A0 A0

XXX XXX Addr Addr

1stꢀBusꢀ

Cycle

Data Data

Addr

F0

AA AA AA

2AA 555 2AA 555

55 55 55 55

555 AAA 555 AAA

90 90 90 90

AA

2AA

55

AA

555

55

AA

2AA

55

AA

555

55

AAA

90

2ndꢀBusꢀ

Cycle

Data

Addr

Data

555

90

AAA

90

555

90

3rdꢀBusꢀ

Cycle

(Sector) (Sector)

X02

Addr

X00 X00 X01 X02

X03

X06

X04

4thꢀBusꢀ

Cycle

99/19(H)ꢀ

89/09(L)

Data

C2h C2h ID1 ID1

00/01

00

00 Data Data

Addr

Data

Addr

Data

X0E X1C

ID2 ID2

X0F X1E

ID3 ID3

5thꢀBusꢀꢀ

Cycle

6thꢀBusꢀꢀ

Cycle

Writeꢀtoꢀ

Bufferꢀ

Programꢀ

conﬁrm

Writeꢀtoꢀ

Bufferꢀ

Program

Bufferꢀ

Programꢀ

Abortꢀ

Program/ Program/

Erase Eraseꢀ

Suspend Resume

DeepꢀPowerꢀDown

Chipꢀ

Erase

Sectorꢀ

Erase

CFIꢀRead

Commandꢀ

Reset

Enter

Exit

Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte

Addr 555 AAA 555 AAA SA SA 555 AAA 555 AAA 55 AA XXX XXX XXX XXX 555 AAA XXX XXX

1stꢀBusꢀ

Cycle

Data AA AA AA AA 29

Addr 2AA 555 2AA 555

29 AA AA AA AA 98 98 B0 B0 30 30 AA AA AB AB

2AA 555 2AA 555

55 55 55 55

555 AAA 555 AAA

80 80 80 80

2AA 555

55 55

2ndꢀBusꢀ

Cycle

Data 55

55

55 55

Addr SA SA 555 AAA

XXX XXX

B9 B9

3rdꢀBusꢀ

Cycle

Data 25

25

F0 F0

Addr SA SA

Data N-1 N-1

Addr WA WA

Data WD WD

555 AAA 555 AAA

AA AA AA AA

2AA 555 2AA 555

4thꢀBusꢀ

Cycle

5thꢀBusꢀ

Cycle

55 55

555 AAA

10 10

55

Sec- Sec-

tor

30

Addr WBL WBL

Data WD WD

6thꢀBusꢀ

Cycle

tor

30

WA=ꢀWriteꢀAddress

WD=ꢀWriteꢀData

SA=ꢀSectorꢀAddress

N=ꢀWordꢀCount

WBL=ꢀWriteꢀBufferꢀLocation

ID1/ID2/ID3:ꢀReferꢀtoꢀTableꢀ2-2ꢀforꢀdetailꢀIDꢀofꢀeachꢀdevice.

Notes:ꢀ

*ꢀItꢀisꢀnotꢀrecommendedꢀtoꢀadoptꢀanyꢀotherꢀcodeꢀnotꢀinꢀtheꢀcommandꢀdeﬁnitionꢀtableꢀwhichꢀwillꢀpotentiallyꢀenterꢀ

theꢀhiddenꢀmode.

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COMMON FLASH MEMORY INTERFACE (CFI) MODE

QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE

TheꢀdeviceꢀfeaturesꢀCFIꢀmode.ꢀHostꢀsystemꢀcanꢀretrieveꢀtheꢀoperatingꢀcharacteristics,ꢀstructureꢀandꢀvendor-

speciﬁedꢀinformationꢀsuchꢀasꢀidentifyingꢀinformation,ꢀmemoryꢀsize,ꢀbyte/wordꢀconﬁguration,ꢀoperatingꢀvoltagesꢀ

andꢀtimingꢀinformationꢀofꢀthisꢀdeviceꢀbyꢀCFIꢀmode.ꢀIfꢀtheꢀsystemꢀwritesꢀtheꢀCFIꢀQueryꢀcommandꢀ"98h",ꢀtoꢀad-

dressꢀ"55h"/"AAh"ꢀ(dependingꢀonꢀWord/Byteꢀmode),ꢀtheꢀdeviceꢀwillꢀenterꢀtheꢀCFIꢀQueryꢀMode,ꢀanyꢀtimeꢀtheꢀde-

viceꢀisꢀreadyꢀtoꢀreadꢀarrayꢀdata.ꢀTheꢀsystemꢀcanꢀreadꢀCFIꢀinformationꢀatꢀtheꢀaddressesꢀgivenꢀinꢀTableꢀ4.ꢀ

OnceꢀuserꢀentersꢀCFIꢀqueryꢀmode,ꢀuserꢀcanꢀissueresetꢀcommandꢀtoꢀexitꢀCFIꢀmodeꢀandꢀreturnꢀtoꢀreadꢀarrayꢀ

mode.

Table 4-1. CFI mode: Identiﬁcation Data Values

(Allꢀvaluesꢀinꢀtheseꢀtablesꢀareꢀinꢀhexadecimal)

Address (h)

Description

Data (h)

(Word Mode) (Byte Mode)

10

11

12

13

14

15

16

17

18

19

1A

20

22

24

26

28

2A

2C

2E

30

32

34

0051

0052

0059

0002

0000

0040

0000

Query-uniqueꢀASCIIꢀstringꢀ"QRY"

PrimaryꢀvendorꢀcommandꢀsetꢀandꢀcontrolꢀinterfaceꢀIDꢀcode

Addressꢀforꢀprimaryꢀalgorithmꢀextendedꢀqueryꢀtableꢀ

AlternateꢀvendorꢀcommandꢀsetꢀandꢀcontrolꢀinterfaceꢀIDꢀcode

Addressꢀforꢀalternateꢀalgorithmꢀextendedꢀqueryꢀtableꢀ

Table 4-2. CFI mode: System Interface Data Values

Address (h)

Description

Data (h)

(Word Mode) (Byte Mode)

Vccꢀsupplyꢀminimumꢀprogram/eraseꢀvoltage

Vccꢀsupplyꢀmaximumꢀprogram/eraseꢀvoltage

VPPꢀsupplyꢀminimumꢀprogram/eraseꢀvoltage

VPPꢀsupplyꢀmaximumꢀprogram/eraseꢀvoltage

Typicalꢀtimeoutꢀperꢀsingleꢀword/byteꢀwrite,ꢀ2ⁿꢀus

Typicalꢀtimeoutꢀforꢀmaximum-sizeꢀbufferꢀwrite,ꢀ2ⁿꢀusꢀ(00h,ꢀnotꢀ

1B

1C

1D

1E

1F

36

38

3A

3C

3E

0027

0036

0000

0003

20

40

0006

support)

Typicalꢀtimeoutꢀperꢀindividualꢀblockꢀerase,ꢀ2ⁿꢀms

Typicalꢀtimeoutꢀforꢀfullꢀchipꢀerase,ꢀ2ⁿꢀmsꢀ(00h,ꢀnotꢀsupport)

Maximumꢀtimeoutꢀforꢀword/byteꢀwrite,ꢀ2^nꢀꢀtimesꢀtypical

Maximumꢀtimeoutꢀforꢀbufferꢀwrite,ꢀ2^nꢀꢀtimesꢀtypical

Maximumꢀtimeoutꢀperꢀindividualꢀblockꢀerase,ꢀ2^nꢀꢀtimesꢀtypical

Maximumꢀtimeoutꢀforꢀchipꢀerase,ꢀ2^nꢀꢀtimesꢀtypicalꢀ(00h,ꢀnotꢀ

21

22

23

24

25

42

44

46

48

4A

0009

0013

0003

0005

0003

26

4C

0002

support)

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Table 4-3. CFI mode: Device Geometry Data Values

Address (h)

Description

Data (h)

(Word Mode) (Byte Mode)

0019/

0018

Deviceꢀsizeꢀ=ꢀ2ⁿꢀinꢀnumberꢀofꢀbytesꢀ(19=256Mb,ꢀ18=128Mb)

Flashꢀdeviceꢀinterfaceꢀdescriptionꢀ(02=asynchronousꢀx8/x16)

27

28

4E

50

52

54

56

58

0002

0000

0006

0000

0001

00xx

29

2A

2B

2C

Maximumꢀnumberꢀofꢀbytesꢀinꢀbufferꢀwriteꢀ=ꢀ2^nꢀ(00h,ꢀnotꢀsupport)

Numberꢀofꢀeraseꢀregionsꢀwithinꢀdeviceꢀ(01h:uniform,ꢀ02h:boot)

IndexꢀforꢀEraseꢀBankꢀAreaꢀ1:

2D

2E

2F

5A

5C

5E

[2E,2D]ꢀ=ꢀ#ꢀofꢀsame-sizeꢀsectorsꢀinꢀregionꢀ1-1

[30,ꢀ2F]ꢀ=ꢀsectorꢀsizeꢀinꢀmultiplesꢀofꢀ256Byte

256Mb=00FF,ꢀ0000,ꢀ0000,ꢀ0002

0000

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

60

62

64

66

68

6A

6C

6E

70

72

74

76

78

0002

0000

128Mb=007F,ꢀ0000,ꢀ0000,ꢀ0002

IndexꢀforꢀEraseꢀBankꢀAreaꢀ2

IndexꢀforꢀEraseꢀBankꢀAreaꢀ3

IndexꢀforꢀEraseꢀBankꢀAreaꢀ4

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Table 4-4. CFI mode: Primary Vendor-Speciﬁc Extended Query Data Values

Address (h)

Description

Data (h)

(Word Mode) (Byte Mode)

40

41

42

43

44

45

46

47

48

49

4A

4B

80

82

84

86

88

8A

8C

8E

90

92

94

96

0050

0052

0049

0031

0033

0014

0002

0001

0000

0008

0000

Queryꢀ-ꢀPrimaryꢀextendedꢀtable,ꢀuniqueꢀASCIIꢀstring,ꢀPRI

Majorꢀversionꢀnumber,ꢀASCII

Minorꢀversionꢀnumber,ꢀASCII

Unlockꢀrecognizesꢀaddressꢀ(0=ꢀrecognize,ꢀ1=ꢀdon'tꢀrecognize)

Eraseꢀsuspendꢀ(2=ꢀtoꢀbothꢀreadꢀandꢀprogram)

Sectorꢀprotectꢀ(N=ꢀ#ꢀofꢀsectors/group)

Temporaryꢀsectorꢀunprotectꢀ(1=supported)

Sectorꢀprotect/Chipꢀunprotectꢀscheme

SimultaneousꢀR/Wꢀoperationꢀ(0=notꢀsupported)

Burstꢀmodeꢀ(0=notꢀsupported)

Pageꢀmodeꢀ(0=notꢀsupported,ꢀ01ꢀ=ꢀ4ꢀwordꢀpage,ꢀ02ꢀ=ꢀ8ꢀwordꢀ

page)

4C

98

0002

MinimumꢀACC(acceleration)ꢀsupplyꢀ(0=ꢀnotꢀsupported),ꢀ[D7:D4]ꢀ

forꢀvolt,ꢀ[D3:D0]ꢀforꢀ100mV

MaximumꢀACC(acceleration)ꢀsupplyꢀ(0=ꢀnotꢀsupported),ꢀ[D7:D4]ꢀ

forꢀvolt,ꢀ[D3:D0]ꢀforꢀ100mV

4D

9A

0095

00A5

4E

9C

WP#ꢀProtection

04=UniformꢀsectorsꢀbottomꢀWP#ꢀprotect

05=UniformꢀsectorsꢀtopꢀWP#ꢀprotect

0004/

0005

4F

50

9E

A0

ProgramꢀSuspendꢀ(0=notꢀsupport,ꢀ1=support)

0001

P/N:PM1484

REV. 0.02, MAR. 06, 2009

38

MX29GA256/257E H/L

MX29GA128/129E H/L

ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM STRESS RATINGS

SurroundingꢀTemperatureꢀwithꢀBias

StorageꢀTemperature

VCCꢀꢀ

-65°Cꢀtoꢀ+125°C

-65°Cꢀtoꢀ+150°C

-0.5Vꢀtoꢀ+4.0ꢀV

VI/O

-0.5Vꢀtoꢀ+4.0ꢀV

VoltageꢀRange

A9,ꢀWP#/ACC

Theꢀotherꢀpins.

OutputꢀShortꢀCircuitꢀCurrentꢀ(lessꢀthanꢀoneꢀsecond)

-0.5Vꢀtoꢀ+10.5ꢀV

-0.5VꢀtoꢀVccꢀ+0.5V

200ꢀmA

OPERATING TEMPERATURE AND VOLTAGE

A

Commercial (C) Grade

SurroundingꢀTemperatureꢀ(T )

0°Cꢀtoꢀ+70°C

-40°Cꢀtoꢀ+85°C

+2.7ꢀVꢀtoꢀ3.6ꢀV

A

Industrial (I) Grade

SurroundingꢀTemperatureꢀ(T )

range

VCC

Supply Voltages

VCC

VI/Oꢀ

P/N:PM1484

REV. 0.02, MAR. 06, 2009

39

MX29GA256/257E H/L

MX29GA128/129E H/L

DC CHARACTERISTICS

Symbol Description

Min

Typ

Max

Remark

Iilk

Iilk9

Iolk

InputꢀLeak

A9ꢀLeak

±2.0uA

35uAꢀ

A9=10.5V

OutputꢀLeak

±1.0uA

CE#=Vil,ꢀOE#=Vih,ꢀ

Vcc=Vccmax;ꢀ

f=1MHz,ꢀByteꢀMode

CE#=Vil,ꢀOE#=Vih,ꢀ

Vcc=Vccmax;ꢀ

6mA

20mA

50mA

lcr1

ReadꢀCurrent

30mA

f=5MHz,ꢀByteꢀMode

CE#=Vil,ꢀOE#=Vih,ꢀ

60mA

0.2mA

26mA

100mA Vcc=Vccmax;ꢀ

f=10MHz

10mA

Iio

V_IOꢀnon-activeꢀcurrent

CE#=Vil,ꢀOE#=Vih,

WE#=Vil

Icw

WriteꢀCurrent

30mA

Vcc=Vccꢀmax,ꢀotherꢀ

pinꢀdisable

Isb

StandbyꢀCurrent

ResetꢀCurrent

ꢀ30uA

30uA

100uA

Vcc=Vccmax,ꢀ

100uA RESET#ꢀenable,ꢀ

otherꢀpinꢀdisable

Isbr

Isbs

Idpd

SleepꢀModeꢀCurrent

30uA

10uA

100uA

Vccꢀdeepꢀpowerꢀdownꢀcurrent

AcceleratedꢀPgmꢀCurrent,ꢀWP#/Accꢀ

pin(Word/Byte)

AcceleratedꢀPgmꢀCurrent,ꢀVccꢀpin,ꢀ

(Word/Byte)

Icp1

Icp2

5mA

10mA

30mA

CE#=Vil,ꢀOE#=Vih

20mA

Vil

InputꢀLowꢀVoltage

-0.1V

0.3xVI/O

Vih

InputꢀHighꢀVoltage

0.7xVI/O

VI/O+0.3V

VeryꢀHighꢀVoltageꢀforꢀhardwareꢀAutoꢀ

Select/AcceleratedꢀProgram

OutputꢀLowꢀVoltage

Vhv

9.5V

10.5V

0.45V

Vol

Iol=100uA

Voh1

Voh2

Vlko

OuputꢀHighꢀVoltage

0.85xVI/O

VI/O-0.4V

2.3V

Ioh1=-100uA

Ioh2=-100uA

OuputꢀHighꢀVoltage

LowꢀVccꢀLock-outꢀvoltage

2.5V

P/N:PM1484

REV. 0.02, MAR. 06, 2009

40

MX29GA256/257E H/L

MX29GA128/129E H/L

SWITCHING TEST CIRCUITS

3.3V

2.7KΩ

DEVICE UNDER

TEST

CL

6.2KΩ

TestꢀConditionꢀ

OutputꢀLoadꢀCapacitance,ꢀCLꢀ:ꢀ1TTLꢀgate,ꢀ30pF(90ns)

Rise/FallꢀTimesꢀ:ꢀ5ns

I/O

Inputꢀpulseꢀlevelsꢀ:ꢀ0.0ꢀ~ꢀV

I/O

In/Outꢀreferenceꢀlevelsꢀ:ꢀV / 2

SWITCHING TEST WAVEFORMS

VI/O

VI/O / 2

Test Points

0.0V

INPUT

OUTPUT

P/N:PM1484

REV. 0.02, MAR. 06, 2009

41

MX29GA256/257E H/L

MX29GA128/129E H/L

AC CHARACTERISTICS-(1)

Symbol Description

29GL256/257E

(VCC=2.7V~3.6V)

29GL256/257E

(VCC=3.0V~3.6V)

Unit

Min. Typ. Max. Min. Typ. Max.

100

25

90

25

90

25

40

ns

Taa

Validꢀdataꢀoutputꢀafterꢀaddressꢀ

Tpa Pageꢀaccessꢀtime

100

25

Tce

Toe

Tdf

ValidꢀdataꢀoutputꢀafterꢀCE#ꢀlow

ValidꢀdataꢀoutputꢀafterꢀOE#ꢀlow

40

DataꢀoutputꢀﬂoatingꢀafterꢀOE#ꢀhigh

Outputꢀholdꢀtimeꢀfromꢀtheꢀearliestꢀrisingꢀedgeꢀofꢀ

address,CE#,ꢀOE#

Toh

Trc

0

ns

100

0

90

0

ns

us

ns

Readꢀperiodꢀtime

Twc Writeꢀperiodꢀtime

Tcwc Commandꢀwriteꢀperiodꢀtime

Tas

Tah

Tds

Addressꢀsetupꢀtime

Addressꢀholdꢀtime

Dataꢀsetupꢀtime

45

30

0

45

30

0

Tdh Dataꢀholdꢀtime

Tvcs Vccꢀsetupꢀtime

500

0

500

0

Tcs

Tch

ChipꢀenableꢀSetupꢀtime

Chipꢀenableꢀholdꢀtime

0

Toes Outputꢀenableꢀsetupꢀtime

0

Readꢀ

0

Toeh Outputꢀenableꢀholdꢀtimeꢀꢀꢀ

Toggleꢀ&ꢀData#ꢀ

Polling

10

ns

Tws WE#ꢀsetupꢀtime

Twh WE#ꢀholdꢀtime

0

ns

0

Tcepw CE#ꢀpulseꢀwidth

Tcepwh CE#ꢀpulseꢀwidthꢀhigh

Twp WE#ꢀpulseꢀwidth

Twph WE#ꢀpulseꢀwidthꢀhigh

35

30

35

30

35

30

35

30

Tbusy Program/EraseꢀactiveꢀtimeꢀbyꢀRY/BY#

Tghwl Readꢀrecoverꢀtimeꢀbeforeꢀwrite

Tghel Readꢀrecoverꢀtimeꢀbeforeꢀwrite

Twhwh1 Programꢀoperationꢀ(Byteꢀmode)

Twhwh1 Programꢀoperationꢀ(Wordꢀmode)

Twhwh1 Accꢀprogramꢀoperationꢀ(Word/Byte)

Twhwh2 Sectorꢀeraseꢀoperation

100

90

ns

us

sec

us

0

11

0.6

5

0.6

5

Tbal Sectorꢀaddꢀholdꢀtime

50

Trdp Releaseꢀfromꢀdeepꢀpowerꢀdownꢀmode

200

P/N:PM1484

REV. 0.02, MAR. 06, 2009

42

MX29GA256/257E H/L

MX29GA128/129E H/L

AC CHARACTERISTICS-(2)

Symbol Description

29GL128/129E

(VCC=2.7V~3.6V)

Unit

Min. Typ. Max.

90

25

90

25

40

ns

Taa

Validꢀdataꢀoutputꢀafterꢀaddressꢀ

Tpa Pageꢀaccessꢀtime

Tce

Toe

Tdf

ValidꢀdataꢀoutputꢀafterꢀCE#ꢀlow

ValidꢀdataꢀoutputꢀafterꢀOE#ꢀlow

DataꢀoutputꢀﬂoatingꢀafterꢀOE#ꢀhigh

Toh

Trc

Outputꢀholdꢀtimeꢀfromꢀtheꢀearliestꢀrisingꢀedgeꢀofꢀaddress,CE#,ꢀOE#

Readꢀperiodꢀtime

0

ns

90

0

ns

us

ns

Twc Writeꢀperiodꢀtime

Tcwc Commandꢀwriteꢀperiodꢀtime

Tas

Tah

Tds

Addressꢀsetupꢀtime

Addressꢀholdꢀtime

Dataꢀsetupꢀtime

45

30

0

Tdh Dataꢀholdꢀtime

Tvcs Vccꢀsetupꢀtime

500

0

Tcs

Tch

ChipꢀenableꢀSetupꢀtime

Chipꢀenableꢀholdꢀtime

0

Toes Outputꢀenableꢀsetupꢀtime

0

Readꢀ

0

Toeh Outputꢀenableꢀholdꢀtimeꢀꢀꢀ

Toggleꢀ&ꢀData#ꢀPolling

10

ns

Tws WE#ꢀsetupꢀtime

Twh WE#ꢀholdꢀtime

0

ns

0

Tcepw CE#ꢀpulseꢀwidth

Tcepwh CE#ꢀpulseꢀwidthꢀhigh

Twp WE#ꢀpulseꢀwidth

Twph WE#ꢀpulseꢀwidthꢀhigh

35

30

35

30

Tbusy Program/EraseꢀactiveꢀtimeꢀbyꢀRY/BY#

Tghwl Readꢀrecoverꢀtimeꢀbeforeꢀwrite

Tghel Readꢀrecoverꢀtimeꢀbeforeꢀwrite

Twhwh1 Programꢀoperationꢀ(Byteꢀmode)

Twhwh1 Programꢀoperationꢀ(Wordꢀmode)

Twhwh1 Accꢀprogramꢀoperationꢀ(Word/Byte)

Twhwh2 Sectorꢀeraseꢀoperation

90

ns

us

sec

us

0

11

0.6

5

Tbal Sectorꢀaddꢀholdꢀtime

50

Trdp Releaseꢀfromꢀdeepꢀpowerꢀdownꢀmode

200

P/N:PM1484

REV. 0.02, MAR. 06, 2009

43

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 1. COMMAND WRITE OPERATION

Tcwc

Vih

CE#

Vil

Tch

Tcs

Vih

WE#

Vil

Toes

Twph

Twp

Vih

Vil

OE#

Vih

Vil

Addresses

VA

Tah

Tas

Tdh

Tds

Vih

Vil

Data

DIN

VA: Valid Address

P/N:PM1484

REV. 0.02, MAR. 06, 2009

44

MX29GA256/257E H/L

MX29GA128/129E H/L

READ/RESET OPERATION

Figure 2. READ TIMING WAVEFORMS

Tce

Vih

CE#

Vil

Vih

WE#

Vil

Toeh

Tdf

Toe

Vih

OE#

Vil

Toh

Taa

Trc

Vih

ADD Valid

Addresses

Vil

HIGH Z

Voh

Vol

Outputs

DATA Valid

P/N:PM1484

REV. 0.02, MAR. 06, 2009

45

MX29GA256/257E H/L

MX29GA128/129E H/L

AC CHARACTERISTICS

Item Description

MIN/MAX Speed

Unit

us

Trp1 RESET#ꢀPulseꢀWidthꢀ(DuringꢀAutomaticꢀAlgorithms)

Trp2 RESET#ꢀPulseꢀWidthꢀ(NOTꢀDuringꢀAutomaticꢀAlgorithms)

MIN

MAX

10

500

200

0

ns

Trh

RESET#ꢀHighꢀTimeꢀBeforeꢀRead

ns

Trb1 RY/BY#ꢀRecoveryꢀTimeꢀ(toꢀCE#,ꢀOE#ꢀgoꢀlow)

ns

Trb2 RY/BY#ꢀRecoveryꢀTimeꢀ(toꢀWE#ꢀgoꢀlow)

50

ns

Tready1 RESET#ꢀPINꢀLowꢀ(DuringꢀAutomaticꢀAlgorithms)ꢀtoꢀReadꢀorꢀWriteꢀ

Tready2 RESET#ꢀPINꢀLowꢀ(NOTꢀDuringꢀAutomaticꢀAlgorithms)ꢀtoꢀReadꢀorꢀWriteꢀ

20

us

500

ns

Figure 3. RESET# TIMING WAVEFORM

Trb1

CE#, OE#

Trb2

WE#

Tready1

RY/BY#

RESET#

Trp1

Reset Timing during Automatic Algorithms

CE#, OE#

Trh

RY/BY#

RESET#

Trp2

Tready2

Reset Timing NOT during Automatic Algorithms

P/N:PM1484

REV. 0.02, MAR. 06, 2009

46

MX29GA256/257E H/L

MX29GA128/129E H/L

ERASE/PROGRAM OPERATION

Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM

CE#

Tch

Twhwh2

Twp

WE#

Twph

Tcs

Tghwl

OE#

Last 2 Erase Command Cycle

Read Status

Tah

Twc

Tas

VA

2AAh

VA

555h

Address

Tds

Tdh

In

Progress

Complete

55h

10h

Data

Tbusy

Trb

RY/BY#

P/N:PM1484

REV. 0.02, MAR. 06, 2009

47

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data# Polling Algorithm or

Toggle Bit Algorithm

NO

Data=FFh ?

YES

Auto Chip Erase Completed

P/N:PM1484

REV. 0.02, MAR. 06, 2009

48

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Read Status

CE#

Tch

Twhwh2

Twp

WE#

Twph

Tcs

Tghwl

OE#

Tbal

Last 2 Erase Command Cycle

Twc

Tas

Sector

VA

2AAh

Address

Address 0

Address 1

Address n

Tah

Tds Tdh

In

Progress

Complete

55h

30h

Data

Tbusy

Trb

RY/BY#

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49

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Last Sector

to Erase

YES

Data# Polling Algorithm or

Toggle Bit Algorithm

NO

Data=FFh

YES

Auto Sector Erase Completed

P/N:PM1484

REV. 0.02, MAR. 06, 2009

50

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 8. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

ERASE SUSPEND

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

ERASE RESUME

Continue Erase

Another

NO

Erase Suspend ?

YES

P/N:PM1484

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51

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS

CE#

Tch

Twhwh1

Twp

WE#

Tcs

Twph

Tghwl

OE#

Last 2 Program Command Cycle

Tas

Last 2 Read Status Cycle

VA

Tah

VA

555h

PA

Address

Tdh

Tds

Status

A0h

PD

DOUT

Data

Tbusy

Trb

RY/BY#

Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM

(9.5V ~ 10.5V)

Vhv

WP#/ACC

Vil or Vih

250nS

P/N:PM1484

REV. 0.02, MAR. 06, 2009

52

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM

WE#

CE#

OE#

Twhwh1 or Twhwh2

Tcepw

Tcepwh

Tghwl

Tah

Tas

VA

555h

PA

Address

Tdh

Tds

Status

A0h

PD

DOUT

Data

Tbusy

RY/BY#

P/N:PM1484

REV. 0.02, MAR. 06, 2009

53

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Data# Polling Algorithm or

Toggle Bit Algorithm

next address

No

Read Again Data:

Program Data?

YES

No

Last Word to be

Programed

YES

Auto Program Completed

P/N:PM1484

REV. 0.02, MAR. 06, 2009

54

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 13. SILICON ID READ TIMING WAVEFORM

VCC

3V

Vhv

Vih

Vil

ADD

A9

Vih

Vil

ADD

A0

Taa

Vih

Vil

A1

A2

Vih

Vil

Vih

Vil

ADD

Disable

Enable

CE#

Tce

Vih

Vil

WE#

Toe

Vih

Vil

OE#

Tdf

Toh

Vih

Vil

DATA

Q0-Q15

DATA OUT

Manufacturer ID

DATA OUT

Device ID

Cycle 1

Device ID

Cycle 2

Device ID

Cycle 3

P/N:PM1484

REV. 0.02, MAR. 06, 2009

55

MX29GA256/257E H/L

MX29GA128/129E H/L

WRITE OPERATION STATUS

Figure 14. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

Tce

CE#

Tch

WE#

Toe

OE#

Toeh

Tdf

Trc

VA

Address

Taa

Toh

High Z

Complement

Status Data

True

Valid Data

Q7

Q0-Q6

Status Data

Tbusy

RY/BY#

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REV. 0.02, MAR. 06, 2009

56

1.ꢀ

ꢀꢀꢀꢀ

Forꢀprogramming,ꢀvalidꢀaddressꢀmeansꢀprogramꢀaddress.

Forꢀerasing,ꢀvalidꢀaddressꢀmeansꢀeraseꢀsectorsꢀaddress.

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 15. DATA# POLLING ALGORITHM

Start

Read Q7~Q0 at valid address

(Note 1)

No

Q7 = Data# ?

Yes

No

Q5 = 1 ?

Yes

Read Q7~Q0 at valid address

No

Q7 = Data# ?

(Note 2)

Yes

FAIL

Pass

Notes:

2.ꢀQ7ꢀshouldꢀbeꢀrecheckedꢀevenꢀQ5="1"ꢀbecauseꢀQ7ꢀmayꢀchangeꢀsimultaneouslyꢀwithꢀQ5.

P/N:PM1484

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57

MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 16. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

Tce

CE#

Tch

WE#

OE#

Toe

Toeh

Tdf

Trc

VA

Address

Taa

Toh

Valid Status

(second read)

Valid Status

(first read)

Valid Data

Q6/Q2

(stops toggling)

Tbusy

RY/BY#

VA : Valid Address

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MX29GA256/257E H/L

MX29GA128/129E H/L

Figure 17. TOGGLE BIT ALGORITHM

Start

Read Q7-Q0 Twice

(Note 1)

NO

Q6 Toggle ?

YES

NO

Q5 = 1?

YES

Read Q7~Q0 Twice

NO

Q6 Toggle ?

YES

PGM/ERS fail

Write Reset CMD

PGM/ERS Complete

Notes:

1.ꢀReadꢀtoggleꢀbitꢀtwiceꢀtoꢀdetermineꢀwhetherꢀorꢀnotꢀitꢀisꢀtoggling.

2.ꢀRecheckꢀtoggleꢀbitꢀbecauseꢀitꢀmayꢀstopꢀtogglingꢀasꢀQ5ꢀchangesꢀtoꢀ"1".

P/N:PM1484

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59

MX29GA256/257E H/L

MX29GA128/129E H/L

AC CHARACTERISTICS

WORD/BYTE CONFIGURATION (BYTE#)

Test

Parameter Description

All Speed Options

Unit

Setup

Max.

Min.

Telﬂ/Telfh CE#ꢀtoꢀBYTE#ꢀfromꢀL/H

5

ns

Tﬂqz

BYTE#ꢀfromꢀLꢀtoꢀOutputꢀHiz

30

90

Tfhqv

BYTE#ꢀfromꢀHꢀtoꢀOutputꢀActive

Figure 18. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to

word mode)

CE#

OE#

Telfh

BYTE#

DOUT

(Q0-Q7)

DOUT

(Q0-Q14)

Q0~Q14

Q15/A-1

DOUT

(Q15)

VA

Tfhqv

Figure 19. PAGE READ TIMING WAVEFORM

Amax:A3

VALID ADD

2'nd ADD

3'rd ADD

tpa

(A-1),A0,A1,A2

1'st ADD

taa

tpa

DATA

Data 1

Data 2

Data 3

CE#/OE#

Note: CE#, OE# are enable.

Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode.

Address are A2~A0 for Word mode, A2~A-1 for Byte mode.

P/N:PM1484

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60

MX29GA256/257E H/L

MX29GA128/129E H/L

AC CHARACTERISTICS

ITEM

TPY

100us

10us

MAX

200us

20us

WEBꢀhighꢀtoꢀreleaseꢀfromꢀdeepꢀpowerꢀdownꢀmode

WEBꢀhighꢀtoꢀdeepꢀpowerꢀdownꢀmode

tRDP

tDP

Figure 20. DEEP POWER DOWN MODE WAVEFORM

CEB

WEB

tDP

tRDP

ADD

XX

55

2AA

XX (don't care)

DATA

AA

55

B9

AB

Standby mode

Deep power down mode

Figure 21. WRITE BUFFER PROGRAM FLOWCHART

Addr=555h

Write CMD: Data=AAh,

Write CMD: Data=55h,

Write CMD: Data=25h,

Addr=2AAh

Addr=SA

Write CMD: Data=29h,

Polling Status

Addr=SA

Write CMD: Data=PWC,

Yes

Pass

No

Write CMD:

Data=PGM_data, Add

Return to read Mode

r=PGM_addr

?

1

No

PWC=PWC-

Fail

Yes

Write a different sector

address to cause Abort

Yes

Want to Abort

No

Yes

Abort

Write Buffer

No

Yes

PWC =0?

No

ed page

SA: Sector Address of to be Programm

MD

Write Abort reset CMD

to return to read Mode

Write reset C

to return to read Mode

m Word Count

PWC: Progra

P/N:PM1484

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61

MX29GA256/257E H/L

MX29GA128/129E H/L

RECOMMENDED OPERATING CONDITIONS

At Device Power-Up

ACꢀtimingꢀillustratedꢀinꢀFigureꢀAꢀisꢀrecommendedꢀforꢀtheꢀsupplyꢀvoltagesꢀandꢀtheꢀcontrolꢀsignalsꢀatꢀdeviceꢀpower-

up.ꢀIfꢀtheꢀtimingꢀinꢀtheꢀﬁgureꢀisꢀignored,ꢀtheꢀdeviceꢀmayꢀnotꢀoperateꢀcorrectly.

Vcc(min)

Vcc

GND

Tvr

Tvcs

Tf

Tce

Tr

Vih

Vil

CE#

WE#

OE#

Vih

Vil

Tf

Toe

Tr

Vih

Vil

Taa

Tr or Tf

Vih

Vil

Valid

Address

ADDRESS

Voh

Vol

High Z

Valid

DATA

Ouput

Vih

Vil

WP#/ACC

Figure A. AC Timing at Device Power-Up

Symbol

Parameter

VccꢀRiseꢀTime

InputꢀSignalꢀRiseꢀTime

InputꢀSignalꢀFallꢀTime

VccꢀSetupꢀTime

Min.

20

Max.

500000

20

Unit

us/V

us

Tvr

Tr

Tf

20

Tvcs

200

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MX29GA128/129E H/L

ERASE AND PROGRAMMING PERFORMANCE

LIMITS

TYP. (1)

PARAMETER

UNITS

MIN.

MAX. (2)

256Mb

128Mb

128

300

sec

ChipꢀEraseꢀTime

64

150

5

sec

SectorꢀEraseꢀTime

0.6

256Mb

128Mb

100

350

sec

ChipꢀProgrammingꢀTimeꢀ

50

180

sec

us

WordꢀProgramꢀTime

11

360

TotalꢀWriteꢀBufferꢀTime

ACCꢀTotalꢀWriteꢀBufferꢀTime

Erase/ProgramꢀCycles

200

100

us

100,000

Cycles

Notes:

1.ꢀ Typicalꢀprogramꢀandꢀeraseꢀtimesꢀassumeꢀtheꢀfollowingꢀconditions:ꢀ25°C,ꢀ3.0VꢀVCC.ꢀProgrammingꢀspeciﬁca-

tionsꢀassumeꢀcheckboardꢀdataꢀpattern.

2.ꢀꢀMaximumꢀvaluesꢀareꢀmeasuredꢀatꢀVCCꢀ=ꢀ3.0ꢀV,ꢀworstꢀcaseꢀtemperature.ꢀMaximumꢀvaluesꢀareꢀvalidꢀupꢀtoꢀandꢀ

includingꢀ100,000ꢀprogram/eraseꢀcycles.

3.ꢀꢀErase/ProgramꢀcyclesꢀcomplyꢀwithꢀJEDECꢀJESD-47Eꢀ&ꢀA117Aꢀstandard.

4.ꢀꢀExcludeꢀ00hꢀprogramꢀbeforeꢀeraseꢀoperation.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

10.5V

InputꢀVoltageꢀvoltageꢀdifferenceꢀwithꢀGNDꢀonꢀWP#/ACC,ꢀA9

InputꢀVoltageꢀvoltageꢀdifferenceꢀwithꢀGNDꢀonꢀallꢀnormalꢀpinsꢀinputꢀ

VccꢀCurrent

-1.0V

1.5Vcc

+100mA

-100mA

AllꢀpinsꢀincludedꢀexceptꢀVcc.ꢀꢀTestꢀconditions:ꢀVccꢀ=ꢀ3.0V,ꢀoneꢀpinꢀperꢀtesting

TSOP PIN CAPACITANCE

Parameter Symbol

Parameter Description

ControlꢀPinꢀCapacitance

OutputꢀCapacitance

InputꢀCapacitance

Test Set

VIN=0

TYP

7.5

8.5

6

MAX

UNIT

pF

CIN2

COUT

CIN

9

VOUT=0

VIN=0

12

7.5

pF

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MX29GA128/129E H/L

ORDERING INFORMATION

Please contact Macronix sales for specific information regarding 64-LFBGA/64-FBGA ordering

information.

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MX29GA256/257E H/L

MX29GA128/129E H/L

PART NAME DESCRIPTION

Please contact Macronix sales for specific information regarding 64-LFBGA/64-FBGA part name

description.

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MX29GA256/257E H/L

MX29GA128/129E H/L

PACKAGE INFORMATION

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MX29GA128/129E H/L

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MX29GA128/129E H/L

REVISION HISTORY

Revision No. Description

Page

Allꢀ

Date

MAR/02/2009

0.01ꢀ

1.ꢀAddedꢀMX29GA257E/129Eꢀinformationꢀ

ꢀ

2.ꢀAddedꢀ"AdvanceꢀSectorꢀProtection"ꢀinformationꢀ

3.ꢀRemovedꢀ"SectorꢀGroupꢀProtect/Unprotectd"ꢀinformation

4.ꢀModiﬁedꢀCFIꢀdataꢀatꢀaddressꢀ21~26ꢀ(Wordꢀmode)ꢀ

5.ꢀModiﬁedꢀtheꢀchipꢀeraseꢀtimeꢀfromꢀ100s/256Mb,ꢀ50s/128Mbꢀtoꢀ

ꢀꢀꢀꢀ128s/256Mb,ꢀ64s/128Mb

P69~77

P38

P65

6.ꢀAddedꢀtheꢀVCCꢀrangeꢀdescriptionꢀofꢀMX29GA256/257Eꢀ

P2,44,66,67

0.02ꢀ

ꢀ

1.ꢀChangedꢀtitleꢀfromꢀ"AdvancedꢀInformation"ꢀtoꢀ"Preliminary"ꢀ

2.ꢀRemovedꢀ64Mbꢀinformationꢀꢀ

3.ꢀAddedꢀ64-CSPꢀDimensionsꢀ"11x13x1.4mm,ꢀP:1.0mm,ꢀB:0.55mm"ꢀꢀP3,64,65

P2ꢀ

All

MAR/06/2009

P67

4.ꢀModiﬁedꢀcontentꢀerror

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MX29GA256/257E H/L

MX29GA128/129E H/L

Macronix'sꢀproductsꢀareꢀnotꢀdesigned,ꢀmanufactured,ꢀorꢀintendedꢀforꢀuseꢀforꢀanyꢀhighꢀriskꢀapplicationsꢀinꢀwhichꢀ

theꢀfailureꢀofꢀaꢀsingleꢀcomponentꢀcouldꢀcauseꢀdeath,ꢀpersonalꢀinjury,ꢀsevereꢀphysicalꢀdamage,ꢀorꢀotherꢀsubstan-

tialꢀharmꢀtoꢀpersonsꢀorꢀproperty,ꢀsuchꢀasꢀlife-supportꢀsystems,ꢀhighꢀtemperatureꢀautomotive,ꢀmedical,ꢀaircraftꢀ

andꢀmilitaryꢀapplication.ꢀMacronixꢀandꢀitsꢀsuppliersꢀwillꢀnotꢀbeꢀliableꢀtoꢀyouꢀand/orꢀanyꢀthirdꢀpartyꢀforꢀanyꢀclaims,ꢀ

injuriesꢀorꢀdamagesꢀthatꢀmayꢀbeꢀincurredꢀdueꢀtoꢀuseꢀofꢀMacronix'sꢀproductsꢀinꢀtheꢀprohibitedꢀapplications.

Logo,ꢀꢀareꢀtrademarksꢀorꢀregisteredꢀtrademarksꢀofꢀMacronixꢀInternationalꢀCo.,ꢀLtd..ꢀꢀTheꢀnamesꢀandꢀbrandsꢀ

ofꢀotherꢀcompaniesꢀareꢀforꢀidentiﬁcationꢀpurposesꢀonlyꢀandꢀmayꢀbeꢀclaimedꢀasꢀtheꢀpropertyꢀofꢀtheꢀrespectiveꢀ

companies.

ACRONIX NTERNATIONAL O., TD.

M

I

C L

Macronix Ofﬁces : Japan

Macronix Asia Limited.

Macronix Ofﬁces : Taiwan

Headquarters, FAB2

Macronix, International Co., Ltd.

16, Li-Hsin Road, Science Park, Hsinchu,

Taiwan, R.O.C.

NKF Bldg. 5F, 1-2 Higashida-cho,

Kawasaki-ku Kawasaki-shi,

Kanagawa Pref. 210-0005, Japan

Tel: +81-44-246-9100

Tel: +886-3-5786688

Fax: +81-44-246-9105

Fax: +886-3-5632888

Taipei Ofﬁce

Macronix Ofﬁces : Korea

Macronix Asia Limited.

#906, 9F, Kangnam Bldg., 1321-4, Seocho-Dong, Seocho-Ku,

135-070, Seoul, Korea

Tel: +82-02-588-6887

Fax: +82-02-588-6828

Macronix, International Co., Ltd.

19F, 4, Min-Chuan E. Road, Sec. 3, Taipei,

Taiwan, R.O.C.

Tel: +886-2-2509-3300

Fax: +886-2-2509-2200

Macronix Ofﬁces : China

Macronix Ofﬁces : Singapore

Macronix Pte. Ltd.

1 Marine Parade Central, #11-03 Parkway Centre,

Macronix (Hong Kong) Co., Limited.

702-703, 7/F, Building 9, Hong Kong Science Park,

5 Science Park West Avenue, Sha Tin,

N.T.

Tel: +86-852-2607-4289

Fax: +86-852-2607-4229

Singapore 449408

Tel: +65-6346-5505

Fax: +65-6348-8096

Macronix Ofﬁces : Europe

Macronix Europe N.V.

Koningin Astridlaan 59, Bus 1 1780

Macronix (Hong Kong) Co., Limited,

SuZhou Ofﬁce

No.5, XingHai Rd, SuZhou Industrial Park,

SuZhou China 215021

Tel: +86-512-62580888 Ext: 3300

Fax: +86-512-62586799

Wemmel Belgium

Tel: +32-2-456-8020

Fax: +32-2-456-8021

Macronix Ofﬁces : USA

Macronix (Hong Kong) Co., Limited,

Shenzhen Ofﬁce

Room 1401 & 1404, Blcok A, TianAN Hi-Tech PLAZA Tower,

Che Gong Miao, FutianDistrict, Shenzhen PRC 518040

Tel: +86-755-83433579

Macronix America, Inc.

680 North McCarthy Blvd. Milpitas, CA 95035,

U.S.A.

Tel: +1-408-262-8887

Fax: +1-408-262-8810

Fax: +86-755-83438078

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and speciﬁcations without notice.

69


型号：	MX29GA129E
厂家：	MACRONIX INTERNATIONAL
描述：	SINGLE VOLTAGE 3V ONLY FLASH MEMORY 单电压3V仅限于Flash存储器存储
文件：	总69页 (文件大小：2216K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29GA129E [Macronix]

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