MX29L1611G-10 [Macronix]
Flash, 1MX16, 100ns, PDIP42;
| 型号： | MX29L1611G-10 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 1MX16, 100ns, PDIP42 光电二极管 内存集成电路 |
| 文件： | 总33页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCED INFORMATION
MX29L1611G
16M-BIT[2Mx8/1Mx16]CMOS
SINGLEVOLTAGEFLASHEEPROM
FEATURES
• 3.3V ±10% for write and read operation
• 11VVpperase/programmingoperation
• Endurance: 100 cycles
• Low VCC write inhibit is equal to or less than 1.8V
• Softwaredataprotection
• Pageprogramoperation
• Fast random access time: 100ns/120ns
• Sectorerasearchitecture
- Internal address and data latches for 64 words per
page
- 32 equal sectors of 64k bytes each
- Sector erase time: 200ms typical
• Auto Erase and Auto Program Algorithms
- Automatically erases any one of the sectors or the
wholechip
- Page programming time: 5ms typical
• Lowpowerdissipation
- 50mA active current
- 20uA standby current
• Two independently Protected sectors
• Package type
-Automaticallyprogramsandverifiesdataatspecified
addresses
- 42 pin plastic DIP
• Status Register feature for detection of program or
erase cycle completion
GENERAL DESCRIPTION
The MX29L1611G is a 16-mega bit Flash memory
organized as either 1M wordx16 or 2M bytex8. The
MX29L1611Gincludes32sectorsof64KB(65,536Bytes
or32,768words). MXIC'sFlashmemoriesofferthemost
cost-effectiveandreliableread/writenon-volatilerandom
access memory. The MX29L1611G is packaged in 42
pin PDIP.
MX29L1611G does require high input voltages for
programming. Commandsrequire11V input to determine
the operation of the device. Reading data out of the
device is similar to reading from an EPROM.
MXICFlashtechnologyreliablystoresmemorycontents
even after 100 cycles. The MXIC's cell is designed to
optimize the erase and programming mechanisms. In
addition, the combination of advanced tunnel oxide
processing and low internal electric fields for erase and
programmingoperationsproducesreliablecycling. The
MX29L1611G uses a 11V Vpp supply to perform the
Auto Erase and Auto Program algorithms.
The standard MX29L1611G offers access times as fast
as 100ns,allowing operation of high-speed
microprocessorswithoutwait. Toeliminatebuscontention,
the MX29L1611G has separate chip enable CE and,
outputenable(OE).
MXIC's Flash memories augment EPROM functionality
with electrical erasure and programming. The
MX29L1611G uses a command register to manage this
functionality.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up
protection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC +1V.
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MX29L1611G
PIN DESCRIPTION
PIN CONFIGURATIONS
SYMBOL
A0 - A19
Q0 - Q14
Q15/A-1
PIN NAME
42 PDIP
Address Input
1
2
3
4
5
6
7
8
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
A19
A8
A9
A18
A17
A7
A6
A5
A4
A3
A2
A1
DataInput/Output
A10
A11
A12
A13
A14
A15
A16
BYTE/VPP
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
Q15(Word mode)/LSB addr.(Byte
mode, for read mode only)
Chip Enable Input
CE
OE
9
Output Enable Input
10
11
12
13
14
15
16
17
18
19
20
21
A0
CE
GND
OE
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
BYTE/VPP Word/Byte Selection Input, Erase/
Programsupplyvoltage
VCC
GND
PowerSupply
GroundPin
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MX29L1611G
BLOCK DIAGRAM
WRITE
STATE
CONTROL
INPUT
PROGRAM/ERASE
HIGH VOLTAGE
CE
OE
MACHINE
(WSM)
LOGIC
BYTE / VPP
COMMAND
INTERFACE
REGISTER
(CIR)
MX29L1611G
FLASH
ADDRESS
LATCH
ARRAY
Q15/A-1
A0-A19
ARRAY
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
Y-select
PROGRAM
DATA LATCH
Q0-Q15/A-1
I/O BUFFER
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MX29L1611G
Table1.PINDESCRIPTIONS
SYMBOL
A0 - A19
TYPE
NAMEANDFUNCTION
INPUT
ADDRESSINPUTS:formemoryaddresses. Addressesareinternallylatched
during a write cycle.
Q0 - Q7
INPUT/OUTPUT
INPUT/OUTPUT
LOW-BYTEDATABUS:InputdataandcommandsduringCommandInterface
Register(CIR) write cycles. Outputs array,status and identifier data in the
appropriatereadmode. Floatedwhenthechipisde-selectedortheoutputsare
disabled.
Q8 - Q14
HIGH-BYTE DATA BUS: Inputs data during x 16 Data-Write operations.
Outputsarray, identifierdataintheappropriatereadmode;notusedforstatus
registerreads. Floatedwhenthechipisde-selectedortheoutputsaredisabled
Selects between high-byte data INPUT/OUTPUT(BYTE = HIGH) and LSB
ADDRESS(BYTE = LOW) for raed operation.
Q15/A -1
CE
INPUT/OUTPUT
INPUT
CHIP ENABLE INPUTS: Activate the device's control logic, Input buffers,
decoders and sense amplifiers. With CE high, the device is deselected and
power consumption reduces to Standby level upon completion of any current
program or erase operations. CE must be low to select the device.
OUTPUTENABLES:Gatesthedevice'sdatathroughtheoutputbuffersduring
a read cycle OE is active low.
OE
INPUT
BYTE/VPP INPUT
BYTE ENABLE: While operating read mode, BYTE Low places device in x8
mode. All data is then input or output on Q0-7 and Q8-14 float. AddressQ15/
A-1selectsbetweenthehighandlowbyte. Whileoperatingreadmode,BYTE
high places the device in x16 mode, and turns off the Q15/A-1 input buffer.
Address A0, then becomes the lowest order address.
ERASE/PROGRAMENABLE:WhenBYTE/VPP=11Vwouldplacethisdevice
into ERASE/PROGRAM mode.
VCC
GND
DEVICE POWER SUPPLY(3.3V ±10%)
GROUND
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MX29L1611G
BUS OPERATION
Flash memory reads, erases and writes in-system via the local CPU . All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
Table 2.1 Bus Operations for Word-Wide Mode (BYTE/VPP = VIH)
Mode
Notes
1
CE
OE BYTE/VPP A0
A1
X
A9
X
Q0-Q7 Q8-Q14 Q15/A-1
DOUT DOUT DOUT
Read
VIL
VIL
VIH
VIL
VIL
VIL
VIL VIH
VIH VIH
X
OutputDisable
Standby
1
X
X
X
High Z High Z HighZ
High Z HIgh Z HighZ
1
X
H/L
X
X
X
ManufacturerID
Device ID
Write
2,4
2,4
1,3,5
VIL VIH
VIL VIH
VIH VPP
VIL
VIL VID
C2H
F6H
DIN
00H
00H
DIN
0B
VIH VIL VID
0B
X
X
X
DIN
Table2.2 Bus Operations for Byte-Wide Mode (BYTE = VIL)
Mode
Notes
1
CE
OE BYTE/VPP A0
A1
X
A9
X
Q0-Q7 Q8-Q14 Q15/A-1
Read
VIL
VIL
VIH
VIL
VIL
VIL
VIL VIL
VIH VIL
X
X
X
DOUT
HighZ
VIL/VIH
OutputDisable
Standby
1
X
X
High Z High Z
High Z HIgh Z
X
X
1
X
H/L
X
X
ManufacturerID
Device ID
Write
2,4
2,4
1,3,5
VIL VIL
VIL VIL
VIH VPP
VIL VIL VID
VIH VIL VID
C2H
F6H
DIN
High Z VIL
High Z VIL
DIN DIN
X
X
X
NOTES :
1. X can be VIH or VIL for address or control pins.
2. A0 and A1 at VIL provide manufacturer ID codes. A0 at VIH and A1 at VIL provide device ID codes. A0 at VIL, A1 at VIH and
with appropriate sector addresses provide Sector Protect Code.(Refer to Table 4),A2~A19=Do not care.
3. Commands for different Erase operations, Data program operations or Sector Protect operations can only be successfully
completed through proper command sequence.
4. VID = 11.5V- 12.5V
5.Word mode only for write operation VPP=10.5V~11.5V
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MX29L1611G
WRITE OPERATIONS
Commands are written to the COMMAND INTERFACE
REGISTER (CIR) using standard microprocessor write
timings. The CIR serves as the interface between the
microprocessorandtheinternalchipoperation. TheCIR
can decipher Read Array, Read Silicon ID, Erase and
Programcommand. Intheeventofareadcommand,the
CIR simply points the read path at either the array or the
silicon ID, depending on the specific read command
given. Foraprogramorerasecycle,theCIRinformsthe
write state machine that a program or erase has been
requested. During a program cycle, the write state
machinewillcontroltheprogramsequencesandtheCIR
will only respond to status reads. During a sector/chip
erase cycle, the CIR will respond to status reads. After
the write state machine has completed its task, it will
allowtheCIRtorespondtoitsfullcommandset. TheCIR
staysatreadstatusregistermodeuntilthemicroprocessor
issues another valid command sequence.
Deviceoperationsareselectedbywritingcommandsinto
the CIR. Table 3 below defines 16 Mbit flash family
command.
TABLE3. COMMANDDEFINITIONS(BYTE/VPP=VHH)
Command
Sequence
Bus Write
Read/
Reset
4
Silicon
ID Read
4
Page
Program
4
Chip
Erase
6
Sector
Erase
6
Read
Clear
Status Reg.
4
Status Reg.
3
Cycles Req'd
First Bus
Addr
Data
Addr
Data
Addr
Data
Addr
5555H
AAH
5555H
AAH
5555H
AAH
5555H
AAH
5555H
AAH
5555H
AAH
2AAAH
55H
5555H
AAH
Write Cycle
Second Bus
Write Cycle
Third Bus
2AAAH 2AAAH
2AAAH
55H
2AAAH 2AAAH
2AAAH
55H
55H
5555H
F0H
RA
55H
55H
55H
5555H
90H
5555H
A0H
5555H
80H
5555H
80H
5555H
70H
5555H
50H
Write Cycle
Fourth Bus
00H/01H PA
C2H/F6H PD
5555H
AAH
5555H
AAH
X
Read/Write Cycle Data
RD
SRD
Fifth Bus
Addr
Data
Addr
Data
2AAAH 2AAAH
Write Cycle
Sixth Bus
Write Cycle
55H
55H
SA
5555H
10H
30H
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MX29L1611G
TABLE 3. COMMAND DEFINITIONS
Command
Sequence
Sector
Protection
6
Sector
Unprotect
6
Verify Sector
Abort
3
Protect
4
Bus Write
Cycles Req'd
First Bus
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
5555H
AAH
5555H
AAH
5555H
AAH
5555H
AAH
Write Cycle
Second Bus
Write Cycle
Third Bus
2AAAH
55H
2AAAH
55H
2AAAH
55H
2AAAH
55H
5555H
60H
5555H
60H
5555H
90H
5555H
E0H
Write Cycle
Fourth Bus
Read/Write Cycle
Fifth Bus
5555H
AAH
5555H
AAH
SA**
C2H*
2AAAH
55H
2AAAH
55H
Write Cycle
Sixth Bus
SA**
SA**
Write Cycle
20H
40H
Notes:
1. Address bit A15 -- A19 = X = Don't care for all address commands except for Program Address(PA) and Sector Address(SA).
5555H and 2AAAH address command codes stand for Hex number starting from A0 to A14.
2. Bus operations are defined in Table 2.
3. RA = Address of the memory location to be read.
PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the CE pulse.
SA = Address of the sector to be erased. The combination of A15 -- A19 will uniquely select any sector.
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the rising edge of CE.
SRD = Data read from status register.
5. Only Q0-Q7 command data is taken, Q8-Q15 = Don't care.
* Refer to Table 4, Figure 11.
** Only the top and the bottom sectors have protect- bit feature. SA = (A19,A18,A17,A16,A15) = 00000B or 11111B is valid.
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MX29L1611G
DEVICE OPERATION
SILICON ID READ
Themanufactureranddevicecodesmayalsobereadvia
the command register, for instances when the
MX29L1611G is erased or programmed in a system
without access to high voltage on the A9 pin. The
command sequence is illustrated in Table 3.
The Silicon ID Read mode allows the reading out of a
binary code from the device and will identify its
manufacturerandtype. Thismodeisintendedforuseby
programmingequipmentforthepurposeofautomatically
matching the device to be programmed with its
corresponding programming algorithm. This mode is
functional over the entire temperature range of the
device.
Byte 0 (A0=VIL) represents the manfacturer's code
(MXIC=C2H) and byte 1 (A0=VIH) the device identifier
code(MX29L1611G=F6H).
Toactivatethismode,theprogrammingequipmentmust
force VID (11.5V~12.5V) on address pin A9. Two
identifier bytes may then be sequenced from the device
outputs by toggling address A0 from VIL to VIH. All
addresses are don't cares except A0 and A1.
To terminate the operation, it is necessary to write the
read/reset command sequence into the CIR.
Table 4. MX29L1611G Silion ID Codes and Verify Sector Protect Code
Type
A19
X
A18
X
A17
X
A16 A15 A1
A0
Code(HEX) Q7
Q6
1
Q5
0
Q4
0
Q3
0
Q2
0
Q1
1
Q0
0
Manufacturer Code
X
X
X
X
VIL VIL C2H*
VIL VIH F6H*
VIH VIL C2H**
1
1
1
MX29L1611G Device Code X
Verify Sector Protect
X
X
1
1
1
1
0
0
0
Sector Address***
1
0
0
0
0
1
0
*
MX29L1611G Manufacturer Code = C2H, Device Code = F6H when BYTE/VPP = VIL
MX29L1611G Manufacturer Code = 00C2H, Device Code = 00F6H when BYTE/VPP = VIH
** Outputs C2H at protected sector address, 00H at unprotected scetor address.
***Only the top and the bottom sectors have protect-bit feature. Sector address = (A19, A18,A17,A16,A15) = 00000B or 11111B
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MX29L1611G
READ/RESET COMMAND
PROGRAM
Thereadorresetoperationisinitiatedbywriting theread/
reset command sequence into the command register.
Microprocessor read cycles retrieve array data from the
memory. Thedeviceremainsenabledforreadsuntilthe
CIRcontentsarealteredbyavalidcommandsequence.
Anypagetobeprogrammedshouldhavethepageinthe
erasedstatefirst,i.e.performingsectoreraseissuggested
beforepageprogrammingcanbeperformed.
The device is programmed on a page basis. If a word of
data within a page is to be changed, data for the entire
page can be loaded into the device. Any word that is not
loaded during the programming of its page will be still in
the erased state (i.e. FFH). Once the words of a page
are loaded into the device, they are simultaneously
programmed during the internal programming period.
Afterthefirstdatawordhasbeenloadedintothedevice,
successivewordsareenteredinthesamemanner. Each
new word to be programmed must have its high to low
transition on CE within 30us of the low to high transition
ofCEoftheprecedingword. A6toA19specifythepage
address, i.e., the device is page-aligned on 64 words
boundary. The page address must be valid during each
high to low transition of CE. A0 to A5 specify the word
addresswithihthepage. Thewordmaybeloadedinany
order; sequential loading is not required. If a high to low
transition of CE is not detected whithin 100us of the last
low to high transition, the load period will end and the
internal programming period will start. The Auto page
programterminateswhenstatusonQ7is'1' atwhichtime
the device stays at read status register mode until the
CIR contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 1,7,8)
Thedevicewillautomaticallypower-upintheread/reset
state. Inthiscase,acommandsequenceisnotrequired
for "read operation". Standard microprocessor read
cycleswillretrievearraydata. Thisdefaultvalueensures
thatnospuriousalterationofthememorycontentoccurs
during the power transition. Refer to the AC Read
Characteristics and Waveforms for the specific timing
parameters.
The MX29L1611G is accessed like an EPROM. When
CEandOEarelowthedatastoredatthememorylocation
determined by the address pins is asserted on the
outputs. Theoutputsareputinthehighimpedancestate
whenever CE or OE is high. This dual line control gives
designers flexibility in preventing bus contention.
Note that the read/reset command is not valid when
program or erase is in progress.
PAGE PROGRAM
The device is set up in the programming mode when
VPP=11V is applied OE=VIH.
CHIP ERASE
ToinitiatePageprogrammode,a three-cyclecommand
sequence is required. There are two "unlock" write
cycles. These are followed by writing the page program
command-A0H.
The device is set up in the erase mode when VPP=11V
is applied OE=VIH.
Chip erase is a six-bus cycle operation. There are two
"unlock" write cycles. These are followed by writing the
"set-up"command-80H. Twomore"unlock"writecycles
are then followed by the chip erase command-10H.
Anyattempttowritetothedevicewithoutthethree-cycle
commandsequencewillnotstarttheinternalWriteState
Machine(WSM), no data will be written to the device.
After three-cycle command sequence is given, a
byte(word) load is performed by applying a low pulse on
the CE input with CE low and OE high. The address is
latched on the falling edge of CE. The data is latched by
thefirstrisingedgeofCE. Maximumof64wordsofdata
maybeloadedintoeachpagebythesameprocedureas
outlined in the page program section below.
Chip erase does not require the user to program the
device prior to erase.
Theautomaticerasebeginsontherisingedgeofthelast
CE pulse in the command sequence and terminates
when the status on Q7 is "1" at which time the device
stays at read status register mode. The device remains
enabled for read status register mode until the CIR
contentsarealteredbyavalidcommandsequence.(Refer
to table 3,6 and Figure 2,6,8)
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MX29L1611G
Table 5. MX29L1611G Sector Address Table
(Byte-Wide Mode)
The status register bits are output on Q3 - Q7(table 6)
whether the device is in the byte-wide (x8) or word-wide
(x16)modefortheMX29L1611G. Intheword-widemode
theupperbyte,Q(8:15)issetto00HduringaReadStatus
command. Inthebyte-widemode,Q(8:14)aretri-stated
and Q15/A-1 retains the low order address function.
A19
0
A18
0
A17
0
A16
0
A15
0
AddressRange[A19,-1]
000000H--00FFFFH
010000H--01FFFFH
020000H--02FFFFH
030000H--03FFFFH
040000H--04FFFFH
................................
1F0000H--1FFFFFH
SA0
SA1
SA2
SA3
SA4
0
0
0
0
1
Itshouldbenotedthatthecontentsofthestatusregister
are latched on the falling edge of OE or CE whichever
occurslastinthereadcycle. Thispreventspossiblebus
errors which might occur if the contents of the status
registerchangewhilereadingthestatusregister. CEor
OE must be toggled with each subsequent status read,
orthecompletionofaprogramoreraseoperationwillnot
be evident.
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
...
1
...
1
...
1
...
1
...
SA31
1
The Status Register is the interface between the
microprocessor and the Write State Machine (WSM).
When the WSM is active, this register will indicate the
status of the WSM, and will also hold the bits indicating
whetherornottheWSMwassuccessfulinperformingthe
desired operation. The WSM sets status bits four
through seven and clears bits six and seven, but cannot
clearstatusbitsfourandfive. IfErasefailorProgramfail
status bit is detected, the Status Register is not cleared
until the Clear Status Register command is written. The
MX29L1611GautomaticallyoutputsStatusRegisterdata
whenreadafterChipErase,SectorErase,PageProgram
or Read Status Command write cycle. The default state
oftheStatusRegisterafterpowerupandreturnfromdeep
power-down mode is (Q7, Q6, Q5, Q4) = 1000B. Q3 = 0
or 1 depends on sector-protect status, can not be
changed by Clear Status Register Command or Write
State Machine.
SECTOR ERASE
Sectoreraseisasix-buscycleoperation. Therearetwo
"unlock" write cycles. These are followed by writing the
set-up command-80H. Two more "unlock" write cycles
are then followed by the sector erase command-30H.
The sector address is latched on the falling edge of CE,
whilethecommand(data)islatchedontherisingedgeof
CE.
Sector erase does not require the user to program the
device prior to erase. The system is not required to
provide any controls or timings during these operations.
Theautomaticsectorerasebegins ontherisingedgeof
the last CE pulse in the command sequence and
terminateswhenthestatusonQ7is"1" atwhichtimethe
device stays at read status register mode. The device
remains enabled for read status register mode until the
CIR contents are altered by a valid command
sequence.(Refer to table 3,6 and Figure 3,4,6,8)
CLEAR STATUS REGISTER
The Eraes fail status bit (Q5) and Program fail status bit
(Q4) are set by the write state machine, and can only be
reset by the system software. These bits can indicate
various failure conditions(see Table 6). By allowing the
system software to control the resetting of these bits,
several operations may be performed (such as
cumulatively programming several pages or erasing
multiple blocks in squence). The status register may
thenbereadtodetermineifanerroroccurredduringthat
programming or erasure series. This adds flexibility to
the way the device may be programmed or erased.
Additionally, once the program(erase) fail bit happens,
READ STATUS REGISTER
The MXIC's 16 Mbit flash family contains a status
registerwhichmaybereadtodeterminewhenaprogram
oreraseoperationiscomplete,andwhetherthatoperation
completed successfully. The status register may be
readatanytimebywritingtheReadStatuscommandto
theCIR. Afterwritingthiscommand,allsubsequentread
operations output data from the status register until
another valid command sequence is written to the CIR.
A Read Array command must be written to the CIR to
return to the Read Array mode.
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MX29L1611G
the program (erase) operation can not be performed
further. The program(erase) fail bit must be reset by
system software before further page program or sector
(chip)eraseareattempted. Toclearthestatusregister,
theClearStatusRegistercommandiswrittentotheCIR.
Then, any other command may be issued to the CIR.
Note again that before a read cycle can be initiated, a
Read command must be written to the CIR to specify
whether the read data is to come from the Array, Status
Register or Silicon ID.
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MX29L1611G
TABLE 6. MX29L1611G STATUS REGISTER
STATUS
NOTES
1,2,5
1,3,5
1,2,5
1,3,5
1,4,5
1,4,5
5
Q7
0
Q6
0
Q5
0
Q4
0
Q3
0/1
0/1
0/1
0/1
0/1
0/1
0/1
IN PROGRESS
COMPLETE
FAIL
PROGRAM
ERASE
0
0
0
0
PROGRAM
ERASE
1
0
0
0
1
0
0
0
PROGRAM
ERASE
1
0
0
1
1
0
1
0
AFTER CLEARING STATUS REGISTER
1
0
0
0
NOTES:
1. Q7 : WRITE STATE MACHINE STATUS
1 = READY, 0 = BUSY
Q5 : ERASE FAIL STATUS
1 = FAIL IN ERASE, 0 = SUCCESSFUL ERASE
Q4 : PROGRAM FAIL STATUS
1 = FAIL IN PROGRAM, 0 = SUCCESSFUL PROGRAM
Q3 : SECTOR-PROTECT STATUS
1 = SECTOR 0 OR/AND 15 PROTECTED
0 = NONE OF SECTOR PROTECTED
Q6,Q2 - 0 = RESERVED FOR FUTURE ENHANCEMENTS.
These bits are reserved for future use ; mask them out when polling the Status Register.
2. PROGRAM STATUS is for the status during Page Programming or Sector Unprotect mode.
3. ERASE STATUS is for the status during Sector/Chip Erase or Sector Protection mode.
4. FAIL STATUS bit(Q4 or Q5) is provided during Page Program or Sector/Chip Erase modes respectively.
5. Q3 = 0 or1 depends on Sector-Protect Status.
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MX29L1611G
SECTOR PROTECTION
The device remains enabled for read status register
mode until the CIR contents are altered by a valid
commandsequence.
To activate this mode, a six-bus cycle operation and
VPP=11V are required. There are two 'unlock' write
cycles. These are followed by writing the 'set-up'
command. Two more 'unlock' write cycles are then
followed by the Lock Sector command - 20H. Sector
address is latched on the falling edge of CE of the sixth
cycle of the command sequence. The automatic Lock
operation begins on the rising edge of the last CE pulse
in the command sequence and terminates when the
Status on Q7 is '1' at which time the device stays at the
read status register mode.
ABORT MODE
To activate Abort mode, a three-bus cycle operation is
required. TheE0Hcommand(Refertotable3)onlystops
PageprogramorSector/Chiperase operationcurrently
in progress and puts the device in Abort mode. So the
programoreraseoperationwillnotbecompleted. Since
the data in some page/sectors is no longer valid due to
an incomplete program or erase operation, the program
fail (Q4) or erase fail (Q5)bit will be set.
The device remains enabled for read status register
mode until the CIR contents are altered by a valid
command sequence (Refer to table 3,6 and Figure 9,11
).
A read array command MUST be written to bring the
device out of the abort state without incurring any wake
up latency. Note that once device is brought out, Clear
status register mode is required before a program or
erase operation can be executed.
VERIFY SECTOR PROTECT
To verify the Protect status of the Top and the Bottom
sector, operation is initiated by writing Silicon ID read
command into the command register. Following the
command write, a read cycle from address XX00H
retrieves the Manufacturer code of C2H. A read cycle
from XX01H returns the Device code F8H. A read cycle
fromappropriateaddressreturnsinformationastowhich
sectors are protected. To terminate the operation, it is
necessary to write the read/reset command sequence
into the CIR.
DATA PROTECTION
TheMX29L1611Gisdesignedtoofferprotectionagainst
accidental erasure or programming caused by spurious
system level signals that may exist during power
transitions. During power up the device automatically
resetstheinternalstatemachineintheReadArraymode.
Also, with its control register architecture, alteration of
the memory contents only occurs after successful
completion of specific multi-bus cycle command
sequences.
(Refer to table 3,4 and Figure 11)
A few retries are required if Protect status can not be
verified successfully after each operation.
Thedevicealsoincorporatesseveralfeaturestoprevent
inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
SECTOR UNPROTECT
It is also possible to unprotect the sector , same as the
first five write command cycles in activating sector
protection mode followed by the Unprotect Sector
command-40H,theautomaticUnprotectoperationbegins
on the rising edge of the last CE pulse in the command
sequence and terminates when the Status on DQ7 is '1'
atwhichtimethedevicestaysatthereadstatusregister
mode.
(Refer to table 3,6 and Figure 10,11)
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13
MX29L1611G
LOW VCC WRITE INHIBIT
To avoid initiation of a write cycle during VCC power-up
andpower-down,awritecycleislockedoutforVCCless
thanVLKO(typically1.8V). IfVCC<VLKO,thecommand
registerisdisabledandallinternalprogram/erasecircuits
aredisabled. Underthisconditionthedevicewillresetto
the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the user's
responsibilitytoensurethatthecontrolpinsarelogically
correcttopreventunintentionalwritewhenVCCisabove
VLKO.
WRITE PULSE "GLITCH" PROTECTION
Noise pulses of less than 10ns (typical) on CE will not
initiate a write cycle.
LOGICAL INHIBIT
Writing is inhibited by holding any one of OE = VIL,CE =
VIH. To initiate a write cycle, CE must be a logical zero
while OE is a logical one, and VPP=11V should be
applied.
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REV. 0.4, MAY 07, 1999
14
MX29L1611G
Figure 1. AUTOMATIC PAGE PROGRAM FLOW CHART
START
BYTE/VPP=VHH
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data A0H Address 5555H
Write Program Data/Address
Loading End?
NO
YES
Wait 100us
BYTE/VPP=VIH/VIL
Read Status Register
NO
SR7 = 1
?
YES
NO
SR4 = 0
?
YES
Page Program Completed
Program Error
To Continue Other Operations,
YES
Program
Do Clear S.R. Mode First
another page?
NO
Operation Done, Device Stays At Read S.R. Mode
Note : S.R. Stands for Status Register
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REV. 0.4, MAY 07, 1999
15
MX29L1611G
Figure 2. AUTOMATIC CHIP ERASE FLOW CHART
START
BYTE/VPP=VHH
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 80H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 10H Address 5555H
BYTE/VPP=VIH/VIL
Read Status Register
NO
SR7 = 1
?
YES
NO
SR5 = 0
?
YES
Chip Erase Completed
Erase Error
To Continue Other
Operations, Do Clear
S.R. Mode First
Operation Done,
Device Stays at
Read S.R. Mode
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REV. 0.4, MAY 07, 1999
16
MX29L1611G
Figure 3. AUTOMATIC SECTOR ERASE FLOW CHART
START
BYTE/VPP=VHH
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 80H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 30H Sector Address
BYTE/VPP=VIH/VIL
Read Status Register
NO
SR7 = 1
?
YES
NO
SR5 = 0
?
YES
Sector Erase Completed
Erase Error
To Continue Other
Operations, Do Clear
S.R. Mode First
Operation Done,
Device Stays at
Read S.R. Mode
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17
MX29L1611G
NOTICE:
ELECTRICAL SPECIFICATIONS
Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is stress rating only and functional operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended period may
affect reliability.
ABSOLUTEMAXIMUMRATINGS
RATING
VALUE
Ambient Operating Temperature
Storage Temperature
Applied Input Voltage
Applied Output Voltage
VCC to Ground Potential
A9
0°C to 70°C
-65°C to 125°C
-0.5V to Vcc+0.5V
-0.5V to Vcc+0.6V
-0.5V to 4.0V
-0.5V to 12.5V
-0.5V to 11.5V
NOTICE:
Specificationscontainedwithinthefollowingtablesaresubject
to change.
BYTE/VPP
CAPACITANCE TA = 25°C, f = 1.0 MHz
SYMBOL
CIN
PARAMETER
MIN.
TYP.
MAX.
14
UNIT
pF
CONDITIONS
VIN = 0V
InputCapacitance
OutputCapacitance
COUT
16
pF
VOUT = 0V
SWITCHING TEST CIRCUITS
2.7K ohm
DEVICE
UNDER
TEST
3.3V
DIODES = IN3064
OR EQUIVALENT
CL
6.2K ohm
CL = 35 pF Including jig capacitance
SWITCHING TEST WAVEFORMS
2.4V
2.0V
0.8V
TEST POINTS
1.5V
0.45V
OUTPUT
INPUT
AC TESTING: Inputs are driven at 2.4V for a logic "1" and 0.45V for a logic "0".
Input pulse rise and fall times are < 5ns.
P/N:PM0604
REV. 0.4, MAY 07, 1999
18
MX29L1611G
DC CHARACTERISTICS VCC = 3.3V ±10%
SYMBOL
PARAMETER
Input Load
NOTES
MIN.
TYP. MAX.
UNITS
TEST CONDITIONS
VCC = VCC Max
VIN = VCC or GND
VCC = VCC Max
VIN = VCC or GND
VCC = VCC Max
CE = VCC ±0.2V
VCC = VCC Max
CE = VIH
IIL
1
±1
uA
Current
ILO
Output Leakage
Current
1
1
±10
uA
ISB1
ISB2
ICC1
ICC2
VCC Standby
Current(CMOS)
VCC Standby
Current(TTL)
VCC Read
20
1
50
2
uA
mA
mA
mA
1
1
50
15
15
80
30
VCC = VCC Max
f = 10MHz, IOUT = 0 mA
Program in Progress
Current
VCC Program
Current
ICC3
VIL
VCC Erase Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
1
2
3
30
mA
V
Erase in Progress
-0.3
0.6
VIH
0.7xVCC
VCC+0.3
0.45
V
VOL
VOH
V
IOL = 2.1mA, Vcc = Vcc Min
IOH = -100uA, Vcc = Vcc Min
2.4
V
NOTES:
1. All currents are in RMS unless otherwise noted. Typical values at VCC = 3.3V, T = 25°C. These currents are valid for all product
versions (package and speeds).
2. VIL min. = -1.0V for pulse width is equal to or less than 50ns.
VIL min. = -2.0V for pulse width is equal to or less than 20ns.
3. VIH max. = VCC + 1.5V for pulse width is equal to oe less than 20ns. If VIH is over the specified maximum value, read operation
cannot be guaranteed.
P/N:PM0604
REV. 0.4, MAY 07, 1999
19
MX29L1611G
AC CHARACTERISTICS -- READ OPERATIONS
29L1611G-10
29L1611G-12
SYMBOL
tACC
tCE
DESCRIPTIONS
MIN. MAX.
MIN.
MAX.
120
120
30
UNIT CONDITIONS
Address to Output Delay
CE to Output Delay
100
100
30
ns
ns
ns
ns
ns
ns
ns
CE=OE=VIL
OE=VIL
tOE
OE to Output Delay
CE=VIL
tDF
OE High to Output Delay
Address to Output hold
BYTE to Output Delay
BYTE Low to Output in High Z
0
0
20
0
0
20
CE=VIL
tOH
CE=OE=VIL
CE= OE=VIL
CE=VIL
tBACC
tBHZ
100
20
120
20
NOTE:
TEST CONDITIONS:
1. tDF is defined as the time at which the output achieves the
open circuit condition and data is no longer driven.
• Input pulse levels: 0.45V/2.4V
• Input rise and fall times: 5ns
• Outputload:1TTLgate+35pF(Includingscopeandjig)
• Reference levels for measuring timing: 1.5V
P/N:PM0604
REV. 0.4, MAY 07, 1999
20
MX29L1611G
Figure 4. NORMAL READ TIMING WAVEFORMS
Device and
Outputs Enabled
Standby
Standby
Power-up
Vcc
address selection
Power-down
Data valid
Vcc
VIH
ADDRESSES STABLE
ADDRESSES
VIL
VIH
VIL
CE
OE
VIH
VIL
tDF
tOE
tCE
tOH
VOH
VOL
HIGH Z
HIGH Z
DATA OUT
Data out valid
tACC
3.3V
VCC
GND
NOTE:
1. For real world application, BYTE/VPP pin should be either static high(word mode) or static low(byte mode);
dynamic switching of BYTE/VPP pin is not recommended.
P/N:PM0604
REV. 0.4, MAY 07, 1999
21
MX29L1611G
Figure 5. BYTE TIMING WAVEFORMS
VIH
ADDRESSES STABLE
ADDRESSES
VIL
VIH
CE
VIL
VIH
OE
VIL
tDF
tBACC
VIH
tOE
BYTE/VPP
VIL
tCE
tOH
VOH
HIGH Z
HIGH Z
Data Output
DATA(Q0-Q7)
Data Output
VOL
tACC
tBHZ
VOH
HIGH Z
HIGH Z
DATA(Q8-Q15)
Data Output
VOL
P/N:PM0604
REV. 0.4, MAY 07, 1999
22
MX29L1611G
AC CHARACTERISTICS -- WRITE/ERASE/PROGRAM OPERATIONS
29L1611G-10
29L1611G-12
SYMBOL
tWC
DESCRIPTION
MIN.
120
0
MAX.
MIN.
120
0
MAX. UNIT
Write Cycle Time
ns
ns
ns
ns
ns
ns
tAS
Address Setup Time
Address Hold Time
tAH
60
50
10
0
60
50
10
0
tDS
Data Setup Time
tDH
Data Hold Time
tCES
tGHWL
tWP
CE Setup Time
ReadRecoverTimeBeforeWrite
Write Pulse Width
0
0
60
40
0.3
100
120
100
2
60
40
0.3
100
120
100
2
ns
ns
us
us
ns
ns
us
ns
us
us
tWPH
tBALC
tBAL
tSRA
tCESR
tVCS
tRAW
tVPS
tVPH
Write Pulse Width High
Byte(Word) Address Load Cycle
Byte(Word)AddressLoadTime
Status Register Access Time
CE Setup before S.R. Read
VCC Setup Time
30
20
30
20
Read Operation Set Up Time After Write
VPP Setup Time
2
2
2
2
VPP Hold Time
P/N:PM0604
REV. 0.4, MAY 07, 1999
23
MX29L1611G
Figure 6. COMMAND WRITE TIMING WAVEFORMS
OE
tWC
CE
tGHWL
tWPH
tWP
tAS
tAH
ADDRESSES
VALID
tDH
tDS
HIGH Z
DATA
DIN
VCC
tVCS
11V
BYTE/VPP
NOTE:
1. BYTE/VPP pin should be static at 11V is equal to or less than during write operation.
2. BYTE/VPP pin should be static at TTL or CMOS level during Read operation.
P/N:PM0604
REV. 0.4, MAY 07, 1999
24
MX29L1611G
Figure 7. AUTOMATIC PAGE PROGRAM TIMING WAVEFORMS
Word offset
Address
Last Word
A0~A5
AAH
2AH
55H
55H
55H
55H
offset Address
Page Address
A6~A14
tAS
tAH
Page Address
tBALC
A15~A19
CE
tWC
tBAL
tWPH
tWP
tCES
OE
tRAW
11V
BYTE/VPP
tVPS
tDS
tDH
tVPH
tSRA
Write
Data
Last Write
Data
DATA
AAH
55H
A0H
SRD
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REV. 0.4, MAY 07, 1999
25
MX29L1611G
Figure 8. AUTOMATIC SECTOR/CHIP ERASE TIMING WAVEFORMS
5555H
A0~A14
5555H
2AAAH
5555H
2AAAH
*/5555H
tAS
tAH
SA/*
A15~A19
tWC
tCESR
CE
tWPH
tWP
tCES
OE
tRAW
11V
BYTE/VPP
DATA
tDS
tDH
tSRA
AAH
55H
80H
AAH
55H
30H
SRD
NOTES:
1."*" means "don't care" in this diagram.
2."SA" means "Sector Adddress".
P/N:PM0604
REV. 0.4, MAY 07, 1999
26
MX29L1611G
Figure 9. SECTOR PROTECTION ALGORITHM
START,
PLSCNT=0
BYTE/VPP=VHH
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Increment PLSCNT,
To Protect Sector Again
Write Data 20H, Sector Address*
BYTE/VPP=VIH/VIL
Read Status Register
NO
SR7 = 1
?
NO
YES
YES
Protect Sector
PLSCNT
Operation Terminated
= 25 ?
NO
Device Failed
To
YES
Verify Protect
Status ?
Verify Protect Status Flow
(Figure 12)
Data
= C2H ?
NO
YES
Device Stays at
Read S.R. Mode
Sector Protected,Operation
Done, Device Stays at
Verify Sector Protect Mode
NOTE :
*Only the Top or the Bottom Sector Address is vaild in this feature.
i.e. Sector Address = (A19,A18,A17,A16,A15) = 00000B or 11111B
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REV. 0.4, MAY 07, 1999
27
MX29L1611G
Figure 10. SECTOR UNPROTECT ALGORITHM
START,
PLSCNT=0
BYTE/VPP=VHH
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 60H Address 5555H
Write Data AAH Address 5555H
Write Data 55H Address 2AAAH
Write Data 40H, Sector Address*
BYTE/VPP=VIH/VIL
Increment PLSCNT,
To Unprotect Sector Again
Read Status Register
NO
SR7 = 1
?
NO
YES
YES
Unprotect Sector
PLSCNT
Operation Terminated
= 25 ?
NO
Device Failed
To
YES
Verify Protect
Status ?
Verify Protect Status Flow
(Figure 12)
Data
= 00H ?
NO
YES
Device Stays at
Read S.R. Mode
Sector Unprotected,Operation
Done, Device Stays at
Verify Sector Protect Mode
NOTE :
*Only the Top or the Bottom Sector Address is vaild in this feature.
i.e. Sector Address = (A19,A18,A17,A16,A15) = 00000B or 11111B
P/N:PM0604
REV. 0.4, MAY 07, 1999
28
MX29L1611G
Figure 11. VERIFY SECTOR PROTECT FLOW CHART
START
BYTE/VPP=VHH
Write Data AAH, Address 5555H
Write Data 55H, Address 2AAAH
Write Data 90H, Address 5555H
BYTE/VPP=VIH/VIL
Protect Status Read*
* 1. Protect Status:
Data Outputs C2H as Protected Sector Verified Code.
Data Outputs 00H as Unprotected Sector Verified Code.
2. Sepecified address will be either
(A19,A18,A17,A16,A15,A1,A0) = (0000010) or (1111110),
the rest of the address pins are don't care.
3. Silicon ID can be read via this Flow Chart.
Refer to Table 4.
P/N:PM0604
REV. 0.4, MAY 07, 1999
29
MX29L1611G
ERASE AND PROGRAMMING PERFORMANCE(1)
LIMITS
PARAMETER
MIN.
TYP.(2)
MAX.
1600
150
UNITS
ms
Chip/Sector Erase Time
PageProgrammingTime
ChipProgrammingTime
Erase/ProgramCycles
200
5
ms
80
240
sec
100
Cycles
Note:
(1).Sampled, not 100% tested. Excludes external system level over head.
(2).Typing values are measured at 25°C, noninal voltage
LATCHUP CHARACTERISTICS
MIN.
MAX.
Input Voltage with respect to GND on all pins except I/O pins
Input Voltage with respect to GND on all I/O pins
Current
-1.0V
-1.0V
-100mA
6.6V
Vcc + 1.0V
+100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.3V, one pin at a time.
P/N:PM0604
REV. 0.4, MAY 07, 1999
30
MX29L1611G
PACKAGE INFORMATION
42-PIN PLASTIC DIP(600 mil)
ITEM
A
MILLIMETERS
52.54 max.
0.76 [REF]
2.54 [TP]
INCHES
42
22
2.070 max.
.030 [REF]
.100 [TP]
B
C
D
E
.46 [Typ.]
50.76
.018 [Typ.]
2.000
1
21
F
1.27 [Typ.]
3.30 ±. 25
.51 [REF]
3.94 ±. 25
5.33 max.
15.22 ± .25
13.97± .25
.25 [Typ.]
.050 [Typ.]
.130 ±.010
.020 [REF]
.155 ±.010
.210 max.
.600 ±.010
.550 ±.010
.010 [Typ.]
A
K
L
G
H
I
I
J
J
H
G
K
L
F
B
0~15¡
C
M
D
M
E
NOTE: Each lead centerline is located within .25
mm[.01 inch] of its true position [TP] at
maximum material condition.
P/N:PM0604
REV. 0.4, MAY 07, 1999
31
MX29L1611G
REVISION HISTORY
Revision Description
Page
Date
0.2
Erase/programmingoperationvoltagechange(10V-->11V)
P1,4,9,14,25
P26,27
P5
Mar/15/1999
Modify Bus operation
Modify command definitions
P6
Modify "Automatic page program time waveforms"
Modify "Sector Protection Algorithm"
Modify "Sector unprotect Algorithm"
Modify"Eraseandprogrammingperformance"
Descriptioncorrection
P26
P28
P29
P31
0.3
0.4
P1,6,7,9,13,19
P22,23
P15,16,17,18,28,29,30
P1,9,20,22
P6,10,12,16,17,19
P1,2
MAR/23/1999
Plug in BYTE/VPP operation description
DeletePagemodeoperation
Delete Erasesuspard/resumeoperation
Modify description
MAY/07/1999
UndateEraseandProgramPerformance
P30
P/N:PM0604
REV. 0.4, MAY 07, 1999
32
MX29L1611G
MACRONIX INTERNATIONAL CO., LTD.
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