MX29LA321DHXCI-70G [Macronix]
Flash, 2MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, MO-216, BGA-64;
| 型号： | MX29LA321DHXCI-70G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 2MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, MO-216, BGA-64 内存集成电路 闪存 |
| 文件： | 总65页 (文件大小：2088K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX29LA321D H/L
MX29LA321D H/L
DATASHEET
P/N:PM1340
REV. 1.2, MAR. 01, 2010
1
MX29LA321D H/L
Contents
FEATURES .............................................................................................................................................................5
GENERAL DESCRIPTION .....................................................................................................................................6
PIN CONFIGURATION ...........................................................................................................................................7
PIN DESCRIPTION.................................................................................................................................................7
BLOCK DIAGRAM..................................................................................................................................................9
BLOCK STRUCTURE...........................................................................................................................................10
Table 1. MX29LA321D SECTOR ARCHITECTURE ........................................................................................10
BUS OPERATION.................................................................................................................................................12
Table 2-1. BUS OPERATION ...........................................................................................................................12
Table 2-2. BUS OPERATION ...........................................................................................................................13
FUNCTIONAL DESCRIPTION..............................................................................................................................14
WRITE COMMANDS/COMMAND SEQUENCES............................................................................................14
REQUIREMENTS FOR READING ARRAY DATA............................................................................................14
ACCELERATED PROGRAM OPERATION......................................................................................................15
RESET# OPERATION......................................................................................................................................15
SECTOR PROTECT OPERATION ..................................................................................................................15
CHIP UNPROTECT OPERATION....................................................................................................................15
TEMPORARY SECTOR UNPROTECT OPERATION......................................................................................16
WRITE PROTECT (WP#).................................................................................................................................16
AUTOMATIC SELECT OPERATION................................................................................................................16
VERIFY SECTOR PROTECT STATUS OPERATION .....................................................................................16
SECURITY SECTOR FLASH MEMORY REGION...........................................................................................16
FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY...........16
CUSTOMER LOCKABLE : SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE FACTORY
.........................................................................................................................................................................17
DATA PROTECTION........................................................................................................................................17
LOW VCC WRITE INHIBIT ..............................................................................................................................17
WRITE PULSE "GLITCH" PROTECTION........................................................................................................17
LOGICAL INHIBIT ............................................................................................................................................17
POWER-UP SEQUENCE.................................................................................................................................17
POWER-UP WRITE INHIBIT ...........................................................................................................................18
POWER SUPPLY DECOUPLING ....................................................................................................................18
COMMAND DEFINITIONS....................................................................................................................................19
TABLE 3. MX29LA321D H/L COMMAND DEFINITIONS.................................................................................19
RESET COMMAND..........................................................................................................................................21
AUTOMATIC SELECT COMMAND SEQUENCE ............................................................................................21
AUTOMATIC PROGRAMMING........................................................................................................................22
CHIP ERASE...................................................................................................................................................23
SECTOR ERASE .............................................................................................................................................23
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MX29LA321D H/L
SECTOR ERASE SUSPEND...........................................................................................................................24
SECTOR ERASE RESUME.............................................................................................................................24
COMMON FLASH INTERFACE (CFI) MODE ......................................................................................................25
QUERY COMMAND AND COMMON FLASH MEMORY INTERFACE (CFI) MODE.......................................25
Table 4-1. CFI mode: Identification Data Values ..............................................................................................25
Table 4-2. CFI Mode: System Interface Data Values .......................................................................................25
Table 4-3. CFI Mode: Device Geometry Data Values.......................................................................................26
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values.................................................27
ELECTRICAL CHARACTERISTICS ....................................................................................................................28
ABSOLUTE MAXIMUM STRESS RATINGS....................................................................................................28
OPERATING TEMPERATURE AND VOLTAGE...............................................................................................28
DC CHARACTERISTICS .................................................................................................................................29
SWITCHING TEST CIRCUITS.........................................................................................................................30
SWITCHING TEST WAVEFORMS..................................................................................................................30
AC CHARACTERISTICS .................................................................................................................................31
WRITE COMMAND OPERATION.........................................................................................................................32
Figure 1. COMMAND WRITE OPERATION WAVEFORM..............................................................................32
READ/RESET OPERATION .................................................................................................................................33
Figure 2. READ TIMING WAVEFORMS...........................................................................................................33
Figure 3. RESET# TIMING WAVEFORM........................................................................................................34
ERASE/PROGRAM OPERATION ........................................................................................................................35
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM............................................................................35
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART.................................................................36
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM.....................................................................37
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART..........................................................38
Figure 8. ERASE SUSPEND/RESUME FLOWCHART....................................................................................39
Figure 9. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART..................................40
Figure 10. AUTOMATIC PROGRAM TIMING WAVEFORMS ..........................................................................41
Figure 11. ACCELERATED PROGRAM TIMING DIAGRAM ...........................................................................41
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART.........................................................42
Figure 13. CEx CONTROLLED PROGRAM TIMING WAVEFORM.................................................................43
SECTOR PROTECT/CHIP UNPROTECT ............................................................................................................44
Figure 14. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) ..................................44
Figure 15-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv.............................................................45
Figure 15-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv...........................................................46
Figure 16. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control) .....................................................47
Figure 17. SECTOR PROTECTION ALGORITHM (A9, OE# Control).............................................................48
Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control) .......................................................49
Figure 19. CHIP UNPROTECT ALROGITHM (A9, OE# Control).....................................................................50
Figure 20. TEMPORARY SECTOR UNPROTECT WAVEFORMS ..................................................................51
Figure 21. TEMPORARY SECTOR UNPROTECT ALROGITHM ....................................................................52
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MX29LA321D H/L
SILICON ID READ OPERATION..........................................................................................................................53
Figure 22. SILICON ID READ TIMING WAVEFORM.......................................................................................53
WRITE OPERATION STATUS..............................................................................................................................54
Figure 23. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS).......................54
Figure 24. DATA# POLLING ALGORITHM ......................................................................................................55
Figure 25. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS) ............................56
Figure 26. TOGGLE BIT ALGORITHM.............................................................................................................57
Figure 27. Q6 versus Q2..................................................................................................................................58
RECOMMENDED OPERATING CONDITIONS....................................................................................................59
ERASE AND PROGRAMMING PERFORMANCE...............................................................................................60
DATA RETENTION ..............................................................................................................................................60
LATCH-UP CHARACTERISTICS.........................................................................................................................60
PIN CAPACITANCE..............................................................................................................................................60
ORDERING INFORMATION.................................................................................................................................61
PART NAME DESCRIPTION................................................................................................................................62
PACKAGE INFORMATION...................................................................................................................................63
REVISION HISTORY ............................................................................................................................................64
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MX29LA321D H/L
32M-BIT [4M x 8 / 2M x 16] CMOS EQUAL SECTOR
FLASH MEMORY
FEATURES
GENERAL FEATURES
• 4,194,304 x 8 / 2,097,152 x 16 switchable
• Sixty-Four Equal Sectors with 32K word/ 64K byte
- Any combination of sectors can be erased with erase suspend/resume function
• Single Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to 1.5 x Vcc
• Low Vcc write inhibit is equal to or less than VLKO
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Access time: 70ns
- Program time: 11us/word (typical)
- Erase time: 0.7s/sector, 35s/chip (typical)
• Low Power Consumption
- Low active read current: 9mA (typical) at 5MHz
- Low standby current: 5uA(typical)
• Typical 100,000 erase/program cycle
• 20-years data retention
SOFTWARE FEATURES
• Support Common Flash Interface (CFI)
- Flash device parameters stored on the device and provide the host system to access
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
• Status Reply
- Data# polling & Toggle bits provide detection of program and erase operation completion
HARDWARE FEATURES
• Ready/Busy (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• ACC input pin
- Provides accelerated program capability
• WP#/ACC input
- Write protect (WP#) function allows protection all sectors, regardless of sector protection settings
SECURITY
• Sector Protection/Chip Unprotect
- Provides sector protect function to prevent program or erase operation in the protected sector
- Provides chip unprotect function to allow code changes
- Provides temporary sector unprotect function for code changes in previously protected sectors
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MX29LA321D H/L
• Sector Permanent Lock
- A unique lock bit feature allows the content to be permanently locked
(Please contact Macronix sales for specific information regarding this permanent lock feature)
• Secured Silicon Sector
- Provides a 128-word area for code or data that can be permanently protected
- Once this sector is protected, it is prohibited to program or erase within the sector again
- Can be programmed and locked at factory or by customer
PACKAGE
• 64-ball FBGA
• All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
MX29LA321D H/L is a 32Mbit flash memory that can be organized as 4Mbytes of 8 bits each or as 2Mbytes of
16 bits each. These devices operate over a voltage range of 2.7V to 3.6V typically using a 3V power supply in-
put. The memory array is divided into 64 equal 64 Kilo byte blocks.
The MX29LA321D H/L is offered in a 64-ball FBGA JEDEC standard package. The package is offered in leaded,
as well as lead-free version that is compliant to the RoHS specifications. The software algorithm used for this de-
vice also adheres to the JEDEC standard for single power supply devices. These flash parts can be programmed
in system or on commercially available EPROM/Flash programmers.
Separate OE# and CEx (Output Enable and Chip Enable) signals are provided to simplify system design. When
used with high speed processors, the 70ns read access time of this flash memory permits operation with minimal
time lost due to system timing delays.
The automatic write algorithm provided on Macronix flash memories perform an automatic erase prior to write.
The user only needs to provide a write command to the command register. The on-chip state machine automati-
cally controls the program and erase functions including all necessary internal timings. Since erase and write
operations take much longer time than read operations, erase/write can be interrupted to perform read opera-
tions in other sectors of the device. For this, Erase Suspend operation along with Erase Resume operation are
provided. Data# polling or Toggle bits are used to indicate the end of the erase/write operation.
The device is manufactured at the Macronix fabrication facility using the time tested and proven Macronix ad-
vanced technology. This proprietary non-epi process provides a very high degree of latch-up protection for
stresses up to 100 milliamperes on address and data pins from -1V to 1.5xVCC.
With low power consumption and enhanced hardware and software features, this flash memory retains data reli-
ably for at least 20 years. Erase and programming functions have been tested to meet a typical specification of
100,000 cycles of operation.
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MX29LA321D H/L
PIN CONFIGURATION
64 BGA
1
2
3
4
5
6
7
8
WP#/
ACC
A0
A5
A7
A12
VCC
A17
NC
A
A1
A2
GND
A6
A8
A9
CE0
A11
A13
A14
NC
NC
A18
A19
CE1
A20
B
C
RES-
ET#
D
A3
Q8
A4
Q1
Q0
A10
Q9
NC
Q4
NC
NC
NC
A15
Q15
NC
A16
RY/
BY#
Q3
E
F
BYTE#
Q10
Q11
Q12
OE#
NC
A-1
NC
Q2
V I/O
GND
Q5
Q6
Q14
Q7
WE#
NC
G
H
CE2
VCC
Q13
GND
PIN DESCRIPTION
LOGIC SYMBOL
SYMBOL PIN NAME
A0~A20/A-1 Address Input/LSB addr (Byte Mode)
VCC
Q0~Q15
CEx
WE#
Data Inputs/Outputs
Chip Enable Input (CE0, CE1, CE2)
Write Enable Input
21
16 or 8
A0-A20
(A-1)
Q0-Q15
OE#
Output Enable Input
RESET#
Hardware Reset Pin, Active Low
Hardware Write Protect/Programming
Acceleration input
WP#/ACC
CEx
RY/BY#
BYTE#
VCC
Read/Busy Output
OE#
Selects 8 bit or 16 bit mode
+3.0V single power supply
Device Ground
WE#
RESET#
GND
RY/BY#
WP#/ACC
BYTE#
V I/O
NC
Pin Not Connected Internally
Output Power Supply (2.7V~3.6V),
which is tied to VCC
V I/O
Note:
If customers do not need WP#/ACC feature, please
connect WP#/ACC pin to Vcc or let it be floating. The
WP#/ACC has an internal pull-up when unconnected
WP#/ACC is at Vih.
GND
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MX29LA321D H/L
Chip Enable Truth Table
DEVICE
Enabled
Disabled
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
CE0
VIL
VIL
VIL
VIL
VIH
VIH
VIH
VIH
CE1
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
CE2
VIL
VIL
VIH
VIH
VIL
VIL
VIH
VIH
Note: For Single-chip applications, CE2 and CE1 can
be strapped to GND.
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MX29LA321D H/L
BLOCK DIAGRAM
VCC
GND
WRITE
CEx
CONTROL
INPUT
PROGRAM/ERASE
STATE
MACHINE
(WSM)
OE#
WE#
HIGH VOLTAGE
LOGIC
RESET#
WP#
ACC
STATE
FLASH
ARRAY
ADDRESS
LATCH
REGISTER
A0-A20
(A-1)
ARRAY
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
V I/O
I/O BUFFER
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MX29LA321D H/L
BLOCK STRUCTURE
Table 1. MX29LA321D SECTOR ARCHITECTURE
Sector Size
Address Range
Sector Address
Byte Mode
(Kbytes)
64
Word Mode
(Kwords)
32
Sector
A20-A15
Byte Mode (x8)
Word Mode (x16)
SA0
SA1
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
000000h-07FFFh
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
64
32
64
32
SA2
64
32
SA3
64
32
SA4
64
32
SA5
64
32
SA6
64
32
SA7
64
32
SA8
64
32
SA9
64
32
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
64
32
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MX29LA321D H/L
Sector Size
Address Range
Sector Address
Byte Mode
Word Mode
Sector
A20-A15
Byte Mode (x8)
Word Mode (x16)
(Kbytes)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
(Kwords)
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA36
SA37
SA38
SA39
SA40
SA41
SA42
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
111000
111001
111010
111011
111100
111101
111110
111111
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
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MX29LA321D H/L
BUS OPERATION
Table 2-1. BUS OPERATION
Data
(I/O)
Q0~Q7
Q8~Q15
WP#/
ACC
Mode Select
RESET# CEx WE# OE#
Address
Word
Byte
Device Reset
Standby Mode
Output Disable
L
X
X
X
H
X
X
X
X
X
HighZ
HighZ
HighZ
HighZ
HighZ
HighZ L/H
Vcc 0.3V disable
HighZ
HighZ
H
±
H
enable
H
HighZ
L/H
Q8~Q14
Read Mode
H
enable
H
L
L
AIN
AIN
DOUT
Note 3
=HighZ DOUT L/H
Q15=A-1
Q8~Q14
=HighZ Note 3 Note 2
Q15=A-1
Write
(Program/Erase)
H
H
enable
enable
H
Q8~Q14
=HighZ Note 3 Vhv
Q15=A-1
Accelerate Program
L
H
AIN
AIN
Note 3
Temporary Sector
Unprotect
Vhv
Vhv
Vhv
X
X
L
L
X
H
H
Note 3
HighZ Note 3 Note 2
Sector Protect
(Note 2)
Sector Address,
A6=L, A1=H, A0=L
enable
enable
X
X
X
X
Note 3
Note 3
H
H
Chip Unprotect
(Note 2)
Sector Address,
A6=H, A1=H, A0=L
Legend:
L=Logic LOW=Vil, H=Logic High=Vih, Vhv=10.0 0.5V, X=Don't Care, AIN=Address IN, DIN=Data IN,
±
DOUT=Data OUT
Notes:
1. Through programming equipment, the sector protect and chip unprotect functions can also be implemented.
2. If WP#=L, all sectors are protected. If WP# remove to H, all sectors recover previous protected or unprotected
status, determined by "sector protect" or "chip unprotect" function.
3. By following the requests of command sequence, sector protection, or data polling algorithm, Q0~Q15 would
be Data Input or Data Output.
4. In Word mode, A20~A0 are address pins. In Byte mode A20~A-1 are address pins. In both modes, A20~A15
are sector address.
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MX29LA321D H/L
Table 2-2. BUS OPERATION
Control Input
A20 A14
A8
A5 A3
Q8
to
Q15
Q7
to
Q0
Item
to to A9 to A6 to to A1 A0
A15 A10
CEx
OE# WE#
A7
A4 A2
Sector Lock Status
Verification
enable
L
L
L
H
H
H
SA
X
X
X
Vhv
Vhv
Vhv
X
L
L
L
X
X
X
L
L
L
H
H
L
L
H
L
X
X
Note 1
Note 2
C2h
Read Indicator Bit
(Q7) For Security
Sector
enable
enable
X
X
X
Read Manufacturer
ID
X
00
Read Device ID
1st cycle
L
H
H
L
H
H
H
L
22
22
22
7Eh
1Dh
00h
2nd cycle
enable
L
H
X
X
Vhv
X
L
X
3rd cycle
H
Legend: L=Logic Low=VIL, H=Logic High=VIH, SA=Sector Address, X=Don't care.
Notes:
1. Sector unprotected code: 00h, sector protected code:01h.
2. Factory locked code:
For 29LA321DL: 88h.
For 29LA321DH: 98h.
Factory unlocked code: For 29LA321DL: 08h.
For 29LA321DH: 18h.
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MX29LA321D H/L
FUNCTIONAL DESCRIPTION
WRITE COMMANDS/COMMAND SEQUENCES
To write a command to the device, system must drive WE# and CEx to Vil, and OE# to Vih. In a command cycle,
all address are latched at the later falling edge of CEx and WE#, and all data are latched at the earlier rising
edge of CE# and WE#.
Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets
of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid
command will bring the device to an undefined state.
REQUIREMENTS FOR READING ARRAY DATA
Read array action is to read the data stored in the array. While the memory device is in powered up or has been
reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the
array, it has to drive CEx (device enable control pin) and OE# (Output control pin) as Vil, and input the address
of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being
read out will be displayed on output pin for microprocessor to access. If CEx or OE# is Vih, the output will be in
tri-state, and there will be no data displayed on output pin at all.
After the memory device completes embedded operation (automatic Erase or Program), it will automatically re-
turn to the status of read array, and the device can read the data in any address in the array. In the process of
erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a
period of time no more than Tready and the device will return to the status of read array. At this time, the device
can read the data stored in any address except the sector being erased in the array. In the status of erase sus-
pend, if user wants to read the data in the sectors being erased, the device will output status data onto the out-
put. Similarly, if program command is issued after erase suspend, after program operation is completed, system
can still read array data in any address except the sectors to be erased.
The device needs to issue reset command to enable read array operation again in order to arbitrarily read the
data in the array in the following two situations:
1. In program or erase operation, the programming or erasing failure causes Q5 to go high.
2. The device is in auto select mode or CFI mode.
In the two situations above, if reset command is not issued, the device is not in read array mode and system
must issue reset command before reading array data.
WORD/BYTE CONFIGURATION
The BYTE# input pin is used to select the organization of the array data and how the data is input/output on the
Data (I/O) pins. If the BYTE# pin is held HIGH, Word mode will be selected and all 16 data lines (Q0 to Q15) will
be active.
If BYTE# is forced LOW, Byte mode will be active and only data lines Q0 to Q7 will be active. Data lines Q8 to
Q14 will remain in a high impedance state and Q15 becomes the A-1 address input pin.
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MX29LA321D H/L
ACCELERATED PROGRAM OPERATION
The accelerated program can improve programming performance compared with word/byte program. By apply-
ing Vhv on WP#/ACC pin, the device will enter accelerated program and draw current no more than Icp1/Icp2
from WP#/ACC pin. Removing the Vhv from WP#/ACC pin will put the device back to normal operation (not ac-
celerated).
RESET# OPERATION
Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in
program or erase operation, the reset operation will take at most a period of Tready for the device to return to
read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status).
When RESET# pin is held at GND 0.3V, the device consumes standby current(Isb).However, device draws larg-
±
er current if RESET# pin is held at Vil but not within GND 0.3V.
±
It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memo-
ry will be reset during system reset and allows system to read the boot-up firware from flash memory.
SECTOR PROTECT OPERATION
When a sector is protected, program or erase operation will be disabled on these sectors. MX29LA321D H/L pro-
vides two methods for sector protection.
Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected
by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details.
The first method is by applying Vhv on RESET# pin. Refer to Figure 14 for timing diagram and Figure 15 for the
algorithm for this method.
The other method is asserting Vhv on A9 and OE# pins, with A6 and CEx at Vil. The protection operation begins
at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
CHIP UNPROTECT OPERATION
MX29LA321D H/L provides two methods for chip unprotect. The chip unprotect operation unprotects all sectors
within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sectors are
unprotected when shipped from the factory.
The first method is by applying Vhv on RESET# pin. Refer to Figure 14 for timing diagram and Figure 15 for al-
gorithm of the operation.
The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil (see Table 2-1). The un-
protect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for de-
tails.
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MX29LA321D H/L
TEMPORARY SECTOR UNPROTECT OPERATION
System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously
protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal opera-
tion once Vhv is removed from RESET# pin and previously protected sectors are again protected.
WRITE PROTECT (WP#)
This Write Protect function provides a hardware protection method to protect all sectors without using Vhv.
By driving the WP#/ACC pin Low, the device disable program and erase function in all sectors. If the WP#/ACC
is held high (Vih to Vcc), these sectors revert to their previous protected/unprotected status.
AUTOMATIC SELECT OPERATION
When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read
silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several
silicon IDs continuously and does not need to issue read silicon ID mode again. In read silicon ID mode, issuing
reset command will reset device back to read array mode or erase-suspended read array mode.
MX29LA321D H/L provide hardware method to access the silicon ID read operation. Which method requires Vhv
on A9 pin, Vil on CEx, OE# and A6 pins. Which apply A1=A0=Vil the device will output MXIC's manufacture code
of C2h. Table 2 shows the sequence for reading MX29LA321D H/L device codes.
VERIFY SECTOR PROTECT STATUS OPERATION
MX29LA321D H/L provides hardware sector protection against Program and Erase operation for protected sec-
tors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on
A9 pin, Vih on WE# and A1 pins, Vil on CEx, OE#, A6 and A0 pins, and sector address on A15 to A20 pins. If the
read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated
sector is not protected.
SECURITY SECTOR FLASH MEMORY REGION
The Security Sector region is an extra OTP memory space of 64KBytes (32KWords) in length. The Security Sec-
tor can be locked by the factory prior to shipping, or it can be locked by the customer later.
FACTORY LOCKED: SECURITY SECTOR PROGRAMMED AND PROTECTED AT THE FACTORY
In a factory locked device, the security silicon region is permanently locked after shipping from factory. The de-
vice will have a 16-byte (8-word) ESN in the security region at address : 000000h - 000007h. Customers may
choose have their code programmed by MXIC. The device are then shipped with the security sector permanently
locked.
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MX29LA321D H/L
CUSTOMER LOCKABLE : SECURITY SECTOR NOT PROGRAMMED OR PROTECTED AT THE FACTORY
When the security feature is not required, the security region can act as an extra memory space.
Security silicon sector can also be protected by two methods. Note that once the security silicon sector is pro-
tected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered.
The first method is to write a three-cycle command of Enter Security Region, and then follow the sector protect
algorithm as illustrated in Figure 15, except that RESET# pin may at either Vih or Vhv.
The other method is to write a three-cycle command of Enter Security Region, and then follow the alternate
method of sector protect with A9, OE# at Vhv.
After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a pow-
er cycle, or issue a hardware reset to return the device to read normal array mode.
DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode
during power up. Besides, only after successful completion of the specified command sets will the device begin
its erase or program operation.
Other features to protect the data from accidental alternation are described as followed.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from spuri-
ously altered. The device automatically resets itself when Vcc is lower than VLKO and write cycles are ignored
until Vcc is greater than VLKO. System must provide proper signals on control pins after Vcc is larger than VLKO
to avoid unintentional program or erase operation
WRITE PULSE "GLITCH" PROTECTION
CEx, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
LOGICAL INHIBIT
A valid write cycle requires both CEx and WE# at Vil with OE# at Vih. Write cycle is ignored when either CEx at
Vih, WE# a Vih, or OE# at Vil.
POWER-UP SEQUENCE
Upon power up, MX29LA321D H/L is placed in read array mode. Furthermore, program or erase operation will
begin only after successful completion of specified command sequences.
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MX29LA321D H/L
POWER-UP WRITE INHIBIT
When WE#, CEx is held at Vil and OE# is held at Vih during power up, the device ignores the first command on
the rising edge of WE#.
POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
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MX29LA321D H/L
COMMAND DEFINITIONS
TABLE 3. MX29LA321D H/L COMMAND DEFINITIONS
Automatic Select
Read Reset
Mode Mode
Security Sector Factory
Command
Manufacturer ID
Device ID
Word Byte
Sector Protect Verify
Protect Verify
Word
555
AA
Byte
AAA
AA
Word
555
AA
Byte
AAA
AA
Word
555
Byte
AAA
Addr Addr
XXX
F0
555
AA
AAA
AA
1st Bus
Cycle
Data Data
Addr
AA
2AA
55
AA
555
55
2AA
55
555
55
2AA
55
555
55
2AA
55
555
55
2nd Bus
Cycle
Data
Addr
Data
555
90
AAA
90
555
90
AAA
90
555
90
AAA
90
555
90
AAA
90
3rd Bus
Cycle
(Sector)
X02
(Sector)
X04
Addr
X00
X00
X01
X02
X03
X06
4th Bus
Cycle
Data
Addr
Data
Addr
Data
C2h
C2h
227E
X0E
221D
X0F
7E
X1C
1D
X1E
00
Note 6
Note 6
00/01
00/01
5th Bus
Cycle
6th Bus
Cycle
2200
Enter Security
Sector Region
Enable
Exit Security
Sector
Sector
Erase
Erase
Suspend Resume
Erase
Program Chip Erase
CFI Read
Command
Word
Byte Word Byte Word Byte Word Byte Word Byte Word Byte Byte/Word Byte/Word
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
555
AA
2AA
55
555
88
AAA 555 AAA 555 AAA 555 AAA 555 AAA 55
AA AA AA AA AA AA AA AA AA 98
555 2AA 555 2AA 555 2AA 555 2AA 555
55 55 55 55 55 55 55 55 55
AAA 555 AAA 555 AAA 555 AAA 555 AAA
88 90 90 A0 A0 80 80 80 80
XXX XXX Addr Addr 555 AAA 555 AAA
00 00 Data Data AA AA AA AA
2AA 555 2AA 555
55 55 55 55
Sec- Sec-
AA
98
XXX
B0
XXX
30
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
Addr
555 AAA
10 10
6th Bus
Cycle
tor
tor
Data
30
30
Notes: It is not allowed to adopt any other code which is not in the above command definition table.
Legend:
X=Don't care
A20-A15: Sector Address
Notes:
1. All values are in hexadecimal.
2. Except when reading array or automatic select data, all bus cycles are write operation.
3. During read mode, the unlock or command cycles are invalid.
4. The Reset command is required to return to the read mode when the device is in the automatic select mode
or if Q5 goes high.
5. The fourth cycle of the automatic select command sequence is a read cycle.
6. Either word mode or byte mode, the Factory Locked Code is 88h (29LA321DL) or 98h (29LA321DH) the fac-
tory unlocked code is 08h (29LA321DL) or 18 (29LA321DH).
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MX29LA321D H/L
7. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.
8. The system may read and program functions in non-erasing sectors, or enter the automatic select mode,
when in the erase Suspend mode. The Erase Suspend command is valid only during a sector erase opera-
tion.
9. The Erase Resume command is valid only during the Erase Suspend mode.
10. It is not allowed to adopt any other code which is not in the above command definition table.
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MX29LA321D H/L
RESET COMMAND
In the following situations, executing reset command will reset device back to read array mode:
• Among erase command sequence (before the full command set is completed)
• Sector erase time-out period
• Erase fail (while Q5 is high)
• Among program command sequence (before the full command set is completed, erase-suspended program
included)
• Program fail (while Q5 is high, and erase-suspended program fail is included)
• Read silicon ID mode
• Sector protect verify
• CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset
device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode,
user must issue reset command to reset device back to read array mode.
When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig-
nore reset command.
AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured
silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles.
The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle,
and user can read at any address any number of times without entering another command sequence. The reset
command is necessary to exit the Automatic Select mode and back to read array. The following table shows the
identification code with corresponding address.
Identifier Code
Word/Byte Mode
Word
Address
X00
Data (Hex) Representation
C2
C2
Manufacturer ID
Byte
X00
Word
Byte
Word
Byte
Word
Byte
X01
X02
X0E
X1C
X0F
227E
7E
221D
1D
2200
00
Device ID, cycle 1
Device ID, cycle 2
Device ID, cycle 3
X1E
98/18 (H)
88/08 (L)
Word
X03
X06
Factory locked/unlocked
Secured Silicon
98/18 (H)
88/08 (L)
00/01
Byte
Factory locked/unlocked
Word
Byte
(Sector address) X 02
(Sector address) X 04
Unprotected/protected
Unprotected/protected
Sector Protect Verify
00/01
There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires
Vhv on address bit A9.
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MX29LA321D H/L
AUTOMATIC PROGRAMMING
The MX29LA321D H/L can provide the user program function by the form of Byte-Mode or Word-Mode. As long
as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs
will automatically be programmed into the array.
Once the program function is executed, the internal write state controller will automatically execute the algo-
rithms and timings necessary for program and verification, which includes generating suitable program pulse,
verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse
if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells
that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal
write state controller, the device requires the user to write the program command and data only.
Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status
from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is
not successfully programmed to "0".
Any command written to the device during programming will be ignored except hardware reset, which will termi-
nate the program operation after a period of time no more than Tready. When the embedded program algorithm
is complete or the program operation is terminated by hardware reset, the device will return to the reading array
data mode.
The typical chip program time at room temperature of the MX29LA321D H/L is less than 35 seconds.
When the embedded program operation is on going, user can confirm if the embedded operation is finished or
not by the following methods:
Status
Q7
Q7#
Q7
Q6
Q5
0
RY/BY# *2
In progress *1
Finished
Toggling
0
1
0
Stop toggling
Toggling
0
Exceed time limit
Q7#
1
*1: The status "in progress" means both program mode and erase-suspended program mode.
*2: RY/BY# is an open drain output pin and should be weakly connected to Vcc through a pull-up resistor.
*3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues
to toggle for about 1us or less and the device returns to read array state without programing the data in the pro-
tected sector.
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MX29LA321D H/L
CHIP ERASE
Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first
two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles,
and the sixth cycle is the chip erase operation.
During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too
low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array.
When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or
not by the following methods:
Status
Q7
0
Q6
Q5
0
Q2
Toggling
1
RY/BY#
In progress
Finished
Toggling
0
1
0
1
Stop toggling
Toggling
0
Exceed time limit
0
1
Toggling
SECTOR ERASE
Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to is-
sue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also
"unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is
issued, there is a time-out period of 50us counted internally. During the time-out period, additional sector ad-
dress and sector erase command can be written multiply. Once user enters another sector erase command, the
time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend dur-
ing time-out period, the erase command would be aborted and the device is reset to read array condition. The
number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase com-
mand is not accepted and erase embedded operation begins.
During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user
can check the status as chip erase.
When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not
by the following methods:
Status
Time-out period
Q7
0
Q6
Q5
0
Q3
0
Q2
RY/BY#*2
Toggling
Toggling
Toggling
1
0
0
1
0
In progress
0
Toggling
0
1
Finished
1
Stop toggling
Toggling
0
1
Exceeded time limit
0
1
1
Toggling
*1: The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible
to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is
valid.
*2: RY/BY# is open drain output pin and should be weakly connected to Vcc through a pull-up resistor.
*3: When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues
to toggle for 100us or less and the device returned to read array status without erasing the data in the protected
sector.
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MX29LA321D H/L
SECTOR ERASE SUSPEND
During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command
in the time-out period of sector erasure, device time-out period will be over immediately and the device will go
back to erase-suspended read array mode. If user issue erase suspend command during the sector erase is be-
ing operated, device will suspend the ongoing erase operation, and after the Tready1 (≤20us) suspend finishes
and the device will enter erase-suspended read array mode. User can judge if the device has finished erase sus-
pend through Q6, Q7, and RY/BY#.
After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend
by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. User can use
Q6 and Q2 to judge the sector is erasing or the erase is suspended.
Status
Q7
1
Q6
No toggle
Data
Q5
0
Q3
N/A
Data
N/A
Q2
Toggle
Data
N/A
RY/BY#
Erase suspend read in erase suspended sector
Erase suspend read in non-erase suspended sector
Erase suspend program in non-erase suspended sector
1
1
0
Data
Q7#
Data
0
Toggle
When the device has suspended erasing, user can execute the command sets except sector erase and chip
erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume.
SECTOR ERASE RESUME
Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user
can issue another erase suspend command, but there should be a 4ms interval between erase resume and the
next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the
time for erasing will increase.
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MX29LA321D H/L
COMMON FLASH INTERFACE (CFI) MODE
QUERY COMMAND AND COMMON FLASH MEMORY INTERFACE (CFI) MODE
MX29LA321D H/L features CFI mode. Host system can retrieve the operating characteristics, structure and
vendor-specified information such as identifying information, memory size, byte/word configuration, operating
voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the
system writes the CFI Query command, 98H, to address 55h/AAh (depending on Word/Byte mode) any time the
device is ready to read array data. The system can read CFI information at the addresses given in Table 4.
Once user enters CFI query mode, user can not issue any other commands except reset command. The reset
command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the
CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select
mode.
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
10
11
12
13
14
15
16
17
18
19
1A
20
22
24
26
28
2A
2C
2E
30
32
34
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Table 4-2. CFI Mode: System Interface Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
Vcc supply minimum program/erase voltage
Vcc supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n us
Typical timeout for maximum-size buffer write, 2n us
Typical timeout per individual block erase, 2n ms
Typical timeout for full chip erase, 2n ms
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
36
38
3A
3C
3E
40
42
44
46
48
4A
4C
0027
0036
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times typical
Maximum timeout for chip erase, 2n times typical
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MX29LA321D H/L
Table 4-3. CFI Mode: Device Geometry Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
Device size = 2n in number of bytes
Flash device interface description (02=asynchronous x8/x16)
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
4E
50
52
54
56
58
5A
5C
5E
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
0016
0002
0000
0000
0000
0001
003F
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Maximum number of bytes in buffer write = 2n (not support)
Number of erase regions within device
Index for Erase Bank Area 1
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256-bytes
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4
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MX29LA321D H/L
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
80
82
84
86
88
8A
8C
8E
90
92
94
96
98
0050
0052
0049
0031
0033
0000
0002
0001
0001
0004
0000
0000
0000
Query - Primary extended table, unique ASCII string, PRI
Major version number, ASCII
Minor version number, ASCII
Unlock recognizes address (0= recognize, 1= don't recognize)
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/Chip unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode (0=not supported)
Page mode (0=not supported)
Minimum ACC (acceleration) supply (0= not supported), [D7:D4]
for volt, [D3:D0] for 100mV
Maximum ACC (acceleration) supply (0= not supported), [D7:D4]
for volt, [D3:D0] for 100mV
4D
4E
9A
9E
00A5
00B5
Top/Bottom Boot Sector Flag
02h=Bottom Boot Device, 03h=Top Boot Device
04h=uniform sectors bottom WP# protect,
05h=uniform sectors top WP# protect
0004/
0005
4F
9E
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ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM STRESS RATINGS
Surrounding Temperature with Bias
Storage Temperature
-65oC to +125oC
-65oC to +150oC
-0.5V to +4.0 V
VCC
RESET#, A9, ACC and OE#
-0.5V to +10.5 V
-0.5V to Vcc +0.5V
200 mA
Voltage Range
The other pins.
Output Short Circuit Current (less than one second)
Note:
1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to Vcc+2V during transition and for less than 20ns during transitions.
OPERATING TEMPERATURE AND VOLTAGE
A
Commercial (C) Grade
Industrial (I) Grade
Surrounding Temperature (T )
0°C to +70°C
-40°C to +85°C
+2.7 V to 3.6 V
A
Surrounding Temperature (T )
range
VCC
Supply Voltages
VCC
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MX29LA321D H/L
DC CHARACTERISTICS
Symbol Description
Min
Typ
Max
Remark
Iilk
Iilk9
Iolk
Icr1
Icr2
Input Leak
1.0uA
35uA
1.0uA
±
A9 Leak
A9=10.5V
Output Leak
±
Read Current(5MHz)
Read Current(1MHz)
9mA
2mA
16mA
4mA
CE#=Vil, OE#=Vih
CE#=Vil, OE#=Vih
CE#=Vil, OE#=Vih,
WE#=Vil
Icw
Isb
Write Current
26mA
30mA
Vcc=Vcc max, other
pin disable
Standby Current
5uA
15uA
Vcc=Vccmax,
Isbr
Reset Current
5uA
15uA
Reset# enable, other
pin disable
Isbs
Icp1
Sleep Mode Current
5uA
15uA
Accelerated Pgm Current, WP#/Acc pin
(Word/Byte)
5mA
10mA
CE#=Vil, OE#=Vih
CE#=Vil, OE#=Vih
Accelerated Pgm Current, Vcc pin,
(Word/Byte)
Icp2
15mA
30mA
Vil
Input Low Voltage
Input High Voltage
-0.5V
0.8V
Vih
0.7xVcc
Vcc+0.3V
Very High Voltage for hardware
Protect/Unprotect/Auto Select/
Temporary Unprotect/
Vhv
9.5V
10.5V
0.45V
Accelerated Program
Vol
Output Low Voltage
Ouput High Voltage
Ouput High Voltage
Low Vcc Lock-out Voltage
Iol=4.0mA
Voh1
Voh2
Vlko
0.85xVcc
Vcc-0.4V
2.3V
Ioh1=-2mA
Ioh2=-100uA
2.5V
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MX29LA321D H/L
SWITCHING TEST CIRCUITS
Vcc
R2
TESTED DEVICE
+3.3V
0.1uF
CL
R1
DIODES=IN3064
OR EQUIVALENT
R1=6.2K ohm
R2=2.7K ohm
Test Condition
Output Load : 1 TTL gate
Output Load Capacitance,CL : 30pF
Rise/Fall Times : 5ns
In/Out reference levels :1.5V
Input Pulse level : 0.0 ~ 3.0V
SWITCHING TEST WAVEFORMS
3.0V
0.0V
1.5V
1.5V
Test Points
INPUT
OUTPUT
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MX29LA321D H/L
AC CHARACTERISTICS
Description
Min
Typ
Max
70
Unit
ns
Symbol
Taa
Valid data output after address
Valid data output after CEx low
Valid data output after OE# low
Data output floating after OE# high
70
ns
Tce
40
ns
Toe
30
ns
Tdf
Output hold time from the earliest rising edge of address,CEx,
OE#
0
ns
Toh
Read period time
70
45
70
70
0
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
Trc
Tsrw
Twc
Tcwc
Tas
Latency between read and write operation (Note*1)
Write period time
Command write period time
Address setup time
Address hold time
45
45
0
Tah
Data setup time
Tds
Tdh
Tvcs
Tcs
Data hold time
Vcc setup time
50
0
Chip enable Setup time
Chip enable hold time
Output enable setup time
Read
0
Tch
0
Toes
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
sec
us
Toeh Output enable hold time
Toggle & Data# Polling
10
0
WE# setup time
Tws
Twh
WE# hold time
0
CEx pulse width
45
30
35
30
Tcep
CEx pulse width high
WE# pulse width
Tceph
Twp
WE# pulse width high
Program/Erase active time by RY/BY#
Read recover time before write
Read recover time before write
Twph
Tbusy
Tghwl
Tghel
90
0
0
Byte
9
11
7
Twhwh1 Program operation
Word
Acc Program operation(Word/Byte)
Twhwh1
Twhwh2
Tbal
Sector Erase Operation
Sector Add hold time
0.7
50
* Note 1: Sampled only, not 100% tested.
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MX29LA321D H/L
WRITE COMMAND OPERATION
Figure 1. COMMAND WRITE OPERATION WAVEFORM
Tcwc
Disable
CEx
Enable
Tch
Tcs
Vih
Vil
WE#
OE#
Toes
Twph
Twp
Vih
Vil
Vih
Vil
Addresses
VA
Tah
Tas
Tdh
Tds
Vih
Vil
Data
DIN
VA: Valid Address
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MX29LA321D H/L
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
Tce
Disable
CEx
Enable
Tsrw
Vih
WE#
OE#
Vil
Toeh
Tdf
Toe
Vih
Vil
Toh
Taa
Trc
Vih
Vil
ADD Valid
Addresses
Outputs
HIGH Z
HIGH Z
Voh
Vol
DATA Valid
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MX29LA321D H/L
AC CHARACTERISTICS
Item Description
Trp1 RESET# Pulse Width (During Automatic Algorithms)
Trp2 RESET# Pulse Width (NOT During Automatic Algorithms)
Setup
MIN
MIN
MIN
MIN
MIN
MAX
Speed
10
500
50
0
50
Unit
us
ns
ns
ns
Trh
RESET# High Time Before Read
Trb1 RY/BY# Recovery Time (to CE#, OE# go low)
Trb2 RY/BY# Recovery Time (to WE# go low)
Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write
ns
us
20
RESET# PIN Low (NOT During Automatic Algorithms) to Read or
Tready2
Write
MAX
500
ns
Figure 3. RESET# TIMING WAVEFORM
Trb1
CEx, OE#
Trb2
WE#
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CEx, OE#
Trh
RY/BY#
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
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MX29LA321D H/L
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Disable
CEx
Enable
Tch
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycle
Read Status
Tah
Twc
Tas
VA
2AAh
VA
SA
Address
Tds
Tdh
In
Progress
Complete
55h
10h
Data
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
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MX29LA321D H/L
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
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MX29LA321D H/L
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
Disable
Enable
CEx
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Tas
Sector
Sector
Sector
VA
VA
2AAh
Address
Address 0
Address 1
Address n
Tah
Tds Tdh
In
Progress
Complete
55h
30h
30h
30h
Data
Tbusy
Trb
RY/BY#
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MX29LA321D H/L
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Last Sector
to Erase
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh
YES
Auto Sector Erase Completed
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MX29LA321D H/L
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
ERASE SUSPEND
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
ERASE RESUME
Continue Erase
Another
NO
Erase Suspend ?
YES
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MX29LA321D H/L
Figure 9. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART
START
Enter Secured Silicon Sector
Wait 1us
First Wait Cycle Data=60h
Second Wait Cycle Data=60h
A6=0, A1=1, A0=0
Wait 300us
No
Data = 01h ?
Yes
Device Failed
Write Reset Command
Secured Sector Protect Complete
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MX29LA321D H/L
Figure 10. AUTOMATIC PROGRAM TIMING WAVEFORMS
Disable
CEx
Enable
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Tas
Last 2 Read Status Cycle
Tah
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
Trb
RY/BY#
Figure 11. ACCELERATED PROGRAM TIMING DIAGRAM
(9.5V ~ 10.5V)
Vhv
WP#/ACC
Vil or Vih
Vil or Vih
250ns
250ns
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MX29LA321D H/L
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
No
Read Again Data:
Program Data?
YES
No
Last Word to be
Programed
YES
Auto Program Completed
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MX29LA321D H/L
Figure 13. CEx CONTROLLED PROGRAM TIMING WAVEFORM
WE#
CEx
OE#
Tcep
Twh
Twhwh1 or Twhwh2
Disable
Enable
Tws
Tceph
Tghwl
Tah
Tas
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
Trb
RY/BY#
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MX29LA321D H/L
SECTOR PROTECT/CHIP UNPROTECT
Figure 14. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)
150us: Sector Protect
1us
15ms: Chip Unprotect
CExDisable
Enable
WE#
OE#
Verification
40h
Status
VA
Data
60h
60h
VA
SA, A6
A1, A0
VA
Vhv
Vih
RESET#
VA: valid address
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MX29LA321D H/L
Figure 15-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No
First CMD=60h?
Yes
Set Up Sector Address
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Wait 150us
Reset
PLSCNT=1
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Retry Count +1
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
No
No
Data=01h?
Yes
Retry Count=25?
Yes
Device fail
Yes
Protect another
sector?
No
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
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MX29LA321D H/L
Figure 15-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No
First CMD=60h?
Yes
No
All sectors
protected?
Protect All Sectors
Yes
Write [A6,A1,A0]:[1,1,0]
data: 60h
Wait 15ms
Write [A6,A1,A0]:[1,1,0]
data: 40h
Retry Count +1
Read [A6,A1,A0]:[1,1,0]
No
No
Retry Count=1000?
Data=00h?
Yes
Yes
Device fail
Last sector
verified?
No
Yes
Temporary Unprotect
RESET#=Vih
Write reset CMD
Chip Unprotect Done
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MX29LA321D H/L
AC CHARACTERISTICS
Parameter Description
Test Setup
Min.
All Speed Options
Unit
us
ns
ns
us
Tvlht
Twpp1
Twpp2
Toesp
Voltage transition time
4
Write pulse width for sector protect
Write pulse width for chip unprotect
OE# setup time to WE# active
Min.
Min.
Min.
100
100
4
Figure 16. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)
A1
A6
10.5V
3V
A9
Tvlht
Verify
10.5V
3V
OE#
Tvlht
Tvlht
Twpp1
WE#
Toesp
Disable
CEx
Enable
Data
01H
F0H
Toe
Sector Address
A20-A15
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MX29LA321D H/L
Figure 17. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
OE#=Vhv, A9=Vhv, CEx=Vil
A6=Vil
Activate WE# Pulse
Time Out 150us
Set WE#=Vih, CEx=OE#=Vil
A9 should remain Vhv
.
Read from Sector
Addr=SA, A1=1
No
No
Data=01H?
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
Remove Vhv from A9
Write Reset Command
Sector Protection
Complete
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MX29LA321D H/L
Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control)
A1
10.5V
3V
A9
A6
Tvlht
Verify
10.5V
3V
OE#
WE#
Tvlht
Tvlht
Twpp2
Toesp
Disable
Enable
CEx
Data
00H
F0H
Toe
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MX29LA321D H/L
Figure 19. CHIP UNPROTECT ALROGITHM (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Set OE#=A9=Vhv
CEx=Vil, A6=1
Activate WE# Pulse
Time Out 15ms
Increment
PLSCNT
Set OE#=CEx=Vil
A9=Vhv, A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Yes
PLSCNT=1000?
Increment
Sector Addr
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove Vhv from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
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MX29LA321D H/L
AC CHARACTERISTICS
Parameter
Trpvhh
Alt Description
Condition Speed Unit
Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET#
Trsp RESET# Vhv to WE# Low
MIN
MIN
500
4
ns
us
Tvhhwl
Figure 20. TEMPORARY SECTOR UNPROTECT WAVEFORMS
Program or Erase Command Sequence
Disable
CEx
Enable
WE#
Tvhhwl
RY/BY#
Vhv 10V
RESET#
0 or Vih
Vil or Vih
Trpvhh
Trpvhh
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MX29LA321D H/L
Figure 21. TEMPORARY SECTOR UNPROTECT ALROGITHM
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Notes:
1. Temporary unprotect all protected sectors Vhv=9.5~10.5V.
2. After leaving temporary unprotect mode, the previously protected sectors are again protected.
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MX29LA321D H/L
SILICON ID READ OPERATION
Figure 22. SILICON ID READ TIMING WAVEFORM
VCC
3V
Vhv
ADD
A9
Vih
Vil
Vih
Vil
ADD
A0
Taa
Taa
Taa
Taa
Vih
Vil
A1
A2
Vih
Vil
Vih
Vil
ADD
Disable
Enable
CEx
Tce
Vih
Vil
WE#
Toe
Vih
Vil
OE#
Tdf
Toh
Toh
Toh
Toh
Vih
Vil
DATA
Q0-Q15
DATA OUT
Manufacturer ID
DATA OUT
DATA OUT
DATA OUT
Device ID
Cycle 1
Device ID
Cycle 2
Device ID
Cycle 3
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WRITE OPERATION STATUS
Figure 23. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
Disable
CEx
Enable
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
VA
VA
Address
Taa
Toh
High Z
High Z
Complement
Complement
Status Data
True
True
Valid Data
Valid Data
Q7
Q0-Q6
Status Data
Tbusy
RY/BY#
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MX29LA321D H/L
Figure 24. DATA# POLLING ALGORITHM
Start
Read Q7~Q0 at valid address
(Note 1)
No
Q7 = Data# ?
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
No
Q7 = Data# ?
(Note 2)
Yes
FAIL
Pass
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
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MX29LA321D H/L
Figure 25. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CExDisable
Enable
Tch
WE#
OE#
Toe
Toeh
Tdf
Trc
VA
VA
VA
VA
Address
Taa
Toh
Valid Status
(second read)
Valid Status
(first read)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
Tbusy
RY/BY#
VA : Valid Address
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MX29LA321D H/L
Figure 26. TOGGLE BIT ALGORITHM
Start
Read Q7-Q0 Twice
(Note 1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
NO
Q6 Toggle ?
YES
Program/Erase fail
Write Reset CMD
Program/Erase Complete
Note:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
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Figure 27. Q6 versus Q2
Enter Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
WE#
Q2
Q6
NOTES:
The system can use OE# or CEx to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended
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MX29LA321D H/L
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-
up. If the timing in the figure is ignored, the device may not operate correctly.
Vcc(min)
Vcc
GND
Tvr
Tvcs
Tf
Tce
Tr
Disable
Enable
CEx
Vih
Vil
WE#
Tf
Toe
Tr
Vih
Vil
OE#
Taa
Tr or Tf
Tr or Tf
Vih
Vil
Valid
Address
ADDRESS
Voh
Vol
High Z
Valid
Ouput
DATA
Vih
Vil
WP#/ACC
Figure A. AC Timing at Device Power-Up
Symbol
Parameter
Min.
Max.
Unit
Tvr
Tr
Vcc Rise Time
80
500000
20
us/V
us/V
us/V
us
Input Signal Rise Time
Input Signal Fall Time
Vcc Setup Time
Tf
20
Tvcs
200
P/N:PM1340
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59
MX29LA321D H/L
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
LIMITS
UNITS
MIN.
TYP. (1)
MAX. (2)
2
0.7
35
Sector Erase Time
sec
sec
Chip Erase Time
50
11
Word Programming Time
Accelerated Word Program Time
360
210
108
72
us
7
us
36
Byte Mode
Chip Programming Time
sec
24
Word Mode
sec
100,000
Erase/Program Cycles
Cycles
Notes:
1. Typical program and erase times assume the following conditions: 25 C, 3.0V VCC. Programming specifica-
°
tions assume checkboard data pattern.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing
the write buffer.
4. Erase/Program cycles comply with JEDEC JESD-47 & A117 standard.
DATA RETENTION
PARAMETER
Condition
Min.
Max.
UNIT
Data retention
55˚C
20
years
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
10.5V
Input Voltage voltage difference with GND on WP#/ACC, A9, OE#, RESET# pins
Input Voltage voltage difference with GND on all I/O pins
Vcc current pulse
-1.0V
1.5 x Vcc
+100mA
-100mA
Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.
PIN CAPACITANCE
Parameter Symbol Parameter Description
Test Set
VIN=0
TYP.
6
MAX.
UNIT
pF
CIN
COUT
CIN2
Input Capacitance
7.5
12
9
Output Capacitance
Control Pin Capacitance
VOUT=0
VIN=0
8.5
7.5
pF
pF
Notes:
1. Test conditions TA=25°C, f=1.0MHz.
P/N:PM1340
REV. 1.2, MAR. 01, 2010
60
MX29LA321D H/L
ORDERING INFORMATION
PART NO.
ACCESS TIME
Ball Pitch /
Ball Size
PACKAGE
Remark
(ns)
MX29LA321DHXCI-70G
MX29LA321DLXCI-70G
70
1.0mm/0.4mm
64 Ball BGA
64 Ball BGA
Pb-free
Pb-free
70
1.0mm/0.4mm
P/N:PM1340
REV. 1.2, MAR. 01, 2010
61
MX29LA321D H/L
PART NAME DESCRIPTION
MX 29 LA 321 D H XC I
70 G
OPTION:
G: Lead-free package
SPEED:
70: 70ns
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
X: FBGA (CSP)
XC - 1.0mm Ball Pitch/0.4mm Ball Size
PRODUCT TYPE:
H: Highest Address Sector
L: Lowest Address Sector
REVISION:
D
DENSITY & MODE:
321: 32M Equal Sector
TYPE:
LA: 3V Security
DEVICE:
29:Flash
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REV. 1.2, MAR. 01, 2010
62
MX29LA321D H/L
PACKAGE INFORMATION
P/N:PM1340
REV. 1.2, MAR. 01, 2010
63
MX29LA321D H/L
REVISION HISTORY
Revision No. Description
Page
P5
Date
MAR/06/2009
1.0
1. Removed "Advanced Information"
2. Modified chip erase time from 45s to 35s
3. Modified sector erase time from 0.9s to 0.7s
4. Modified data retention from 10 years to 20 years
1. Added table for DATA RETENTION
1. Modified WP#/ACC description
2. Added "OTP" description at security sector
3. Added Tsrw parameter
P5,60
P31,60
P5,6
P60
P5,7
P16
1.1
1.2
MAY/07/2009
MAR/01/2010
P31
4. Modified Figure 13. CEx Controlled Program Timing Waveform
5. Modified note 4 of Erase and Programming Performance
P43
P58
P/N:PM1340
REV. 1.2, MAR. 01, 2010
64
MX29LA321D H/L
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65
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MX29LA321DLXCI-70G
Flash, 2MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, MO-216, FBGA-64
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