MX29LA321MHXCI-70R_技术文档

MX29LA321M H/L

32M-BIT SINGLE VOLTAGE 3V ONLY

UNIFORM SECTOR FLASH MEMORY

FEATURES

GENERAL FEATURES

- Data# polling & Toggle bits provide detection of pro-

gram and erase operation completion

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program opera-

tions

• Configuration

- 4,194,304 x 8 / 2,097,152 x 16 switchable

• Sector structure

HARDWARE FEATURES

• Ready/Busy (RY/BY#) Output

- Provides a hardware method of detecting program

and erase operation completion

• Hardware Reset (RESET#) Input

- Provides a hardware method to reset the internal

state machine to read mode

- 64KB(32KW) x 64

• Latch-up protected to 250mA from -1V to VCC + 1V

• Low VCC write inhibit is equal to or less than 1.5V

• Compatible with JEDEC standard

- Pin-out and software compatible to single power sup-

ply Flash

• WP#/ACC input

- Write protect (WP#) function allows protection of all

sectors, regardless of sector protection settings

- ACC (high voltage) accelerates programming time

for higher throughput during system

PERFORMANCE

• High Performance

- Fast access time: 70R/90ns

- Page read time:25ns

SECURITY

• Sector Protection/Chip Unprotect

- Provides sector group protect function to prevent pro-

gram or erase operation in the protected sector group

- Provides chip unprotect function to allow code

changes

- Sector erase time: 0.5s (typ.)

- 4 word/8 byte page read buffer

- 16 word/ 32 byte write buffer:reduces programming

time for multiple-word/byte updates

• Low Power Consumption

• Sector Permanent Lock

- Active read current: 18mA(typ.)

- Active write current: 20mA(typ.)

- Standby current: 20uA(typ.)

• Minimum 100,000 erase/program cycle

• 20-year data retention

- Through a unique permanent locking scheme, the

device allows the user to permanently lock any ran-

domly selected sector(s) within the memory array

(Please contact Macronix for specifics relating to

this feature - this datasheet does not include any

other information relating to this feature)

• Secured Silicon Sector

SOFTWARE FEATURES

• Supports Common Flash Interface (CFI)

- Flash device parameters stored on the device and

provide the host system to access.

• Program Suspend/Program Resume

- Suspend program operation to read other sectors

• Erase Suspend/ Erase Resume

- Suspends sector erase operation to read data/pro-

gram other sectors

- Provides a 128-word OTP area for permanent, se-

cure identification

- Can be programmed and locked at factory or by cus-

tomer

PACKAGE

• 56-pinTSOP

• 64-ball CSP

• Status Reply

• All Pb-free devices are RoHS Compliant

64-ball CSP. It is designed to be reprogrammed and

erased in system or in standard EPROM programmers.

GENERAL DESCRIPTION

The MX29LA321M H/L is a 32-mega bit Flash memory

organized as 4M bytes of 8 bits or 2M words of 16 bits.

MXIC's Flash memories offer the most cost-effective and

reliable read/write non-volatile random access memory.

The MX29LA321M H/L is packaged in 56-pinTSOP and

The standard MX29LA321M H/L offers access time as

fast as 70ns, allowing operation of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion, the MX29LA321M H/L has separate chip enable

P/N:PM1145

REV. 1.0, FEB. 27, 2006

1

MX29LA321M H/L

(CE#) and output enable (OE#) controls.

fication of electrical erase are controlled internally within

the device.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29LA321M H/L uses a command register to manage

this functionality.

AUTOMATIC SECTOR ERASE

The MX29LA321M H/L is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically programs

the specified sector(s) prior to electrical erase. The tim-

ing and verification of electrical erase are controlled inter-

nally within the device.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and program

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and programming operations produces reliable

cycling. The MX29LA321M H/L uses a 2.7V to 3.6V

VCC supply to perform the High Reliability Erase and

auto Program/Erase algorithms.

AUTOMATIC ERASE ALGORITHM

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamperes on

address and data pins from -1V to VCC + 1V.

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

AUTOMATIC PROGRAMMING

The MX29LA321M H/L is byte/word/page programmable

using the Automatic Programming algorithm. The Auto-

matic Programming algorithm does not require the exter-

nal system to have a time-out sequence nor verification

of the data programmed.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE# .

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (including 2

unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the program

verification, and counts the number of sequences. A sta-

tus bit similar to DATA# polling and a status bit toggling

between consecutive read cycles, provide feedback to

the user as to the status of the programming operation.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, reli-

ability, and cost effectiveness. The MX29LA321M H/L

electrically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by us-

ing the EPROM programming mechanism of hot elec-

tron injection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 50 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm. The

Automatic Erase algorithm automatically programs the

entire array prior to electrical erase. The timing and veri-

P/N:PM1145

REV. 1.0, FEB. 27, 2006

2

MX29LA321M H/L

PIN CONFIGURATION

56TSOP

NC

CE1

A21

A20

A19

A18

A17

A16

VDD

A15

A14

A13

A12

CE0

WP#/ACC

RESET#

A11

A10

A9

1

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

NC

2

WE#

OE#

RY/BY#

Q15

Q7

3

4

5

6

7

Q14

Q6

8

9

VSS

S13

Q5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

Q12

Q4

VCC

GND

Q11

Q3

Q10

Q2

A8

VDD

Q9

VSS

A7

Q1

A6

Q8

A5

Q0

A4

A0

A3

BYTE#

NC

A2

A1

CE2

64 CSP

1

2

3

4

5

6

7

8

WP#/

ACC

A1

A6

A8

A13

VCC

A18

NC

A

A2

A3

GND

A7

A9

CE0

A12

A14

A15

NC

A19

A20

CE1

A21

B

C

A10

RES-

ET#

D

E

A4

Q8

A5

Q1

Q0

A11

Q9

NC

Q4

NC

A16

Q15

NC

A17

RY/

BY#

Q3

Q10

Q11

Q12

OE#

BYTE#

NC

F

A0

Q2

VCC

GND

Q5

Q6

Q14

Q7

WE#

NC

G

H

CE2

NC

VDD

Q13

GND

P/N:PM1145

REV. 1.0, FEB. 27, 2006

3

MX29LA321M H/L

LOGIC SYMBOL

PIN DESCRIPTION

SYMBOL PIN NAME

22

A0

Byte-Select Address

16 or 8

A0-A21

Q0-Q15

(A-1)

A1~A21

Q0~Q15

CE#

Address Input

Data Inputs/Outputs

Chip Enable Input

WE#

Write Enable Input

CE#

OE#

Output Enable Input

Hardware Reset Pin, Active Low

OE#

RESET#

WE#

WP#/ACC HardwareWrite Protect/Programming

Acceleration input

RESET#

WP#/ACC

BYTE#

VI/O

RY/BY#

BYTE#

VCC

Read/Busy Output

Selects 8 bit or 16 bit mode

+3.0V single power supply

Output Buffer Power (This input should

be tied directly to VCC 2.7V~3.6V)

Device Ground

VI/O

GND

NC

Pin Not Connected Internally

Chip Enable Truth Table

CE2

VIL

VIH

CE1

VIL

VIH

VIL

VIH

CE0

VIL

VIH

VIL

VIH

VIL

VIH

VIL

VIH

DEVICE

Enabled

Disabled

Enabled

Disabled

Note:For Single-chip applications, CE2 and CE1 can be

strapped to GND.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

4

MX29LA321M H/L

BLOCK DIAGRAM

CE#

OE#

WRITE

CONTROL

INPUT

PROGRAM/ERASE

STATE

MACHINE

(WSM)

WE#

HIGH VOLTAGE

WP#

LOGIC

BYTE#

RESET#

STATE

FLASH

ARRAY

ADDRESS

LATCH

REGISTER

ARRAY

A0-A21

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q15

I/O BUFFER

P/N:PM1145

REV. 1.0, FEB. 27, 2006

5

MX29LA321M H/L

MX29LA321M H/L SECTOR ADDRESS TABLE

Sector

Sector Address

A21-A16

000000

000001

000010

000011

000100

000101

000110

000111

001000

001001

001010

001011

001100

001101

001110

001111

010000

010001

010010

010011

010100

010101

010110

010111

011000

011001

011010

011011

011100

011101

011110

011111

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Address Range

000000-0FFFF

010000-1FFFF

020000-2FFFF

030000-3FFFF

040000-4FFFF

050000-5FFFF

060000-6FFFF

070000-7FFFF

080000-8FFFF

090000-9FFFF

0A0000-AFFFF

0B0000-BFFFF

0C0000-CFFFF

0D0000-DFFFF

0E0000-EFFFF

0F0000-FFFFF

100000-0FFFF

110000-1FFFF

120000-2FFFF

130000-3FFFF

140000-4FFFF

150000-5FFFF

160000-6FFFF

170000-7FFFF

180000-8FFFF

190000-9FFFF

1A0000-AFFFF

1B0000-BFFFF

1C0000-CFFFF

1D0000-DFFFF

1E0000-EFFFF

1F0000-FFFFF

Address Range

000000-07FFF

008000-0FFFF

010000-17FFF

018000-1FFFF

020000-27FFF

028000-2FFFF

030000-37FFF

038000-3FFFF

040000-47FFF

048000-4FFFF

050000-57FFF

058000-5FFFF

060000-67FFF

068000-6FFFF

070000-77FFF

078000-7FFFF

080000-87FFF

088000-8FFFF

090000-97FFF

098000-9FFFF

0A0000-A7FFF

0A8000-AFFFF

0B0000-B7FFF

0B8000-BFFFF

0C0000-C7FFF

0C8000-CFFFF

0D0000-D7FFF

0D8000-DFFFF

0E0000-E7FFF

0E8000-EFFFF

0F0000-F7FFF

0F8000-FFFFF

SA0

SA1

64/32

SA2

64/32

SA3

64/32

SA4

64/32

SA5

64/32

SA6

64/32

SA7

64/32

SA8

64/32

SA9

64/32

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

64/32

P/N:PM1145

REV. 1.0, FEB. 27, 2006

6

MX29LA321M H/L

Sector

Sector Address

A21-A16

100000

100001

100010

100011

100100

100101

100110

100111

101000

101001

101010

101011

101100

101101

101110

101111

110000

110001

110010

110011

110100

110101

110110

110111

111000

111001

111010

111011

111100

111101

111110

111111

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Address Range

200000-0FFFF

210000-1FFFF

220000-2FFFF

230000-3FFFF

240000-4FFFF

250000-5FFFF

260000-6FFFF

270000-7FFFF

280000-8FFFF

290000-9FFFF

2A0000-AFFFF

2B0000-BFFFF

2C0000-CFFFF

2D0000-DFFFF

2E0000-EFFFF

2F0000-FFFFF

300000-0FFFF

310000-1FFFF

320000-2FFFF

330000-3FFFF

340000-4FFFF

350000-5FFFF

360000-6FFFF

370000-7FFFF

380000-8FFFF

390000-9FFFF

3A0000-AFFFF

3B0000-BFFFF

3C0000-CFFFF

3D0000-DFFFF

3E0000-EFFFF

3F0000-FFFFF

Address Range

100000-07FFF

108000-0FFFF

110000-17FFF

118000-1FFFF

120000-27FFF

128000-2FFFF

130000-37FFF

138000-3FFFF

140000-47FFF

148000-4FFFF

150000-57FFF

158000-5FFFF

160000-67FFF

168000-6FFFF

170000-77FFF

178000-7FFFF

180000-87FFF

188000-8FFFF

190000-97FFF

198000-9FFFF

1A0000-A7FFF

1A8000-AFFFF

1B0000-B7FFF

1B8000-BFFFF

1C0000-C7FFF

1C8000-CFFFF

1D0000-D7FFF

1D8000-DFFFF

1E0000-E7FFF

1E8000-EFFFF

1F0000-F7FFF

1F8000-FFFFF

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

64/32

P/N:PM1145

REV. 1.0, FEB. 27, 2006

7

MX29LA321M H/L

MX29LA321M H/L Sector Group Protection Address Table

Sector Group

SA0

A21-A13

000000

000001

000010

000011

0001xx

0010xx

0011xx

0100xx

0101xx

0110xx

0111xx

1000xx

1001xx

1010xx

1011xx

1100xx

1101xx

1110xx

111100

111101

111110

111111

SA1

SA2

SA3

SA4-SA7

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

SA60

SA61

SA62

SA63

P/N:PM1145

REV. 1.0, FEB. 27, 2006

8

MX29LA321M H/L

Table 1. BUS OPERATION (1)

Q8~Q15

Operation

CE# OE# WE# RE-

WP# ACC

Address

Q0~Q7 Word

Mode

Byte

Mode

SET#

Read

L

H

X

H

L

H

X

A_IN

X

D_OUT

Q8-Q15=

High Z

Write (Program/Erase)

Accelerated Program

Standby

H

(Note 3)

(Note 4) (Note 4 Q8-Q15=

High Z

L

(Note 3) V_HH

(Note 4) (Note 4) Q8-Q15=

High Z

VCC±

X

VCC±

0.3V

H

X

H

High-Z High-Z

High-Z

0.3V

Output Disable

Reset

L

X

L

H

X

H

X

L

X

H

X

High-Z High-Z

High-Z

X

L

Sector Group Protect

(Note 2)

V_ID

Sector Addresses, (Note 4)

A7=L,A4=L, A3=L,

A2=H,A1=L

X

Chip unprotect

(Note 2)

L

H

L

V_ID

H

X

Sector Addresses, (Note 4)

A7=H, A4=L, A3=L,

A2=H, A1=L

X

Legend:

L=Logic LOW=V_IL, H=Logic High=V_IH, V_ID=12.0±0.5V, V_HH=12.0±0.5V, X=Don't Care, A_IN=Address IN, D_IN=Data IN,

D_OUT=Data OUT

Notes:

1. Address are A21:A1 in word mode; A21:A0 in byte mode. Sector addresses are A21:A14 in both modes.

2. The sector group protect and chip unprotect functions may also be implemented via programming equipment.See

the "Sector Group Protection and Chip Unprotect" section.

3. If WP#=VIL, all the sectors remain protected.If WP#=VIH, all sectors protection depends on whether they were last

protected or unprotect using the method described in "Sector/ Sector Block Protection and Unprotect".

4. D_INor D_OUTas required by command sequence, Data# polling or sector protect algorithm (seeTable 3 and Figure 15).

P/N:PM1145

REV. 1.0, FEB. 27, 2006

9

MX29LA321M H/L

Table 2. AUTOSELECT CODES (High Voltage Method)

A21 A15

CE# OE# WE# to to A10 to A7 to

A16 A11

A9

A6 A4

Q8 to Q15

Byte

Description

to A2 A1 Word

Q7 to Q0

A8

A5 A3

Mode

00

Mode

Manufacturer ID

Cycle 1

L

H

X

VID

X

L

X

L

H

L

X

C2h

7Eh

22

Cycle 2

L

H

X

VID

X

L

X

H

22

1Dh

Cycle 3

H

22

00h

Sector Group

Protection

01h (protected),

L

H

SA

X

VID

L

X

L

H

L

X

Verification

00h (unprotected)

98h

Secured Silicon

Sector Indicator

Bit (Q7), WP#

protects highest

address sector

Secured Silicon

Sector Indicator

Bit (Q7), WP#

protects lowest

address sector

(factory locked),

X

H

X

18h

(not factory locked)

88h

(factory locked),

L

H

X

VID

L

X

L

H

X

08h

(not factory locked)

Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don't care.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

10

MX29LA321M H/L

dress bits required to uniquely select a sector.The "Writ-

ing specific address and data commands or sequences

into the command register initiates device operations.

Table 3 defines the valid register command sequences.

Writing incorrect address and data values or writing them

in the improper sequence resets the device to reading

array data.Section has details on erasing a sector or the

entire chip, or suspending/resuming the erase operation.

REQUIREMENTS FOR READING ARRAY

DATA

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins.WE# should re-

main at VIH.

After the system writes the Automatic Select command

sequence, the device enters the Automatic Select mode.

The system can then read Automatic Select codes from

the internal register (which is separate from the memory

array) on Q7-Q0. Standard read cycle timings apply in

this mode. Refer to the Automatic Select Mode and Au-

tomatic Select Command Sequence section for more

information.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address on

the device address inputs produce valid data on the de-

vice data outputs. The device remains enabled for read

access until the command register contents are altered.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC

Characteristics" section contains timing specification

table and timing diagrams for write operations.

PAGE MODE READ

The MX29LA321M H/L offers "fast page mode read" func-

tion. This mode provides faster read access speed for

random locations within a page. The page size of the

device is 4 words/8 bytes. The appropriate page is se-

lected by the higher address bits A1~A2(Word Mode)/

A0~A2(Byte Mode) This is an asynchronous operation;

the microprocessor supplies the specific word location.

WRITE BUFFER

Write Buffer Programming allows the system to write a

maximum of 16 words/32 bytes in one programming op-

eration.This results in faster effective programming time

than the standard programming algorithms. See "Write

Buffer" for more information.

The system performance could be enhanced by initiating

1 normal read and 3 fast page read (for word mode A1-

A2) or 7 fast page read (for byte mode A0~A2). When

CE# is deasserted and reasserted for a subsequent ac-

cess, the access time is tACC or tCE. Fast page mode

accesses are obtained by keeping the "read-page ad-

dresses" constant and changing the "intra-read page"

addresses.

ACCELERATED PROGRAM OPERATION

The device offers accelerated program operations through

the ACC function. This is one of two functions provided

by the ACC pin. This function is primarily intended to

allow faster manufacturing throughput at the factory.

WRITING COMMANDS/COMMAND SE-

QUENCES

If the system asserts VHH on this pin, the device auto-

matically enters the aforementioned Unlock Bypass

mode, temporarily unprotects any protected sectors, and

uses the higher voltage on the pin to reduce the time

required for program operations. The system would use

a two-cycle program command sequence as required by

the Unlock Bypass mode. RemovingVHH from the ACC

pin must not be at VHH for operations other than accel-

erated programming, or device damage may result.

To program data to the device or erase sectors of memory,

the system must driveWE# and CE# toVIL, and OE# to

VIH.

An erase operation can erase one sector, multiple sec-

tors, or the entire device. The Sector Address Table on

page 6 and 7 indicates the address space that each

sector occupies. A "sector address" consists of the ad-

P/N:PM1145

REV. 1.0, FEB. 27, 2006

11

MX29LA321M H/L

greater.

STANDBY MODE

The RESET# pin may be tied to system reset circuitry.

A system reset would that also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

When using both pins of CE# and RESET#, the device

enter CMOS Standby with both pins held atVCC ±0.3V.

If CE# and RESET# are held at VIH, but not within the

range ofVCC ±0.3V, the device will still be in the standby

mode, but the standby current will be larger.During Auto

Algorithm operation,VCC active current (ICC2) is required

even CE# = "H" until the operation is completed. The

device can be read with standard access time (tCE) from

either of these standby modes, before it is ready to read

data.

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains a "0" (busy) until the

internal reset operation is complete, which requires a time

of tREADY (during Embedded Algorithms).The system

can thus monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asserted when a

program or erase operation is completed within a time of

tREADY (not during Embedded Algorithms).The system

can read data tRH after the RESET# pin returns to VIH.

AUTOMATIC SLEEP MODE

The automatic sleep mode minimizes Flash device en-

ergy consumption.The device automatically enables this

mode when address remain stable for tACC+30ns. The

automatic sleep mode is independent of the CE#, WE#,

and OE# control signals. Standard address access tim-

ings provide new data when addresses are changed.While

in sleep mode, output data is latched and always avail-

able to the system. ICC4 in the DC Characteristics table

represents the automatic sleep mode current specifica-

tion.

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 3 for the timing diagram.

SECTOR GROUP PROTECT OPERATION

The MX29LA321M H/L features hardware sector group

protection. This feature will disable both program and

erase operations for these sector group protected. In

this device, a sector group consists of four adjacent sec-

tors which are protected or unprotected at the same time

(See "MX29LA321M H/L Sector Group Protection Address

Table" on page 8). To activate this mode, the program-

ming equipment must forceVID on address pin A10 and

control pin OE#, (suggestVID = 12V) A7 =VIL and CE#

= VIL. (see Table 2) Programming of the protection cir-

cuitry begins on the falling edge of theWE# pulse and is

terminated on the rising edge. Please refer to sector

group protect algorithm and waveform.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output

from the devices are disabled.This will cause the output

pins to be in a high impedance state.

RESET# OPERATION

MX29LA321M H/L also provides another method.Which

requires VID on the RESET# only. This method can be

implemented either in-system or via programming equip-

ment. This method uses standard microprocessor bus

cycle timing.

The RESET# pin provides a hardware method of resetting

the device to reading array data.When the RESET# pin

is driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write

commands for the duration of the RESET# pulse. The

device also resets the internal state machine to reading

array data.The operation that was interrupted should be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

To verify programming of the protection circuitry, the pro-

gramming equipment must forceVID on address pin A10

(with CE# and OE# atVIL and WE# atVIH). When A2=1,

it will produce a logical "1" code at device output Q0 for a

protected sector. Otherwise the device will produce 00H

for the unprotected sector. In this mode, the addresses,

except for A2, are don't care. Address locations with A2

=VIL are reserved to read manufacturer and device codes.

(Read Silicon ID)

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at VSS±0.3V, the device draws

CMOS standby current (ICC4).If RESET# is held atVIL

but not within VSS±0.3V, the standby current will be

P/N:PM1145

REV. 1.0, FEB. 27, 2006

12

MX29LA321M H/L

It is also possible to determine if the group is protected

in the system by writing a Read Silicon ID command.

Performing a read operation with A2=VIH, it will produce

a logical "1" at Q0 for the protected sector.

last protected or unprotect using the method described in

"Sector/Sector Group Protection and Chip Unprotect".

Note that the WP# pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result.

CHIP UNPROTECT OPERATION

SILICON ID READ OPERATION

The MX29LA321M H/L also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in

the code. It is recommended to protect all sectors before

activating chip unprotect mode.

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A10 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design prac-

tice.

To activate this mode, the programming equipment must

force VID on control pin OE# and address pin A10. The

CE# pins must be set at VIL. Pins A7 must be set to

VIH.(seeTable 2) Refer to chip unprotect algorithm and

waveform for the chip unprotect algorithm. The unprotect

mechanism begins on the falling edge of the WE# pulse

and is terminated on the rising edge.

MX29LA321M H/L provides hardware method to access

the silicon ID read operation.Which method requiresVID

on A10 pin, VIL on CE#, OE#, A7, and A2 pins. Which

applyVIL on A1 pin, the device will output MXIC's manu-

facture code of which applyVIH on A1 pin, the device will

output MX29LA321M H/L device code.

MX29LA321M H/L also provides another method.Which

requires VID on the RESET# only. This method can be

implemented either in-system or via programming equip-

ment. This method uses standard microprocessor bus

cycle timing.

VERIFY SECTOR GROUP PROTECT STATUS

OPERATION

It is also possible to determine if the chip is unprotect in

the system by writing the Read Silicon ID command.

Performing a read operation with A2=VIH, it will produce

00H at data outputs (Q0-Q7) for an unprotect sector.It is

noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

MX29LA321M H/L provides hardware method for sector

group protect status verify. Which method requires VID

on A10 pin, VIH on WE# and A2 pins, VIL on CE#, OE#,

A7, and A1 pins, and sector address on A17 to A22 pins.

Which the identified sector is protected, the device will

output 01H.Which the identified sector is not protect, the

device will output 00H.

WRITE PROTECT (WP#)

The write protect function provides a hardware method

to protect all sectors without using V_ID.

DATA PROTECTION

The MX29LA321M H/L is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transition. During power up the device automatically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorporates several features to prevent inadvertent write

cycles resulting fromVCC power-up and power-down tran-

sition or system noise.

If the system asserts VIL on the WP# pin, the device

disables program and erase functions in all sectors inde-

pendently of whether those sectors were protected or

unprotect using the method described in Sector/Sector

Group Protection and Chip Unprotect".

If the system asserts VIH on the WP# pin, the device

reverts to whether the sectors were last set to be pro-

tected or unprotect. That is, sector protection or

unprotection for the sectors depends on whether they were

P/N:PM1145

REV. 1.0, FEB. 27, 2006

13

MX29LA321M H/L

SECURED SILICON SECTOR

FACTORY LOCKED:Secured Silicon Sector

Programmed and Protected At the Factory

The MX29LA321M H/L features a OTP memory region

where the system may access through a command se-

quence to create a permanent part identification as so

called Electronic Serial Number (ESN) in the device.

Once this region is programmed, any further modifica-

tion on the region is impossible.The secured silicon sec-

tor is a 128 words in length, and uses a Secured Silicon

Sector Indicator Bit (Q7) to indicate whether or not the

Secured Silicon Sector is locked when shipped from the

factory. This bit is permanently set at the factory and

cannot be changed, which prevent duplication of a fac-

tory locked part. This ensures the security of the ESN

once the product is shipped to the field.

In device with an ESN, the Secured Silicon Sector is

protected when the device is shipped from the factory.

The Secured Silicon Sector cannot be modified in any

way.A factory locked device has an 8-word random ESN

at address 000000h-000007h.

CUSTOMER LOCKABLE:Secured Silicon

Sector NOT Programmed or Protected At the

Factory

As an alternative to the factory-locked version, the device

may be ordered such that the customer may program

and protect the 128-word Secured Silicon Sector.

Programming and protecting the Secured Silicon Sector

must be used with caution since, once protected, there

is no procedure available for unprotected the Secured

Silicon Sector area and none of the bits in the Secured

Silicon Sector memory space can be modified in any

way.

The MX29LA321M H/L offers the device with Secured

Silicon Sector either factory locked or customer lock-

able.The factory-locked version is always protected when

shipped from the factory , and has the Secured Silicon

Sector Indicator Bit permanently set to a "1". The cus-

tomer-lockable version is shipped with the Secured Sili-

con Sector unprotected, allowing customers to utilize that

sector in any form they prefer. The customer-lockable

version has the secured sector Indicator Bit permanently

set to a "0". Therefore, the Secured Silicon Sector Indi-

cator Bit prevents customer, lockable device from being

used to replace devices that are factory locked.

The Secured Silicon Sector area can be protected using

one of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 15, except

that RESET# may be at eitherVIH orVID.This allows in-

system protection of the Secured Silicon Sector without

raising any device pin to a high voltage. Note that method

is only applicable to the Secured Silicon Sector.

The system access the Secured Silicon Sector through

a command sequence (refer to "Enter Secured Silicon/

Exit Secured Silicon Sector command Sequence). After

the system has written the Enter Secured Silicon Sector

command sequence, it may read the Secured Silicon

Sector by using the address normally occupied by the

first sector SA1. Once entry the Secured Silicon Sector

the operation of boot sectors is disabled but the operation

of main sectors is as normally. This mode of operation

continues until the system issues the Exit Secured Sili-

con Sector command sequence, or until power is removed

from the device. On power-up, or following a hardware

reset, the device reverts to sending command to sector

SA1.

Write the three-cycle Enter Secured Silicon Sector Region

command sequence, and then alternate method of sector

protection described in the :Sector Group Protection and

Unprotect" section.

Once the Secured Silicon Sector is programmed, locked

and verified, the system must write the Exit Secured

Silicon Sector Region command sequence to return to

reading and writing the remainder of the array.

Secured Silicon ESN factory

Customer

lockable

Sector address

range

locked

LOW VCC WRITE INHIBIT

000000h-000007h

ESN

Determined by

Customer

When VCC is less than VLKO the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down.The command register and all

000008h-00007Fh Unavailable

P/N:PM1145

REV. 1.0, FEB. 27, 2006

14

MX29LA321M H/L

internal program/erase circuits are disabled, and the de-

vice resets. Subsequent writes are ignored until VCC is

greater thanVLKO. The system must provide the proper

signals to the control pins to prevent unintentional write

whenVCC is greater thanVLKO.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on CE# or WE#

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

POWER-UP SEQUENCE

The MX29LA321M H/L powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

POWER-UP WRITE INHIBIT

If WE#=CE#=VIL and OE#=VIH during power up, the

device does not accept commands on the rising edge of

WE#. The internal state machine is automatically reset

to the read mode on power-up.

POWER SUPPLY DE COUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

15

MX29LA321M H/L

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

SOFTWARE COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. Table 3 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data are latched on

rising edge of WE# or CE#, whichever happens first.

TABLE 3. MX29LA321M H/L COMMAND DEFINITIONS

First Bus

Cycle

Second Bus Third Bus Fourth Bus

Cycle Cycle Cycle

Fifth Bus Sixth Bus

Cycle Cycle

Command

Bus

Cycles Addr Data Addr Data Addr Data Addr

Data

Addr Data Addr Data

Read (Note 5)

1

RA

RD

Reset (Note 6)

XXX F0

Automatic Select (Note 7)

Manufacturer ID

Word

Byte

4

3

4

6

1

3

6

1

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

555 90 X00

AAA 90 X00

555 90 X01

AAA 90 X02

555 90 X03

AAA 90 X06

C2H

ID1

Device ID

(Note 8)

Word

Byte

X0E ID2 X0F ID3

X1C ID2 X1E ID3

ID1

Secured Sector Fact- Word

see

ory Protect (Note 9)

Sector Group Protect

Verify (Note 10)

Enter Secured Silicon

Sector

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Note 9

555 90 (SA)X02 XX00/

AAA 90 (SA)X04 XX01

555 88

AAA 88

Exit Secured Silicon

Sector

555 90 XXX

AAA 90 XXX

555 A0 PA

AAA A0 PA

SA 25 SA

00

Program

PD

WC

BC

Write to Buffer (Note 11) Word

PA PD WBL PD

Byte

Program Buffer to Flash Word

Byte

SA

29

Write to Buffer Abort

Reset (Note 12)

Chip Erase

Word

Byte

Word

Byte

Word

Byte

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

XXX B0

XXX 30

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

555 F0

AAA F0

555 80 555

AAA 80 AAA

555 80 555

AAA 80 AAA

AA

2AA 55

555 55

2AA 55

555 55

555 10

AAA 10

SA 30

Sector Erase

Program/Erase Suspend (Note 13)

Program/Erase Resume (Note 14)

CFI Query (Note 15)

Word

Byte

55

AA

98

P/N:PM1145

REV. 1.0, FEB. 27, 2006

16

MX29LA321M H/L

Legend:

X=Don't care

PD=Data to be programmed at location PA. Data is

latched on the rising edge of WE# or CE# pulse.

SA=Address of the sector to be erase or verified (in

autoselect mode).

Address bits A21-A13 uniquely select any sector.

WBL=Write Buffer Location. Address must be within the

same write buffer page as PA.

RA=Address of the memory location to be read.

RD=Data read from location RA during read operation.

PA=Address of the memory location to be programmed.

Addresses are latched on the falling edge of the WE# or

CE# pulse, whichever happen later.

DDI=Data of device identifier

C2H for manufacture code

WC=Word Count. Number of write buffer locations to load

minus 1.

BC=Byte Count. Number of write buffer locations to load

minus 1.

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or automatic select data, all bus cycles are write operation.

4. Address bits are don't care for unlock and command cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in read mode.

6. The Reset command is required to return to the read mode when the device is in the automatic select mode or if

Q5 goes high.

7. The fourth cycle of the automatic select command sequence is a read cycle.

8. The device ID must be read in three cycles.The data is 01h for top boot and 00h for bottom boot.

9. If WP# protects the highest address sectors, the data is 98h for factory locked and 18h for not factory locked. If

WP# protects the lowest address sectors, the data is 88h for factory locked and 08h for not factor locked.

10. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block.

11. The total number of cycles in the command sequence is determined by the number of words written to the write

buffer.The maximum number of cycles in the command sequence is 21(Word Mode) / 37(Byte Mode).

12. Command sequence resets device for next command after aborted write-to-buffer operation.

13. The system may read and program functions in non-erasing sectors, or enter the automatic select mode, when in

the erase Suspend mode.The Erase Suspend command is valid only during a sector erase operation.

14. The Erase Resume command is valid only during the Erase Suspend mode.

15. Command is valid when device is ready to read array data or when device is in automatic select mode.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

17

MX29LA321M H/L

array data (also applies during Erase Suspend).

READING ARRAY DATA

The device is automatically set to reading array data

after device power-up. No commands are required to re-

trieve data. The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algorithm.

SILICON ID READ COMMAND SEQUENCE

The SILICON ID READ command sequence allows the

host system to access the manufacturer and devices

codes, and determine whether or not a sector is pro-

tected.Table 2 shows the address and data requirements.

This method is an alternative to that shown in Table 1,

which is intended for PROM programmers and requires

VID on address bit A10.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data. Af-

ter completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See Erase Suspend/Erase

Resume Commands for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or

while in the automatic select mode. See the "Reset Com-

mand" section, next.

The SILICON ID READ command sequence is initiated

by writing two unlock cycles, followed by the SILICON

ID READ command. The device then enters the SILI-

CON ID READ mode, and the system may read at any

address any number of times, without initiating another

command sequence. A read cycle at address XX00h

retrieves the manufacturer code. A read cycle at address

XX01h returns the device code. A read cycle containing

a sector address (SA) and the address 02h returns 01h if

that sector is protected, or 00h if it is unprotected. Refer

to Sector Address Table on page 6 and 7 for valid sector

addresses.

RESET COMMAND

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don't care for

this command.

The system must write the reset command to exit the

automatic select mode and return to reading array data.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data.Once erasure begins, however, the device ignores

reset commands until the operation is complete.

BYTE/WORD PROGRAM COMMAND SE-

QUENCE

The command sequence requires four bus cycles, and

is initiated by writing two unlock write cycles, followed

by the program set-up command.The program address

and data are written next, which in turn initiate the Em-

bedded Program algorithm. The system is not required

to provide further controls or timings. The device auto-

matically generates the program pulses and verifies the

programmed cell margin.Table 3 shows the address and

data requirements for the byte program command se-

quence.

The reset command may be written between the se-

quence cycles in a program command sequence before

programming begins. This resets the device to reading

array data (also applies to programming in Erase Sus-

pend mode). Once programming begins, however, the

device ignores reset commands until the operation is

complete.

The reset command may be written between the se-

quence cycles in an SILICON ID READ command se-

quence. Once in the SILICON ID READ mode, the reset

command must be written to return to reading array data

(also applies to SILICON ID READ during Erase Sus-

pend).

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses

are no longer latched. The system can determine the

status of the program operation by using Q7, Q6, or RY/

BY#. See "Write Operation Status" for information on

these status bits.

If Q5 goes high during a program or erase operation,

writing the reset command returns the device to reading

Any commands written to the device during the Embed-

P/N:PM1145

REV. 1.0, FEB. 27, 2006

18

MX29LA321M H/L

ded Program Algorithm are ignored.Note that a hardware

reset immediately terminates the programming operation.

The Byte/Word Program command sequence should be

reinitiated once the device has reset to reading array data,

to ensure data integrity.

Note that if a Write Buffer address location is loaded

multiple times, the address/data pair counter will be

decremented for every data load operation.The host sys-

tem must therefore account for loading a write-buffer lo-

cation more than once.The counter decrements for each

data load operation, not for each unique write-buffer-ad-

dress location. Note also that if an address location is

loaded more than once into the buffer, the final data loaded

for that address will be programmed.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the op-

eration and set Q5 to "1", or cause the Data# Polling

algorithm to indicate the operation was successful. How-

ever, a succeeding read will show that the data is still

"0". Only erase operations can convert a "0" to a "1".

Once the specified number of write buffer locations have

been loaded, the system must then write the Program

Buffer to Flash command at the sector address. Any

other address and data combination aborts the Write

Buffer Programming operation. The device then begins

programming. Data polling should be used while monitor-

ing the last address location loaded into the write buffer.

Q7, Q6, Q5, and Q1 should be monitored to determine

the device status during Write Buffer Programming.

Write Buffer Programming

Write Buffer Programming allows the system write to a

maximum of 16 words/32 bytes in one programming op-

eration.This results in faster effective programming time

than the standard programming algorithms. The Write

Buffer Programming command sequence is initiated by

first writing two unlock cycles.This is followed by a third

write cycle containing the Write Buffer Load command

written at the Sector Address in which programming will

occur. The fourth cycle writes the sector address and

the number of word locations, minus one, to be pro-

grammed. For example, if the system will program 6

unique address locations, then 05h should be written to

the device. This tells the device how many write buffer

addresses will be loaded with data and therefore when to

expect the Program Buffer to Flash command.The num-

ber of locations to program cannot exceed the size of

the write buffer or the operation will abort.

The write-buffer programming operation can be suspended

using the standard program suspend/resume commands.

Upon successful completion of the Write Buffer Program-

ming operation, the device is ready to execute the next

command.

TheWrite Buffer Programming Sequence can be aborted

in the following ways:

•

Load a value that is greater than the page buffer size

during the Number of Locations to Program step.

Write to an address in a sector different than the one

specified during the Write-Buffer-Load command.

Write an Address/Data pair to a different write-buffer-

page than the one selected by the Starting Address

during the write buffer data loading stage of the op-

eration.

The fifth cycle writes the first address location and data

to be programmed.The write-buffer-page is selected by

address bits A_MAX-4. All subsequent address/data pairs

must fall within the selected-write-buffer-page.The sys-

tem then writes the remaining address/data pairs into

the write buffer. Write buffer locations may be loaded in

any order.

•

Write data other than the Confirm Command after the

specified number of data load cycles.

The abort condition is indicated by Q1 = 1, Q7 = DATA#

(for the last address location loaded), Q6 = toggle, and

Q5=0.AWrite-to-Buffer-Abort Reset command sequence

must be written to reset the device for the next opera-

tion. Note that the full 3-cycle Write-to-Buffer-Abort Re-

set command sequence is required when using Write-

Buffer-Programming features in Unlock Bypass mode.

The write-buffer-page address must be the same for all

address/data pairs loaded into the write buffer. (This

means Write Buffer Programming cannot be performed

across multiple write-buffer pages.This also means that

Write Buffer Programming cannot be performed across

multiple sectors. If the system attempts to load program-

ming data outside of the selected write-buffer page, the

operation will abort.

Program Suspend/Program Resume Command

Sequence

The Program Suspend command allows the system to

P/N:PM1145

REV. 1.0, FEB. 27, 2006

19

MX29LA321M H/L

interrupt a programming operation or aWrite to Buffer pro-

gramming operation so that data can be read from any

non-suspended sector.When the Program Suspend com-

mand is written during a programming process, the de-

vice halts the program operation within 15us maximum

(5 us typical) and updates the status bits. Addresses are

not required when writing the Program Suspend com-

mand.

AUTOMATIC CHIP/SECTOR ERASE COM-

MAND

The device does not require the system to preprogram

prior to erase.The Automatic Erase algorithm automati-

cally pre-program and verifies the entire memory for an

all zero data pattern prior to electrical erase.The system

is not required to provide any controls or timings during

these operations. Table 3 shows the address and data

requirements for the chip erase command sequence.

After the programming operation has been suspended,

the system can read array data from any non-suspended

sector. The Program Suspend command may also be

issued during a programming operation while an erase is

suspended. In this case, data may be read from any

addresses not in Erase Suspend or Program Suspend. If

a read is needed from the Secured Silicon Sector area

(One-time Program area), then user must use the proper

command sequences to enter and exit this region.

Any commands written to the chip during the Automatic

Erase algorithm are ignored. Note that a hardware reset

during the chip erase operation immediately terminates

the operation.The Chip Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

The system may also write the autoselect command

sequence when the device is in the Program Suspend

mode. The system can read as many autoselect codes

as required.When the device exits the autoselect mode,

the device reverts to the Program Suspend mode, and

is ready for another valid operation. See Autoselect Com-

mand Sequence for more information.

The system can determine the status of the erase op-

eration by using Q7, Q6, Q2, or RY/BY#.See "Write Op-

eration Status" for information on these status bits.When

the Automatic Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched.

Figure 10 illustrates the algorithm for the erase opera-

tion. See the Erase/Program Operations tables in "AC

Characteristics" for parameters, and to Figure 9 for tim-

ing diagrams.

After the Program Resume command is written, the de-

vice reverts to programming.The system can determine

the status of the program operation using the Q7 or Q6

status bits, just as in the standard program operation.

See Write Operation Status for more information.

SETUP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H, or

the sector erase command 30H.

The MX29LA321M H/L contains a Silicon-ID-Read op-

eration to supplement traditional PROM programming

methodology. The operation is initiated by writing the read

silicon ID command sequence into the command regis-

ter. Following the command write, a read cycle with

A2=VIL,A1=VIL retrieves the manufacturer code.A read

cycle with A2=VIL, A1=VIH returns the device code.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

20

MX29LA321M H/L

device requires a maximum 20us to suspend the sector

erase operation.However,When the Erase Suspend com-

mand is written during the sector erase time-out, the

device immediately terminates the time-out period and

suspends the erase operation. After this command has

been executed, the command register will initiate erase

suspend mode. The state machine will return to read

mode automatically after suspend is ready. At this time,

state machine only allows the command register to re-

spond to the Erase Resume, program data to, or read

data from any sector not selected for erasure.

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Set-up Sector Erase command and Automatic

Sector Erase command. Upon executing the Automatic

Sector Erase command, the device will automatically

program and verify the sector(s) memory for an all-zero

data pattern. The system is not required to provide any

control or timing during these operations.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended blocks.

ERASE RESUME

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array

(no erase verification command is required). Sector erase

is a six-bus cycle operation. There are two "unlock" write

cycles. These are followed by writing the set-up com-

mand 80H. Two more "unlock" write cycles are then fol-

lowed by the sector erase command 30H. The sector

address is latched on the falling edge of WE# or CE#,

whichever happens later , while the command (data) is

latched on the rising edge of WE# or CE#, whichever

happens first. Sector addresses selected are loaded

into internal register on the sixth falling edge of WE# or

CE#, whichever happens later. Each successive sector

load cycle started by the falling edge of WE# or CE#,

whichever happens later must begin within 50us from

the rising edge of the precedingWE# or CE#, whichever

happens first. Otherwise, the loading period ends and

internal auto sector erase cycle starts. (Monitor Q3 to

determine if the sector erase timer window is still open,

see section Q3, Sector EraseTimer.) Any command other

than Sector Erase(30H) or Erase Suspend(B0H) during

the time-out period resets the device to read mode.

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

Sector Erase operation. When the Erase Suspend com-

mand is issued during the sector erase operation, the

P/N:PM1145

REV. 1.0, FEB. 27, 2006

21

MX29LA321M H/L

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Standby mode, and Read ID mode;however, it is ignored

otherwise.

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE

MX29LA321M H/L is capable of operating in the CFI mode.

This mode all the host system to determine the manu-

facturer of the device such as operating parameters and

configuration.Two commands are required in CFI mode.

Query command of CFI mode is placed first, then the

Reset command exits CFI mode.These are described in

Table 4.

The Reset command exits from the CFI mode to the

Read mode, or Erase Suspend mode, or read ID mode.

The command is valid only when the device is in the CFI

mode.

Table 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Addressh Addressh

Datah

(x16)

10

(x8)

20

22

24

26

28

2A

2C

2E

30

32

34

Query-unique ASCII string "QRY"

0051

0052

0059

0002

0000

0040

0000

11

12

Primary vendor command set and control interface ID code

Address for primary algorithm extended query table

13

14

15

16

Alternate vendor command set and control interface ID code (none)

Address for secondary algorithm extended query table (none)

17

18

19

1A

Table 4-2. CFI Mode: System Interface Data Values

Description

Addressh Addressh

Datah

(x16)

1B

1C

1D

1E

1F

20

(x8)

36

VCC supply, minimum (2.7V)

0027

0036

0000

0007

000A

0000

0001

0005

0004

0000

VCC supply, maximum (3.6V)

38

VPP supply, minimum (none)

3A

3C

3E

40

VPP supply, maximum (none)

Typical timeout for single word/byte write (2^Nus)

Typical timeout for maximum size buffer write (2^Nus)

Typical timeout for individual block erase (2^Nms)

Typical timeout for full chip erase (2^Nms)

Maximum timeout for single word/byte write times (2^NX Typ)

Maximum timeout for maximum size buffer write times (2^NX Typ)

Maximum timeout for individual block erase times (2^NX Typ)

Maximum timeout for full chip erase times (not supported)

21

42

22

44

23

46

24

48

25

4A

4C

26

P/N:PM1145

REV. 1.0, FEB. 27, 2006

22

MX29LA321M H/L

Table 4-3. CFI Mode: Device Geometry Data Values

Description

Addressh Addressh

Datah

(x16)

27

(x8)

4E

50

52

54

56

58

5A

5C

5E

60

62

64

66

68

6A

6C

6E

70

72

74

76

78

Device size (2ⁿbytes)

0016

0002

0000

0005

0000

0001

003F

0000

0001

0000

Flash device interface code

28

29

Maximum number of bytes in multi-byte write = 2ⁿ

2A

2B

2C

2D

2E

2F

30

Number of erase block regions

Erase block region 1 information

[2E,2D] = # of blocks in region -1

[30, 2F] = size in multiples of 256-bytes

31

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

32

33

34

35

36

37

38

39

3A

3B

3C

P/N:PM1145

REV. 1.0, FEB. 27, 2006

23

MX29LA321M H/L

Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

Description

Addressh Addressh

Datah

(x16)

40

(x8)

80

82

84

86

88

8A

8C

8E

90

92

94

96

98

9A

Query-unique ASCII string "PRI"

0050

0052

0049

0031

0033

0000

0002

0001

0000

0004

0000

0001

00B5

41

42

Major version number, ASCII

43

Minor version number, ASCII

44

Address sensitive unlock (0=required, 1= not required)

Erase suspend (2= to read and write)

Sector protect (N= # of sectors/group)

Temporarysectorunprotect(1=supported)

Sector protect/unprotect scheme

45

46

47

48

49

SimultaneousR/Woperation(0=notsupported)

Burst mode type (0=not supported)

Page mode type (1=4 word page)

4A

4B

4C

4D

ACC (Acceleration) Supply Minimum

00h=NotSupported,D7-D4:Volt,D3-D0:100mV

ACC (Acceleration) Supply Maximum

00h=NotSupported,D7-D4:Volt,D3-D0:100mV

Top/Bottom Boot Sector Flag

4E

4F

9C

9E

00C5

0004/

0005

02h=Bottom Boot Device, 03h=Top Boot Device

04h=uniform sectors bottom WP# protect,

05h=uniform sectors top WP# protect

ProgramSuspend

50

A0

0001

00h=NotSupported,01h=Supported

P/N:PM1145

REV. 1.0, FEB. 27, 2006

24

MX29LA321M H/L

WRITE OPERATION STATUS

The device provides several bits to determine the status

of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#.

Table 5 and the following subsections describe the func-

tions of these bits. Q7, RY/BY#, and Q6 each offer a

method for determining whether a program or erase op-

eration is complete or in progress. These three bits are

discussed first.

Table 5. Write Operation Status

Status

Q7

Q6

Q5

Q3

Q2

No

Q1

RY/BY#

Byte/Word Program in Auto Program Algorithm

Q7# Toggle

0

N/A

0

Toggle

Auto Erase Algorithm

Erase Suspend Read

0

1

Toggle

No

0

1

Toggle N/A

0

1

N/A Toggle N/A

Erase

(Erase Suspended Sector)

Erase Suspend Read

Toggle

Suspended

Mode

Data

Data Data

Data Data Data

1

(Non-Erase Suspended Sector)

Erase Suspend Program

Q7# Toggle

0

N/A

0

1

Program-SuspendedRead

(Program-SuspendedSector)

Program-SuspendedRead

(Non-Program-SuspendedSector)

Invalid (not allowed)

Program

Suspend

Data

1

Write-to-Buffer Busy

Abort

Q7# Toggle

0

N/A

0

1

0

Notes:

1. Q5 switches to "1" when an Word/Byte Program, Erase, or Write-to-Buffer operation has exceeded the maximum

timing limits. Refer to the section on Q5 for more information.

2.Q7 and Q2 require a valid address when reading status information.Refer to the appropriate subsection for further

details.

3.The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.

4. Q1 switches to "1" when the device has aborted the write-to-buffer operation.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

25

MX29LA321M H/L

happens first pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

Q7: Data# Polling

The Data# Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend. Data#

Polling is valid after the rising edge of the finalWE# pulse

in the program or erase command sequence.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

control the read cycles.When the operation is complete,

Q6 stops toggling.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7.This Q7 status also applies to programming dur-

ing Erase Suspend.When the Automatic Program algo-

rithm is complete, the device outputs the datum pro-

grammed to Q7.The system must provide the program

address to read valid status information on Q7. If a pro-

gram address falls within a protected sector, Data# Poll-

ing on Q7 is active for approximately 1 us, then the de-

vice returns to reading array data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles for

100us and returns to reading array data. If not all se-

lected sectors are protected, the Automatic Erase algo-

rithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase suspended.

When the device is actively erasing (that is, the Auto-

matic Erase algorithm is in progress), Q6 toggling.When

the device enters the Erase Suspend mode, Q6 stops

toggling. However, the system must also use Q2 to de-

termine which sectors are erasing or erase-suspended.

Alternatively, the system can use Q7.

During the Automatic Erase algorithm, Data# Polling pro-

duces a "0" on Q7.When the Automatic Erase algorithm

is complete, or if the device enters the Erase Suspend

mode, Data# Polling produces a "1" on Q7.This is analo-

gous to the complement/true datum output described for

the Automatic Program algorithm: the erase function

changes all the bits in a sector to "1" prior to this, the

device outputs the "complement," or "0". The system

must provide an address within any of the sectors se-

lected for erasure to read valid status information on Q7.

If a program address falls within a protected sector, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling on

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

Table 5 shows the outputs for Toggle Bit I on Q6.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output Enable

(OE#) is asserted low.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit II is valid

after the rising edge of the final WE# or CE#, whichever

happens first pulse in the command sequence.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE# or CE#, whichever

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE# or CE# to control the read

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

P/N:PM1145

REV. 1.0, FEB. 27, 2006

26

MX29LA321M H/L

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 5 to compare outputs for Q2 and Q6.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte/word pro-

gramming operation, it specifies that the entire sector

containing that byte is bad and this sector may not be

reused, (other sectors are still functional and can be re-

used).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

The Q5 failure condition may appear if the system tries

to program a to a "1" location that is previously pro-

grammed to "0". Only an erase operation can change a

"0" back to a "1". Under this condition, the device halts

the operation, and when the operation has exceeded the

timing limits, Q5 produces a "1".

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it returns to determine the status of the

operation.

Q3:Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data# Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

Q5:Program/Erase Timing

Q5 will indicate if the program or erase time has exceeded

the specified limits (internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data# Polling and Toggle Bit are

the only operating functions of the device under this con-

dition.

If Data# Polling or the Toggle Bit indicates the device

has been written with a valid erase command, Q3 may

be used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data# Polling or

P/N:PM1145

REV. 1.0, FEB. 27, 2006

27

MX29LA321M H/L

Toggle Bit. If Q3 is low ("0"), the device will accept addi-

tional sector erase commands. To insure the command

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been accepted.

If the time between additional erase commands from the

system can be less than 50us, the system need not to

monitor Q3.

Q1: Write-to-Buffer Abort

Q1 indicates whether a Write-to-Buffer operation was

aborted.Under these conditions Q1 produces a "1".The

system must issue theWrite-to-Buffer-Abort-Reset com-

mand sequence to return the device to reading array data.

See Write Buffer section for more details.

RY/BY#:READY/BUSY OUTPUT

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in progress

or complete. The RY/BY# status is valid after the rising

edge of the final WE# pulse in the command sequence.

Since RY/BY# is an open-drain output, several RY/BY#

pins can be tied together in parallel with a pull-up resistor

to VCC .

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device

is ready to read array data (including during the Erase

Suspend mode), or is in the standby mode.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

28

MX29LA321M H/L

OPERATING RATINGS

ABSOLUTE MAXIMUM RATINGS

StorageTemperature

Commercial (C) Devices

Plastic Packages . . . . . . . . . . . . . ..... -65^oC to +150^oC

Ambient Temperature (T^A). . . . . . . . . . . . . 0° C to +70°C

Industrial (I) Devices

AmbientTemperature

with Power Applied. . . . . . . . . . . . . .... -65^oC to +125^oC

Voltage with Respect to Ground

Ambient Temperature (T^A). . . . . . . . . . . -40°C to +85°C

VCC Supply Voltages

VCC for full voltage range. . . . . . . . . . . . +2.7 V to 3.6 V

VCC for regulated voltage range. . . . . . . +3.0 V to 3.6 V

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A10, OE#, and

RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Operating ranges define those limits between which the

functionality of the device is guaranteed.

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-

mum DC voltage on input or I/O pins is VCC +0.5 V.

During voltage transitions, input or I/O pins may over-

shoot to VCC +2.0 V for periods up to 20ns.

2. Minimum DC input voltage on pins A10, OE#, and

RESET# is -0.5 V. During voltage transitions, A10,

OE#, and RESET# may overshoot VSS to -2.0 V for

periods of up to 20 ns. Maximum DC input voltage on

pin A10 is +12.5 V which may overshoot to 14.0 V for

periods up to 20 ns.

3.No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

29

MX29LA321M H/L

DC CHARACTERISTICS

for 70R)

TA=-40°C to 85°C, VCC=2.7V~3.6V (TA=0°C to 70° C, VCC=3.0V~3.6V

Para-

meter Description

Test Conditions

Min.

Typ.

Max.

Unit

I LI

Input Load Current (Note 1)

VIN = VSS to VCC ,

VCC = VCC max

±1.0

uA

I LIT A10 Input Leakage Current

I LO Output Leakage Current

VCC=VCC max; A10= 12.5V

VOUT = VSS to VCC ,

VCC=VCC max

35

uA

±1.0

ICC1 VCC Initial Read Current

(Notes 2,3)

CE#= VIL,

OE# = VIH

10 MHz

5 MHz

35

18

5

50

25

20

40

60

mA

1 MHz

ICC2 VCC Intra-Page Read

Current (Notes 2,3)

ICC3 VCC Active Write Current

(Notes 2,4,6)

CE#= VIL ,

OE# = VIH

10 MHz

40 MHz

5

10

50

CE#= VIL , OE# = VIH

WE#=VIL

ICC4 VCC Standby Current

(Note 2)

CE#,RESET#=VCC±0.3V

WP#=VIH

20

50

uA

ICC5 VCC Reset Current

(Note 2)

RESET#=VSS±0.3V

WP#=VIH

ICC6 Automatic Sleep Mode

(Notes 2,5)

VIL = V SS ± 0.3 V,

VIH = VCC ±0.3 V,

WP#=VIH

VIL

Input LowVoltage

-0.5

0.7xVCC

11.5

0.8

VCC+0.5

12.5

V

VIH Input HighVoltage

VHH Voltage for ACC Program

Acceleration

VCC = 2.7V ~ 3.6V

12.0

VID Voltage for Autoselect

VCC = 3.0 V ±10%

11.5

12.5

0.45

V

VOL Output LowVoltage

VOH1 Output HighVoltage

VOH2

IOL= 4.0mA,VCC=VCC min

V

IOH=-2.0mA,VCC=VCC min 0.85VCC

IOH=-100uA,VCC=VCC min VCC-0.4

2.3

VLKO LowVCC Lock-OutVoltage

(Note 4)

2.5

Notes:

1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ±5.0uA.

2. Maximum ICC specifications are tested with VCC = VCC max.

3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH. Typical specifications are for VCC =

3.0V.

4. ICC active while Embedded Erase or Embedded Program is in progress.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns.

6. Not 100% tested.

7. A9=12.5V whenTA=0°C to 85°C, A9=12V when whenTA=-40°C to 0°C.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

30

MX29LA321M H/L

SWITCHING TEST CIRCUITS

TEST SPECIFICATIONS

Test Condition

All Speeds

1 TTL gate

30

Unit

pF

Output Load

DEVICE UNDER

TEST

2.7K ohm

Output Load Capacitance, CL

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

3.3V

5

ns

V

0.0-3.0

1.5

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

Input timing measurement

reference levels

V

Output timing measurement

reference levels

1.5

V

KEY TO SWITCHING WAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State(High Z)

SWITCHING TEST WAVEFORMS

3.0V

0.0V

Measurement Level

1.5V

INPUT

OUTPUT

P/N:PM1145

REV. 1.0, FEB. 27, 2006

31

MX29LA321M H/L

AC CHARACTERISTICS

Read-Only Operations TA=-40°C to 85°C, VCC=2.7V~3.6V (TA=0°C to 70° C, VCC=3.0V~3.6V for

70R)

Parameter

Std.

Speed Options

Description

Test Setup

70R

70

90

25

35

Unit

ns

tRC

Read CycleTime (Note 1)

Address to Output Delay

Min

CE#, OE#=VIL Max

tACC

tCE

70

Chip Enable to Output Delay

Page Access Time

OE#=VIL

Max

Min

70

tPACC

tOE

25

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

Output HoldTime From Address, CE#

or OE#, whichever Occurs First

Read

35

tDF

16

0

tDF

tOH

Min

35

10

ns

tOEH

Output Enable HoldTime Toggle and

(Note 1)

Data# Polling

Notes:

1. Not 100% tested.

2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

32

MX29LA321M H/L

Figure 1. READ TIMING WAVEFORMS

tRC

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE#

tRH

VIL

tRH

VIH

WE#

tDF

VIL

VIH

VIL

tOEH

tOE

OE#

tOH

tACC

HIGH Z

VOH

VOL

Outputs

DATA Valid

VIH

VIL

RESET#

RY/BY#

0V

Figure 2. PAGE READ TIMING WAVEFORMS

Same Page

A3-A21

(A0), A1~A2

tACC

CE#

tPACC

OE#

Qa

Qb

Qc

Qd

Output

P/N:PM1145

REV. 1.0, FEB. 27, 2006

33

MX29LA321M H/L

AC CHARACTERISTICS

Parameter Description

Test Setup All Speed Options Unit

tREADY1

RESET# PIN Low (During Automatic Algorithms)

MAX

20

us

to Read or Write (See Note)

tREADY2

RESET# PIN Low (NOT During Automatic Algorithms)

to Read or Write (See Note)

MAX

500

ns

tRP

RESET# Pulse Width (NOT During Automatic Algorithms)

RESET# HighTime Before Read (See Note)

RY/BY# Recovery Time(to CE#, OE# go low)

RESET# Low to Standby Mode

MIN

500

50

0

ns

us

tRH

tRB

tRPD

20

Note:Not 100% tested

Figure 3. RESET# TIMING WAVEFORM

RY/BY#

CE#, OE#

tRH

RESET#

tRP

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY#

tRB

CE#, OE#

RESET#

tRP

Reset Timing during Automatic Algorithms

P/N:PM1145

REV. 1.0, FEB. 27, 2006

34

MX29LA321M H/L

AC CHARACTERISTICS

Erase and Program Operations

TA=-40° C to 85°C,VCC=2.7V~3.6V (TA=0°C to 70°C, VCC=3.0V~3.6V for 70R)

Parameter

Std.

Speed Options

Description

70R

90

Unit

ns

tWC

Write CycleTime (Note 1)

Address SetupTime

Min

70

90

tAS

0

15

45

0

ns

tASO

tAH

Address Setup Time to OE# low during toggle bit polling

Address HoldTime

ns

tAHT

Address HoldTime From CE# or OE# high during toggle

bit polling

ns

tDS

Data SetupTime

Min

35

0

ns

tDH

Data HoldTime

tCEPH

tOEPH

tGHWL

CE# High DuringToggle Bit Polling

Output Enable High during toggle bit polling

Read RecoveryTime BeforeWrite

(OE# High to WE# Low)

20

0

tGHEL

tCS

Read RecoveryTime BeforeWrite

CE# SetupTime

Min

Typ

Min

Max

0

ns

us

sec

us

ns

us

tCH

CE# HoldTime

0

tWP

Write PulseWidth

35

30

240

60

54

0.5

50

0

tWPH

Write PulseWidth High

Write Buffer Program Operation (Notes 2,3)

SingleWord/Byte Program

Byte

Word

Byte

Word

tWHWH1

Operation (Notes 2,5)

Accelerated Single Word/Byte

Programming Operation (Notes 2,5)

Sector Erase Operation (Note 2)

VCC SetupTime (Note 1)

tWHWH2

tVCS

tRB

Write RecoveryTime from RY/BY#

Program/EraseValid to RY/BY# Delay

VHH Rise and FallTime (Note 1)

Program Valid Before Status Polling (Note 6)

tBUSY

tVHH

70

90

250

4

tPOLL

Notes:

1. Not 100% tested.

2.See the "Erase And Programming Performance" section for more information.

3.For 1-16 words/1-32 bytes programmed.

4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5.Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write

buffer.

6.When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be

fully re-applied upon resuming the programming operation.If the suspend command is issued after tPOLL, tPOLL is

not required again prior to reading the status bits upon resuming.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

35

MX29LA321M H/L

ERASE/PROGRAM OPERATION

Figure 4. AUTOMATIC PROGRAM TIMING WAVEFORMS

Program Command Sequence(last two cycle)

Read Status Data (last two cycle)

tWC

tAS

PA

XXXh

PA

Address

CE#

tAH

tCH

OE#

WE#

tWP

tWHWH1

tCS

tWPH

tDS tDH

Status

A0h

PD

DOUT

Data

tBUSY

tRB

RY/BY#

tVCS

VCC

Note :

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

Figure 5. ACCELERATED PROGRAM TIMING DIAGRAM

VHH

ACC

VIL or VIH

tVHH

P/N:PM1145

REV. 1.0, FEB. 27, 2006

36

MX29LA321M H/L

Figure 6. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Data Poll

Increment

Address

from system

No

Verify Word Ok ?

YES

Last Address ?

YES

Auto Program Completed

P/N:PM1145

REV. 1.0, FEB. 27, 2006

37

MX29LA321M H/L

Figure 7. WRITE BUFFER PROGRAMMING ALGORITHM FLOWCHART

Write "Write to Buffer"

command and

Sector Address

Write number of addresses

to program minus 1(WC)

and Sector Address

Part of "Write to Buffer"

Command Sequence

Write first address/data

Yes

WC = 0 ?

No

Yes

Write to a different

sector address

Abort Write to

Buffer Operation ?

No

Write to buffer ABORTED.

Must write "Write-to-buffer

Abort Reset" command sequence

to return to read mode.

Write next address/data pair

(Note 1)

WC = WC - 1

Write program buffer

to flash sector address

Notes:

1. When Sector Address is specified, any address in

Read Q7~Q0 at Last

Loaded Address

the selected sector is acceptable. However, when

loading Write-Buffer address locations with data, all

addresses must fall within the selected Write-Buffer

Page.

Yes

2. Q7 may change simultaneously with Q5.

Therefore, Q7 should be verified.

Q7 = Data ?

No

3. If this flowchart location was reached because Q5=

"1" then the device FAILED. If this flowchart location

was reached because Q1="1", then the Write to

Buffer operation was ABORTED. In either case, the

proper reset command must be written before the

device can begin another operation. If Q1=1, write

the Write-Buffer-Programming-Abort-Reset com-

mand. If Q5=1, write the Reset command.

4. See Table 3 for command sequences required for

write buffer programming.

No

Q1 = 1 ?

Yes

Q5 = 1 ?

Yes

Read Q7~Q0 with address

= Last Loaded Address

Yes

(Note 2)

(Note 3)

Q7 and Q15 = Data ?

No

FAIL or ABORT

PASS

P/N:PM1145

REV. 1.0, FEB. 27, 2006

38

MX29LA321M H/L

Figure 8. PROGRAM SUSPEND/RESUME FLOWCHART

Program Operation

or Write-to-Buffer

Sequence in Progress

Write Program Suspend

Command Sequence

Command is also valid for

Erase-suspended-program

operations

Write address/data

XXXh/B0h

Wait 15us

Autoselect and Secured Sector

read operations are also allowed

Data cannot be read from erase-or

program-suspended sectors

Read data as

required

No

Done reading ?

Yes

Write Program Resume

Command Sequence

Write address/data

XXXh/30h

Device reverts to

operation prior to

Program Suspend

P/N:PM1145

REV. 1.0, FEB. 27, 2006

39

MX29LA321M H/L

Figure 9. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

VA

tWC

tAS

VA

2AAh

SA

Address

CE#

555h for chip erase

tAH

tCH

OE#

WE#

tWHWH2

tWP

tCS

tWPH

tDS tDH

In

Progress

55h

30h

Complete

Data

10 for Chip Erase

tBUSY

tRB

RY/BY#

tVCS

VCC

Note :

1. SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

P/N:PM1145

REV. 1.0, FEB. 27, 2006

40

MX29LA321M H/L

Figure 10. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data Poll

from system

YES

No

DATA = FFh ?

YES

Auto Erase Completed

P/N:PM1145

REV. 1.0, FEB. 27, 2006

41

MX29LA321M H/L

Figure 11. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Last Sector

to Erase ?

YES

Data Poll from System

NO

Data=FFh?

YES

Auto Sector Erase Completed

P/N:PM1145

REV. 1.0, FEB. 27, 2006

42

MX29LA321M H/L

Figure 12. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

ERASE SUSPEND

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

ERASE RESUME

Continue Erase

Another

NO

Erase Suspend ?

YES

P/N:PM1145

REV. 1.0, FEB. 27, 2006

43

MX29LA321M H/L

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

TA=-40°C to 85° C,VCC=2.7V~3.6V (TA=0°C to 70° C, VCC=3.0V~3.6V for 70R)

Parameter

Std.

Speed Options

Description

70R

90

Unit

ns

tWC

Write CycleTime (Note 1)

Address SetupTime

Min

70

90

tAS

0

45

35

0

ns

tAH

Address HoldTime

ns

tDS

Data SetupTime

ns

tDH

Data HoldTime

ns

tGHEL

Read RecoveryTime Before Write

(OE# High to WE# Low)

WE# SetupTime

0

ns

tWS

tWH

tCP

Min

Typ

Min

Max

0

ns

us

sec

ns

us

WE# HoldTime

CE# PulseWidth

35

25

240

60

54

0.5

50

4

tCPH

CE# Pulse Width High

Write Buffer Program Operation (Notes 2,3)

SingleWord/Byte Program

Operation (Notes 2,5)

Byte

Word

Byte

Word

tWHWH1

Accelerated Single Word/Byte

Programming Operation (Notes 2,5)

Sector Erase Operation (Note 2)

RESET HIGHTime BeforeWrite (Note 1)

Program Valid Before Status Polling (Note 6)

tWHWH2

tRH

tPOLL

Notes:

1. Not 100% tested.

2.See the "Erase And Programming Performance" section for more information.

3.For 1-16 words/1-32 bytes programmed.

4.Effective write buffer specification is based upon a 16-word/32-byte write buffer operation.

5.Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write

buffer.

6.When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be

fully re-applied upon resuming the programming operation.If the suspend command is issued after tPOLL, tPOLL is

not required again prior to reading the status bits upon resuming.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

44

MX29LA321M H/L

Figure 13. CE# CONTROLLED PROGRAM TIMING WAVEFORM

PA for program

555 for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Address

PA

tWC

tWH

tAS

tAH

WE#

OE#

tGHEL

tCP

tWHWH1 or 2

CE#

Data

tWS

tDS

tCPH

tBUSY

tDH

Q7

DOUT

PD for program

30 for sector erase

10 for chip erase

A0 for program

55 for erase

tRH

RESET#

RY/BY#

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

45

MX29LA321M H/L

SECTOR GROUP PROTECT/CHIP UNPROTECT

Figure 14. Sector Group Protect / Chip Unprotect Waveform (RESET# Control)

VID

VIH

RESET#

SA, A7

A2, A1

Valid*

Sector Group Protect or Chip Unprotect

Verify

40h

Status

Data

60h

Sector Group Protect:150us

Chip Unprotect:15ms

1us

CE#

WE#

OE#

Note: For sector group protect A7=0, A2=1, A1=0. For chip unprotect A7=1, A2=1, A1=0

P/N:PM1145

REV. 1.0, FEB. 27, 2006

46

MX29LA321M H/L

Figure 15. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH

RESET#=VID

START

Protect all sectors:

The indicated portion of

the sector protect algorithm

must be performed

PLSCNT=1

RESET#=VID

Wait 1us

PLSCNT=1

RESET#=VID

Wait 1us

for all unprotected sectors

prior to issuing the first

sector unprotect address

First Write

Cycle=60h

First Write

Cycle=60h

Set up sector address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A7=0, A2=1, A1=0

Yes

Set up first sector address

Wait 150us

Sector Unprotect:

Write 60h to sector

address with

Verify Sector Protect:

Write 40h to sector

address with

Reset

PLSCNT=1

A7=1, A2=1, A1=0

A7=0, A2=1, A1=0

Increment PLSCNT

Wait 15 ms

Read from

sector address

with

A7=0, A2=1, A1=0

Verify Sector Unprotect:

Write 40h to sector

address with

No

Increment PLSCNT

A7=1, A2=1, A1=0

No

Data=01h?

Yes

PLSCNT=25?

Read from

sector address

with

Yes

A7=1, A2=1, A1=0

No

Device failed

Reset

Yes

Protect another

sector?

PLSCNT=1

No

PLSCNT=1000?

Data=00h?

Yes

No

Sector Protect

Algorithm

Yes

Remove VID from RESET#

Device failed

No

Last sector

verified?

Write reset command

Yes

Chip Unprotect

Algorithm

Sector Protect complete

Remove VID from RESET#

Write reset command

Sector Unprotect complete

P/N:PM1145

REV. 1.0, FEB. 27, 2006

47

MX29LA321M H/L

AC CHARACTERISTICS

Parameter

tVLHT

Description

Test Setup

Min.

All Speed Options Unit

Voltage transition time

4

100

4

us

ns

us

tWPP1

Write pulse width for sector group protect

OE# setup time to WE# active

Min.

tOESP

Min.

Figure 16. SECTOR GROUP PROTECT TIMING WAVEFORM (A10, OE# Control)

A2

A7

12V

3V

A10

tVLHT

Verify

12V

3V

OE#

tVLHT

tWPP 1

WE#

tOESP

CE#

Data

01H

F0H

tOE

Sector Address

A21-A17

P/N:PM1145

REV. 1.0, FEB. 27, 2006

48

MX29LA321M H/L

Figure 17. SECTOR GROUP PROTECTION ALGORITHM (A10, OE# Control)

START

Set Up Sector Addr

PLSCNT=1

OE#=VID, A10=VID, CE#=VIL

A7=VIL

Activate WE# Pulse

Time Out 150us

Set WE#=VIH, CE#=OE#=VIL

A10 should remain VID

Read from Sector

Addr=SA, A2=1

No

Data=01H?

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector?

Remove VID from A10

Write Reset Command

Sector Protection

Complete

P/N:PM1145

REV. 1.0, FEB. 27, 2006

49

MX29LA321M H/L

Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A10, OE# Control)

A2

12V

3V

A10

A7

tVLHT

Verify

12V

3V

OE#

tVLHT

tWPP 2

WE#

CE#

tOESP

Data

00H

F0H

tOE

P/N:PM1145

REV. 1.0, FEB. 27, 2006

50

MX29LA321M H/L

Figure 19. CHIP UNPROTECT FLOWCHART (A10, OE# Control)

START

Protect All Sectors

PLSCNT=1

Set OE#=A10=VID

CE#=VIL, A7=1

Activate WE# Pulse

Time Out 15ms

Increment

PLSCNT

Set OE#=CE#=VIL

A10=VID, A2=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

PLSCNT=1000?

Increment

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A10

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

51

MX29LA321M H/L

Figure 20. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART

START

Enter Secured Silicon Sector

Wait 1us

First Wait Cycle Data=60h

Second Wait Cycle Data=60h

A7=0, A2=1, A1=0

Wait 300us

No

Data = 01h ?

Yes

Device Failed

Write Reset Command

Secured Sector Protect Complete

P/N:PM1145

REV. 1.0, FEB. 27, 2006

52

MX29LA321M H/L

Figure 21. SILICON ID READ TIMING WAVEFORM

VCC

3V

VID

ADD

A10

VIH

VIL

VIH

VIL

ADD

A1

tACC

VIH

VIL

A2

A3

VIH

VIL

VIH

VIL

ADD

CE#

VIH

VIL

tCE

VIH

VIL

WE#

OE#

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q15

DATA OUT

Manufacturer ID

DATA OUT

Device ID

Cycle 1

Device ID

Cycle 2

Device ID

Cycle 3

P/N:PM1145

REV. 1.0, FEB. 27, 2006

53

MX29LA321M H/L

WRITE OPERATION STATUS

Figure 22. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE#

tACC

tCE

tCH

tOE

OE#

WE#

tOEH

tDF

tOH

High Z

Complement

Status Data

True

Valid Data

Q7

Q0-Q6

True

tBUSY

RY/BY#

Note :

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

54

MX29LA321M H/L

Figure 23. DATA# POLLING ALGORITHM

Start

Read Q7~Q0

Add.=VA(1)

Yes

Q7 = Data ?

No

Q5 = 1 ?

Yes

Read Q7~Q0

Add.=VA

Yes

(2)

Q7 = Data ?

No

FAIL

Pass

Notes:

1.VA=valid address for programming.

2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

55

MX29LA321M H/L

Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE#

tACC

tCE

tCH

tOE

OE#

tOEH

tDF

WE#

tOH

tDH

Valid Status

(second read)

Valid Status

(first read)

Valid Data

Q6/Q2

Valid Status

(stops toggling)

RY/BY#

Note :

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and

array data read cycle.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

56

MX29LA321M H/L

Figure 25. TOGGLE BIT ALGORITHM

START

Read Q7~Q0

(Note 1)

NO

Toggle Bit Q6

=Toggle?

YES

NO

Q5=1?

YES

(Note 1,2)

Read Q7~Q0 Twice

Toggle Bit Q6=

Toggle?

YES

Program/Erase Operation Not

Program/Erase Operation Complete

Complete, Write Reset Command

Notes :

1. Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".

P/N:PM1145

REV. 1.0, FEB. 27, 2006

57

MX29LA321M H/L

Figure 26. Q6 versus Q2

Enter Embedded

Erasing

Erase

Enter Erase

Erase

Suspend

Suspend Program

Resume

Erase

Erase Suspend

Read

Erase

Erase Suspend

Read

Erase

WE#

Q6

Suspend

Program

Complete

Q2

Note :

The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

P/N:PM1145

REV. 1.0, FEB. 27, 2006

58

MX29LA321M H/L

RECOMMENDED OPERATING CONDITIONS

At Device Power-Up

AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.

If the timing in the figure is ignored, the device may not operate correctly.

VCC(min)

VCC

GND

tVR

tACC

tR or tF

VIH

VIL

Valid

ADDRESS

CE#

Address

tF

tCE

tR

VIH

VIL

VIH

VIL

WE#

tF

tOE

tR

VIH

VIL

OE#

VIH

VIL

WP#/ACC

DATA

VOH

VOL

High Z

Valid

Ouput

Figure A. ACTiming at Device Power-Up

Notes

Symbol

Parameter

Min.

Max.

Unit

us/V

tVR

tR

VCC RiseTime

1

20

500000

20

Input Signal Rise Time

Input Signal Fall Time

1,2

tF

20

Notes :

1. Sampled, not 100% tested.

2. This specification is applied for not only the device power-up but also the normal operations.

P/N:PM1145

REV. 1.0, FEB. 27, 2006

59

MX29LA321M H/L

ERASE AND PROGRAMMING PERFORMANCE (1)

PARAMETER

Typ (Note 1)

Max (Note 2)

Unit

Comments

Excludes 00h

programming

prior to erasure

Note 6

Sector Erase Time

0.5

2

sec

Chip Erase Time

32

64

sec

Total Write Buffer Program Time (Note 4)

Total Accelerated Effective Write Buffer

Program Time (Note 4)

240

200

us

Excludes

system level

overhead

Chip Program Time

31.5

sec

Note 7

Notes:

1. Typical program and erase times assume the following conditions: 25° C, 3.0V VCC. Programming specifications

assume checkboard data pattern.

2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and

including 100,000 program/erase cycles.

3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the

write buffer.

4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation.

5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer

operation.

6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.

7. System-level overhead is the time required to execute the command sequence(s) for the program command.See

Table 3 for further information on command definitions.

8. The device has a minimum erase and program cycle endurance of 100,000 cycles.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

13.5V

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

-1.0V

VCC + 1.0V

+100mA

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

DATA RETENTION

Parameter

Min

20

Unit

Minimum Pattern Data Retention Time

Years

P/N:PM1145

REV. 1.0, FEB. 27, 2006

60

MX29LA321M H/L

TSOP PIN AND BGA PACKAGE CAPACITANCE

Parameter Symbol

Parameter Description

Test Set

TYP

6

MAX

7.5

5.0

12

UNIT

pF

CIN

Input Capacitance

VIN=0

TSOP

CSP

4.2

8.5

5.4

7.5

3.9

pF

COUT

CIN2

Output Capacitance

VOUT=0

VIN=0

TSOP

CSP

pF

6.5

9

pF

Control Pin Capacitance

TSOP

CSP

pF

4.7

pF

Notes:

1. Sampled, not 100% tested.

2.Test conditions TA=25°C, f=1.0MHz

P/N:PM1145

REV. 1.0, FEB. 27, 2006

61

MX29LA321M H/L

ORDERING INFORMATION

PART NO.

ACCESS TIME

Ball Pitch/

Ball size

PACKAGE

Remark

(ns)

MX29LA321MHTC-70R

MX29LA321MHTC-90

MX29LA321MLTC-70R

MX29LA321MLTC-90

MX29LA321MHTI-90

MX29LA321MLTI-90

MX29LA321MHTC-90G

MX29LA321MLTC-90G

MX29LA321MHTI-90G

MX29LA321MLTI-90G

70

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

56 Pin TSOP

(Normal Type)

64 ball CSP

90

70

90

PB-free

MX29LA321MHXCC-70R

MX29LA321MHXCC-90

MX29LA321MLXCC-70R

MX29LA321MLXCC-90

MX29LA321MHXCI-70R

MX29LA321MHXCI-90

MX29LA321MLXCI-70R

MX29LA321MLXCI-90

MX29LA321MHXCC-90G

MX29LA321MLXCC-90G

MX29LA321MHXCI-90G

MX29LA321MLXCI-90G

70

90

70

90

70

90

70

90

PB-free

P/N:PM1145

REV. 1.0, FEB. 27, 2006

62

MX29LA321M H/L

PACKAGE INFORMATION

P/N:PM1145

REV. 1.0, FEB. 27, 2006

63

MX29LA321M H/L

P/N:PM1145

REV. 1.0, FEB. 27, 2006

64

MX29LA321M H/L

REVISION HISTORY

Revision No. Description

Page

P1

Date

FEB/27/2006

1.0

1. Removed title "Preliminary"

2.Removed temporary sector group unprotect information

All

3.To add "Recommended operating conditions" for device power-up

P59

P/N:PM1145

REV. 1.0, FEB. 27, 2006

65

MX29LA321M H/L

MACRONIX INTERNATIONALCO., LTD .

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX29LA321MHXCI-70R
厂家：	MACRONIX INTERNATIONAL
描述：	32M-BIT SINGLE VOLTAGE 3V ONLY UNIFORM SECTOR FLASH MEMORY 32M - BIT单电压3V ONLY制服行业的FLASH MEMORY
文件：	总66页 (文件大小：510K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29LA321MHXCI-70R [Macronix]

相关型号：

MX29LA321MHXCI-90

MX29LA321MHXCI-90G

MX29LA321ML

MX29LA321MLTC-70R

MX29LA321MLTC-90

MX29LA321MLTC-90G

MX29LA321MLTI-90

MX29LA321MLTI-90G

MX29LA321MLXCC-70R

MX29LA321MLXCC-90

MX29LA321MLXCC-90G

MX29LA321MLXCI-70R