MX29LA640EHXCI-70G [Macronix]
Flash, 4MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, MO-216, BGA-64;
| 型号： | MX29LA640EHXCI-70G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Flash, 4MX16, 70ns, PBGA64, 10 X 13 MM, 1.20 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, MO-216, BGA-64 内存集成电路 闪存 |
| 文件： | 总60页 (文件大小：1969K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX29LA640E H/L
64M-BIT [4M x 16/8M x 8] CMOS EQUAL SECTOR
FLASH MEMORY
FEATURES
GENERAL FEATURES
•ꢀ 8M Bytes/4M Words switchable
•ꢀ 128ꢀꢀEqualꢀSectorsꢀwithꢀ64KꢀBytesꢀ(32Kꢀwords)ꢀeach
ꢀ -ꢀAnyꢀcombinationꢀofꢀsectorsꢀcanꢀbeꢀerasedꢀwithꢀeraseꢀsuspend/resumeꢀfunction
•ꢀ SingleꢀPowerꢀSupplyꢀOperation
ꢀ -ꢀ2.7ꢀtoꢀ3.6ꢀvoltꢀforꢀread,ꢀerase,ꢀandꢀprogramꢀoperations
•ꢀ Latch-upꢀprotectedꢀtoꢀ100mAꢀfromꢀ-1.0Vꢀtoꢀ1.5ꢀxꢀVcc
•ꢀ LowꢀVccꢀwriteꢀinhibitꢀisꢀequalꢀtoꢀorꢀlessꢀthanꢀVLKO
•ꢀ CompatibleꢀwithꢀJEDECꢀstandard
ꢀ -ꢀPinoutꢀandꢀsoftwareꢀcompatibleꢀtoꢀsingleꢀpowerꢀsupplyꢀFlash
PERFORMANCE
•ꢀ HighꢀPerformance
- Access time: 70ns
ꢀ -ꢀProgramꢀtime:ꢀ11us/word
ꢀ -ꢀEraseꢀtime:ꢀ0.7s/sector,ꢀ45s/chipꢀ(typical)
•ꢀ LowꢀPowerꢀConsumption
ꢀ -ꢀLowꢀactiveꢀreadꢀcurrent:ꢀ9mAꢀ(typical)ꢀatꢀ5MHz
ꢀ -ꢀLowꢀstandbyꢀcurrent:ꢀ5uA(typical)
•ꢀ 100,000ꢀerase/programꢀcyclesꢀ(typical)
•ꢀ 10ꢀyearsꢀdataꢀretention
SOFTWARE FEATURES
•ꢀ SupportꢀCommonꢀFlashꢀInterfaceꢀ(CFI)
ꢀ -ꢀFlashꢀdeviceꢀparametersꢀstoredꢀonꢀtheꢀdeviceꢀandꢀprovideꢀtheꢀhostꢀsystemꢀtoꢀaccess
•ꢀ EraseꢀSuspend/ꢀEraseꢀResume
ꢀ -ꢀSuspendsꢀsectorꢀeraseꢀoperationꢀtoꢀreadꢀdataꢀfromꢀorꢀprogramꢀdataꢀtoꢀanotherꢀsectorꢀwhichꢀisꢀnotꢀbeingꢀ
erased
•ꢀ StatusꢀReply
ꢀ -ꢀData#ꢀpollingꢀ&ꢀToggleꢀbitsꢀprovideꢀdetectionꢀofꢀprogramꢀandꢀeraseꢀoperationꢀcompletionꢀorꢀnot
HARDWARE FEATURES
•ꢀ Ready/Busyꢀ(RY/BY#)ꢀOutput
ꢀ -ꢀProvidesꢀaꢀhardwareꢀmethodꢀofꢀdetectingꢀprogramꢀandꢀeraseꢀoperationꢀcompletion
•ꢀ HardwareꢀResetꢀ(RESET#)ꢀInput
ꢀ -ꢀProvidesꢀaꢀhardwareꢀmethodꢀtoꢀresetꢀtheꢀinternalꢀstateꢀmachineꢀtoꢀreadꢀmode
•ꢀ ACCꢀinputꢀpin
ꢀ -ꢀProvidesꢀacceleratedꢀprogramꢀcapability
•ꢀ WP#/ACCꢀinput
ꢀ -ꢀWriteꢀprotectꢀ(WP#)ꢀfunctionꢀallowsꢀprotectionꢀallꢀsectors,ꢀregardlessꢀofꢀsectorꢀprotectionꢀsettings
SECURITY
•ꢀꢀ SectorꢀProtection/ChipꢀUnprotect
ꢀ -ꢀProvidesꢀsectorꢀprotectꢀfunctionꢀtoꢀpreventꢀꢀprogramꢀorꢀeraseꢀoperationꢀinꢀtheꢀprotectedꢀsector
ꢀ -ꢀProvidesꢀchipꢀunprotectꢀfunctionꢀtoꢀallowꢀcodeꢀchanges
ꢀ -ꢀProvidesꢀtemporaryꢀsectorꢀunprotectꢀfunctionꢀforꢀcodeꢀchangesꢀinꢀpreviouslyꢀprotectedꢀsector
P/N:PM1424
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MX29LA640E H/L
•ꢀ SectorꢀPermanentꢀLock
ꢀ -ꢀAꢀuniqueꢀlockꢀbitꢀfeatureꢀallowsꢀtheꢀcontentꢀtoꢀbeꢀpermanentlyꢀlocked
(Please contact Macronix sales for specific information regarding this permanent lock feature)
•ꢀꢀ SecuredꢀSiliconꢀSector
ꢀ -ꢀProvidesꢀaꢀ128-wordꢀareaꢀforꢀcodeꢀorꢀdataꢀthatꢀcanꢀbeꢀpermanentlyꢀprotected
ꢀ -ꢀOnceꢀthisꢀsectorꢀisꢀprotected,ꢀitꢀisꢀprohibitedꢀtoꢀprogramꢀorꢀeraseꢀwithinꢀtheꢀsectorꢀagain
PACKAGE
•ꢀ 64-ballꢀFBGA
•ꢀꢀ All Pb-free devices are RoHS Compliant
GENERAL DESCRIPTION
MX29LA640EꢀH/Lꢀisꢀaꢀ64Mbitꢀflashꢀmemoryꢀthatꢀcanꢀbeꢀorganizedꢀasꢀ8Mbytesꢀofꢀ8ꢀbitsꢀeachꢀorꢀasꢀ4Mbytesꢀofꢀ16ꢀ
bitsꢀeach.ꢀTheseꢀdevicesꢀoperateꢀoverꢀaꢀvoltageꢀrangeꢀofꢀ2.7Vꢀtoꢀ3.6Vꢀtypicallyꢀusingꢀaꢀ3Vꢀpowerꢀsupplyꢀinput.ꢀ
Theꢀmemoryꢀarrayꢀisꢀdividedꢀintoꢀ128ꢀequalꢀ64ꢀKiloꢀbyteꢀblocks.ꢀ
TheꢀMX29LA640EꢀH/Lꢀisꢀofferedꢀinꢀaꢀ64-ballꢀBGA(FBGA)ꢀJEDECꢀstandardꢀpackage.ꢀTheꢀpackageꢀisꢀofferedꢀinꢀ
leaded,ꢀasꢀwellꢀasꢀlead-freeꢀversionꢀthatꢀisꢀcompliantꢀtoꢀtheꢀRoHSꢀspecifications.ꢀTheꢀsoftwareꢀalgorithmꢀusedꢀforꢀ
thisꢀdeviceꢀalsoꢀadheresꢀtoꢀtheꢀJEDECꢀstandardꢀforꢀsingleꢀpowerꢀsupplyꢀdevices.ꢀTheseꢀflashꢀpartsꢀcanꢀbeꢀpro-
grammedꢀinꢀsystemꢀorꢀonꢀcommerciallyꢀavailableꢀEPROM/Flashꢀprogrammers.ꢀ
SeparateꢀOE#ꢀandꢀCE#ꢀ(OutputꢀEnableꢀandꢀChipꢀEnable)ꢀsignalsꢀareꢀprovidedꢀtoꢀsimplifyꢀsystemꢀdesign.ꢀWhenꢀ
usedꢀwithꢀhighꢀspeedꢀprocessors,ꢀtheꢀ70nsꢀreadꢀaccessꢀtimeꢀofꢀthisꢀflashꢀmemoryꢀpermitsꢀoperationꢀwithꢀminimalꢀ
timeꢀlostꢀdueꢀtoꢀsystemꢀtimingꢀdelays.ꢀ
TheꢀautomaticꢀwriteꢀalgorithmꢀprovidedꢀonꢀMacronixꢀflashꢀmemoriesꢀperformꢀanꢀautomaticꢀeraseꢀpriorꢀtoꢀwrite.ꢀ
Theꢀuserꢀonlyꢀneedsꢀtoꢀprovideꢀaꢀwriteꢀcommandꢀtoꢀtheꢀcommandꢀregister.ꢀTheꢀon-chipꢀstateꢀmachineꢀautomati-
callyꢀcontrolsꢀtheꢀprogramꢀandꢀeraseꢀfunctionsꢀincludingꢀallꢀnecessaryꢀinternalꢀtimings.ꢀSinceꢀeraseꢀandꢀwriteꢀ
operationsꢀtakeꢀmuchꢀlongerꢀtimeꢀthanꢀreadꢀoperations,ꢀerase/writeꢀcanꢀbeꢀinterruptedꢀtoꢀperformꢀreadꢀopera-
tionsꢀinꢀotherꢀsectorsꢀofꢀtheꢀdevice.ꢀForꢀthis,ꢀEraseꢀSuspendꢀoperationꢀalongꢀwithꢀEraseꢀResumeꢀoperationꢀareꢀ
provided.ꢀData#ꢀpollingꢀorꢀToggleꢀbitsꢀareꢀusedꢀtoꢀindicateꢀtheꢀendꢀofꢀtheꢀerase/writeꢀoperation.ꢀ
TheꢀdeviceꢀisꢀmanufacturedꢀatꢀtheꢀMacronixꢀfabricationꢀfacilityꢀusingꢀtheꢀtimeꢀtestedꢀandꢀprovenꢀMacronixꢀad-
vancedꢀꢀtechnology.ꢀThisꢀproprietaryꢀnon-epiꢀprocessꢀprovidesꢀaꢀveryꢀhighꢀdegreeꢀofꢀlatch-upꢀprotectionꢀforꢀ
stressesꢀupꢀtoꢀ100ꢀmilliamperesꢀonꢀaddressꢀandꢀdataꢀpinsꢀfromꢀ-1Vꢀtoꢀ1.5xVCC.ꢀ
Withꢀlowꢀpowerꢀconsumptionꢀandꢀenhancedꢀhardwareꢀandꢀsoftwareꢀfeatures,ꢀthisꢀflashꢀmemoryꢀretainsꢀdataꢀreli-
ablyꢀforꢀatꢀleastꢀtenꢀyears.ꢀEraseꢀandꢀprogrammingꢀfunctionsꢀhaveꢀbeenꢀtestedꢀtoꢀmeetꢀaꢀtypicalꢀspecificationꢀofꢀ
100,000ꢀcyclesꢀofꢀoperation.
P/N:PM1424
REV. 1.3, MAY 19, 2010
2
MX29LA640E H/L
PIN CONFIGURATION
64 BGA
NC
NC
NC
GND
NC
NC
NC
8
VI/O
A15
A11
Q15/
A-1
A13
A9
A12
A8
A14
A10
A16
Q7
BYTE#
Q14
GND
Q6
7
6
Q13
VCC
Q11
Q9
RES-
ET#
5
WE#
A21
A18
A6
A19
A20
A5
Q5
Q2
Q0
Q12
Q10
Q8
Q4
Q3
Q1
RY/
BY#
WP#/
ACC
4
3
A17
A7
A3
NC
A4
A2
A1
A0
CE#
VI/O
OE#
NC
GND
NC
2
1
NC
NC
NC
NC
A
B
C
D
E
F
G
H
PIN DESCRIPTION
SYMBOL PIN NAME
LOGIC SYMBOL
A0~A21/A-1 AddressꢀInput/LSBꢀaddrꢀ(ByteꢀMode)
22
Q0~Q15 DataꢀInputs/Outputs
A0-A21
16
CE#
WE#
OE#
ChipꢀEnableꢀInput
WriteꢀEnableꢀInput
OutputꢀEnableꢀInput
(A-1)
Q0-Q15
CE#
OE#
WE#
RESET# HardwareꢀResetꢀPin,ꢀActiveꢀLow
HardwareꢀWriteꢀProtect/Programmingꢀ
Accelerationꢀinput
WP#/ACC
RY/BY# Read/BusyꢀOutput
RESET#
BYTE# Selectsꢀ8ꢀbitsꢀorꢀ16ꢀbitsꢀmode
WP#/ACC
RY/BY#
VCC
VꢀI/O
+3.0Vꢀsingleꢀpowerꢀsupply
V I/O
OutputꢀPowerꢀSupplyꢀ(2.7V~3.6V),ꢀ
whichꢀisꢀtiedꢀtoꢀVCC
GND
NC
DeviceꢀGround
PinꢀNotꢀConnectedꢀInternally
P/N:PM1424
REV. 1.3, MAY 19, 2010
3
MX29LA640E H/L
BLOCK DIAGRAM
VCC
GND
WRITE
CE#
CONTROL
INPUT
PROGRAM/ERASE
STATE
MACHINE
(WSM)
OE#
WE#
HIGH VOLTAGE
LOGIC
RESET#
WP#
ACC
STATE
FLASH
ARRAY
ADDRESS
LATCH
REGISTER
A0-A21
(A-1)
ARRAY
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
V I/O
I/O BUFFER
P/N:PM1424
REV. 1.3, MAY 19, 2010
4
MX29LA640E H/L
Table 1. BLOCK STRUCTURE
MX29LA640E SECTOR ARCHITECTURE
Sector Size
Kbytes Kwords
Sector Address
(x8)
(x16)
Address Range
Sector
A21-A15
Address Range
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001011
0001100
0001101
0001110
0001111
0010000
0010001
0010010
0010011
0010100
0010101
0010110
0010111
0011000
0011001
0011010
0011011
0011100
0011101
0011110
0011111
0100000
0100001
0100010
0100011
0100100
0100101
0100110
0100111
0101000
0101001
0101010
000000h-00FFFFh
010000h-01FFFFh
020000h-02FFFFh
030000h-03FFFFh
040000h-04FFFFh
050000h-05FFFFh
060000h-06FFFFh
070000h-07FFFFh
080000h-08FFFFh
090000h-09FFFFh
0A0000h-0AFFFFh
0B0000h-0BFFFFh
0C0000h-0CFFFFh
0D0000h-0DFFFFh
0E0000h-0EFFFFh
0F0000h-0FFFFFh
100000h-10FFFFh
110000h-11FFFFh
120000h-12FFFFh
130000h-13FFFFh
140000h-14FFFFh
150000h-15FFFFh
160000h-16FFFFh
170000h-17FFFFh
180000h-18FFFFh
190000h-19FFFFh
1A0000h-1AFFFFh
1B0000h-1BFFFFh
1C0000h-1CFFFFh
1D0000h-1DFFFFh
1E0000h-1EFFFFh
1F0000h-1FFFFFh
200000h-20FFFFh
210000h-21FFFFh
220000h-22FFFFh
230000h-23FFFFh
240000h-24FFFFh
250000h-25FFFFh
260000h-26FFFFh
270000h-27FFFFh
280000h-28FFFFh
290000h-29FFFFh
2A0000h-2AFFFFh
000000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
100000h-107FFFh
108000h-10FFFFh
110000h-117FFFh
118000h-11FFFFh
120000h-127FFFh
128000h-12FFFFh
130000h-137FFFh
138000h-13FFFFh
140000h-147FFFh
148000h-14FFFFh
150000h-157FFFh
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
SA35
SA36
SA37
SA38
SA39
SA40
SA41
SA42
P/N:PM1424
REV. 1.3, MAY 19, 2010
5
MX29LA640E H/L
Sector Size
Kbytes Kwords
Sector Address
(x8)
(x16)
Address Range
Sector
A21-A15
Address Range
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA43
SA44
SA45
SA46
SA47
SA48
SA49
SA50
SA51
SA52
SA53
SA54
SA55
SA56
SA57
SA58
SA59
SA60
SA61
SA62
SA63
SA64
SA65
SA66
SA67
SA68
SA69
SA70
SA71
SA72
SA73
SA74
SA75
SA76
SA77
SA78
SA79
SA80
SA81
SA82
SA83
SA84
SA85
0101011
0101100
0101101
0101110
0101111
0110000
0110001
0110010
0110011
0110100
0110101
0110110
0110111
0111000
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
1000011
1000100
1000101
1000110
1000111
1001000
1001001
1001010
1001011
1001100
1001101
1001110
1001111
1010000
1010001
1010010
1010011
1010100
1010101
2B0000h-2BFFFFh
2C0000h-2CFFFFh
2D0000h-2DFFFFh
2E0000h-2EFFFFh
2F0000h-2FFFFFh
300000h-30FFFFh
310000h-31FFFFh
320000h-32FFFFh
330000h-33FFFFh
340000h-34FFFFh
350000h-35FFFFh
360000h-36FFFFh
370000h-37FFFFh
380000h-38FFFFh
390000h-39FFFFh
3A0000h-3AFFFFh
3B0000h-3BFFFFh
3C0000h-3CFFFFh
3D0000h-3DFFFFh
3E0000h-3EFFFFh
3F0000h-3FFFFFh
400000h-40FFFFh
410000h-41FFFFh
420000h-42FFFFh
430000h-43FFFFh
440000h-44FFFFh
450000h-45FFFFh
460000h-46FFFFh
470000h-47FFFFh
480000h-48FFFFh
490000h-49FFFFh
4A0000h-4AFFFFh
4B0000h-4BFFFFh
4C0000h-4CFFFFh
4D0000h-4DFFFFh
4E0000h-4EFFFFh
4F0000h-4FFFFFh
500000h-50FFFFh
510000h-51FFFFh
520000h-52FFFFh
530000h-53FFFFh
540000h-54FFFFh
550000h-55FFFFh
158000h-15FFFFh
160000h-167FFFh
168000h-16FFFFh
170000h-177FFFh
178000h-17FFFFh
180000h-187FFFh
188000h-18FFFFh
190000h-197FFFh
198000h-19FFFFh
1A0000h-1A7FFFh
1A8000h-1AFFFFh
1B0000h-1B7FFFh
1B8000h-1BFFFFh
1C0000h-1C7FFFh
1C8000h-1CFFFFh
1D0000h-1D7FFFh
1D8000h-1DFFFFh
1E0000h-1E7FFFh
1E8000h-1EFFFFh
1F0000h-1F7FFFh
1F8000h-1FFFFFh
200000h-207FFFh
208000h-20FFFFh
210000h-217FFFh
218000h-21FFFFh
220000h-227FFFh
228000h-22FFFFh
230000h-237FFFh
238000h-23FFFFh
240000h-247FFFh
248000h-24FFFFh
250000h-257FFFh
258000h-25FFFFh
260000h-267FFFh
268000h-26FFFFh
270000h-277FFFh
278000h-27FFFFh
280000h-287FFFh
288000h-28FFFFh
290000h-297FFFh
298000h-29FFFFh
2A0000h-2A7FFFh
2A8000h-2AFFFFh
P/N:PM1424
REV. 1.3, MAY 19, 2010
6
MX29LA640E H/L
Sector Size
Kbytes Kwords
Sector Address
(x8)
(x16)
Address Range
Sector
A21-A15
Address Range
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA86
SA87
1010110
1010111
1011000
1011001
1011010
1011011
1011100
1011101
1011110
1011111
1100000
1100001
1100010
1100011
1100100
1100101
1100110
1100111
1101000
1101001
1101010
1101011
1101100
1101101
1101110
1101111
1110000
1110001
1110010
1110011
1110100
1110101
1110110
1110111
1111000
1111001
1111010
1111011
1111100
1111101
1111110
1111111
560000h-56FFFFh
570000h-57FFFFh
580000h-58FFFFh
590000h-59FFFFh
5A0000h-5AFFFFh
5B0000h-5BFFFFh
5C0000h-5CFFFFh
5D0000h-5DFFFFh
5E0000h-5EFFFFh
5F0000h-5FFFFFh
600000h-60FFFFh
610000h-61FFFFh
620000h-62FFFFh
630000h-63FFFFh
640000h-64FFFFh
650000h-65FFFFh
660000h-66FFFFh
670000h-67FFFFh
680000h-68FFFFh
690000h-69FFFFh
6A0000h-6AFFFFh
6B0000h-6BFFFFh
6C0000h-6CFFFFh
6D0000h-6DFFFFh
6E0000h-6EFFFFh
6F0000h-6FFFFFh
700000h-70FFFFh
710000h-71FFFFh
720000h-72FFFFh
730000h-73FFFFh
740000h-74FFFFh
750000h-75FFFFh
760000h-76FFFFh
770000h-77FFFFh
780000h-78FFFFh
790000h-79FFFFh
7A0000h-7AFFFFh
7B0000h-7BFFFFh
7C0000h-7CFFFFh
7D0000h-7DFFFFh
7E0000h-7EFFFFh
7F0000h-7FFFFFh
2B0000h-2B7FFFh
2B8000h-2BFFFFh
2C0000h-2C7FFFh
2C8000h-2CFFFFh
2D0000h-2D7FFFh
2D8000h-2DFFFFh
2E0000h-2E7FFFh
2E8000h-2EFFFFh
2F0000h-2F7FFFh
2F8000h-2FFFFFh
300000h-307FFFh
308000h-30FFFFh
310000h-317FFFh
318000h-31FFFFh
320000h-327FFFh
328000h-32FFFFh
330000h-337FFFh
338000h-33FFFFh
340000h-347FFFh
348000h-34FFFFh
350000h-357FFFh
358000h-35FFFFh
360000h-367FFFh
368000h-36FFFFh
370000h-377FFFh
378000h-37FFFFh
380000h-387FFFh
388000h-38FFFFh
390000h-397FFFh
398000h-39FFFFh
3A0000h-3A7FFFh
3A8000h-3AFFFFh
3B0000h-3B7FFFh
3B8000h-3BFFFFh
3C0000h-3C7FFFh
3C8000h-3CFFFFh
3D0000h-3D7FFFh
3D8000h-3DFFFFh
3E0000h-3E7FFFh
3E8000h-3EFFFFh
3F0000h-3F7FFFh
3F8000h-3FFFFFh
SA88
SA89
SA90
SA91
SA92
SA93
SA94
SA95
SA96
SA97
SA98
SA99
SA100
SA101
SA102
SA103
SA104
SA105
SA106
SA107
SA108
SA109
SA110
SA111
SA112
SA113
SA114
SA115
SA116
SA117
SA118
SA119
SA120
SA121
SA122
SA123
SA124
SA125
SA126
SA127
P/N:PM1424
REV. 1.3, MAY 19, 2010
7
MX29LA640E H/L
Table 2-1. BUS OPERATION
Byte#
Data
RE-
Mode Select
Vil
Vih
WP#/
ACC
CE# WE# OE#
Address
I/O
SET#
Data (I/O)
Q8~Q15
Q0~Q7
DeviceꢀResetꢀ
StandbyꢀModeꢀ
Lꢀ
X
X
X
X
X
X
X
HighZꢀ HighZꢀ
HighZꢀ HighZꢀ
HighZꢀ HighZꢀ
HighZꢀ
L/H
H
Vcc± Vcc±
0.3V
HighZꢀ
0.3V
OutputꢀDisable
Read Mode
Hꢀ
Lꢀ
Hꢀ
Hꢀ
Lꢀ
Hꢀ
Lꢀ
X
HighZꢀ
DOUTꢀ
DINꢀ
L/H
L/H
H
Hꢀ
Hꢀ
Hꢀ
Lꢀ
Lꢀ
Lꢀ
AINꢀ
AINꢀ
AINꢀ
DOUTꢀ
Q8-Q14=
Writeꢀ(Note1)ꢀ
AccelerateꢀProgramꢀ
Hꢀ
Hꢀ
DINꢀ
DINꢀ
HighZ,
Q15=A1
Lꢀ
DINꢀ
Vhv
Temporaryꢀ
Sector-Groupꢀ
Unprotect
Vhvꢀ
X
X
X
AINꢀ
DINꢀ
HighZꢀ
DINꢀ
H
Sector-Groupꢀ
Protectꢀ(Note2)
SectorꢀAddress,ꢀ
DIN,ꢀ
Vhvꢀ
Vhvꢀ
Lꢀ
Lꢀ
Lꢀ
Lꢀ
Hꢀ
Hꢀ
X
X
X
X
H
H
A6=L,ꢀA1=H,ꢀA0=L DOUT
SectorꢀAddress,ꢀ DIN,ꢀ
A6=L,ꢀA1=H,ꢀA0=L DOUT
ChipꢀUnprotectꢀ
(Note2)
Notes:
1.ꢀꢀAllꢀsectorsꢀwillꢀbeꢀunprotectedꢀifꢀWP#/ACC=Vhv.
2.ꢀ AllꢀsectorsꢀareꢀprotectedꢀifꢀWP#/ACC=Vil.
3.ꢀ Q0~Q15ꢀareꢀinputꢀ(DIN)ꢀorꢀoutputꢀ(DOUT)ꢀpinsꢀaccordingꢀtoꢀtheꢀrequestsꢀofꢀcommandꢀsequence,ꢀsectorꢀpro-
tection,ꢀorꢀdataꢀpollingꢀalgorithm.
4.ꢀ InꢀWordꢀModeꢀ(Byte#=Vih),ꢀtheꢀaddressesꢀareꢀAMꢀtoꢀA0.
ꢀ
InꢀByteꢀModeꢀ(Byte#=Vil),ꢀtheꢀaddressesꢀareꢀAMꢀtoꢀA-1ꢀ(Q15).
5.ꢀ AM:ꢀMSBꢀofꢀaddress.
P/N:PM1424
REV. 1.3, MAY 19, 2010
8
MX29LA640E H/L
Table 2-2. BUS OPERATION
Control Input
A21 A14
A8
A5 A3
Q8
to
Q15
Q7 to
Q0
Item
to to A9 to A6 to to A1 A0
A15 A10
CE#
OE# WE#
A7
A4 A2
SectorꢀLockꢀStatusꢀ
Verification
enable
L
L
L
H
H
H
SA
X
X
X
Vhv
Vhv
Vhv
X
L
L
L
X
X
X
X
X
L
H
H
L
L
H
L
X
X
Note 1
Note 2
C2h
ReadꢀIndicatorꢀBitꢀ
(Q7)ꢀforꢀSecurityꢀ
Sector
enable
enable
X
X
X
ManufacturerꢀID
X
00
DeviceꢀIDꢀ
Cycleꢀ1
enable
enable
enable
enable
L
L
L
L
H
H
H
H
X
X
X
X
X
X
X
X
Vhv
Vhv
Vhv
Vhv
X
X
X
X
L
L
L
L
X
X
X
X
L
H
H
H
L
H
H
H
H
L
22
22
22
22
7Eh
13h
01h
00h
Cycleꢀ2
640EH
Cycleꢀ3
H
H
640EL
Legend:ꢀL=LogicꢀLow=Vil,ꢀH=LogicꢀHigh=Vih,ꢀSA=SectorꢀAddress,ꢀX=Don'tꢀcare,ꢀVhv=10.0±0.5V.
Notes:
1.ꢀSectorꢀunprotectedꢀcode:ꢀ00h,ꢀsectorꢀprotectedꢀcode:01h.
2.ꢀFactoryꢀlockedꢀcode:ꢀ Forꢀ29LA640EL:ꢀ88h.
ꢀ ꢀ
Forꢀ29LA640EH:ꢀ98h.
ꢀꢀꢀFactoryꢀunlockedꢀcode:ꢀ Forꢀ29LA640EL:ꢀ08h.
ꢀ ꢀ
Forꢀ29LA640EH:ꢀ18h.
P/N:PM1424
REV. 1.3, MAY 19, 2010
9
MX29LA640E H/L
WRITE COMMANDS/COMMAND SEQUENCES
Toꢀwriteꢀaꢀcommandꢀtoꢀtheꢀdevice,ꢀsystemꢀmustꢀdriveꢀWE#ꢀandꢀCE#ꢀtoꢀVil,ꢀandꢀOE#ꢀtoꢀVih.ꢀInꢀaꢀcommandꢀcycle,ꢀ
allꢀaddressꢀareꢀlatchedꢀatꢀtheꢀlaterꢀfallingꢀedgeꢀofꢀCE#ꢀandꢀWE#,ꢀandꢀallꢀdataꢀareꢀlatchedꢀatꢀtheꢀearlierꢀrisingꢀ
edgeꢀofꢀCE#ꢀandꢀWE#.ꢀ
Figureꢀ1ꢀillustratesꢀtheꢀACꢀtimingꢀwaveformꢀofꢀaꢀwriteꢀcommand,ꢀandꢀTableꢀ3ꢀdefinesꢀallꢀtheꢀvalidꢀcommandꢀsetsꢀ
ofꢀtheꢀdevice.ꢀSystemꢀisꢀnotꢀallowedꢀtoꢀwriteꢀinvalidꢀcommandsꢀnotꢀdefinedꢀinꢀthisꢀdatasheet.ꢀWritingꢀanꢀinvalidꢀ
commandꢀwillꢀbringꢀtheꢀdeviceꢀtoꢀanꢀundefinedꢀstate.
REQUIREMENTS FOR READING ARRAY DATA
Readꢀarrayꢀactionꢀisꢀtoꢀreadꢀtheꢀdataꢀstoredꢀinꢀtheꢀarray.ꢀWhileꢀtheꢀmemoryꢀdeviceꢀisꢀinꢀpoweredꢀupꢀorꢀhasꢀbeenꢀ
reset,ꢀitꢀwillꢀautomaticallyꢀenterꢀtheꢀstatusꢀofꢀreadꢀarray.ꢀIfꢀtheꢀmicroprocessorꢀwantsꢀtoꢀreadꢀtheꢀdataꢀstoredꢀinꢀtheꢀ
array,ꢀitꢀhasꢀtoꢀdriveꢀCE#ꢀ(deviceꢀenableꢀcontrolꢀpin)ꢀandꢀOE#ꢀ(Outputꢀcontrolꢀpin)ꢀasꢀVil,ꢀandꢀinputꢀtheꢀaddressꢀ
ofꢀtheꢀdataꢀtoꢀbeꢀreadꢀintoꢀaddressꢀpinꢀatꢀtheꢀsameꢀtime.ꢀAfterꢀaꢀperiodꢀofꢀreadꢀcycleꢀ(TceꢀorꢀTaa),ꢀtheꢀdataꢀbeingꢀ
readꢀoutꢀwillꢀbeꢀdisplayedꢀonꢀoutputꢀpinꢀforꢀmicroprocessorꢀtoꢀaccess.ꢀIfꢀCE#ꢀorꢀOE#ꢀisꢀVih,ꢀtheꢀoutputꢀwillꢀbeꢀinꢀ
tri-state,ꢀandꢀthereꢀwillꢀbeꢀnoꢀdataꢀdisplayedꢀonꢀoutputꢀpinꢀatꢀall.
Afterꢀtheꢀmemoryꢀdeviceꢀcompletesꢀembeddedꢀoperationꢀ(automaticꢀEraseꢀorꢀProgram),ꢀitꢀwillꢀautomaticallyꢀre-
turnꢀtoꢀtheꢀstatusꢀofꢀreadꢀarray,ꢀandꢀtheꢀdeviceꢀcanꢀreadꢀtheꢀdataꢀinꢀanyꢀaddressꢀinꢀtheꢀarray.ꢀInꢀtheꢀprocessꢀofꢀ
erasing,ꢀifꢀtheꢀdeviceꢀreceivesꢀtheꢀEraseꢀsuspendꢀcommand,ꢀeraseꢀoperationꢀwillꢀbeꢀstoppedꢀtemporarilyꢀafterꢀaꢀ
periodꢀofꢀtimeꢀnoꢀmoreꢀthanꢀTreadyꢀandꢀtheꢀdeviceꢀwillꢀreturnꢀtoꢀtheꢀstatusꢀofꢀreadꢀarray.ꢀAtꢀthisꢀtime,ꢀtheꢀdeviceꢀ
canꢀreadꢀtheꢀdataꢀstoredꢀinꢀanyꢀaddressꢀexceptꢀtheꢀsectorꢀbeingꢀerasedꢀinꢀtheꢀarray.ꢀInꢀtheꢀstatusꢀofꢀeraseꢀsus-
pend,ꢀifꢀuserꢀwantsꢀtoꢀreadꢀtheꢀdataꢀinꢀtheꢀsectorsꢀbeingꢀerased,ꢀtheꢀdeviceꢀwillꢀoutputꢀstatusꢀdataꢀontoꢀtheꢀout-
put.ꢀSimilarly,ꢀifꢀprogramꢀcommandꢀisꢀissuedꢀafterꢀeraseꢀsuspend,ꢀafterꢀprogramꢀoperationꢀisꢀcompleted,ꢀsystemꢀ
canꢀstillꢀreadꢀarrayꢀdataꢀinꢀanyꢀaddressꢀexceptꢀtheꢀsectorsꢀtoꢀbeꢀerased.
Theꢀdeviceꢀneedsꢀtoꢀissueꢀresetꢀcommandꢀtoꢀenableꢀreadꢀarrayꢀoperationꢀagainꢀinꢀorderꢀtoꢀarbitrarilyꢀreadꢀtheꢀ
dataꢀinꢀtheꢀarrayꢀinꢀtheꢀfollowingꢀtwoꢀsituations:ꢀꢀ
1.ꢀInꢀprogramꢀorꢀeraseꢀoperation,ꢀtheꢀprogrammingꢀorꢀerasingꢀfailureꢀcausesꢀQ5ꢀtoꢀgoꢀhigh.
2.ꢀTheꢀdeviceꢀisꢀinꢀautoꢀselectꢀmodeꢀorꢀCFIꢀmode.
Inꢀtheꢀtwoꢀsituationsꢀabove,ꢀifꢀresetꢀcommandꢀisꢀnotꢀissued,ꢀtheꢀdeviceꢀisꢀnotꢀinꢀreadꢀarrayꢀmodeꢀandꢀsystemꢀ
mustꢀissueꢀresetꢀcommandꢀbeforeꢀreadingꢀarrayꢀdata.
ACCELERATED PROGRAM OPERATION
Theꢀacceleratedꢀprogramꢀcanꢀimproveꢀprogrammingꢀperformanceꢀcomparedꢀwithꢀword/byteꢀprogram.ꢀByꢀapply-
ingꢀVhvꢀonꢀWP#/ACCꢀpin,ꢀtheꢀdeviceꢀwillꢀenterꢀacceleratedꢀprogramꢀandꢀdrawꢀcurrentꢀnoꢀmoreꢀthanꢀIACCꢀfromꢀ
WP#/ACCꢀpin.ꢀRemovingꢀtheꢀVhvꢀfromꢀWP#/ACCꢀpinꢀwillꢀputꢀtheꢀdeviceꢀbackꢀtoꢀnormalꢀoperationꢀ(notꢀacceler-
ated).
P/N:PM1424
REV. 1.3, MAY 19, 2010
10
MX29LA640E H/L
RESET# OPERATION
DrivingꢀRESET#ꢀpinꢀlowꢀforꢀaꢀperiodꢀmoreꢀthanꢀTrpꢀwillꢀresetꢀtheꢀdeviceꢀbackꢀtoꢀreadꢀmode.ꢀIfꢀtheꢀdeviceꢀisꢀinꢀ
programꢀorꢀeraseꢀoperation,ꢀtheꢀresetꢀoperationꢀwillꢀtakeꢀatꢀmostꢀaꢀperiodꢀofꢀTreadyꢀforꢀtheꢀdeviceꢀtoꢀreturnꢀtoꢀ
readꢀarrayꢀmode.ꢀBeforeꢀtheꢀdeviceꢀreturnsꢀtoꢀreadꢀarrayꢀmode,ꢀtheꢀRY/BY#ꢀpinꢀremainsꢀlowꢀ(busyꢀstatus).
WhenꢀRESET#ꢀpinꢀisꢀheldꢀatꢀGND±0.3V,ꢀtheꢀdeviceꢀconsumesꢀstandbyꢀcurrent(Isb).However,ꢀdeviceꢀdrawsꢀlarg-
erꢀcurrentꢀifꢀRESET#ꢀpinꢀisꢀheldꢀatꢀVilꢀbutꢀnotꢀwithinꢀGND±0.3V.
ItꢀisꢀrecommendedꢀthatꢀtheꢀsystemꢀtoꢀtieꢀitsꢀresetꢀsignalꢀtoꢀRESET#ꢀpinꢀofꢀflashꢀmemory,ꢀsoꢀthatꢀtheꢀflashꢀmemo-
ryꢀwillꢀbeꢀresetꢀduringꢀsystemꢀresetꢀandꢀallowsꢀsystemꢀtoꢀreadꢀtheꢀboot-upꢀfirwareꢀfromꢀflashꢀmemory.
SECTOR PROTECT OPERATION
Whenꢀaꢀsectorꢀisꢀprotected,ꢀprogramꢀorꢀeraseꢀoperationꢀwillꢀbeꢀdisabledꢀonꢀtheseꢀsectors.ꢀMX29LA640EꢀH/Lꢀpro-
videsꢀtwoꢀmethodsꢀforꢀsectorꢀprotection.ꢀ
Onceꢀtheꢀsectorꢀisꢀprotected,ꢀtheꢀsectorꢀremainsꢀprotectedꢀuntilꢀnextꢀchipꢀunprotect,ꢀorꢀisꢀtemporarilyꢀunprotectedꢀ
byꢀassertingꢀRESET#ꢀpinꢀatꢀVhv.ꢀReferꢀtoꢀtemporaryꢀsectorꢀunprotectꢀoperationꢀforꢀfurtherꢀdetails.
TheꢀfirstꢀmethodꢀisꢀbyꢀapplyingꢀVhvꢀonꢀRESET#ꢀpin.ꢀReferꢀtoꢀFigureꢀ14ꢀforꢀtimingꢀdiagramꢀandꢀFigureꢀ15ꢀforꢀtheꢀ
algorithmꢀforꢀthisꢀmethod.
TheꢀotherꢀmethodꢀisꢀassertingꢀVhvꢀonꢀA9ꢀandꢀOE#ꢀpins,ꢀwithꢀA6ꢀandꢀCE#ꢀatꢀVil.ꢀTheꢀprotectionꢀoperationꢀbeginsꢀ
atꢀtheꢀfallingꢀedgeꢀofꢀWE#ꢀandꢀterminatesꢀatꢀtheꢀrisingꢀedge.ꢀContactꢀMacronixꢀforꢀdetails.
CHIP UNPROTECT OPERATION
MX29LA640EꢀH/Lꢀprovidesꢀtwoꢀmethodsꢀforꢀchipꢀunprotect.ꢀTheꢀchipꢀunprotectꢀoperationꢀunprotectsꢀallꢀsectorsꢀ
withinꢀtheꢀdevice.ꢀItꢀisꢀrecommendedꢀtoꢀprotectꢀallꢀsectorsꢀbeforeꢀactivatingꢀchipꢀunprotectꢀmode.ꢀAllꢀsectorsꢀareꢀ
unprotectedꢀwhenꢀshippedꢀfromꢀtheꢀfactory.
TheꢀfirstꢀmethodꢀisꢀbyꢀapplyingꢀVhvꢀonꢀRESET#ꢀpin.ꢀReferꢀtoꢀFigureꢀ14ꢀforꢀtimingꢀdiagramꢀandꢀFigureꢀ15ꢀforꢀal-
gorithmꢀofꢀtheꢀoperation.
TheꢀotherꢀmethodꢀisꢀassertingꢀVhvꢀonꢀA9ꢀandꢀOE#ꢀpins,ꢀwithꢀA6ꢀatꢀVihꢀandꢀCE#ꢀatꢀVilꢀ(seeꢀTableꢀ2).ꢀTheꢀunpro-
tectꢀoperationꢀbeginsꢀatꢀtheꢀfallingꢀedgeꢀofꢀWE#ꢀandꢀterminatesꢀatꢀtheꢀrisingꢀedge.ꢀContactꢀMacronixꢀforꢀdetails.
TEMPORARY SECTOR UNPROTECT OPERATION
SystemꢀcanꢀapplyꢀRESET#ꢀpinꢀatꢀVhvꢀtoꢀplaceꢀtheꢀdeviceꢀinꢀtemporaryꢀunprotectꢀmode.ꢀInꢀthisꢀmode,ꢀpreviouslyꢀ
protectedꢀsectorsꢀcanꢀbeꢀprogrammedꢀorꢀerasedꢀjustꢀasꢀitꢀisꢀunprotected.ꢀTheꢀdevicesꢀreturnsꢀtoꢀnormalꢀopera-
tionꢀonceꢀVhvꢀisꢀremovedꢀfromꢀRESET#ꢀpinꢀandꢀpreviouslyꢀprotectedꢀsectorsꢀareꢀagainꢀprotected.
P/N:PM1424
REV. 1.3, MAY 19, 2010
11
MX29LA640E H/L
WRITE PROTECT (WP#)
ThisꢀWriteꢀProtectꢀfunctionꢀprovidesꢀaꢀhardwareꢀprotectionꢀmethodꢀtoꢀprotectꢀallꢀsectorsꢀwithoutꢀusingꢀVhv.
ByꢀdrivingꢀtheꢀWP#/ACCꢀpinꢀLow,ꢀtheꢀdeviceꢀdisableꢀprogramꢀandꢀeraseꢀfunctionꢀinꢀallꢀsectors.ꢀIfꢀtheꢀWP#/ACCꢀ
isꢀheldꢀhighꢀ(VihꢀtoꢀVcc),ꢀtheseꢀsectorsꢀrevertꢀtoꢀtheirꢀpreviousꢀprotected/unprotectedꢀstatus.
AUTOMATIC SELECT OPERATION
WhenꢀtheꢀdeviceꢀisꢀinꢀReadꢀarrayꢀmode,ꢀerase-suspendedꢀreadꢀarrayꢀmodeꢀorꢀCFIꢀmode,ꢀuserꢀcanꢀissueꢀreadꢀ
siliconꢀIDꢀcommandꢀtoꢀenterꢀreadꢀsiliconꢀIDꢀmode.ꢀAfterꢀenteringꢀreadꢀsiliconꢀIDꢀmode,ꢀuserꢀcanꢀqueryꢀseveralꢀ
siliconꢀIDsꢀcontinuouslyꢀandꢀdoesꢀnotꢀneedꢀtoꢀissueꢀreadꢀsiliconꢀIDꢀmodeꢀagain.ꢀInꢀreadꢀsiliconꢀIDꢀmode,ꢀissuingꢀ
resetꢀcommandꢀwillꢀresetꢀdeviceꢀbackꢀtoꢀreadꢀarrayꢀmodeꢀorꢀerase-suspendedꢀreadꢀarrayꢀmode.
MX29LA640EꢀH/LꢀprovideꢀhardwareꢀmethodꢀtoꢀaccessꢀtheꢀsiliconꢀIDꢀreadꢀoperation.ꢀWhichꢀmethodꢀrequiresꢀVhvꢀ
onꢀA9ꢀpin,ꢀVilꢀonꢀCE#,ꢀOE#ꢀandꢀA6ꢀpins.ꢀWhichꢀapplyꢀA1=Vil,ꢀA0=Vil,ꢀtheꢀdeviceꢀwillꢀoutputꢀMXIC'sꢀmanufactureꢀ
codeꢀofꢀC2h.ꢀWhichꢀapplyꢀA1=Vil,ꢀA0=Vih,ꢀtheꢀdeviceꢀwillꢀoutputꢀdeviceꢀcodeꢀofꢀ227Eh.ꢀTableꢀ2ꢀshowsꢀtheꢀse-
quenceꢀforꢀreadingꢀMX29LA640EꢀH/Lꢀdeviceꢀcodes.
VERIFY SECTOR PROTECT STATUS OPERATION
MX29LA640EꢀH/LꢀprovidesꢀhardwareꢀsectorꢀprotectionꢀagainstꢀProgramꢀandꢀEraseꢀoperationꢀforꢀprotectedꢀsec-
tors.ꢀTheꢀsectorꢀprotectꢀstatusꢀcanꢀbeꢀreadꢀthroughꢀSectorꢀProtectꢀVerifyꢀcommand.ꢀThisꢀmethodꢀrequiresꢀVhvꢀonꢀ
A9ꢀpin,ꢀVihꢀonꢀWE#ꢀandꢀA1ꢀpins,ꢀVilꢀonꢀCE#,ꢀOE#,ꢀA6ꢀandꢀA0ꢀpins,ꢀandꢀsectorꢀaddressꢀonꢀA15ꢀtoꢀA21ꢀpins.ꢀIfꢀtheꢀ
readꢀoutꢀdataꢀisꢀ01H,ꢀtheꢀdesignatedꢀsectorꢀisꢀprotected.ꢀOppositely,ꢀifꢀtheꢀreadꢀoutꢀdataꢀisꢀ00H,ꢀtheꢀdesignatedꢀ
sectorꢀisꢀnotꢀprotected.
SECURITY SECTOR FLASH MEMORY REGION
TheꢀSecurityꢀSectorꢀregionꢀisꢀanꢀextraꢀOTPꢀmemoryꢀspaceꢀofꢀ128ꢀwordsꢀinꢀlength.ꢀTheꢀsecurityꢀsectorsꢀcanꢀbeꢀ
lockedꢀuponꢀshippingꢀfromꢀfactory,ꢀorꢀitꢀcanꢀbeꢀlockedꢀbyꢀcustomerꢀafterꢀshipping.ꢀCustomerꢀcanꢀissueꢀSecurityꢀ
SectorꢀFactoryꢀProtectꢀVerifyꢀand/orꢀSecurityꢀSectorꢀProtectꢀVerifyꢀtoꢀqueryꢀtheꢀlockꢀstatusꢀofꢀtheꢀdevice.ꢀ
Inꢀfactory-lockedꢀdevice,ꢀsecurityꢀsectorꢀregionꢀisꢀprotectedꢀwhenꢀshippedꢀfromꢀfactoryꢀandꢀtheꢀsecurityꢀsiliconꢀ
sectorꢀindicatorꢀbitꢀisꢀsetꢀtoꢀ"1".ꢀInꢀcustomerꢀlockableꢀdevice,ꢀsecurityꢀsectorꢀregionꢀisꢀunprotectedꢀwhenꢀshippedꢀ
fromꢀfactoryꢀandꢀtheꢀsecurityꢀsiliconꢀindicatorꢀbitꢀisꢀsetꢀtoꢀ"0".ꢀ
Factory Locked: Security Sector Programmed and Protected at the Factory
Inꢀaꢀfactoryꢀlockedꢀdevice,ꢀtheꢀsecurityꢀsiliconꢀregionꢀisꢀpermanentlyꢀlockedꢀafterꢀshippingꢀfromꢀfactory.ꢀTheꢀde-
viceꢀwillꢀhaveꢀaꢀ16-byteꢀ(8-word)ꢀESNꢀinꢀtheꢀsecurityꢀregionꢀatꢀaddressꢀ:ꢀ000000hꢀ-ꢀ000007h.
Theꢀsecuredꢀsiliconꢀsectorꢀaddressꢀspaceꢀinꢀthisꢀdeviceꢀisꢀallocatedꢀasꢀfollows.
Secured Silicon Sector
Address Range
Express Flash
Factory Locked
Standard Factory Locked
Customer Lockable
ESNꢀorꢀDeterminedꢀbyꢀ
Customer
000000h-000007h
ESN
DeterminedꢀbyꢀCustomer
000008h-00007Fh
Unavailable
DeterminedꢀbyꢀCustomer
P/N:PM1424
REV. 1.3, MAY 19, 2010
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MX29LA640E H/L
Customer Lockable: Security Sector NOT Programmed or Protected at the Factory
Whenꢀtheꢀsecurityꢀfeatureꢀisꢀnotꢀrequired,ꢀtheꢀsecurityꢀregionꢀcanꢀactꢀasꢀanꢀextraꢀmemoryꢀspace.ꢀ
Securityꢀsiliconꢀsectorꢀcanꢀalsoꢀbeꢀprotectedꢀbyꢀtwoꢀmethods.ꢀNoteꢀthatꢀonceꢀtheꢀsecurityꢀsiliconꢀsectorꢀisꢀpro-
tected,ꢀthereꢀisꢀnoꢀwayꢀtoꢀunprotectꢀtheꢀsecurityꢀsiliconꢀsectorꢀandꢀtheꢀcontentꢀofꢀitꢀcanꢀnoꢀlongerꢀbeꢀaltered.
Theꢀfirstꢀmethodꢀisꢀtoꢀwriteꢀaꢀthree-cycleꢀcommandꢀofꢀEnterꢀSecurityꢀRegion,ꢀandꢀthenꢀfollowꢀtheꢀsectorꢀprotectꢀ
algorithmꢀasꢀillustratedꢀinꢀFigureꢀ15,ꢀexceptꢀthatꢀRESET#ꢀpinꢀmayꢀatꢀeitherꢀVihꢀorꢀVhv.ꢀ
Theꢀotherꢀmethodꢀisꢀtoꢀwriteꢀaꢀthree-cycleꢀcommandꢀofꢀEnterꢀSecurityꢀRegion,ꢀandꢀthenꢀfollowꢀtheꢀalternateꢀ
methodꢀofꢀsectorꢀprotectꢀwithꢀA9,ꢀOE#ꢀatꢀVhv.
Afterꢀtheꢀsecurityꢀsiliconꢀisꢀlockedꢀandꢀverified,ꢀsystemꢀmustꢀwriteꢀExitꢀSecurityꢀSectorꢀRegion,ꢀgoꢀthroughꢀaꢀpow-
erꢀcycle,ꢀorꢀissueꢀaꢀhardwareꢀresetꢀtoꢀreturnꢀtheꢀdeviceꢀtoꢀreadꢀnormalꢀarrayꢀmode.
DATA PROTECTION
Toꢀavoidꢀaccidentalꢀerasureꢀorꢀprogrammingꢀofꢀtheꢀdevice,ꢀtheꢀdeviceꢀisꢀautomaticallyꢀresetꢀtoꢀreadꢀarrayꢀmodeꢀ
duringꢀpowerꢀup.ꢀBesides,ꢀonlyꢀafterꢀsuccessfulꢀcompletionꢀofꢀtheꢀspecifiedꢀcommandꢀsetsꢀwillꢀtheꢀdeviceꢀbeginꢀ
itsꢀeraseꢀorꢀprogramꢀoperation.
Otherꢀfeaturesꢀtoꢀprotectꢀtheꢀdataꢀfromꢀaccidentalꢀalternationꢀareꢀdescribedꢀasꢀfollowed.
LOW VCC WRITE INHIBIT
TheꢀdeviceꢀrefusesꢀtoꢀacceptꢀanyꢀwriteꢀcommandꢀwhenꢀVccꢀisꢀlessꢀthanꢀVLKO.ꢀThisꢀpreventsꢀdataꢀfromꢀspuri-
ouslyꢀaltered.ꢀTheꢀdeviceꢀautomaticallyꢀresetsꢀitselfꢀwhenꢀVccꢀisꢀlowerꢀthanꢀVLKOꢀandꢀwriteꢀcyclesꢀareꢀignoredꢀ
untilꢀVccꢀisꢀgreaterꢀthanꢀVLKO.ꢀSystemꢀmustꢀprovideꢀproperꢀsignalsꢀonꢀcontrolꢀpinsꢀafterꢀVccꢀisꢀlargerꢀthanꢀVLKOꢀ
toꢀavoidꢀunintentionalꢀprogramꢀorꢀeraseꢀoperation
WRITE PULSE "GLITCH" PROTECTION
CE#,ꢀWE#,ꢀOE#ꢀpulsesꢀshorterꢀthanꢀ5nsꢀareꢀtreatedꢀasꢀglitchesꢀandꢀwillꢀnotꢀbeꢀregardedꢀasꢀanꢀeffectiveꢀwriteꢀ
cycle.
LOGICAL INHIBIT
AꢀvalidꢀwriteꢀcycleꢀrequiresꢀbothꢀCE#ꢀandꢀWE#ꢀatꢀVilꢀwithꢀOE#ꢀatꢀVih.ꢀWriteꢀcycleꢀisꢀignoredꢀwhenꢀeitherꢀCE#ꢀatꢀ
Vih,ꢀWE#ꢀaꢀVih,ꢀorꢀOE#ꢀatꢀVil.
POWER-UP SEQUENCE
Uponꢀpowerꢀup,ꢀMX29LA640EꢀH/Lꢀisꢀplacedꢀinꢀreadꢀarrayꢀmode.ꢀFurthermore,ꢀprogramꢀorꢀeraseꢀoperationꢀwillꢀ
beginꢀonlyꢀafterꢀsuccessfulꢀcompletionꢀofꢀspecifiedꢀcommandꢀsequences.
P/N:PM1424
REV. 1.3, MAY 19, 2010
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MX29LA640E H/L
POWER-UP WRITE INHIBIT
WhenꢀWE#,ꢀCE#ꢀisꢀheldꢀatꢀVilꢀandꢀOE#ꢀisꢀheldꢀatꢀVihꢀduringꢀpowerꢀup,ꢀtheꢀdeviceꢀignoresꢀtheꢀfirstꢀcommandꢀonꢀ
theꢀrisingꢀedgeꢀofꢀWE#.
POWER SUPPLY DECOUPLING
Aꢀ0.1uFꢀcapacitorꢀshouldꢀbeꢀconnectedꢀbetweenꢀtheꢀVccꢀandꢀGNDꢀtoꢀreduceꢀtheꢀnoiseꢀeffect.
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MX29LA640E H/L
TABLE 3. MX29LA640E H/L COMMAND DEFINITIONS
AutomaticꢀSelect
Read Reset
Mode Mode
DeviceꢀIDꢀ
(*Notes)
SecurityꢀSectorꢀFactoryꢀ
Commandꢀ
ManufacturerꢀID
SectorꢀProtectꢀVerify
Protect Verify
Word
555
AA
2AA
55
Byte
AAA
AA
555
55
Word Byte
Word
555
AA
2AA
55
Byte
AAA
AA
555
55
Word
555
Byte
AAA
Addr Addr
XXX
555
AA
AAA
AA
1stꢀBusꢀ
Cycle
Data Data
Addr
Data
F0
AA
2AA
55
AA
555
55
2AA
55
555
55
2ndꢀBusꢀ
Cycle
Addr
Data
555
90
AAA
90
555
90
AAA
90
555
90
AAA
90
555
90
AAA
90
3rdꢀBusꢀꢀ
Cycle
(Sector)
X02
(Sector)
X04
Addr
X00
X00
X01
X02
X03
X06
4thꢀBusꢀ
Cycle
98/18(T)ꢀ
88/08(B)
98/18(T)ꢀ
88/08(B)
Data
C2h
C2h
ID1
ID1
00/01
00/01
Addr
Data
Addr
Data
X0E ꢀX1C
5thꢀBusꢀꢀ
Cycle
ID2ꢀ
X0F
ID3
ID2ꢀ
X1E
ID3
6thꢀBusꢀꢀ
Cycle
EnterꢀSecurityꢀ
SectorꢀRegionꢀ
Enable
Exitꢀ
Securityꢀ
Sector
Sectorꢀ
Erase
Erase
Suspend Resume
Erase
Program ChipꢀErase
CFIꢀRead
Commandꢀ
Word
Byte Word Byte Word Byte Word Byte Word Byte Word Byte Byte/Word Byte/Word
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
555
AA
2AA
55
555
88
AAA
AA
555
55
AAA
88
555 AAA 555 AAA 555 AAA 555 AAA 55
AA AA AA AA AA AA AA AA 98
2AA 555 2AA 555 2AA 555 2AA 555
55 55 55 55 55 55 55 55
555 AAA 555 AAA 555 AAA 555 AAA
90 90 A0 A0 80 80 80 80
XXX XXX Addr Addr 555 AAA 555 AAA
AA
98
XXX
B0
XXX
30
1stꢀBusꢀ
Cycle
2ndꢀBusꢀ
Cycle
3rdꢀBusꢀꢀ
Cycle
4thꢀBusꢀ
Cycle
00
00 Data Data AA
2AA 555 2AA 555
55 55 55 55
Sec- Sec-
AA
AA AA
5thꢀBusꢀꢀ
Cycle
Addr
555 AAA
6thꢀBusꢀꢀ
Cycle
tor
tor
Data
10
10
30
30
DeviceꢀID
ID1
ID2
ID3
Interface
MX29LA640EH
MX29LA640EL
Word
227E
227E
Byte
7E
7E
Word
2213
2213
Byte
13
13
Word
2201
2200
Byte
01
00
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REV. 1.3, MAY 19, 2010
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MX29LA640E H/L
RESET
Inꢀtheꢀfollowingꢀsituations,ꢀexecutingꢀresetꢀcommandꢀwillꢀresetꢀdeviceꢀꢀbackꢀtoꢀreadꢀarrayꢀmode:
•ꢀ Amongꢀeraseꢀcommandꢀsequenceꢀ(beforeꢀtheꢀfullꢀcommandꢀsetꢀisꢀcompleted)
•ꢀ Sectorꢀeraseꢀtime-outꢀperiod
•ꢀ Eraseꢀfailꢀ(whileꢀQ5ꢀisꢀhigh)
•ꢀ Amongꢀprogramꢀcommandꢀsequenceꢀ(beforeꢀtheꢀfullꢀcommandꢀsetꢀisꢀcompleted,ꢀerase-suspendedꢀprogramꢀ
included)
•ꢀ Programꢀfailꢀ(whileꢀQ5ꢀisꢀhigh,ꢀandꢀerase-suspendedꢀprogramꢀfailꢀisꢀincluded)
•ꢀ ReadꢀsiliconꢀIDꢀmode
•ꢀ Sectorꢀprotectꢀverify
•ꢀ CFIꢀmode
Whileꢀdeviceꢀisꢀatꢀtheꢀstatusꢀofꢀprogramꢀfailꢀorꢀeraseꢀfailꢀ(Q5ꢀisꢀhigh),ꢀuserꢀmustꢀissueꢀresetꢀcommandꢀtoꢀresetꢀ
deviceꢀꢀbackꢀtoꢀreadꢀarrayꢀmode.ꢀWhileꢀtheꢀdeviceꢀisꢀinꢀreadꢀsiliconꢀIDꢀmode,ꢀsectorꢀprotectꢀverifyꢀorꢀCFIꢀmode,ꢀ
userꢀmustꢀissueꢀresetꢀcommandꢀtoꢀresetꢀdeviceꢀꢀbackꢀtoꢀreadꢀarrayꢀmode.ꢀꢀꢀ
Whenꢀtheꢀdeviceꢀisꢀinꢀtheꢀprogressꢀofꢀprogrammingꢀ(notꢀprogramꢀfail)ꢀorꢀerasingꢀ(notꢀeraseꢀfail),ꢀdeviceꢀwillꢀꢀig-
nore reset command.
AUTOMATIC SELECT COMMAND SEQUENCE
AutomaticꢀSelectꢀmodeꢀisꢀusedꢀtoꢀaccessꢀtheꢀmanufacturerꢀID,ꢀdeviceꢀIDꢀandꢀtoꢀverifyꢀwhetherꢀorꢀnotꢀsecuredꢀ
siliconꢀisꢀlockedꢀandꢀwhetherꢀorꢀnotꢀaꢀsectorꢀisꢀprotected.ꢀTheꢀautomaticꢀselectꢀmodeꢀhasꢀfourꢀcommandꢀcycles.ꢀ
Theꢀfirstꢀtwoꢀareꢀunlockꢀcycles,ꢀandꢀfollowedꢀbyꢀaꢀspecificꢀcommand.ꢀTheꢀfourthꢀcycleꢀisꢀaꢀnormalꢀreadꢀcycle,ꢀ
andꢀuserꢀcanꢀreadꢀatꢀanyꢀaddressꢀanyꢀnumberꢀofꢀtimesꢀwithoutꢀenteringꢀanotherꢀcommandꢀsequence.ꢀTheꢀresetꢀ
commandꢀisꢀnecessaryꢀtoꢀexitꢀtheꢀAutomaticꢀSelectꢀmodeꢀandꢀbackꢀtoꢀreadꢀarray.ꢀTheꢀfollowingꢀtableꢀshowsꢀtheꢀ
identificationꢀcodeꢀwithꢀcorrespondingꢀaddress.
Identifier Code
Word/Byte Mode
Address
Data (Hex)
Representation
Word
X00
C2
ManufacturerꢀID
Byte
Word
Byte
X00
X01
X02
C2
227E
7E
DeviceꢀID,ꢀcycleꢀ1
Word
Byte
Word
Byte
Word
Byte
Word
Byte
X0E
X1C
X0F
X1E
X03
2213
13
2201/2200
01/00
98/18ꢀ(H) Factoryꢀlocked/unlocked
98/18ꢀ(H) Factoryꢀlocked/unlocked
00/01
00/01
DeviceꢀID,ꢀcycleꢀ2
DeviceꢀID,ꢀcycleꢀ3
SecuredꢀSilicon
29LA640EꢀH/L
X06
(Sectorꢀaddress)ꢀXꢀ02
(Sectorꢀaddress)ꢀXꢀ04
Unprotected/protected
Unprotected/protected
SectorꢀProtectꢀVerify
ThereꢀisꢀanꢀalternativeꢀmethodꢀtoꢀthatꢀshownꢀinꢀTableꢀ2,ꢀwhichꢀisꢀintendedꢀforꢀEPROMꢀprogrammersꢀandꢀrequiresꢀ
VhvꢀonꢀaddressꢀbitꢀA9.
P/N:PM1424
REV. 1.3, MAY 19, 2010
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MX29LA640E H/L
AUTOMATIC PROGRAMMING
TheꢀMX29LA640EꢀꢀH/LꢀcanꢀprovideꢀtheꢀuserꢀprogramꢀfunctionꢀbyꢀtheꢀformꢀofꢀByte-ModeꢀorꢀWord-Mode.ꢀAsꢀlongꢀ
asꢀtheꢀusersꢀenterꢀtheꢀrightꢀcycleꢀdefinedꢀinꢀtheꢀTable.3ꢀ(includingꢀ2ꢀunlockꢀcyclesꢀandꢀA0H),ꢀanyꢀdataꢀuserꢀinputsꢀ
willꢀautomaticallyꢀbeꢀprogrammedꢀintoꢀtheꢀarray.
Onceꢀtheꢀprogramꢀfunctionꢀisꢀexecuted,ꢀtheꢀinternalꢀwriteꢀstateꢀcontrollerꢀwillꢀautomaticallyꢀexecuteꢀtheꢀalgo-
rithmsꢀandꢀtimingsꢀnecessaryꢀforꢀprogramꢀandꢀverification,ꢀwhichꢀincludesꢀgeneratingꢀsuitableꢀprogramꢀpulse,ꢀ
verifyingꢀwhetherꢀtheꢀthresholdꢀvoltageꢀofꢀtheꢀprogrammedꢀcellꢀisꢀhighꢀenoughꢀandꢀrepeatingꢀtheꢀprogramꢀpulseꢀ
ifꢀanyꢀofꢀtheꢀcellsꢀdoesꢀnotꢀpassꢀverification.ꢀMeanwhile,ꢀtheꢀinternalꢀcontrolꢀwillꢀprohibitꢀtheꢀprogrammingꢀtoꢀcellsꢀ
thatꢀpassꢀverificationꢀwhileꢀtheꢀotherꢀcellsꢀfailꢀinꢀverificationꢀinꢀorderꢀtoꢀavoidꢀover-programming.ꢀWithꢀtheꢀinternalꢀ
writeꢀstateꢀcontroller,ꢀtheꢀdeviceꢀrequiresꢀtheꢀuserꢀtoꢀwriteꢀtheꢀprogramꢀcommandꢀandꢀdataꢀonly.ꢀ
Programmingꢀwillꢀonlyꢀchangeꢀtheꢀbitꢀstatusꢀfromꢀ"1"ꢀtoꢀ"0".ꢀThatꢀisꢀtoꢀsay,ꢀitꢀisꢀimpossibleꢀtoꢀconvertꢀtheꢀbitꢀstatusꢀ
fromꢀ"0"ꢀtoꢀ"1"ꢀbyꢀprogramming.ꢀMeanwhile,ꢀtheꢀinternalꢀwriteꢀverificationꢀonlyꢀdetectsꢀtheꢀerrorsꢀofꢀtheꢀ"1"ꢀthatꢀisꢀ
notꢀsuccessfullyꢀprogrammedꢀtoꢀ"0".ꢀ
Anyꢀcommandꢀwrittenꢀtoꢀtheꢀdeviceꢀduringꢀprogrammingꢀwillꢀbeꢀignoredꢀexceptꢀhardwareꢀreset,ꢀwhichꢀwillꢀtermi-
nateꢀtheꢀprogramꢀoperationꢀafterꢀaꢀperiodꢀofꢀtimeꢀnoꢀmoreꢀthanꢀTready.ꢀWhenꢀtheꢀembeddedꢀprogramꢀalgorithmꢀ
isꢀcompleteꢀorꢀtheꢀprogramꢀoperationꢀisꢀterminatedꢀbyꢀhardwareꢀreset,ꢀtheꢀdeviceꢀwillꢀreturnꢀtoꢀtheꢀreadingꢀarrayꢀ
data mode.
TheꢀtypicalꢀchipꢀprogramꢀtimeꢀatꢀroomꢀtemperatureꢀofꢀtheꢀMX29LA640EꢀH/Lꢀisꢀlessꢀthanꢀ45ꢀseconds.
Whenꢀtheꢀembeddedꢀprogramꢀoperationꢀisꢀonꢀgoing,ꢀuserꢀcanꢀconfirmꢀifꢀtheꢀembeddedꢀoperationꢀisꢀfinishedꢀorꢀ
notꢀbyꢀtheꢀfollowingꢀmethods:
Status
Q7
Q7#
Q7
Q6
Q5
0
RY/BY# *2
Inꢀprogressꢀ*1
Finished
Toggling
0
1
0
Stopꢀtoggling
Toggling
0
Exceedꢀtimeꢀlimit
Q7#
1
*1:ꢀTheꢀstatusꢀ"inꢀprogress"ꢀmeansꢀbothꢀprogramꢀmodeꢀandꢀerase-suspendedꢀprogramꢀmode.
*2:ꢀRY/BY#ꢀisꢀanꢀopenꢀdrainꢀoutputꢀpinꢀandꢀshouldꢀbeꢀweaklyꢀconnectedꢀtoꢀVDDꢀthroughꢀaꢀpull-upꢀresistor.
*3:ꢀWhenꢀanꢀattemptꢀisꢀmadeꢀtoꢀprogramꢀaꢀprotectedꢀsector,ꢀQ7ꢀwillꢀoutputꢀitsꢀcomplementꢀdataꢀorꢀQ6ꢀcontinuesꢀ
toꢀtoggleꢀforꢀaboutꢀ1usꢀorꢀlessꢀandꢀtheꢀdeviceꢀreturnsꢀtoꢀreadꢀarrayꢀstateꢀwithoutꢀprogramingꢀtheꢀdataꢀinꢀtheꢀpro-
tected sector.
P/N:PM1424
REV. 1.3, MAY 19, 2010
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MX29LA640E H/L
CHIP ERASE
ChipꢀEraseꢀisꢀtoꢀeraseꢀallꢀtheꢀdataꢀwithꢀ"1"ꢀandꢀ"0"ꢀasꢀallꢀ"1".ꢀItꢀneedsꢀ6ꢀcyclesꢀtoꢀwriteꢀtheꢀactionꢀin,ꢀandꢀtheꢀfirstꢀ
twoꢀcyclesꢀareꢀ"unlock"ꢀcycles,ꢀtheꢀthirdꢀoneꢀisꢀaꢀconfigurationꢀcycle,ꢀtheꢀfourthꢀandꢀfifthꢀareꢀalsoꢀ"unlock"ꢀcycles,ꢀ
andꢀtheꢀsixthꢀcycleꢀisꢀtheꢀchipꢀeraseꢀoperation.ꢀ
Duringꢀchipꢀerasing,ꢀallꢀtheꢀcommandsꢀwillꢀnotꢀbeꢀacceptedꢀexceptꢀhardwareꢀresetꢀorꢀtheꢀworkingꢀvoltageꢀisꢀtooꢀ
lowꢀthatꢀchipꢀeraseꢀwillꢀbeꢀinterrupted.ꢀAfterꢀChipꢀErase,ꢀtheꢀchipꢀwillꢀreturnꢀtoꢀtheꢀstateꢀofꢀReadꢀArray.
Whenꢀtheꢀembeddedꢀchipꢀeraseꢀoperationꢀisꢀonꢀgoing,ꢀuserꢀcanꢀconfirmꢀifꢀtheꢀembeddedꢀoperationꢀisꢀfinishedꢀorꢀ
notꢀbyꢀtheꢀfollowingꢀmethods:
Status
Q7
0
Q6
Q5
0
Q2
Toggling
1
RY/BY#
Inꢀprogress
Finished
Toggling
0
1
0
1
Stopꢀtoggling
Toggling
0
Exceedꢀtimeꢀlimit
0
1
Toggling
SECTOR ERASE
SectorꢀEraseꢀisꢀtoꢀeraseꢀallꢀtheꢀdataꢀinꢀaꢀsectorꢀwithꢀ"1"ꢀandꢀ"0"ꢀasꢀallꢀ"1".ꢀItꢀrequiresꢀsixꢀcommandꢀcyclesꢀtoꢀis-
sue.ꢀTheꢀfirstꢀtwoꢀcyclesꢀareꢀ"unlockꢀcycles",ꢀtheꢀthirdꢀoneꢀisꢀaꢀconfigurationꢀcycle,ꢀtheꢀfourthꢀandꢀfifthꢀareꢀalsoꢀ
"unlockꢀcycles"ꢀandꢀtheꢀsixthꢀcycleꢀisꢀtheꢀsectorꢀeraseꢀcommand.ꢀAfterꢀtheꢀsectorꢀeraseꢀcommandꢀsequenceꢀisꢀ
issued,ꢀthereꢀisꢀaꢀtime-outꢀperiodꢀofꢀ50usꢀcountedꢀinternally.ꢀDuringꢀtheꢀtime-outꢀperiod,ꢀadditionalꢀsectorꢀad-
dressꢀandꢀsectorꢀeraseꢀcommandꢀcanꢀbeꢀwrittenꢀmultiply.ꢀOnceꢀuserꢀentersꢀanotherꢀsectorꢀeraseꢀcommand,ꢀtheꢀ
time-outꢀperiodꢀofꢀ50usꢀisꢀrecounted.ꢀIfꢀuserꢀentersꢀanyꢀcommandꢀotherꢀthanꢀsectorꢀeraseꢀorꢀeraseꢀsuspendꢀdur-
ingꢀtime-outꢀperiod,ꢀtheꢀeraseꢀcommandꢀwouldꢀbeꢀabortedꢀandꢀtheꢀdeviceꢀisꢀresetꢀtoꢀreadꢀarrayꢀcondition.ꢀTheꢀ
numberꢀofꢀsectorsꢀcouldꢀbeꢀfromꢀoneꢀsectorꢀtoꢀallꢀsectors.ꢀAfterꢀtime-outꢀperiodꢀpassingꢀby,ꢀadditionalꢀeraseꢀcom-
mandꢀisꢀnotꢀacceptedꢀandꢀeraseꢀembeddedꢀoperationꢀbegins.
Duringꢀsectorꢀerasing,ꢀallꢀcommandsꢀwillꢀnotꢀbeꢀacceptedꢀexceptꢀhardwareꢀresetꢀandꢀeraseꢀsuspendꢀandꢀuserꢀ
canꢀcheckꢀtheꢀstatusꢀasꢀchipꢀerase.
Whenꢀtheꢀembeddedꢀeraseꢀoperationꢀisꢀonꢀgoing,ꢀuserꢀcanꢀconfirmꢀifꢀtheꢀembeddedꢀoperationꢀisꢀfinishedꢀorꢀnotꢀ
byꢀtheꢀfollowingꢀmethods:
Status
Time-outꢀperiod
Q7
0
Q6
Q5
0
Q3
0
Q2
RY/BY#*2
Toggling
Toggling
Toggling
1
0
0
1
0
Inꢀprogress
0
Toggling
0
1
Finished
1
Stopꢀtoggling
Toggling
0
1
Exceededꢀtimeꢀlimit
0
1
1
Toggling
*1:ꢀTheꢀstatusꢀQ3ꢀisꢀtheꢀtime-outꢀperiodꢀindicator.ꢀWhenꢀQ3=0,ꢀtheꢀdeviceꢀisꢀinꢀtime-outꢀperiodꢀandꢀisꢀacceptibleꢀ
toꢀanotherꢀsectorꢀaddressꢀtoꢀbeꢀerased.ꢀWhenꢀQ3=1,ꢀtheꢀdeviceꢀisꢀinꢀeraseꢀoperationꢀandꢀonlyꢀeraseꢀsuspendꢀ
isꢀvalid.
*2:ꢀRY/BY#ꢀisꢀopenꢀdrainꢀoutputꢀpinꢀandꢀshouldꢀbeꢀweaklyꢀconnectedꢀtoꢀVDDꢀthroughꢀaꢀpull-upꢀresistor.
*3:ꢀWhenꢀanꢀattemptꢀisꢀmadeꢀtoꢀeraseꢀaꢀprotectedꢀsector,ꢀQ7ꢀwillꢀoutputꢀitsꢀcomplementꢀdataꢀorꢀQ6ꢀcontinuesꢀtoꢀ
toggleꢀforꢀ100usꢀorꢀlessꢀandꢀtheꢀdeviceꢀreturnedꢀtoꢀreadꢀarrayꢀstatusꢀwithoutꢀerasingꢀtheꢀdataꢀinꢀtheꢀprotectedꢀ
sector.
P/N:PM1424
REV. 1.3, MAY 19, 2010
18
MX29LA640E H/L
SECTOR ERASE SUSPEND
Duringꢀsectorꢀerasure,ꢀsectorꢀeraseꢀsuspendꢀisꢀtheꢀonlyꢀvalidꢀcommand.ꢀIfꢀuserꢀissueꢀeraseꢀsuspendꢀcommandꢀ
inꢀtheꢀtime-outꢀperiodꢀofꢀsectorꢀerasure,ꢀdeviceꢀtime-outꢀperiodꢀwillꢀbeꢀoverꢀimmediatelyꢀandꢀtheꢀdeviceꢀwillꢀgoꢀ
backꢀtoꢀerase-suspendedꢀreadꢀarrayꢀmode.ꢀIfꢀuserꢀissueꢀeraseꢀsuspendꢀcommandꢀduringꢀtheꢀsectorꢀeraseꢀisꢀbe-
ingꢀoperated,ꢀdeviceꢀwillꢀsuspendꢀtheꢀongoingꢀeraseꢀoperation,ꢀandꢀafterꢀtheꢀTready1ꢀ(<=20us)ꢀsuspendꢀfinishesꢀ
andꢀtheꢀdeviceꢀwillꢀenterꢀerase-suspendedꢀreadꢀarrayꢀmode.ꢀUserꢀcanꢀjudgeꢀifꢀtheꢀdeviceꢀhasꢀfinishedꢀeraseꢀsus-
pendꢀthroughꢀQ6,ꢀQ7,ꢀandꢀRY/BY#.
Afterꢀdeviceꢀhasꢀenteredꢀerase-suspendedꢀreadꢀarrayꢀmode,ꢀuserꢀcanꢀreadꢀotherꢀsectorsꢀnotꢀatꢀeraseꢀsuspendꢀ
byꢀtheꢀspeedꢀofꢀTaa;ꢀwhileꢀreadingꢀtheꢀsectorꢀinꢀerase-suspendꢀmode,ꢀdeviceꢀwillꢀoutputꢀitsꢀstatus.ꢀUserꢀcanꢀuseꢀ
Q6ꢀandꢀQ2ꢀtoꢀjudgeꢀtheꢀsectorꢀisꢀerasingꢀorꢀtheꢀeraseꢀisꢀsuspended.
Status
Q7
1
Q6
Noꢀtoggle
Data
Q5
0
Q3
N/A
Data
N/A
Q2
toggle
Data
N/A
RY/BY#
Eraseꢀsuspendꢀreadꢀinꢀeraseꢀsuspendedꢀsector
Eraseꢀsuspendꢀreadꢀinꢀnon-eraseꢀsuspendedꢀsector
Eraseꢀsuspendꢀprogramꢀinꢀnon-eraseꢀsuspendedꢀsector
1
1
0
Data
Q7#
Data
0
Toggle
Whenꢀtheꢀdeviceꢀhasꢀsuspendedꢀerasing,ꢀuserꢀcanꢀexecuteꢀtheꢀcommandꢀsetsꢀexceptꢀsectorꢀeraseꢀandꢀchipꢀ
erase,ꢀsuchꢀasꢀreadꢀsiliconꢀID,ꢀsectorꢀprotectꢀverify,ꢀprogram,ꢀCFIꢀqueryꢀandꢀeraseꢀresume.ꢀ
SECTOR ERASE RESUME
Sectorꢀeraseꢀresumeꢀcommandꢀisꢀvalidꢀonlyꢀwhenꢀtheꢀdeviceꢀisꢀinꢀeraseꢀsuspendꢀstate.ꢀAfterꢀeraseꢀresume,ꢀuserꢀ
canꢀissueꢀanotherꢀeraseꢀsuspendꢀcommand,ꢀbutꢀthereꢀshouldꢀbeꢀaꢀ4msꢀintervalꢀbetweenꢀeraseꢀresumeꢀandꢀtheꢀ
nextꢀeraseꢀsuspend.ꢀIfꢀuserꢀissueꢀinfiniteꢀsuspend-resumeꢀloop,ꢀorꢀsuspend-resumeꢀexceedsꢀ1024ꢀtimes,ꢀtheꢀ
timeꢀforꢀerasingꢀwillꢀincrease.
P/N:PM1424
REV. 1.3, MAY 19, 2010
19
MX29LA640E H/L
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LA640EꢀH/LꢀfeaturesꢀCFIꢀmode.ꢀHostꢀsystemꢀcanꢀretrieveꢀtheꢀoperatingꢀcharacteristics,ꢀstructureꢀandꢀ
vendor-specifiedꢀinformationꢀsuchꢀasꢀidentifyingꢀinformation,ꢀmemoryꢀsize,ꢀbyte/wordꢀconfiguration,ꢀoperatingꢀ
voltagesꢀandꢀtimingꢀinformationꢀofꢀthisꢀdeviceꢀbyꢀCFIꢀmode.ꢀTheꢀdeviceꢀentersꢀtheꢀCFIꢀQueryꢀmodeꢀwhenꢀtheꢀ
systemꢀwritesꢀtheꢀCFIꢀQueryꢀcommandꢀ"98H"ꢀtoꢀaddressꢀ"55H"ꢀanyꢀtimeꢀtheꢀdeviceꢀisꢀreadyꢀtoꢀreadꢀarrayꢀdata.ꢀ
TheꢀsystemꢀcanꢀreadꢀCFIꢀinformationꢀatꢀtheꢀaddressesꢀgivenꢀinꢀTableꢀ4.ꢀAꢀresetꢀcommandꢀisꢀrequiredꢀtoꢀexitꢀCFIꢀ
modeꢀandꢀgoꢀbackꢀtoꢀreadyꢀarrayꢀmodeꢀorꢀeraseꢀsuspendꢀmode.ꢀTheꢀsystemꢀcanꢀwriteꢀtheꢀCFIꢀQueryꢀcommandꢀ
onlyꢀwhenꢀtheꢀdeviceꢀisꢀinꢀreadꢀmode,ꢀeraseꢀsuspend,ꢀstandbyꢀmodeꢀorꢀautomaticꢀselectꢀmode.
Table 4-1. CFI mode: Identification Data Values
(Allꢀvaluesꢀinꢀtheseꢀtablesꢀareꢀinꢀhexadecimal)
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
10
11
12
13
14
15
16
17
18
19
1A
20
22
24
26
28
2A
2C
2E
30
32
34
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Query-uniqueꢀASCIIꢀstringꢀ"QRY"
PrimaryꢀvendorꢀcommandꢀsetꢀandꢀcontrolꢀinterfaceꢀIDꢀcode
Addressꢀforꢀprimaryꢀalgorithmꢀextendedꢀqueryꢀtableꢀ
AlternateꢀvendorꢀcommandꢀsetꢀandꢀcontrolꢀinterfaceꢀIDꢀcode
Addressꢀforꢀalternateꢀalgorithmꢀextendedꢀqueryꢀtableꢀ
Table 4-2. CFI Mode: System Interface Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
Vccꢀsupplyꢀminimumꢀprogram/eraseꢀvoltage
Vccꢀsupplyꢀmaximumꢀprogram/eraseꢀvoltage
VPPꢀsupplyꢀminimumꢀprogram/eraseꢀvoltage
VPPꢀsupplyꢀmaximumꢀprogram/eraseꢀvoltage
Typicalꢀtimeoutꢀperꢀsingleꢀword/byteꢀwrite,ꢀ2nꢀus
Typicalꢀtimeoutꢀforꢀmaximum-sizeꢀbufferꢀwrite,ꢀ2nꢀusꢀ(00h,ꢀnotꢀ
support)
1B
1C
1D
1E
1F
36
38
3A
3C
3E
0027
0036
0000
0000
0004
20
40
0000
Typicalꢀtimeoutꢀperꢀindividualꢀblockꢀerase,ꢀ2n ms
Typicalꢀtimeoutꢀforꢀfullꢀchipꢀerase,ꢀ2nꢀmsꢀ(00h,ꢀnotꢀsupport)
Maximumꢀtimeoutꢀforꢀword/byteꢀwrite,ꢀ2n timesꢀtypical
Maximumꢀtimeoutꢀforꢀbufferꢀwrite,ꢀ2n ꢀtimesꢀtypical
Maximumꢀtimeoutꢀperꢀindividualꢀblockꢀerase,ꢀ2n ꢀtimesꢀtypical
Maximumꢀtimeoutꢀforꢀchipꢀerase,ꢀ2n ꢀtimesꢀtypicalꢀ(00h,ꢀnotꢀ
21
22
23
24
25
42
44
46
48
4A
000A
0000
0005
0000
0004
26
4C
0000
support)
P/N:PM1424
REV. 1.3, MAY 19, 2010
20
MX29LA640E H/L
Table 4-3. CFI Mode: Device Geometry Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
Deviceꢀsizeꢀ=ꢀ2nꢀinꢀnumberꢀofꢀbytes
0017
0002
0000
27
28
4E
50
52
54
56
58
5A
5C
5E
60
62
64
66
68
6A
6C
6E
70
72
74
76
78
Flashꢀdeviceꢀinterfaceꢀdescriptionꢀ(02=asynchronousꢀx8/x16)
29
2A
2B
2C
2D
0000
0000
0001
007F
0000
0000
0001
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
Maximumꢀnumberꢀofꢀbytesꢀinꢀbufferꢀwriteꢀ=ꢀ2n (notꢀsupport)
Numberꢀofꢀeraseꢀregionsꢀwithinꢀdeviceꢀ
IndexꢀforꢀEraseꢀBankꢀAreaꢀ1:
[2E,2D]ꢀ=ꢀ#ꢀofꢀsame-sizeꢀsectorsꢀinꢀregionꢀ1-1
[30,ꢀ2F]ꢀ=ꢀsectorꢀsizeꢀinꢀmultiplesꢀofꢀ256K-bytes
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
IndexꢀforꢀEraseꢀBankꢀAreaꢀ2
IndexꢀforꢀEraseꢀBankꢀAreaꢀ3
IndexꢀforꢀEraseꢀBankꢀAreaꢀ4
P/N:PM1424
REV. 1.3, MAY 19, 2010
21
MX29LA640E H/L
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Address (h)
Address (h)
Description
Data (h)
(Word Mode) (Byte Mode)
40
41
42
43
44
45
46
47
48
49
4A
4B
80
82
84
86
88
8A
8C
8E
90
92
94
96
0050
0052
0049
0031
0033
0000
0002
0001
0001
0004
0000
0000
Queryꢀ-ꢀPrimaryꢀextendedꢀtable,ꢀuniqueꢀASCIIꢀstring,ꢀPRI
Majorꢀversionꢀnumber,ꢀASCII
Minorꢀversionꢀnumber,ꢀASCII
Unlockꢀrecognizesꢀaddressꢀ(0=ꢀrecognize,ꢀ1=ꢀdon'tꢀrecognize)
Eraseꢀsuspendꢀ(2=ꢀtoꢀbothꢀreadꢀandꢀprogram)
Sectorꢀprotectꢀ(N=ꢀ#ꢀofꢀsectors/group)
Temporaryꢀsectorꢀunprotectꢀ(1=supported)
Sectorꢀprotect/Chipꢀunprotectꢀscheme
SimultaneousꢀR/Wꢀoperationꢀ(0=notꢀsupported)
Burstꢀmodeꢀ(0=notꢀsupported)
Pageꢀmodeꢀ(0=notꢀsupported,ꢀ01ꢀ=ꢀ4ꢀwordꢀpage,ꢀ02ꢀ=ꢀ8ꢀwordꢀ
page)
4C
4D
98
9A
0000
MinimumꢀACC(acceleration)ꢀsupplyꢀ(0=ꢀnotꢀsupported),ꢀ[D7:D4]ꢀ
forꢀvolt,ꢀ[D3:D0]ꢀforꢀ100mV
0095
MaximumꢀACC(acceleration)ꢀsupplyꢀ(0=ꢀnotꢀsupported),ꢀ[D7:D4]ꢀ
forꢀvolt,ꢀ[D3:D0]ꢀforꢀ100mV
4E
9C
00A5
WP#ꢀProtection
04=UniformꢀsectorsꢀbottomꢀWP#ꢀprotect
05=UniformꢀsectorsꢀtopꢀWP#ꢀprotect
0004/
0005
4F
9E
P/N:PM1424
REV. 1.3, MAY 19, 2010
22
MX29LA640E H/L
ABSOLUTE MAXIMUM STRESS RATINGS
SurroundingꢀTemperatureꢀwith Bias
StorageꢀTemperature
VCCꢀꢀ
-65oCꢀtoꢀ+125oC
-65oCꢀtoꢀ+150oC
-0.5Vꢀtoꢀ+4.0ꢀV
RESET#,ꢀA9,ꢀACCꢀandꢀOE#
Theꢀotherꢀpins.
-0.5Vꢀtoꢀ+10.5ꢀV
-0.5VꢀtoꢀVccꢀ+0.5V
200 mA
VoltageꢀRange
OutputꢀShortꢀCircuitꢀCurrentꢀ(lessꢀthanꢀoneꢀsecond)
Note:
1.ꢀMinimumꢀvoltageꢀmayꢀundershootꢀtoꢀ-2Vꢀduringꢀtransitionꢀandꢀforꢀlessꢀthanꢀ20nsꢀduringꢀtransitions.
2.ꢀMaximumꢀvoltageꢀmayꢀovershootꢀtoꢀVcc+2Vꢀduringꢀtransitionꢀandꢀforꢀlessꢀthanꢀ20nsꢀduringꢀtransitions.
OPERATING TEMPERATURE AND VOLTAGE
A
Commercial (C) Grade
Industrial (I) Grade
SurroundingꢀTemperatureꢀ(T )
0°Cꢀtoꢀ+70°C
-40°Cꢀtoꢀ+85°C
+2.7ꢀVꢀtoꢀ3.6ꢀV
A
SurroundingꢀTemperatureꢀ(T )
range
VCC
Supply Voltages
VCC
P/N:PM1424
REV. 1.3, MAY 19, 2010
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MX29LA640E H/L
DC CHARACTERISTICS
Symbol Description
Min
Typ
Max
Remark
Iilk
Iilk9
Iolk
InputꢀLeak
A9ꢀLeak
±2.0uA
35uAꢀ
A9=10.5V
OutputꢀLeak
±1.0uA
Icr1
Icr2
ReadꢀCurrentꢀ(5MHz)
ReadꢀCurrentꢀ(1MHz)
9mA
2mA
16mA
CE#=Vil,ꢀOE#=Vih
CE#=Vil,ꢀOE#=Vih
4mA
CE#=Vil,ꢀOE#=Vih,
WE#=Vil
Icw
Isb
WriteꢀCurrent
26mA
5uA
30mA
Vcc=Vccꢀmax,ꢀotherꢀ
pinꢀdisable
StandbyꢀCurrent
15uA
Vcc=Vccmax,ꢀ
Isbr
ResetꢀCurrent
5uA
15uA
RESET#ꢀenable,ꢀ
otherꢀpinꢀdisable
Isbs
Icp1
SleepꢀModeꢀCurrent
5uA
15uA
AcceleratedꢀPgmꢀCurrent,ꢀWP#/Accꢀ
pin(Word/Byte)
AcceleratedꢀPgmꢀCurrent,ꢀVccꢀpin,ꢀ
(Word/Byte)
5mA
10mA
CE#=Vil,ꢀOE#=Vih
CE#=Vil,ꢀOE#=Vih
Icp2
15mA
30mA
Vil
InputꢀLowꢀVoltage
-0.5V
0.8V
Vih
InputꢀHighꢀVoltage
0.7xVcc
Vcc+0.3V
VeryꢀHighꢀVoltageꢀforꢀhardwareꢀProtect/
Unprotect/AutoꢀSelect/Temporaryꢀ
Unprotect/AcceleratedꢀProgram
OutputꢀLowꢀVoltage
Vhv
9.5V
10.5V
0.45V
Vol
Iol=4.0mA
Voh1
Voh2
Vlko
OuputꢀHighꢀVoltage
0.85xVI/O
VI/O-0.4V
2.3V
Ioh1=-2mA
Ioh2=-100uA
OuputꢀHighꢀVoltage
LowꢀVccꢀLock-outꢀvoltage
2.5V
P/N:PM1424
REV. 1.3, MAY 19, 2010
24
MX29LA640E H/L
SWITCHING TEST CIRCUITS
Vcc
R2
TESTED DEVICE
+3.3V
0.1uF
CL
R1
DIODES=IN3064
OR EQUIVALENT
R1=6.2Kꢀohm
R2=2.7Kꢀohm
TestꢀConditionꢀ
OutputꢀLoadꢀ:ꢀ1ꢀTTLꢀgate
OutputꢀLoadꢀCapacitance,CLꢀ:ꢀ30pF
Rise/FallꢀTimesꢀ:ꢀ5ns
In/Outꢀreferenceꢀlevelsꢀ:1.5V
InputꢀPulseꢀlevelꢀ:ꢀ0.0ꢀ~ꢀ3.0V
SWITCHING TEST WAVEFORMS
3.0V
1.5V
1.5V
Test Points
0.0V
INPUT
OUTPUT
P/N:PM1424
REV. 1.3, MAY 19, 2010
25
MX29LA640E H/L
AC CHARACTERISTICS
Symbol Description
Min
Typ
Max
70
Unit
ns
Taa
Tce
Toe
Tdf
Toh
Validꢀdataꢀoutputꢀafterꢀaddressꢀ
70
ns
ValidꢀdataꢀoutputꢀafterꢀCE#ꢀlow
ValidꢀdataꢀoutputꢀafterꢀOE#ꢀlow
DataꢀoutputꢀfloatingꢀafterꢀOE#ꢀhigh
30
ns
30
ns
Outputꢀholdꢀtimeꢀfromꢀtheꢀearliestꢀrisingꢀedgeꢀofꢀaddress,CE#,ꢀ
OE#
0
ns
70
70
70
0
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
Trc
Readꢀperiodꢀtime
Twc Writeꢀperiodꢀtime
Tcwc Commandꢀwriteꢀperiodꢀtime
Tas
Tah
Tds
Addressꢀsetupꢀtime
Address hold time
Dataꢀsetupꢀtime
45
45
0
Tdh Dataꢀholdꢀtime
Tvcs Vccꢀsetupꢀtime
100
0
Tcs
Tch
ChipꢀenableꢀSetupꢀtime
Chipꢀenableꢀholdꢀtime
0
Toes Outputꢀenableꢀsetupꢀtime
0
Read
0
ns
ns
Toeh Outputꢀenableꢀholdꢀtimeꢀꢀꢀ
Toggleꢀ&ꢀData#ꢀPolling
10
Tws WE#ꢀsetupꢀtime
Twh WE#ꢀholdꢀtime
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
us
sec
us
0
Tcep CE#ꢀpulseꢀwidth
Tceph CE#ꢀpulseꢀwidthꢀhigh
Twp WE#ꢀpulseꢀwidth
Twph WE#ꢀpulseꢀwidthꢀhigh
45
30
35
30
70
Tbusy Program/EraseꢀactiveꢀtimeꢀbyꢀRY/BY#
Tghwl Readꢀrecoverꢀtimeꢀbeforeꢀwrite
Tghel Readꢀrecoverꢀtimeꢀbeforeꢀwrite
0
0
Byte
9
11
7
Twhwh1 Programꢀoperation
Word
Twhwh1 Accꢀprogramꢀoperation(Word/Byte)
Twhwh2 Sectorꢀeraseꢀoperation
Tbal Sectorꢀaddꢀholdꢀtime
0.7
50
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MX29LA640E H/L
Figure 1. COMMAND WRITE OPERATION
Tcwc
Disable
CE#
Enable
Tch
Tcs
Vih
WE#
Vil
Toes
Twph
Twp
Vih
Vil
OE#
Vih
Vil
Addresses
VA
Tah
Tas
Tdh
Tds
Vih
Vil
Data
DIN
VA: Valid Address
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MX29LA640E H/L
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
Tce
Vih
CE#
Vil
Tsrw
Vih
WE#
OE#
Vil
Toeh
Tdf
Toe
Vih
Vil
Toh
Taa
Trc
Vih
Vil
ADD Valid
Addresses
Outputs
HIGH Z
HIGH Z
Voh
Vol
DATA Valid
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MX29LA640E H/L
AC CHARACTERISTICS
Item Description
Setup Speed
Unit
us
Trp1 RESET#ꢀPulseꢀWidthꢀ(DuringꢀAutomaticꢀAlgorithms)
Trp2 RESET#ꢀPulseꢀWidthꢀ(NOTꢀDuringꢀAutomaticꢀAlgorithms)
MIN
MIN
MIN
MIN
MIN
MAX
MAX
10
500
50
ns
Trh
RESET#ꢀHighꢀTimeꢀBeforeꢀRead
ns
Trb1 RY/BY#ꢀRecoveryꢀTimeꢀ(toꢀCE#,ꢀOE#ꢀgoꢀlow)
0
ns
Trb2 RY/BY#ꢀRecoveryꢀTimeꢀ(toꢀWE#ꢀgoꢀlow)
50
ns
Tready1 RESET#ꢀPINꢀLowꢀ(DuringꢀAutomaticꢀAlgorithms)ꢀtoꢀReadꢀorꢀWriteꢀ
Tready2 RESET#ꢀPINꢀLowꢀ(NOTꢀDuringꢀAutomaticꢀAlgorithms)ꢀtoꢀReadꢀorꢀWriteꢀ
20
us
500
ns
Figure 3. RESET# TIMING WAVEFORM
Trb1
CE#, OE#
WE#
Trb2
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
RY/BY#
Trh
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
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MX29LA640E H/L
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Disable
CE#
Enable
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycle
Read Status
Tah
Twc
Tas
VA
2AAh
VA
SA
Address
Tds
Tdh
In
Progress
Complete
55h
10h
Data
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
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MX29LA640E H/L
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
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MX29LA640E H/L
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
Disable
Enable
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Tas
Sector
Sector
Sector
VA
VA
2AAh
Address
Address 0
Address 1
Address n
Tah
Tds Tdh
In
Progress
Complete
55h
30h
30h
30h
Data
Tbusy
Trb
RY/BY#
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MX29LA640E H/L
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
NO
Last Sector
to Erase
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh
YES
Auto Sector Erase Completed
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MX29LA640E H/L
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
ERASE SUSPEND
NO
Toggle Bit checking Q6
not toggled
YES
Read Array or
Program
Reading or
NO
Programming End
YES
Write Data 30H
Continue Erase
ERASE RESUME
Another
NO
Erase Suspend ?
YES
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MX29LA640E H/L
Figure 9. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART
START
Enter Secured Silicon Sector
Wait 1us
First Wait Cycle Data=60h
Second Wait Cycle Data=60h
A6=0, A1=1, A0=0
Wait 300us
No
Data = 01h ?
Yes
Device Failed
Write Reset Command
Secured Sector Protect Complete
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MX29LA640E H/L
Figure 10. AUTOMATIC PROGRAM TIMING WAVEFORMS
Disable
CE#
Enable
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Tas
Last 2 Read Status Cycle
Tah
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
Trb
RY/BY#
Figure 11. Accelerated Program Timing Diagram
(9.5V ~ 10.5V)
Vhv
WP#/ACC
Vil or Vih
Vil or Vih
250ns
250ns
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MX29LA640E H/L
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
No
Read Again Data:
Program Data?
YES
No
Last Word to be
Programed
YES
Auto Program Completed
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MX29LA640E H/L
Figure 13. CE# CONTROLLED WRITE TIMING WAVEFORM
WE#
Twhwh1 or Twhwh2
Tcep
Disable
CE#
Enable
Tceph
Tghwl
OE#
Tah
Tas
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
RY/BY#
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MX29LA640E H/L
SECTOR PROTECT/CHIP UNPROTECT
Figure 14. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)
150us: Sector Protect
1us
15ms: Chip Unprotect
CE#Disable
Enable
WE#
OE#
Verification
40h
Status
VA
Data
60h
60h
VA
SA, A6
A1, A0
VA
Vhv
Vih
RESET#
VA: valid address
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MX29LA640E H/L
Figure 15-1. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No
First CMD=60h?
Yes
Set Up Sector Address
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Wait 150us
Reset
PLSCNT=1
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Retry Count +1
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
No
No
Data=01h?
Yes
Retry Count=25?
Yes
Device fail
Yes
Protect another
sector?
No
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
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MX29LA640E H/L
Figure 15-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No
First CMD=60h?
Yes
No
All sectors
protected?
Protect All Sectors
Yes
Write [A6,A1,A0]:[1,1,0]
data: 60h
Wait 15ms
Write [A6,A1,A0]:[1,1,0]
data: 40h
Retry Count +1
Read [A6,A1,A0]:[1,1,0]
No
No
Retry Count=1000?
Data=00h?
Yes
Yes
Device fail
Last sector
verified?
No
Yes
Temporary Unprotect
RESET#=Vih
Write reset CMD
Chip Unprotect Done
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MX29LA640E H/L
AC CHARACTERISTICS
Parameter Description
Test Setup
Min.
All Speed Options
Unit
us
ns
ns
us
Tvlht
Twpp1
Twpp2
Toesp
Voltageꢀtransitionꢀtime
4
Writeꢀpulseꢀwidthꢀforꢀsectorꢀprotect
Writeꢀpulseꢀwidthꢀforꢀchipꢀunprotect
OE#ꢀsetupꢀtimeꢀtoꢀWE#ꢀactive
Min.
Min.
Min.
100
100
4
Figure 16. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)
A1
A6
10V
3V
A9
Tvlht
Verify
10V
3V
OE#
Tvlht
Tvlht
Twpp1
WE#
Toesp
Disable
CE#
Enable
Data
01H
F0H
Toe
Sector Address
A21-A15
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MX29LA640E H/L
Figure 17. SECTOR PROTECTION ALGORITHM (A9, OE# Control)
START
Set Up Sector Addr
PLSCNT=1
OE#=Vhv, A9=Vhv, CE#=Vil
A6=Vil
Activate WE# Pulse
Time Out 150us
Set WE#=Vih, CE#=OE#=Vil
A9 should remain Vhv
Read from Sector
Addr=SA, A1=1
No
No
Data=01H?
PLSCNT=32?
Yes
Device Failed
Yes
Protect Another
Sector?
Remove Vhv from A9
Write Reset Command
Sector Protection
Complete
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MX29LA640E H/L
Figure 18. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control)
A1
10V
3V
A9
A6
Tvlht
Verify
10V
3V
OE#
WE#
Tvlht
Tvlht
Twpp2
Toesp
Disable
Enable
CE#
Data
00H
F0H
Toe
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MX29LA640E H/L
Figure 19. CHIP UNPROTECT FLOWCHART (A9, OE# Control)
START
Protect All Sectors
PLSCNT=1
Set OE#=A9=Vhv
CE#=Vil, A6=1
Activate WE# Pulse
Time Out 15ms
Increment
PLSCNT
Set OE#=CE#=Vil
A9=Vhv, A1=1
Set Up First Sector Addr
Read Data from Device
No
No
Data=00H?
Yes
PLSCNT=1000?
Increment
Sector Addr
Yes
Device Failed
No
All sectors have
been verified?
Yes
Remove Vhv from A9
Write Reset Command
Chip Unprotect
Complete
* It is recommended before unprotect whole chip, all sectors should be protected in advance.
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MX29LA640E H/L
AC CHARACTERISTICS
Parameter
Trpvhh
Alt Description
Condition Speed Unit
Tvidr RESET#ꢀRiseꢀTimeꢀtoꢀVhvꢀandꢀVhvꢀFallꢀTimeꢀtoꢀRESET#
Trsp RESET#ꢀVhvꢀtoꢀWE#ꢀLow
MIN
MIN
500
ns
Tvhhwl
4
us
Figure 20. TEMPORARY SECTOR UNPROTECT WAVEFORMS
Program or Erase Command Sequence
Disable
Enable
CE#
WE#
Tvhhwl
RY/BY#
RESET#
Vhv 10V
0 or Vih
Vil or Vih
Trpvhh
Trpvhh
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MX29LA640E H/L
Figure 21. TEMPORARY SECTOR UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Notes:
1.ꢀTemporaryꢀunprotectꢀallꢀprotectedꢀsectorsꢀVhv=9.5~10.5V.
2.ꢀAfterꢀleavingꢀtemporaryꢀunprotectꢀmode,ꢀtheꢀpreviouslyꢀprotectedꢀsectorsꢀareꢀagainꢀprotected.
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MX29LA640E H/L
Figure 22. SILICON ID READ TIMING WAVEFORM
VCC
3V
Vhv
ADD
A9
Vih
Vil
Vih
Vil
ADD
A0
Taa
Taa
Taa
Taa
Vih
Vil
A1
A2
Vih
Vil
Vih
Vil
ADD
Disable
Enable
CE#
Tce
Vih
Vil
WE#
Toe
Vih
Vil
OE#
Tdf
Toh
Toh
Toh
Toh
Vih
Vil
DATA
Q0-Q15
DATA OUT
Manufacturer ID
DATA OUT
DATA OUT
DATA OUT
Device ID
Cycle 1
Device ID
Cycle 2
Device ID
Cycle 3
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MX29LA640E H/L
WRITE OPERATION STATUS
Figure 23. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
Disable
CE#
Enable
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
VA
VA
Address
Taa
Toh
High Z
High Z
Complement
Status Data
Status Data
True
True
Valid Data
Valid Data
Q7
Q0-Q6
Status Data
Tbusy
RY/BY#
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1.ꢀ
ꢀꢀꢀꢀ
Forꢀprogramming,ꢀvalidꢀaddressꢀmeansꢀprogramꢀaddress.
Forꢀerasing,ꢀvalidꢀaddressꢀmeansꢀeraseꢀsectorsꢀaddress.
MX29LA640E H/L
Figure 24. DATA# POLLING ALGORITHM
Start
Read Q7~Q0 at valid address
(Note 1)
No
Q7 = Data# ?
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
No
Q7 = Data# ?
(Note 2)
Yes
FAIL
Pass
Notes:
2.ꢀQ7ꢀshouldꢀbeꢀrecheckedꢀevenꢀQ5="1"ꢀbecauseꢀQ7ꢀmayꢀchangeꢀsimultaneouslyꢀwithꢀQ5.
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MX29LA640E H/L
Figure 25. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#Disable
Enable
Tch
WE#
OE#
Toe
Toeh
Tdf
Trc
VA
VA
VA
VA
Address
Taa
Toh
Valid Status
(second read)
Valid Status
(first read)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
Tbusy
RY/BY#
VA : Valid Address
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MX29LA640E H/L
Figure 26. TOGGLE BIT ALGORITHM
Start
Read Q7-Q0 Twice
(Note 1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
NO
Q6 Toggle ?
YES
PGM/ERS fail
Write Reset CMD
PGM/ERS Complete
Note:
1.ꢀReadꢀtoggleꢀbitꢀtwiceꢀtoꢀdetermineꢀwhetherꢀorꢀnotꢀitꢀisꢀtoggling.
2.ꢀRecheckꢀtoggleꢀbitꢀbecauseꢀitꢀmayꢀstopꢀtogglingꢀasꢀQ5ꢀchangesꢀtoꢀ"1".
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MX29LA640E H/L
Figure 27. Q6 versus Q2
Enter Embedded
Erasing
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
Erase
Complete
WE#
Q6
Q2
NOTES:
The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended.
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MX29LA640E H/L
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
ACꢀtimingꢀillustratedꢀinꢀFigureꢀAꢀisꢀrecommendedꢀforꢀtheꢀsupplyꢀvoltagesꢀandꢀtheꢀcontrolꢀsignalsꢀatꢀdeviceꢀpower-
up.ꢀIfꢀtheꢀtimingꢀinꢀtheꢀfigureꢀisꢀignored,ꢀtheꢀdeviceꢀmayꢀnotꢀoperateꢀcorrectly.
Vcc(min)
Vcc
GND
Tvr
Tvcs
Tf
Tce
Tr
Disable
Enable
CE#
Vih
Vil
WE#
Tf
Toe
Tr
Vih
Vil
OE#
Taa
Tr or Tf
Tr or Tf
Vih
Vil
Valid
Address
ADDRESS
Voh
Vol
High Z
Valid
Ouput
DATA
Vih
Vil
WP#/ACC
Figure A. AC Timing at Device Power-Up
Symbol
Tvr
Parameter
VccꢀRiseꢀTime
Min.
Max.
Unit
80
500000
20
us/V
us/V
us/V
us
Tr
InputꢀSignalꢀRiseꢀTime
InputꢀSignalꢀFallꢀTime
VccꢀSetupꢀTime
Tf
20
Tvcs
200
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MX29LA640E H/L
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
LIMITS
UNITS
MIN.
TYP. (1)
MAX. (2)
2
0.7
SectorꢀEraseꢀTime
sec
sec
us
45
ChipꢀEraseꢀTime
65
11
WordꢀProgrammingꢀTime
ByteꢀProgrammingꢀTime
AcceleratedꢀByte/WordꢀProgramꢀTime
360
300
210
160
140
9
7
us
us
Byte mode
ChipꢀProgrammingꢀTime
50
sec
sec
Cycles
Word mode
45
100,000
Erase/ProgramꢀCycles
Notes:
1.ꢀ Typicalꢀprogramꢀandꢀeraseꢀtimesꢀassumeꢀtheꢀfollowingꢀconditions:ꢀ25°C,ꢀ3.0VꢀVCC.ꢀProgrammingꢀspecifica-
tionsꢀassumeꢀcheckboardꢀdataꢀpattern.
2.ꢀꢀMaximumꢀvaluesꢀareꢀmeasuredꢀatꢀVCCꢀ=ꢀ3.0ꢀV,ꢀworstꢀcaseꢀtemperature.ꢀMaximumꢀvaluesꢀareꢀvalidꢀupꢀtoꢀandꢀ
includingꢀ100,000ꢀprogram/eraseꢀcycles.
3.ꢀꢀWord/Byteꢀprogrammingꢀspecificationꢀisꢀbasedꢀuponꢀaꢀsingleꢀword/byteꢀprogrammingꢀoperationꢀnotꢀutilizingꢀ
theꢀwriteꢀbuffer.
4.ꢀ Erase/ProgramꢀcyclesꢀcomplyꢀwithꢀJEDECꢀJESD-47ꢀ&ꢀA117ꢀstandard.
DATA RETENTION
PARAMETER
Condition
Min.
Max.
UNIT
Dataꢀretention
55˚C
10
years
LATCH-UP CHARACTERISTICS
MIN.
-1.0V
MAX.
10.5V
InputꢀVoltageꢀvoltageꢀdifferenceꢀwithꢀGNDꢀonꢀWP#/ACC,ꢀA9,ꢀOE,ꢀReset#ꢀpins
InputꢀVoltageꢀvoltageꢀdifferenceꢀwithꢀGNDꢀonꢀallꢀnormalꢀpinsꢀinputꢀ
VccꢀCurrent
-1.0V
Vccꢀxꢀ1.5Vcc
+100mA
-100mA
AllꢀpinsꢀincludedꢀexceptꢀVcc.ꢀꢀTestꢀconditions:ꢀVccꢀ=ꢀ3.0V,ꢀoneꢀpinꢀperꢀtesting
PIN CAPACITANCE
Parameter Symbol
Parameter Description
ControlꢀPinꢀCapacitance
OutputꢀCapacitance
InputꢀCapacitance
Test Set
VIN=0
TYP.
7.5
8.5
6
MAX.
UNIT
pF
CIN2
COUT
CIN
9
VOUT=0
VIN=0
12
7.5
pF
pF
Notes:
1.ꢀTestꢀconditionsꢀTA=25°C,ꢀf=1.0MHz.
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MX29LA640E H/L
ORDERING INFORMATION
PART NO.
ACCESS TIME
Ball Pitch /
Ball Size
PACKAGE
Remark
(ns)
MX29LA640EHXCI-70G
MX29LA640ELXCI-70G
70
1.0mm/0.4mm
64ꢀBGA
64ꢀBGA
Pb-free
Pb-free
70
1.0mm/0.4mm
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MX29LA640E H/L
PART NAME DESCRIPTION
MX 29 LA 640 E H XC I
70 G
OPTION:
G: Lead-free package
SPEED:
70: 70ns
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
X: FBGA (CSP)
XC - 1.0mm Ball
PRODUCT TYPE:
H: Highest Address Sector
L: Lowest Address Sector
REVISION:
E
DENSITY & MODE:
640: 64M (x8/x16) Equal Sector
TYPE:
LA: 3V Security
DEVICE:
29:Flash
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MX29LA640E H/L
PACKAGE INFORMATION
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MX29LA640E H/L
REVISION HISTORY
Revision No. Description
Page
P1ꢀ
P22ꢀ
Date
DEC/19/2008ꢀ
ꢀꢀ
1.0ꢀ
ꢀ
1.ꢀRemovedꢀ"AdvancedꢀInformation"ꢀ
2.ꢀRevisedꢀCFIꢀdataꢀ-ꢀSectorꢀprotectꢀ(N=#ꢀofꢀsectors/group),ꢀꢀ
data from 0004 to 0001
ꢀ
1.1ꢀ
1.2ꢀ
1.3ꢀ
ꢀ
1.ꢀCorrectꢀtypoꢀerrorꢀ
P1,2ꢀ
P55ꢀ
FEB/25/2009
MAY/04/2009
1.ꢀAddedꢀconditionꢀofꢀdataꢀretentionꢀ
1.ꢀAddedꢀ64-FBGAꢀinformationꢀonꢀpackageꢀpinꢀconfiguration,ꢀ
ꢀꢀꢀꢀorderingꢀandꢀpartꢀname
P3,56,57ꢀ MAY/19/2010
2. Modifiedꢀnotesꢀ4ꢀ
P55
P/N:PM1424
REV. 1.3, MAY 19, 2010
59
MX29LA640E H/L
Macronix'sꢀproductsꢀareꢀnotꢀdesigned,ꢀmanufactured,ꢀorꢀintendedꢀforꢀuseꢀforꢀanyꢀhighꢀriskꢀapplicationsꢀinꢀwhichꢀ
theꢀfailureꢀofꢀaꢀsingleꢀcomponentꢀcouldꢀcauseꢀdeath,ꢀpersonalꢀinjury,ꢀsevereꢀphysicalꢀdamage,ꢀorꢀotherꢀsubstan-
tialꢀharmꢀtoꢀpersonsꢀorꢀproperty,ꢀsuchꢀasꢀlife-supportꢀsystems,ꢀhighꢀtemperatureꢀautomotive,ꢀmedical,ꢀaircraftꢀ
andꢀmilitaryꢀapplication.ꢀMacronixꢀandꢀitsꢀsuppliersꢀwillꢀnotꢀbeꢀliableꢀtoꢀyouꢀand/orꢀanyꢀthirdꢀpartyꢀforꢀanyꢀclaims,ꢀ
injuriesꢀorꢀdamagesꢀthatꢀmayꢀbeꢀincurredꢀdueꢀtoꢀuseꢀofꢀMacronix'sꢀproductsꢀinꢀtheꢀprohibitedꢀapplications.
Copyright©ꢀꢀMacronixꢀInternationalꢀCo.,ꢀLtd.ꢀ2008~2010.ꢀAllꢀRightsꢀReserved.ꢀMacronix,ꢀMXIC,ꢀMXICꢀLogo,ꢀ
MXꢀLogo,ꢀꢀareꢀtrademarksꢀorꢀregisteredꢀtrademarksꢀofꢀMacronixꢀInternationalꢀCo.,ꢀLtd.ꢀꢀTheꢀnamesꢀandꢀbrandsꢀ
ofꢀotherꢀcompaniesꢀareꢀforꢀidentificationꢀpurposesꢀonlyꢀandꢀmayꢀbeꢀclaimedꢀasꢀtheꢀpropertyꢀofꢀtheꢀrespectiveꢀ
companies.
Forꢀtheꢀcontactꢀandꢀorderꢀinformation,ꢀpleaseꢀvisitꢀMacronix’sꢀWebꢀsiteꢀat:ꢀhttp://www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
60
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MX29LA641DHXCI-90G
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