MX29LV161DBXHI90G [Macronix]
16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY;
| 型号： | MX29LV161DBXHI90G |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | 16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY |
| 文件： | 总63页 (文件大小：2210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX29LV161D T/B
MX29LV161D T/B
DATASHEET
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MX29LV161D T/B
Contents
FEATURES ............................................................................................................................................................5
GENERAL DESCRIPTION ....................................................................................................................................6
PIN CONFIGURATIONS........................................................................................................................................7
PIN DESCRIPTION................................................................................................................................................9
BLOCK DIAGRAM...............................................................................................................................................10
BLOCK DIAGRAM DESCRIPTION..................................................................................................................... 11
BLOCK STRUCTURE..........................................................................................................................................12
Table 1-1. MX29LV161DT SECTOR ARCHITECTURE ............................................................................. 12
Table 1-2. MX29LV161DB SECTOR ARCHITECTURE ............................................................................ 13
BUS OPERATIONS .............................................................................................................................................14
Table 2-1. BUS OPERATION ..................................................................................................................... 14
Table 2-2. BUS OPERATION ..................................................................................................................... 15
FUNCTIONAL OPERATION DESCRIPTIONS....................................................................................................16
WRITE COMMANDS/COMMAND SEQUENCES...................................................................................... 16
REQUIREMENTS FOR READING ARRAY DATA...................................................................................... 16
RESET# OPERATION ............................................................................................................................... 17
SECTOR PROTECT OPERATION ............................................................................................................ 17
CHIP UNPROTECT OPERATION............................................................................................................. 17
HARDWARE WRITE PROTECT................................................................................................................ 17
ACCELERATED PROGRAMMING OPERATION ..................................................................................... 17
TEMPORARY SECTOR UNPROTECT OPERATION ............................................................................... 18
AUTOMATIC SELECT OPERATION.......................................................................................................... 18
VERIFY SECTOR PROTECT STATUS OPERATION................................................................................ 18
DATA PROTECTION.................................................................................................................................. 18
LOW VCC WRITE INHIBIT ........................................................................................................................ 18
WRITE PULSE "GLITCH" PROTECTION.................................................................................................. 19
LOGICAL INHIBIT...................................................................................................................................... 19
POWER-UP SEQUENCE .......................................................................................................................... 19
POWER-UP WRITE INHIBIT ..................................................................................................................... 19
POWER SUPPLY DECOUPLING.............................................................................................................. 19
COMMAND OPERATIONS..................................................................................................................................20
TABLE 3. MX29LV161D T/B COMMAND DEFINITIONS........................................................................... 20
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY ..................................................................... 21
ERASING THE MEMORY ARRAY............................................................................................................. 21
SECTOR ERASE ....................................................................................................................................... 22
CHIP ERASE............................................................................................................................................. 23
SECTOR ERASE SUSPEND..................................................................................................................... 23
SECTOR ERASE RESUME....................................................................................................................... 24
AUTOMATIC SELECT OPERATIONS ....................................................................................................... 24
AUTOMATIC SELECT COMMAND SEQUENCE ...................................................................................... 24
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MX29LV161D T/B
READ MANUFACTURER ID OR DEVICE ID ............................................................................................ 25
VERIFY SECTOR PROTECTION.............................................................................................................. 25
RESET ...................................................................................................................................................... 25
COMMON FLASH MEMORY INTERFACE (CFI) MODE ....................................................................................26
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE.................................................. 26
Table 4-1. CFI mode: Identification Data Values ........................................................................................ 26
Table 4-2. CFI Mode: System Interface Data Values ................................................................................. 26
Table 4-3. CFI Mode: Device Geometry Data Values................................................................................. 27
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values........................................... 28
ELECTRICAL CHARACTERISTICS ...................................................................................................................29
ABSOLUTE MAXIMUM STRESS RATINGS.............................................................................................. 29
OPERATING TEMPERATURE AND VOLTAGE......................................................................................... 29
DC CHARACTERISTICS ........................................................................................................................... 30
SWITCHING TEST CIRCUIT..................................................................................................................... 31
SWITCHING TEST WAVEFORM.............................................................................................................. 31
AC CHARACTERISTICS ........................................................................................................................... 32
WRITE COMMAND OPERATION........................................................................................................................33
Figure 1. COMMAND WRITE OPERATION............................................................................................... 33
READ/RESET OPERATION ................................................................................................................................34
Figure 2. READ TIMING WAVEFORM....................................................................................................... 34
Figure 3. RESET# TIMING WAVEFORM.................................................................................................. 35
ERASE/PROGRAM OPERATION .......................................................................................................................36
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM ..................................................................... 36
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART........................................................... 37
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM............................................................... 38
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART ................................................... 39
Figure 8. ERASE SUSPEND/RESUME FLOWCHART ............................................................................. 40
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM......................................................................... 41
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM.................................................................... 41
Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM.................................................................. 42
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART................................................... 43
SECTOR PROTECT/CHIP UNPROTECT ...........................................................................................................44
Figure 13. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control) ........................... 44
Figure 14. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv........................................................... 45
Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv........................................................... 46
Table 5. TEMPORARY SECTOR UNPROTECT........................................................................................ 47
Figure 16. TEMPORARY SECTOR UNPROTECT WAVEFORM .............................................................. 47
Figure 17. TEMPORARY SECTOR UNPROTECT FLOWCHART............................................................. 48
Figure 18. SILICON ID READ TIMING WAVEFORM................................................................................. 49
WRITE OPERATION STATUS.............................................................................................................................50
Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)...................... 50
Figure 20. DATA# POLLING ALGORITHM ................................................................................................ 51
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MX29LV161D T/B
Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)........................... 52
Figure 22. TOGGLE BIT ALGORITHM....................................................................................................... 53
RECOMMENDED OPERATING CONDITIONS...................................................................................................54
ERASE AND PROGRAMMING PERFORMANCE..............................................................................................55
DATA RETENTION ..............................................................................................................................................55
LATCH-UP CHARACTERISTICS........................................................................................................................55
TSOP PIN CAPACITANCE ..................................................................................................................................55
ORDERING INFORMATION................................................................................................................................56
PART NAME DESCRIPTION...............................................................................................................................57
PACKAGE INFORMATION..................................................................................................................................58
REVISION HISTORY ...........................................................................................................................................62
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MX29LV161D T/B
16M-BIT [1M x 16] 3V SUPPLY FLASH MEMORY
FEATURES
GENERAL FEATURES
• Word mode only
- 1,048,576 x 16
• Sector Structure
- 8K-Word x 1, 4K-Word x 2, 16K-Word x 1, 32K-Word x 31
- Provides sector protect function to prevent program or erase operation in the protected sector
- Provides chip unprotect function to allow code changing
- Provides temporary sector unprotect function for code changing in previously protected sector
• Power Supply Operation
- VCC 2.7 to 3.6 volt for read, erase, and program operations
- VI/O 1.65V to 3.6V for Input/Output
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc ≤ Vlko
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
PERFORMANCE
• High Performance
- Fast access time: 90ns
- Word program time: 11us/word (typical)
- Fast erase time: 0.7s/sector, 15s/chip (typical)
• Low Power Consumption
- Low active read current: 5mA (typical) at 5MHz
- Low standby current: 5uA (typical)
• 100,000 erase/program cycle (typical)
• 20 years data retention
SOFTWARE FEATURES
• Erase Suspend/ Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC
- Provide accelerated program capability
PACKAGE
• 48-Pin TSOP
• 48-Ball CSP (TFBGA)
• 48-Ball WFBGA/XFLGA
• All Pb-free devices are RoHS Compliant
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MX29LV161D T/B
GENERAL DESCRIPTION
MX29LV161DT/B is a 16Mbit flash memory that can be organized as 1,048,576 words. These devices operate
over a voltage range of 2.7V to 3.6V typically using a 3V power supply input. The memory array is divided into 32
equal 64 Kilo byte blocks. However, depending on the device being used as a Top-Boot or Bottom-Boot device.
The outermost two sectors at the top or at the bottom are respectively the boot blocks for this device.
The MX29LV161DT/B is offered in a 48-pin TSOP, 48-ball XFLGA/WFBGA and a 48-ball CSP(TFBGA) JEDEC
standard package. These packages are offered lead-free versions that are compliant to the RoHS specifications.
The software algorithm used for this device also adheres to the JEDEC standard for single power supply devic-
es. These flash parts can be programmed in system or on commercially available EPROM/Flash programmers.
Separate OE# and CE# (Output Enable and Chip Enable) signals are provided to simplify system design. When
used with high speed processors, the 90ns read access time of this flash memory permits operation with minimal
time lost due to system timing delays.
The automatic write algorithm provided on Macronix flash memories perform an automatic erase prior to write.
The user only needs to provide a write command to the command register. The on-chip state machine automati-
cally controls the program and erase functions including all necessary internal timings. Since erase and write
operations take much longer time than read operations, erase/write can be interrupted to perform read opera-
tions in other sectors of the device. For this, Erase Suspend operation along with Erase Resume operation are
provided. Data# polling or Toggle bits are used to indicate the end of the erase/write operation.
These devices are manufactured at the Macronix fabrication facility using the time tested and proven MXIC's
advance technology. This proprietary non-epi process provides a very high degree of latch-up protection for
stresses up to 100 milliamperes on address and data pins from -1V to 1.5xVCC.
With low power consumption and enhanced hardware and software features, this flash memory retains data reli-
ably for at least twenty years. Erase and programming functions have been tested to meet a typical specification
of 100,000 cycles of operation.
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MX29LV161D T/B
PIN CONFIGURATIONS
48 TSOP (Standard Type) (12mm x 20mm)
A15
A14
A13
A12
A11
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
VI/O
GND
Q15
Q7
2
3
4
5
A10
A9
6
Q14
Q6
7
A8
8
Q13
Q5
A19
NC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q12
Q4
WE#
RESET#
NC
VCC
Q11
Q3
WP#/ACC
RY/BY#
A18
A17
A7
Q10
Q2
Q9
Q1
A6
Q8
A5
Q0
A4
OE#
GND
CE#
A0
A3
A2
A1
48-Ball CSP (TFBGA) (Ball Pitch =0.8mm, Top View, Balls Facing Down, 6 x 8 mm)
GND
V
I/O
A13
A9
A12
A8
A14
A15
A16
Q15
Q13
6
5
4
3
2
1
A10
NC
Q7
Q5
Q14
Q12
Q6
Q4
A11
A19
RE-
SET#
WE#
VCC
WP#/
ACC
RY/
BY#
A18
A6
NC
A5
A1
Q2
Q0
Q10
Q8
Q11
Q9
Q3
Q1
A7
A3
A17
A4
A2
C
GND
A0
E
CE#
F
OE#
G
A
B
D
H
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MX29LV161D T/B
48-Ball WFBGA (Balls Facing Down, 4 x 6 x 0.75 mm)
RE-
SET#
A11
WE#
A9
A2
A1
A0
A4
A6
A17
NC
NC
6
5
4
3
2
1
WP#/
ACC
VI/O
A3
A5
A7
A10
A8
A13
A12
A14
A15
A18
CE#
Q8
Q10
Q9
Q4
Q5
Q11
Q6
A16
Q7
GND
A19
Q2
OE#
Q0
NC
Q15
Q1
C
Q13
GND
Q3
E
VCC
F
Q12
G
Q14
J
A
B
D
H
K
L
48-Ball XFLGA (Balls Facing Down, 4 x 6 x 0.5 mm)
RE-
SET#
A11
WE#
A9
A2
A1
A0
A4
A6
A17
NC
NC
6
5
4
3
2
1
WP#/
ACC
VI/O
A3
A5
A7
A10
A8
A13
A12
A14
A15
A18
CE#
Q8
Q10
Q9
Q4
Q5
Q11
Q6
A16
Q7
GND
A19
Q2
OE#
Q0
NC
Q15
Q1
C
Q13
GND
Q3
E
VCC
F
Q12
G
Q14
J
A
B
D
H
K
L
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MX29LV161D T/B
LOGIC SYMBOL
PIN DESCRIPTION
Vcc
VI/O
SYMBOL PIN NAME
A0~A19 Address Input
Q0~Q15 Data Input/Output
20
16
CE#
Chip Enable Input
Write Enable Input
A0-A19
Q0-Q15
WE#
Hardware Reset Pin/Sector Protect
Unlock
RESET#
OE#
Output Enable Input
CE#
OE#
RY/BY# Ready/Busy Output
WE#
VCC
GND
VI/O
Power Supply Pin (2.7V~3.6V)
Ground Pin
RESET#
WP#/ACC
RY/BY#
Power Supply for Input/Output
WP#/ACC Hardware write Protect/Acceleration Pin
NC
Pin Not Connected Internally
GND
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MX29LV161D T/B
BLOCK DIAGRAM
WRITE
CE#
OE#
CONTROL
INPUT
PROGRAM/ERASE
STATE
MACHINE
(WSM)
WE#
HIGH VOLTAGE
RESET#
WP#/ACC
LOGIC
STATE
FLASH
ARRAY
ADDRESS
LATCH
REGISTER
ARRAY
A0-AM
AND
SOURCE
HV
BUFFER
Y-PASS GATE
COMMAND
DATA
DECODER
PGM
SENSE
DATA
HV
AMPLIFIER
COMMAND
DATA LATCH
PROGRAM
DATA LATCH
Q0-Q15
I/O BUFFER
AM: MSB address
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MX29LV161D T/B
BLOCK DIAGRAM DESCRIPTION
The block diagram on Page 10 illustrates a simplified architecture of MX29LV161D T/B. Each block in the block
diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the
memory array.
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET# and WP#/ACC. It creates
internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND BUFFER"
to latch the external address pins A0-AM(A19). The internal addresses are output from this block to the main ar-
ray and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", and "FLASH ARRAY". The X-
DECODER decodes the word-lines of the flash array, while the Y-DECODER decodes the bit-lines of the flash ar-
ray. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" selectively through
the y-pass gates. Sense amplifiers are used to read out the contents of the flash memory, while the "PGM DATA
HV" block is used to selectively deliver high power to bit-lines during programming. The "I/O BUFFER" controls
the input and output on the Q0-Q15 pads. During read operation, the I/O buffer receives data from sense ampli-
fiers and drives the output pads accordingly. In the last cycle of program command, the I/O buffer transmits the
data on Q0-Q15 to "PROGRAM DATA LATCH", which controls the high power drivers in "PGM DATA HV" to se-
lectively program the bits in a word according to the user input pattern.
The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary
high voltage to the "X-DECODER", "FLASH ARRAY", and "PGM DATA HV" block. The logic control module
comprises of the "WRITE STATE MACHINE(WSM)", "STATE REGISTER", "COMMAND DATA DECODER", and
"COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-Q15 is
latched in the command data latch and is decoded by the command data decoder. The state register receives
the command and records the current state of the device. The WSM implements the internal algorithms for pro-
gram or erase according to the current command state by controlling each block in the block diagram.
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MX29LV161D T/B
BLOCK STRUCTURE
The main flash memory array can be organized as 1M Words. The details of the address ranges and the cor-
responding sector addresses are shown in Table 1-1&1-2. Table 1-1. shows the sector architecture for the Top
Boot part, whereas Table 1-2. shows the sector architecture for the Bottom Boot part.
Table 1-1. MX29LV161DT SECTOR ARCHITECTURE
Sector Size
Word Mode (Kwords)
32
Sector Address
A19-A12
Address Range
Word Mode (x16)
000000h-07FFFh
Sector
SA0
SA1
00000xxx
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
16
4
00001xxx
00010xxx
00011xxx
00100xxx
00101xxx
00110xxx
00111xxx
01000xxx
01001xxx
01010xxx
01011xxx
01100xxx
01101xxx
01110xxx
01111xxx
10000xxx
10001xxx
10010xxx
10011xxx
10100xxx
10101xxx
10110xxx
10111xxx
11000xxx
11001xxx
11010xxx
11011xxx
11100xxx
11101xxx
11110xxx
111110xx
11111100
11111101
1111111x
008000h-0FFFFh
010000h-17FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FBFFFh
0FC000h-0FCFFFh
0FD000h-0FDFFFh
0FE000h-0FFFFFh
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
4
8
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MX29LV161D T/B
Table 1-2. MX29LV161DB SECTOR ARCHITECTURE
Sector Size
Sector
Sector Address
A19-A12
Address Range
Word Mode (x16)
000000h-001FFFh
Word Mode (Kwords)
8
SA0
SA1
0000000x
4
00000010
00000011
000001xx
00001xxx
00010xxx
00011xxx
00100xxx
00101xxx
00110xxx
00111xxx
01000xxx
01001xxx
01010xxx
01011xxx
01100xxx
01101xxx
01110xxx
01111xxx
10000xxx
10001xxx
10010xxx
10011xxx
10100xxx
10101xxx
10110xxx
10111xxx
11000xxx
11001xxx
11010xxx
11011xxx
11100xxx
11101xxx
11110xxx
11111xxx
002000h-002FFFh
003000h-003FFFh
004000h-007FFFh
008000h-00FFFFh
010000h-017FFFh
018000h-01FFFFh
020000h-027FFFh
028000h-02FFFFh
030000h-037FFFh
038000h-03FFFFh
040000h-047FFFh
048000h-04FFFFh
050000h-057FFFh
058000h-05FFFFh
060000h-067FFFh
068000h-06FFFFh
070000h-077FFFh
078000h-07FFFFh
080000h-087FFFh
088000h-08FFFFh
090000h-097FFFh
098000h-09FFFFh
0A0000h-0A7FFFh
0A8000h-0AFFFFh
0B0000h-0B7FFFh
0B8000h-0BFFFFh
0C0000h-0C7FFFh
0C8000h-0CFFFFh
0D0000h-0D7FFFh
0D8000h-0DFFFFh
0E0000h-0E7FFFh
0E8000h-0EFFFFh
0F0000h-0F7FFFh
0F8000h-0FFFFFh
4
SA2
16
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
SA13
SA14
SA15
SA16
SA17
SA18
SA19
SA20
SA21
SA22
SA23
SA24
SA25
SA26
SA27
SA28
SA29
SA30
SA31
SA32
SA33
SA34
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MX29LV161D T/B
BUS OPERATIONS
Table 2-1. BUS OPERATION
Data I/O
Mode Select
Device Reset
RESET#
CE#
WE#
OE#
Address
WP#/ACC
Q0~Q7
HighZ
HighZ
HighZ
L
X
X
X
H
X
X
H
X
X
X
L/H
H
Standby Mode
Vcc±0.3V Vcc± 0.3V
Output Disable
H
H
H
H
L
L
L
L
L/H
Read Mode
H
L
L
L
H
H
AIN
AIN
AIN
DOUT
DIN
L/H
Note3
Vhv
Write (Note1)
Accelerate Program
DIN
Temporary Sector
Unprotect
Vhv
Vhv
Vhv
X
L
L
X
L
L
X
H
H
AIN
DIN
Note3
L/H
Sector Protect
(Note2)
Sector Address,
A6=L, A1=H, A0=L
DIN, DOUT
DIN, DOUT
Chip Unprotect
(Note2)
Sector Address,
A6=H, A1=H, A0=L
Note3
Notes:
1. All sectors will be unprotected if WP#/ACC=Vhv.
2. The one outmost boot sectors are protected if WP#/ACC=Vil.
3. When WP#/ACC = Vih, the protection conditions of the one outmost boot sectors depend on previous protec-
tion conditions."Sector/Sector Block Protection and Unprotection" describes the protect and unprotect meth-
od.
4. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector pro-
tection, or data polling algorithm.
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MX29LV161D T/B
Table 2-2. BUS OPERATION
Control Input
CE# WE# OE#
AM A11
to to A9 to A6 to A1 A0
A12 A10
A8
A5
Item
Q0 ~ Q7
Q8 ~ Q15
A7
A2
Sector Lock Status
Verification
01h or 00h
(Note 1)
L
L
L
L
H
H
H
H
L
L
L
L
SA
x
x
x
x
x
Vhv
Vhv
Vhv
Vhv
x
L
L
L
L
x
H
L
L
L
L
L
x
Read Silicon ID
Manufacturer
Code
x
x
x
x
x
x
C2h
C4h
49h
x
Read Silicon ID
MX29LV161DT
x
H
H
22h
22h
Read Silicon ID
MX29LV161DB
x
Notes:
1. Sector unprotected code:00h. Sector protected code:01h.
2. AM: MSB of address.
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MX29LV161D T/B
FUNCTIONAL OPERATION DESCRIPTIONS
WRITE COMMANDS/COMMAND SEQUENCES
To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle,
all addresses are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising
edge of CE# and WE#.
Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets
of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid
command will bring the device to an undefined state.
REQUIREMENTS FOR READING ARRAY DATA
Read array action is to read the data stored in the array. While the memory device is in powered up or has been
reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in ar-
ray, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of
the data to be read into address pins at the same time. After a period of read cycle (Tce or Taa), the data being
read out will be displayed on output pins for microprocessor to access. If CE# or OE# is Vih, the output will be in
tri-state, and there will be no data displayed on output pin at all.
After the memory device completes embedded operation (automatic Erase or Program), it will automatically re-
turn to the status of read array, and the device can read the data in any address in the array. In the process of
erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a
period of time no more than Tready1 and the device will return to the status of read array. At this time, the device
can read the data stored in any address except the sector being erased in the array. In the status of erase sus-
pend, if user wants to read the data in the sectors being erased, the device will output status data onto the out-
put. Similarly, if program command is issued after erase suspend, after program operation is completed, system
can still read array data in any address except the sectors to be erased.
The device needs to issue reset command to enable read array operation again in order to arbitrarily read the
data in the array in the following two situations:
1. In program or erase operation, the programming or erasing failure causes Q5 to go high.
2. The device is in auto select mode or CFI mode.
In the two situations above, if reset command is not issued, the device is not in read array mode and system
must issue reset command before reading array data.
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MX29LV161D T/B
RESET# OPERATION
Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in
program or erase operation, the reset operation will take at most a period of Tready1 for the device to return to
read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status).
When RESET# pin is held at GND 0.3V, the device consumes standby current(Isb).However, device draws larg-
±
er current if RESET# pin is held at Vil but not within GND 0.3V.
±
It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memo-
ry will be reset during system reset and allows system to read boot code from flash memory.
SECTOR PROTECT OPERATION
When a sector is protected, program or erase operation will be disabled on that protected sector. MX29LV161D
T/B provides two methods for sector protection.
Once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected
by asserting RESET# pin at Vhv. Refer to temporary sector unprotect operation for further details.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 13 for the
algorithm for this method.
The other method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins
at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
CHIP UNPROTECT OPERATION
MX29LV161D T/B provides two methods for chip unprotect. The chip unprotect operation unprotects all sectors
within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sectors are
unprotected when shipped from the factory.
The first method is by applying Vhv on RESET# pin. Refer to Figure 12 for timing diagram and Figure 14 for al-
gorithm of the operation.
The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil. The unprotect operation
begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
HARDWARE WRITE PROTECT
By driving the WP#/ACC pin LOW, the outermost one boot sectors are protected from all erase/program opera-
tions. If WP#/ACC is held HIGH (Vih), these one outermost sectors revert to their previously protected/unpro-
tected status.
ACCELERATED PROGRAMMING OPERATION
By applying high voltage (Vhv) to the WP#/ACC pin, the device will enter the Accelerated Programming mode.
This mode permits the system to skip the normal command unlock sequences and program word locations di-
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MX29LV161D T/B
rectly.
Typically, this mode provides a 30% reduction in overall programming times. During accelerated programming,
the current drawn from the WP#/ACC pin is no more than ICP1.
TEMPORARY SECTOR UNPROTECT OPERATION
System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously
protected sectors can be programmed or erased just as it is unprotected. The devices return to normal operation
once Vhv is removed from RESET# pin and previously protected sectors are again protected.
AUTOMATIC SELECT OPERATION
When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read
silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several
silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will out-
put Macronix Manufacture ID C2h. When A0 is high, device will output Device ID. In read silicon ID mode, issu-
ing reset command will reset device back to read array mode or erase-suspended read array mode.
Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While
the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read
array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID
C2h. When A0 is high, device will output Device ID.
VERIFY SECTOR PROTECT STATUS OPERATION
MX29LV161D T/B provides hardware sector protection against Program and Erase operation for protected sec-
tors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on
A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to AM pins. If the
read out data is 01h, the designated sector is protected. Oppositely, if the read out data is 00h, the designated
sector is not protected.
DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode
during power up. Besides, only after successful completion of the specified command sets will the device begin
its erase or program operation.
Other features to protect the data from accidental alternation are described as followed.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than Vlko. This prevents data from spuriously
altered. The device automatically resets itself when Vcc is lower than Vlko and write cycles are ignored until Vcc
is greater than Vlko. System must provide proper signals on control pins after Vcc is larger than Vlko to avoid un-
intentional program or erase operation.
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MX29LV161D T/B
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at
Vih, WE# at Vih, or OE# at Vil.
POWER-UP SEQUENCE
Upon power up, MX29LV161D T/B is placed in read array mode. Furthermore, program or erase operation will
begin only after successful completion of specified command sequences.
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on
the rising edge of WE#.
POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
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MX29LV161D T/B
COMMAND OPERATIONS
TABLE 3. MX29LV161D T/B COMMAND DEFINITIONS
Automatic Select
Command
Read Mode Reset Mode
Program
Chip Erase
Manifacture
Sector
Protect Verify
555
Device ID
ID
555
Addr
Data
Addr
Data
Addr
Data
Addr
Addr
XXX
F0
555
AA
2AA
55
555
90
X01
555
AA
2AA
55
555
A0
555
AA
2AA
55
555
80
555
AA
1st Bus
Cycle
Data
AA
2AA
55
555
90
AA
2AA
55
555
90
2nd Bus
Cycle
3rd Bus
Cycle
X00
(Sector) X02
Address
4th Bus
Cycle
Data
C2h
ID
00/01
Data
Addr
Data
Addr
Data
2AA
55
555
10
5th Bus
Cycle
6th Bus
Cycle
Erase
Suspend
Erase
Resume
Command
Sector Erase CFI Read
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
Addr
Data
555
AA
2AA
55
555
80
555
AA
2AA
55
Sector
30
55
98
XXX
B0
XXX
30
1st Bus
Cycle
2nd Bus
Cycle
3rd Bus
Cycle
4th Bus
Cycle
5th Bus
Cycle
6th Bus
Cycle
Notes:
1. Device ID : MX29LV161DT: 22C4h; MX29LV161DB: 2249h.
2. For sector protect verify result, XX00h/00h means sector is not protected, XX01h/01h means sector has been
protected.
3. Sector Protect command is valid during Vhv at RESET# pin, Vih at A1 pin and Vil at A0, A6 pins. The last Bus
cycle is for protect verify.
4. It is not allowed to adopt any other code which is not in the above command definition table.
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MX29LV161D T/B
COMMAND OPERATIONS (cont'd)
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY
The MX29LV161D T/B provides the user the ability to program the memory array in Word mode. As long as the
users enters the correct cycle defined in the Table 3 (including 2 unlock cycles and the A0h program command),
any word data provided on the data lines by the system will automatically be programmed into the array at the
specified location.
After the program command sequence has been executed, the internal write state machine (WSM) automatically
executes the algorithms and timings necessary for programming and verification, which includes generating suit-
able program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do
not pass verification or have low margins. The internal controller protects cells that do pass verification and mar-
gin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells
continue to be programmed.
With the internal WSM automatically controlling the programming process, the user only needs to enter the pro-
gram command and data once.
Programming will only change the bit status from "1" to "0". It is not possible to change the bit status from "0" to
"1" by programming. This can only be done by an erase operation. Furthermore, the internal write verification
only checks and detects errors in cases where a "1" is not successfully programmed to "0".
Any commands written to the device during programming will be ignored except hardware reset, which will termi-
nate the program operation after a period of time no more than Tready1. When the embedded program algorithm
is complete or the program operation is terminated by a hardware reset, the device will return to Read mode.
After the embedded program operation has begun, the user can check for completion by reading the following
bits in the status register:
Status
Q7*1
Q7#
Q7
Q6*1
Toggling
Q5
0
RY/BY# *2
In progress *3
Finished
0
1
0
Stop toggling
Toggling
0
Exceed time limit
Q7#
1
*1: When an attempt is made to program a protected sector, the program operation will abort thus preventing
any data changes in the protected sector. Q7 will output complement data and Q6 will toggle briefly (1us or less)
before aborting and returning the device to Read mode.
*2: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
*3: The status "in progress" means both program and erase-suspended program mode.
ERASING THE MEMORY ARRAY
There are two types of erase operations performed on the memory array -- Sector Erase and Chip Erase. In the
Sector Erase operation, one or more selected sectors may be erased simultaneously. In the Chip Erase opera-
tion, the complete memory array is erased except for any protected sectors.
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MX29LV161D T/B
COMMAND OPERATIONS (cont'd)
SECTOR ERASE
The sector erase operation is used to clear data within a sector by returning all of its memory locations to the
"1" state. It requires six command cycles to initiate the erase operation. The first two cycles are "unlock cycles",
the third is a configuration cycle, the fourth and fifth are also "unlock cycles", and the sixth cycle is the Sector
Erase command. After the sector erase command sequence has been issued, an internal 50us time-out counter
is started. Until this counter reaches zero, additional sector addresses and Sector Erase commands may be is-
sued thus allowing multiple sectors to be selected and erased simultaneously. After the 50us time-out counter
has expired, no new commands will be accepted and the embedded sector erase operation will begin. Note that
the 50us timer-out counter is restarted after every erase command sequence. If the user enters any command
other than Sector Erase or Erase Suspend during the time-out period, the erase operation will abort and the de-
vice will return to Read mode.
After the embedded sector erase operation begins, all commands except Erase Suspend will be ignored. The
only way to interrupt the operation is with an Erase Suspend command or with a hardware reset. The hardware
reset will completely abort the operation and return the device to Read mode.
The system can determine the status of the embedded sector erase operation by the following methods:
Status
Time-out period
In progress
Q7
0
Q6
Q5
0
Q3 (*1)
Q2
RY/BY#(*2)
Toggling
0
1
1
1
Toggling
Toggling
1
0
0
1
0
0
Toggling
0
Finished
1
Stop toggling
Toggling
0
Exceeded time limit
0
1
Toggling
Note :
1. The Q3 status bit is the time-out indicator. When Q3=0, the time-out counter has not yet reached zero and
a new Sector Erase command may be issued to specify the address of another sector to be erased. When
Q3=1, the time-out counter has expired and the Sector Erase operation has already begun. Erase Suspend
is the only valid command that may be issued once the embedded erase operation is underway.
2. RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
3. When an attempt is made to erase only protected sector(s), the program operation will abort thus preventing
any data changes in the protected sector(s). Q7 will output its complement data and Q6 will toggle briefly (100us
or less) before aborting and returning the device to Read mode. If unprotected sectors are also specified,
however, they will be erased normally and the protected sector(s) will remain unchanged.
4. Q2 is a localized indicator showing a specified sector is undergoing erase operation or not. Q2 toggles when
user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase
suspend mode). When a sector has been completely erased, Q2 stops toggling at the sector even when the
device is still in erase operation for remaining selected sectors. At that circumstance, Q2 will still toggle when
device is read at any other sector that remains to be erased.
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MX29LV161D T/B
COMMAND OPERATIONS (cont'd)
CHIP ERASE
The Chip Erase operation is used erase all the data within the memory array. All memory cells containing a "0"
will be returned to the erased state of "1". This operation requires 6 write cycles to initiate the action. The first
two cycles are "unlock" cycles, the third is a configuration cycle, the fourth and fifth are also "unlock" cycles, and
the sixth cycle initiates the chip erase operation.
During the chip erase operation, no other software commands will be accepted, but if a hardware reset is re-
ceived or the working voltage is too low, that chip erase will be terminated. After Chip Erase, the chip will auto-
matically return to Read mode.
The system can determine the status of the embedded chip erase operation by the following methods:
Status
In progress
Finished
Q7
0
1
Q6
Toggling
Stop toggling
Toggling
Q5
0
0
Q2
Toggling
1
RY/BY#*1
0
1
0
Exceed time limit
0
1
Toggling
*1: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
SECTOR ERASE SUSPEND
After beginning a sector erase operation, Erase Suspend is the only valid command that may be issued. If sys-
tem issues an Erase Suspend command during the 50us time-out period following a Sector Erase command, the
time-out period will terminate immediately and the device will enter Erase-Suspended Read mode. If the system
issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter
Erase-Suspended Read mode until Tready1 time has elapsed. The system can determine if the device has en-
tered the Erase-Suspended Read mode through Q6, Q7, and RY/BY#.
After the device has entered Erase-Suspended Read mode, the system can read or program any sector(s) ex-
cept those being erased by the suspended erase operation. Reading any sector being erased or programmed
will return the contents of the status register. Whenever a suspend command is issued, user must issue a re-
sume command and check Q6 toggle bit status, before issue another erase command. The system can use the
status register bits shown in the following table to determine the current state of the device:
Status
Q7
1
Data
Q6
No toggle
Data
Q5
0
Data
0
Q3
N/A
Data
N/A
Q2 RY/BY#
Erase suspend read in erase suspended sector
Erase suspend read in non-erase suspended sector
Erase suspend program in non-erase suspended sector Q7#
Toggle
1
1
0
Data
N/A
Toggle
When the device has suspended erasing, user can execute the command sets except sector erase and chip
erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume.
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MX29LV161D T/B
COMMAND OPERATIONS (cont'd)
SECTOR ERASE RESUME
The sector Erase Resume command is valid only when the device is in Erase-Suspended Read mode. After
erase resumes, the user can issue another Ease Suspend command, but there should be a 4ms interval be-
tween Ease Resume and the next Erase Suspend command. If the user enters an infinite suspend-resume loop,
or suspend-resume exceeds 1024 times, erase times will increase dramatically.
AUTOMATIC SELECT OPERATIONS
When the device is in Read mode, Erase-Suspended Read mode, or CFI mode, the user can issue the Automat-
ic Select command shown in Table 3 (two unlock cycles followed by the Automatic Select command 90h) to enter
Automatic Select mode. After entering Automatic Select mode, the user can query the Manufacturer ID, Device
ID, or Sector protected status multiple times without issuing a new Automatic Select command.
While In Automatic Select mode, issuing a Reset command (F0h) will return the device to Read mode (or Erase-
Suspended Read mode if Erase-Suspend was active).
Another way to enter Automatic Select mode is to use one of the bus operations shown in Table 2-2. BUS
OPERATION. After the high voltage (Vhv) is removed from the A9 pin, the device will automatically return to
Read mode or Erase-Suspended Read mode.
AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not a sector is
protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by
a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of
times without entering another command sequence. The reset command is necessary to exit the Automatic Se-
lect mode and back to read array. The following table shows the identification code with corresponding address.
Address (Hex)
Data (Hex)
00C2
22C4/2249
00/01
Representation
Manufacturer ID
Device ID
Sector Protect Verify
X00
X01
Top/Bottom Boot Sector
Unprotected/protected
(Sector address) X 02
After entering automatic select mode, no other commands are allowed except the reset command.
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MX29LV161D T/B
COMMAND OPERATIONS (cont'd)
READ MANUFACTURER ID OR DEVICE ID
The Manufacturer ID (identification) is a unique hexadecimal number assigned to each manufacturer by the JE-
DEC committee. Each company has its own manufacturer ID, which is different from the ID of all other compa-
nies. The number assigned to Macronix is C2h.
The Device ID is a unique hexadecimal number assigned by the manufacturer for each one of the flash devices
made by that manufacturer.
The above two ID types are stored in a 16-bit register on the flash device -- eight bits for each ID. This register is
normally read by the user or by the programming machine to identify the manufacturer and the specific device.
After entering Automatic Select mode, performing a read operation with A1 & A0 held LOW will cause the device
to output the Manufacturer ID on the Data I/O (Q7 to Q0) pins. Performing a read operation with A1 LOW and A0
HIGH will cause the device to output the Device ID.
VERIFY SECTOR PROTECTION
After entering Automatic Select mode, performing a read operation with A1 held HIGH and A0, A6 held LOW and
the address of the sector to be checked applied to A19 to A12, data bit Q0 will indicate the protected status of the
addressed sector. If Q0 is HIGH, the sector is protected. Conversely, if Q0 is LOW, the sector is unprotected.
RESET
In the following situations, executing reset command will reset device back to read array mode:
• Among erase command sequence (before the full command set is completed)
• Sector erase time-out period
• Erase fail (while Q5 is high)
• Among program command sequence (before the full command set is completed, erase-suspended program
included)
• Program fail (while Q5 is high, and erase-suspended program fail is included)
• Read silicon ID mode
• Sector protect verify
• CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset
device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode,
user must issue reset command to reset device back to read array mode.
When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig-
nore reset command.
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MX29LV161D T/B
COMMON FLASH MEMORY INTERFACE (CFI) MODE
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE
MX29LV161D T/B features CFI mode. Host system can retrieve the operating characteristics, structure and ven-
dor-specified information such as identifying information, memory size, byte/word configuration, operating volt-
ages and timing information of this device by CFI mode. If the system writes the CFI Query command "98h", to
address "55h"/"AAh", the device will enter the CFI Query Mode, any time the device is ready to read array data.
The system can read CFI information at the addresses given in Table 4.
Once user enters CFI query mode, user can not issue any other commands except reset command. The reset
command is required to exit CFI mode and go back to the mode before entering CFI. The system can write the
CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select
mode.
Table 4-1. CFI mode: Identification Data Values
(All values in these tables are in hexadecimal)
Address (h)
Description
Data (h)
(Word Mode)
10
11
12
13
14
15
16
17
18
19
1A
0051
0052
0059
0002
0000
0040
0000
0000
0000
0000
0000
Query-unique ASCII string "QRY"
Primary vendor command set and control interface ID code
Address for primary algorithm extended query table
Alternate vendor command set and control interface ID code
Address for alternate algorithm extended query table
Table 4-2. CFI Mode: System Interface Data Values
Description
Address (h)
(Word Mode)
1B
Data (h)
Vcc supply minimum program/erase voltage
Vcc supply maximum program/erase voltage
VPP supply minimum program/erase voltage
VPP supply maximum program/erase voltage
Typical timeout per single word/byte write, 2n us
Typical timeout for maximum-size buffer write, 2n us
Typical timeout per individual block erase, 2n ms
Typical timeout for full chip erase, 2n ms
Maximum timeout for word/byte write, 2n times typical
Maximum timeout for buffer write, 2n times typical
Maximum timeout per individual block erase, 2n times typical
Maximum timeout for chip erase, 2n times typical
0027
0036
0000
0000
0004
0000
000A
0000
0005
0000
0004
0000
1C
1D
1E
1F
20
21
22
23
24
25
26
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MX29LV161D T/B
Table 4-3. CFI Mode: Device Geometry Data Values
Address (h)
Data (h)
Description
(Word Mode)
Device size = 2n in number of bytes (MX29LV161D)
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
0015
0001
0000
0000
0000
0004
0000
0000
0040
0000
0001
0000
0020
0000
0000
0000
0080
0000
001E
0000
0000
0001
Flash device interface description (01=asynchronous x16)
Maximum number of bytes in buffer write = 2n (not support)
Number of erase regions within device
Index for Erase Bank Area 1
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256-bytes
Index for Erase Bank Area 2
Index for Erase Bank Area 3
Index for Erase Bank Area 4 (for MX29LV160D)
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MX29LV161D T/B
Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values
Address (h)
(Word Mode)
Description
Data (h)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
0050
0052
0049
0031
0030
0000
0002
0001
0001
0004
0000
0000
0000
Query - Primary extended table, unique ASCII string, PRI
Major version number, ASCII
Minor version number, ASCII
Unlock recognizes address (0= recognize, 1= don't recognize)
Erase suspend (2= to both read and program)
Sector protect (N= # of sectors/group)
Temporary sector unprotect (1=supported)
Sector protect/Chip unprotect scheme
Simultaneous R/W operation (0=not supported)
Burst mode (0=not supported)
Page mode (0=not supported)
Minimum acceleration supply (0= not supported), [D7:D4] for volt, [D3:D0] for
4D
4E
4F
00A5
00B5
100mV
Maximum acceleration supply (0= not supported), [D7:D4] for volt, [D3:D0] for
100mV
Top/Bottom boot block indicator
0002/0003
02h=bottom boot device 03h=top boot device
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MX29LV161D T/B
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM STRESS RATINGS
Surrounding Temperature with Bias
Storage Temperature
-65oC to +125oC
-65oC to +150oC
-0.5V to +4.0V
-0.5V to +4.0V
-0.5V to +10.5V
-0.5V to Vcc +0.5V
200 mA
VCC
VI/O
Voltage Range
RESET#, A9 and OE#
The other pins
Output Short Circuit Current (less than one second)
Note:
1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to Vcc+2V during transition and for less than 20ns during transitions.
OPERATING TEMPERATURE AND VOLTAGE
A
Commercial (C) Grade
Industrial (I) Grade
Surrounding Temperature (T )
0°C to +70°C
A
Surrounding Temperature (T )
-40°C to +85°C
+2.7V to 3.6V
1.65V to 3.6V
Supply Voltages
Supply Voltages
range
range
VCC
VI/O
VCC
VI/O
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MX29LV161D T/B
DC CHARACTERISTICS
Symbol
Description
Min.
Typ.
Max.
± 1.0uA
35uA
Remark
A9=10.5V
Iilk
Iilk9
Iolk
Input Leak
A9 Leak
Output Leak
± 1.0uA
CE#=Vil,
OE#=Vih
CE#=Vil,
OE#=Vih
Icr1
Icr2
Read Current(5MHz)
Read Current(1MHz)
5mA
2mA
12mA
4mA
CE#=Vil,
Icw
Isb
Write Current
15mA
5uA
30mA
15uA
15uA
OE#=Vih,
WE#=Vil
Vcc=Vcc max,
other pins disable
Vcc=Vccmax,
Reset# enable,
other pins disable
Standby Current
Isbr
Reset Current
5uA
Isbs
Sleep Mode Current
5uA
15uA
CE#=Vil,
OE#=Vih
CE#=Vil,
OE#=Vih
Icp1 Accelerated Pgm Current, WP#/Acc pin
Icp2 Accelerated Pgm Current, Vcc pin
5mA
10mA
15mA
30mA
Vil
Input Low Voltage
-0.1V
0.3xVI/O
Vih
Input High Voltage
0.7 x VI/O
VI/O + 0.3V
Very High Voltage for hardware Protect/
Unprotect/Auto Select/Temporary Unprotect
Output Low Voltage
Vhv
9.5V
10.5V
I/O
0.15 x V
Vol
Iol=100uA
I/O
0.85 x V
Voh
Output High Voltage
Ioh=-100uA
Vlko Low Vcc Lock-out Voltage
2.3V
2.5V
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MX29LV161D T/B
SWITCHING TEST CIRCUIT
VI/O
R1
DEVICE UNDER
TEST
OUT
CL
R2
Test Condition
Output Load Capacitance,CL : 30pF(90ns)
R1=R2=25K
Ω
Rise/Fall Times : 5ns
I/O
In/Out reference levels :V / 2
SWITCHING TEST WAVEFORM
VI/O
1
2
1
2
VI/O
VI/O
Test Points
0.0V
INPUT
OUTPUT
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MX29LV161D T/B
AC CHARACTERISTICS
Symbol
Description
Min.
Typ. Max. Unit
Taa
Tce
Valid data output after address
Valid data output after CE# low
90
90
40
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
us
sec
us
Toe
Tdf
Valid data output after OE# low
Data output floating after OE# high
Output hold time from the earliest rising edge of address, CE#, OE#
Read period time
Toh
Trc
0
90
45
90
90
0
Tsrw
Twc
Tcwc
Tas
Latency Between Read and Write Operation (*Note 1)
Write period time
Command write period time
Address setup time
Tah
Tds
Tdh
Tvcs
Tcs
Address hold time
45
35
0
Data setup time
Data hold time
Vcc setup time
200
0
Chip enable Setup time
Tch
Chip enable hold time
0
Toes
Output enable setup time
0
Read
Output enable hold time
0
Toeh
Toggle & Data# Polling
10
0
Tws
Twh
Tcep
WE# setup time
WE# hold time
CE# pulse width
0
35
30
35
30
Tceph CE# pulse width high
Twp WE# pulse width
Twph WE# pulse width high
Tbusy Program/Erase active time by RY/BY#
Tghwl Read recover time before write
Tghel Read recover time before write
Twhwh1 Program operation
90
0
0
11
7
Twhwh1 Accelerated program operation
Twhwh2 Sector Erase operation
210
50
0.7
Tbal
Sector Add hold time
* Note 1: Sampled only, not 100% tested.
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MX29LV161D T/B
WRITE COMMAND OPERATION
Figure 1. COMMAND WRITE OPERATION
Tcwc
Vih
CE#
Vil
Tch
Tcs
Vih
WE#
Vil
Toes
Twph
Twp
Vih
Vil
OE#
Vih
Vil
Addresses
VA
Tah
Tas
Tdh
Tds
Vih
Vil
Data
DIN
VA: Valid Address
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MX29LV161D T/B
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORM
Tce
Vih
CE#
Vil
Tsrw
Vih
WE#
OE#
Vil
Toeh
Tdf
Toe
Vih
Vil
Toh
Taa
Trc
Vih
Vil
ADD Valid
Addresses
Outputs
HIGH Z
HIGH Z
Voh
Vol
DATA Valid
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MX29LV161D T/B
AC CHARACTERISTICS
Item
Description
Setup
Speed
Unit
Trp1
Trp2
Trh
RESET# Pulse Width (During Automatic Algorithms)
RESET# Pulse Width (NOT During Automatic Algorithms)
RESET# High Time Before Read
MIN
MIN
MIN
MIN
MIN
MAX
MAX
10
500
70
us
ns
ns
ns
ns
us
ns
Trb1
Trb2
RY/BY# Recovery Time (to CE#, OE# go low)
RY/BY# Recovery Time (to WE# go low)
0
50
Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write
Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write
20
500
Figure 3. RESET# TIMING WAVEFORM
Trb1
CE#, OE#
Trb2
WE#
Tready1
RY/BY#
RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
Trh
RY/BY#
RESET#
Trp2
Tready2
Reset Timing NOT during Automatic Algorithms
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MX29LV161D T/B
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
CE#
Tch
Twp
WE#
Twph
Tcs
Tghwl
OE#
Last 2 Erase Command Cycles
Read Status
Tah
Twc
Tas
VA
2AAh
VA
SA
Address
Tds
Tdh
In
Progress
Complete
55h
10h
Data
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
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MX29LV161D T/B
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 80h Address 555h
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 10h Address 555h
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
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MX29LV161D T/B
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
CE#
Tch
Twhwh2
Twp
WE#
Twph
Tcs
Tghwl
OE#
Tbal
Last 2 Erase Command Cycle
Twc
Tas
Sector
Sector
Sector
VA
VA
2AAh
Address
Address 0
Address 1
Address n
Tah
Tds Tdh
In
Progress
Complete
55h
30h
30h
30h
Data
Tbusy
Trb
RY/BY#
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MX29LV161D T/B
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 80h Address 555h
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data 30h Sector Address
NO
Last Sector
to Erase ?
YES
Data# Polling Algorithm or
Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Sector Erase Completed
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MX29LV161D T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0h
ERASE SUSPEND
NO
Toggle Bit checking Q6
not toggled ?
YES
Read Array or
Program
Reading or
NO
Programming End ?
YES
Write Data 30h
ERASE RESUME
Continue Erase
Another
NO
Erase Suspend ?
YES
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MX29LV161D T/B
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORM
CE#
Tch
Twhwh1
Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Tas
Last 2 Read Status Cycle
Tah
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
Trb
RY/BY#
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM
(9.5V ~ 10.5V)
Vhv
WP#/ACC
Vil or Vih
Vil or Vih
250ns
250ns
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MX29LV161D T/B
Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM
WE#
Twhwh1 or Twhwh2
Tcep
CE#
Tceph
Tghwl
OE#
Tah
Tas
VA
VA
555h
PA
Address
Tdh
Tds
Status
A0h
PD
DOUT
Data
Tbusy
RY/BY#
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MX29LV161D T/B
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAh Address 555h
Write Data 55h Address 2AAh
Write Data A0h Address 555h
Write Program Data/Address
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
No
Read Again Data:
Program Data?
YES
No
Last Address to be
Programed ?
YES
Auto Program Completed
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MX29LV161D T/B
SECTOR PROTECT/CHIP UNPROTECT
Figure 13. SECTOR PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)
150us: Sector Protect
1us
15ms: Chip Unprotect
CE#
WE#
OE#
Verification
40h
Status
VA
Data
60h
60h
VA
SA, A6
A1, A0
VA
Vhv
Vih
RESET#
VA: valid address
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MX29LV161D T/B
Figure 14. IN-SYSTEM SECTOR PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No
First CMD=60h?
Yes
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 60h
Wait 150us
Reset
PLSCNT=1
Write Sector Address
with [A6,A1,A0]:[0,1,0]
data: 40h
Retry Count +1
Read at Sector Address
with [A6,A1,A0]:[0,1,0]
No
No
Data=01h?
Yes
Retry Count=25?
Yes
Device fail
Yes
Protect another
sector?
No
Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
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MX29LV161D T/B
Figure 15. CHIP UNPROTECT ALGORITHM WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No
First CMD=60h?
Yes
No
All sectors
protected?
Protect All Sectors
Yes
Write [A6,A1,A0]:[1,1,0]
data: 60h
Wait 15ms
Write [A6,A1,A0]:[1,1,0]
data: 40h
Retry Count +1
Read [A6,A1,A0]:[1,1,0]
No
No
Retry Count=1000?
Data=00h?
Yes
Yes
Device fail
Last sector
verified?
No
Yes
Temporary Unprotect
RESET#=Vih
Write reset CMD
Chip Unprotect Done
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MX29LV161D T/B
Table 5. TEMPORARY SECTOR UNPROTECT
Parameter Alt Description
Tvidr RESET# Rise Time to Vhv and Vhv Fall Time to RESET#
Trsp RESET# Vhv to WE# Low
Condition Speed
Unit
ns
Trpvhh
Tvhhwl
MIN
MIN
500
4
us
Figure 16. TEMPORARY SECTOR UNPROTECT WAVEFORM
Program or Erase Command Sequence
CE#
WE#
Tvhhwl
RY/BY#
RESET#
Vhv 10V
0 or Vih
Vil or Vih
Trpvhh
Trpvhh
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MX29LV161D T/B
Figure 17. TEMPORARY SECTOR UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from Reset#
(2) RESET# = Vih
Completed Temporary Sector
Unprotected Mode
Notes:
1. Temporary unprotect all protected sectors Vhv=9.5~10.5V.
2. After leaving temporary unprotect mode, the previously protected sectors are again protected.
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MX29LV161D T/B
Figure 18. SILICON ID READ TIMING WAVEFORM
Vih
CE#
Vil
Tce
Vih
WE#
Vil
Toe
Vih
OE#
Vil
Tdf
Toh
Toh
Vhv
Vih
A9
Vil
Vih
A0
Vil
Taa
Taa
Vih
A1
Vil
Vih
A6
Vil
Vih
ADD
Vil
Vih
DATA
Q15-Q0
DATA OUT
00C2h
DATA OUT
Vil
22C4h (Top boot)
2249h (Bottom boot)
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MX29LV161D T/B
WRITE OPERATION STATUS
Figure 19. DATA# POLLING TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh
Tdf
Trc
VA
VA
Address
Taa
Toh
High Z
High Z
Complement
Complement
Status Data
True
True
Valid Data
Valid Data
Q7
Q6-Q0
Status Data
Tbusy
RY/BY#
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MX29LV161D T/B
Figure 20. DATA# POLLING ALGORITHM
Start
Read Q7~Q0 at valid address
(Note 1)
No
Q7 = Data# ?
Yes
No
Q5 = 1 ?
Yes
Read Q7~Q0 at valid address
No
Q7 = Data# ?
(Note 2)
Yes
FAIL
Pass
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
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MX29LV161D T/B
Figure 21. TOGGLE BIT TIMING WAVEFORM (DURING AUTOMATIC ALGORITHM)
Tce
CE#
Tch
WE#
OE#
Toe
Toeh
Tdf
Trc
VA
VA
VA
VA
Address
Taa
Toh
Valid Status
(second read)
Valid Status
(first read)
Valid Data
Valid Data
Q6/Q2
(stops toggling)
Tbusy
RY/BY#
VA : Valid Address
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MX29LV161D T/B
Figure 22. TOGGLE BIT ALGORITHM
Start
Read Q7-Q0 Twice
(Note 1)
NO
Q6 Toggle ?
YES
NO
Q5 = 1?
YES
Read Q7~Q0 Twice
NO
Q6 Toggle ?
YES
Program/Erase fail
Write Reset CMD
Program/Erase Completed
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
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MX29LV161D T/B
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-
up. If the timing in the figure is ignored, the device may not operate correctly.
Vcc(min)
Vcc
GND
Tvr
Tvcs
Tf
Tce
Tr
Vih
Vil
CE#
WE#
OE#
Vih
Vil
Tf
Toe
Tr
Vih
Vil
Taa
Tr or Tf
Tr or Tf
Vih
Vil
Valid
Address
ADDRESS
Voh
Vol
High Z
Valid
Ouput
DATA
Vih
Vil
WP#/ACC
Figure A. AC Timing at Device Power-Up
Symbol
Parameter
Min.
Max.
Unit
Tvr
Tr
Tf
Vcc Rise Time
20
500000
20
us/V
us/V
us/V
us
Input Signal Rise Time
Input Signal Fall Time
Vcc Setup Time
20
Tvcs
200
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MX29LV161D T/B
ERASE AND PROGRAMMING PERFORMANCE
PARAMETER
LIMITS
UNITS
MIN.
TYP.
MAX.
Chip Erase Time
15
32
sec
sec
Sector Erase Time
Erase/Program Cycles
Chip Programming Time
Word Program Time
Accelerated Program Time
Notes:
0.7
100,000
12
2
Cycles
sec
36
11
360
210
us
7
us
1. Erase/Program cycle comply with JEDEC JESD-47E & A117A standand.
DATA RETENTION
PARAMETER
Condition
Min.
20
Max.
UNIT
Data retention
55˚C
years
LATCH-UP CHARACTERISTICS
MIN.
MAX.
Input voltage difference with GND on all pins except I/O pins
-1.0V
10.5V
Input voltage difference with GND on all I/O pins
Vcc Current
-1.0V
1.5 x Vcc
+100mA
-100mA
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
TSOP/BGA PIN CAPACITANCE
Parameter Symbol
Parameter Description
Control Pin Capacitance
Output Capacitance
Test Set
VIN=0
TYP
7.5
8.5
6
MAX
9
UNIT
CIN2
COUT
CIN
pF
pF
pF
VOUT=0
VIN=0
12
Input Capacitance
7.5
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MX29LV161D T/B
ORDERING INFORMATION
PART NO.
ACCESS
TIME (ns)
Ball Pitch/
Ball Size
PACKAGE
Remark
48 Pin TSOP
(Normal Type)
48 Pin TSOP
(Normal Type)
48 Ball BGA
MX29LV161DTTI-90G
MX29LV161DBTI-90G
MX29LV161DTXBI-90G
MX29LV161DBXBI-90G
MX29LV161DTGBI-90G
MX29LV161DBGBI-90G
MX29LV161DTXHI-90G
MX29LV161DBXHI-90G
90
90
90
90
90
90
90
90
PB free
PB free
PB free
PB free
PB free
PB free
PB free
PB free
0.8mm/0.3mm
0.8mm/0.3mm
(ball size:0.3mm)
48 Ball BGA
(ball size:0.3mm)
48 Ball XFLGA
(4 x 6 x 0.5mm)
48 Ball XFLGA
(4 x 6 x 0.5mm)
48 Ball WFBGA
(4 x 6 x 0.75mm)
48 Ball WFBGA
(4 x 6 x 0.75mm)
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MX29LV161D T/B
PART NAME DESCRIPTION
MX 29 LV 161 D T T I
90 G
OPTION:
G: Pb-free package
SPEED:
90: 90ns
TEMPERATURE RANGE:
I: Industrial (-40°C to 85°C)
PACKAGE:
T: TSOP
X: FBGA (CSP)
XB - 6 x 8 x 1.2mm, Pitch 0.8mm, 0.3mm Ball
XH: WFBGA - 4 x 6 x 0.75mm, Pitch 0.5mm, 0.3mm Ball
GB: XFLGA - 4 x 6 x 0.5mm, Pitch 0.5mm, 0.25mm Ball
BOOT BLOCK TYPE:
T: Top Boot
B: Bottom Boot
REVISION:
D
DENSITY & MODE:
161: 16Mb, x16 Boot Block
TYPE:
LV: 3V
DEVICE:
29:Flash
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MX29LV161D T/B
PACKAGE INFORMATION
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MX29LV161D T/B
48-Ball TFBGA (for MX29LV161D TXBI/BXBI)
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MX29LV161D T/B
48-Ball WFBGA (for MX29LV161D TXHI/BXHI)
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MX29LV161D T/B
48-Ball XFLGA (for MX29LV161D TGBI/BGBI)
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MX29LV161D T/B
REVISION HISTORY
Revision No. Description
Page
Date
0.01
1. Modified Pin Configurations -- 48-ball WFBGA/XFLGA from
P7
OCT/17/2007
RY/BY# to NC
2. Modified Output Load Capacitance,CL from 100pF to 30pF
3. Added WP#/ACC function
P30
P5,7,8,9,14
P17,30,32,41
P55
4. Modified Output Load Capacitance,CL from 100pF to 30pF
1. Modified Tvcs from 100us to 200us
1. Table 4-4. CFI added address 4D~4F
1. Modified Tvcs from 100us to 200us
1. Modified table 4-4. address 4D data from 00B5 to 00A5;
address 4E data from 00C5 to 00B5
P31
P54
P28
P32
0.02
0.03
0.04
0.05
OCT/23/2007
NOV/29/2007
DEC/07/2007
DEC/18/2007
P28
0.06
0.07
0.08
1. Swapped A19 with VI/O Ball Location
1. Modified WFBGA & XFLGA for WP#/ACC pin
1. Changed Toe spec from 30ns to 40ns
2. Revised Vhv data from 10.5V~11.5V to 9.5V~10.5V
3. Changed Vol/Voh spec
P8
P8
JAN/15/2008
JAN/29/2008
JUN/16/2008
P32
P30,41,47,48
P30
4. Modified switching test circuit
P31
5. Changed output load capacitance, CL from 50pF to 30pF
1. Changed Icr1 from 7mA(typ.) to 5mA(typ.)
1. Removed "Advanced Information"
P31
P5,30
All
0.09
1.0
JUL/29/2008
JUN/03/2010
2. Revised data retention from 10 years to 20 years
3. Added Tsrw (AC/WAVEFORM, Min. 45ns)
4. Added WP#ACC PIN note
P5-6,55
P32,34
P9
P/N:PM1359
REV. 1.0, JUN. 03, 2010
62
MX29LV161D T/B
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