MX29LV320ABTI-70_技术文档

MX29LV320AT/B

32M-BIT[4Mx8/2Mx16]SINGLEVOLTAGE

3VONLYFLASHMEMORY

FEATURES

• Low Power Consumption

GENERAL FEATURES

- Low active read current: 10mA (typical) at 5MHz

- Low standby current: 200nA (typical)

• Minimum 100,000 erase/program cycle

• 10 years data retention

• 4,194,304 x 8 / 2,097,152 x 16 switchable

• Sector Structure

- 8K-Byte x 8 and 64K-Byte x 63

• Extra 64K-Byte sector for security

- Features factory locked and identifiable, and cus-

tomer lockable

SOFTWARE FEATURES

• Erase Suspend/ Erase Resume

- Suspends sector erase operation to read data from

or program data to another sector which is not being

erased

• Twenty-Four Sector Groups

- Provides sector group protect function to prevent pro-

gram or erase operation in the protected sector group

- Provides chip unprotect function to allow code chang-

ing

• Status Reply

- Data polling & Toggle bits provide detection of pro-

gram and erase operation completion

• Support Common Flash Interface (CFI)

- Provides temporary sector group unprotect function

for code changing in previously protected sector groups

• Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program opera-

tions

HARDWARE FEATURES

• Latch-up protected to 250mA from -1V to Vcc + 1V

• Low Vcc write inhibit is equal to or less than 1.4V

• Compatible with JEDEC standard

- Pinout and software compatible to single power sup-

ply Flash

• Ready/Busy (RY/BY) Output

- Provides a hardware method of detecting program

and erase operation completion

• Hardware Reset (RESET) Input

- Provides a hardware method to reset the internal state

machine to read mode

• 2nd generation of 3V/32M Flash product

- Fully compatible with MX29LV320T/B device

• WP/ACC input pin

- Provides accelerated program capability

PERFORMANCE

• High Performance

PACKAGE

- Fast access time: 70/90ns

- Fast program time:7us/word typical utilizing acceler-

ate function

• 48-PinTSOP

• 48-Ball CSP

- Fast erase time: 0.9s/sector, 35s/chip (typical)

GENERAL DESCRIPTION

The MX29LV320AT/B is a 32-mega bit Flash memory

organized as 4M bytes of 8 bits and 2M words of 16 bits.

MXIC's Flash memories offer the most cost-effective and

reliable read/write non-volatile random access memory.

The MX29LV320AT/B is packaged in 48-pin TSOP and

48-ball CSP. It is designed to be reprogrammed and

erased in system or in standard EPROM programmers.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29LV320AT/B uses a command register to manage

this functionality.

MXIC Flash technology reliably stores memory

contents even after 100,000 erase and program

cycles. The MXIC cell is designed to optimize the

erase and program mechanisms. In addition, the

combination of advanced tunnel oxide processing

and low internal electric fields for erase and

programming operations produces reliable cycling.

The standard MX29LV320AT/B offers access time as

fast as 70ns, allowing operation of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion, the MX29LV320AT/B has separate chip enable (CE)

and output enable (OE) controls.

P/N:PM1008

REV. 1.1, MAY 28, 2004

1

MX29LV320AT/B

The MX29LV320AT/B uses a 2.7V to 3.6V VCC

supply to perform the High Reliability Erase and

auto Program/Erase algorithms.

modes allow sectors of the array to be erased in one

erase cycle. The Automatic Sector Erase algorithm

automatically programs the specified sector(s) prior to

electrical erase. The timing and verification of

electrical erase are controlled internally within the

device.

The highest degree of latch-up protection is

achieved with MXIC's proprietary non-epi process.

Latch-up protection is proved for stresses up to 100

milliamperes on address and data pin from -1V to

VCC + 1V.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

AUTOMATIC PROGRAMMING

The MX29LV320AT/B is byte/word programmable using

the Automatic Programming algorithm. The Automatic

Programming algorithm makes the external system do

not need to have time out sequence nor to verify the

data programmed. The typical chip programming time at

room temperature of the MX29LV320AT/B is less than

36 seconds.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE .

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user

to only write program set-up commands (including 2 un-

lock write cycle and A0H) and a program command (pro-

gram data and address). The device automatically times

the programming pulse width, provides the program veri-

fication, and counts the number of sequences. A status

bit similar to DATA polling and a status bit toggling be-

tween consecutive read cycles, provide feedback to the

user as to the status of the programming operation.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness.The MX29LV320AT/B elec-

trically erases all bits simultaneously using Fowler-Nord-

heim tunneling. The bytes/words are programmed by

using the EPROM programming mechanism of hot elec-

tron injection.

AUTOMATIC CHIP ERASE

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

The entire chip is bulk erased using 50 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 35 seconds. The Automatic Erase algorithm

automatically programs the entire array prior to electri-

cal erase. The timing and verification of electrical erase

are controlled internally within the device.

AUTOMATIC SECTOR ERASE

The MX29LV320AT/B is sector(s) erasable using

MXIC's Auto Sector Erase algorithm. Sector erase

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REV. 1.1, MAY 28, 2004

2

MX29LV320AT/B

PIN CONFIGURATION

A15

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE

GND

Q15/A-1

Q7

48TSOP

A14

A13

A12

A11

A10

A9

2

3

4

5

6

Q14

Q6

7

A8

8

Q13

Q5

A19

A20

WE

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Q12

Q4

RESET

NC

VCC

Q11

Q3

MX29LV320AT/B

WP/ACC

RY/BY

A18

A17

A7

Q10

Q2

Q9

Q1

A6

Q8

A5

Q0

A4

OE

A3

GND

CE

A2

A1

A0

48-Ball CSP 6mm x 8mm (Ball Pitch = 0.8 mm),Top View, Balls Facing Down

A

B

C

D

E

F

G

H

6

5

4

3

2

1

A13

A9

WE

A12

A14

A15

A11

A19

A20

A5

A16

Q7

Q5

Q2

Q0

A0

BYTE

Q14

Q12

Q10

Q8

Q15/A-1 GND

A8

A10

NC

Q13

Vcc

Q11

Q9

Q6

RESET

Q4

RY/BY WP/ACC A18

Q3

A7

A3

A17

A4

A6

A2

Q1

A1

CE

OE

GND

PIN DESCRIPTION

LOGIC SYMBOL

SYMBOL

A0~A20

Q0~Q14

Q15/A-1

PIN NAME

21

Address Input

16 or 8

15 Data Inputs/Outputs

A0-A20

Q0-Q15

(A-1)

Q15(Data Input/Output, word mode)

A-1(LSB Address Input, byte mode)

Chip Enable Input

CE

WE

Write Enable Input

OE

Output Enable Input

OE

BYTE

RESET

RY/BY

VCC

Word/Byte Selection Input

Hardware Reset Pin, Active Low

Read/Busy Output

WE

RESET

BYTE

3.0 volt-only single power supply

HardwareWrite Protect/Acceleration

RY/BY

WP/ACC

GND

NC

Device Ground

Pin Not Connected Internally

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REV. 1.1, MAY 28, 2004

3

MX29LV320AT/B

BLOCK DIAGRAM

WRITE

STATE

CE

OE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

WE

MACHINE

(WSM)

LOGIC

RESET

BYTE

STATE

MX29LV320AT/B

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A20

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q15/A-1

I/O BUFFER

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REV. 1.1, MAY 28, 2004

4

MX29LV320AT/B

Table 1.a: MX29LV320AT SECTOR GROUP ARCHITECTURE

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

1

A20-A12

Address Range

SA0

000000xxx

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

000000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

000000h-07FFFh

008000h-0FFFFh

010000h-17FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

1

SA1

1

SA2

1

SA3

2

SA4

2

SA5

2

SA6

2

SA7

3

SA8

3

SA9

3

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

SA39

3

4

5

6

7

8

9

10

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REV. 1.1, MAY 28, 2004

5

MX29LV320AT/B

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

8/4

(x8)

(x16)

Group

11

12

13

14

15

16

17

18

19

20

21

22

23

24

A20-A12

Address Range

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111000

111111001

111111010

111111011

111111100

111111101

111111110

111111111

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3F1FFFh

3F2000h-3F3FFFh

3F4000h-3F5FFFh

3F6000h-3F7FFFh

3F8000h-3F9FFFh

3FA000h-3FBFFFh

3FC000h-3FDFFFh

3FE000h-3FFFFFh

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-147FFFh

168000h-14FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1F8FFFh

1F9000h-1F9FFFh

1FA000h-1FAFFFh

1FB000h-1FBFFFh

1FC000h-1FCFFFh

1FD000h-1FDFFFh

1FE000h-1FEFFFh

1FF000h-1FFFFFh

8/4

Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)

Top Boot Security Sector Addresses

Sector Address

A20~A12

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Address Range

3F0000h-3FFFFFh

Address Range

1F8000h-1FFFFFh

111111xxx

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REV. 1.1, MAY 28, 2004

6

MX29LV320AT/B

Table 1.b: MX29LV320AB SECTOR GROUP ARCHITECTURE

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

8/4

(x8)

(x16)

Group

1

A20-A12

Address Range

SA0

000000000

000000001

000000010

000000011

000000100

000000101

000000110

000000111

000001xxx

000010xxx

000011xxx

000100xxx

000101xxx

000110xxx

000111xxx

001000xxx

001001xxx

001010xxx

001011xxx

001100xxx

001101xxx

001110xxx

001111xxx

010000xxx

010001xxx

010010xxx

010011xxx

010100xxx

010101xxx

010110xxx

010111xxx

011000xxx

011001xxx

011010xxx

011011xxx

011100xxx

011101xxx

011110xxx

011111xxx

000000h-001FFFh

002000h-003FFFh

004000h-005FFFh

006000h-007FFFh

008000h-009FFFh

00A000h-00BFFFh

00C000h-00DFFFh

00E000h-00FFFFh

010000h-01FFFFh

020000h-02FFFFh

030000h-03FFFFh

040000h-04FFFFh

050000h-05FFFFh

060000h-06FFFFh

070000h-07FFFFh

080000h-08FFFFh

090000h-09FFFFh

0A0000h-0AFFFFh

0B0000h-0BFFFFh

0C0000h-0CFFFFh

0D0000h-0DFFFFh

0E0000h-0EFFFFh

0F0000h-0FFFFFh

100000h-10FFFFh

110000h-11FFFFh

120000h-12FFFFh

130000h-13FFFFh

140000h-14FFFFh

150000h-15FFFFh

160000h-16FFFFh

170000h-17FFFFh

180000h-18FFFFh

190000h-19FFFFh

1A0000h-1AFFFFh

1B0000h-1BFFFFh

1C0000h-1CFFFFh

1D0000h-1DFFFFh

1E0000h-1EFFFFh

1F0000h-1FFFFFh

000000h-000FFFh

001000h-001FFFh

002000h-002FFFh

003000h-003FFFh

004000h-004FFFh

005000h-005FFFh

006000h-006FFFh

007000h-007FFFh

008000h-00FFFFh

010000h-017FFFh

018000h-01FFFFh

020000h-027FFFh

028000h-02FFFFh

030000h-037FFFh

038000h-03FFFFh

040000h-047FFFh

048000h-04FFFFh

050000h-057FFFh

058000h-05FFFFh

060000h-067FFFh

068000h-06FFFFh

070000h-077FFFh

078000h-07FFFFh

080000h-087FFFh

088000h-08FFFFh

090000h-097FFFh

098000h-09FFFFh

0A0000h-0A7FFFh

0A8000h-0AFFFFh

0B0000h-0B7FFFh

0B8000h-0BFFFFh

0C0000h-0C7FFFh

0C8000h-0CFFFFh

0D0000h-0D7FFFh

0D8000h-0DFFFFh

0E0000h-0E7FFFh

0E8000h-0EFFFFh

0F0000h-0F7FFFh

0F8000h-0FFFFFh

2

SA1

8/4

3

SA2

8/4

4

SA3

8/4

5

SA4

8/4

6

SA5

8/4

7

SA6

8/4

8

SA7

8/4

9

SA8

64/32

9

SA9

9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

SA38

10

11

12

13

14

15

16

P/N:PM1008

REV. 1.1, MAY 28, 2004

7

MX29LV320AT/B

Sector Sector Sector Address

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Group

17

18

19

20

21

22

23

24

A20-A12

Address Range

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

100000xxx

100001xxx

100010xxx

100011xxx

100100xxx

100101xxx

100110xxx

100111xxx

101000xxx

101001xxx

101010xxx

101011xxx

101100xxx

101101xxx

101110xxx

101111xxx

110000xxx

110001xxx

110010xxx

110011xxx

110100xxx

110101xxx

110110xxx

110111xxx

111000xxx

111001xxx

111010xxx

111011xxx

111100xxx

111101xxx

111110xxx

111111xxx

200000h-20FFFFh

210000h-21FFFFh

220000h-22FFFFh

230000h-23FFFFh

240000h-24FFFFh

250000h-25FFFFh

260000h-26FFFFh

270000h-27FFFFh

280000h-28FFFFh

290000h-29FFFFh

2A0000h-2AFFFFh

2B0000h-2BFFFFh

2C0000h-2CFFFFh

2D0000h-2DFFFFh

2E0000h-2EFFFFh

2F0000h-2FFFFFh

300000h-30FFFFh

310000h-31FFFFh

320000h-32FFFFh

330000h-33FFFFh

340000h-34FFFFh

350000h-35FFFFh

360000h-36FFFFh

370000h-37FFFFh

380000h-38FFFFh

390000h-39FFFFh

3A0000h-3AFFFFh

3B0000h-3BFFFFh

3C0000h-3CFFFFh

3D0000h-3DFFFFh

3E0000h-3EFFFFh

3F0000h-3FFFFFh

100000h-107FFFh

108000h-10FFFFh

110000h-117FFFh

118000h-11FFFFh

120000h-127FFFh

128000h-12FFFFh

130000h-137FFFh

138000h-13FFFFh

140000h-147FFFh

148000h-14FFFFh

150000h-157FFFh

158000h-15FFFFh

160000h-167FFFh

168000h-16FFFFh

170000h-177FFFh

178000h-17FFFFh

180000h-187FFFh

188000h-18FFFFh

190000h-197FFFh

198000h-19FFFFh

1A0000h-1A7FFFh

1A8000h-1AFFFFh

1B0000h-1B7FFFh

1B8000h-1BFFFFh

1C0000h-1C7FFFh

1C8000h-1CFFFFh

1D0000h-1D7FFFh

1D8000h-1DFFFFh

1E0000h-1E7FFFh

1E8000h-1EFFFFh

1F0000h-1F7FFFh

1F8000h-1FFFFFh

64/32

Note:The address range is A20:A-1 in byte mode (BYTE=VIL) or A20:A0 in word mode (BYTE=VIH)

Bottom Boot Security Sector Addresses

Sector Address

A20~A12

Sector Size

(Kbytes/Kwords)

64/32

(x8)

(x16)

Address Range

000000h-00FFFFh

Address Range

00000h-07FFFh

111111xxx

P/N:PM1008

REV. 1.1, MAY 28, 2004

8

MX29LV320AT/B

Table 2. BUS OPERATION--1

Operation

CE OE WE RESET WP/ACC

Addresses

(Note 2)

A_IN

Q0~Q7

Q8 ~ Q15

Byte=VIH

Byte=VIL

Q8-A14

Read

L

H

L/H

D_OUT

=High-Z

Q15=A-1

Write (Note 1)

Accelerate

Program

L

H

L

H

Note 3

V_HH

A_IN

D_IN

Standby

VCC ± X

X

VCC ±

0.3V

H

X

High-Z

0.3V

Output Disable

Reset

L

X

L

H

X

H

X

L

L/H

X

High-Z

X

High-Z

X

L

Sector Group

Protect (Note 2)

Chip Unprotect

(Note 2)

V_ID

Sector Addresses, D_IN, D_OUT

A6=L, A1=H, A0=L

L

H

X

L

V_ID

Note 3 Sector Addresses, D_IN, D_OUT

A6=H, A1=H, A0=L

X

Temporary Sector

Group Unprotect

X

Note 3

A_IN

D_IN

High-Z

Legend:

L=Logic LOW=V_IL, H=Logic High=V_IH, V_ID=12.0±0.5V, V_HH=11.5-12.5V, X=Don't Care, A_IN=Address IN, D_IN=Data IN,

D_OUT=Data OUT

Notes:

1. When the WP/ACC pin is at V_HH, the device enters the accelerated program mode. See "Accelerated Program

Operations" for more information.

2.The sector group protect and chip unprotect functions may also be implemented via programming equipment. See

the "Sector Group Protection and Chip Unprotection" section.

3.If WP/ACC=V_IL, the two outermost boot sectors remain protected. If WP/ACC=V_IH, the two outermost boot sector

protection depends on whether they were last protected or unprotected using the method described in "Sector/

Sector Block Protection and Unprotection". If WP/ACC=V_HH, all sectors will be unprotected.

4.DIN or Dout as required by command sequence, data polling, or sector protection algorithm.

5.Address are A20:A0 in word mode (BYTE=V_IH), A20:A-1 in byte mode (BYTE=V_IL).

P/N:PM1008

REV. 1.1, MAY 28, 2004

9

MX29LV320AT/B

BUS OPERATION--2

Operation

A20 A11 A9

to to

A12 A10

A8

to

A6

A5

to

CE OE WE

A1

A0 Q0-Q7 Q8-Q15

A7

X

A2

X

Read Silicon ID

Manufacturer Code

Read Silicon ID

MX29LV320AT

Read Silicon ID

MX29LV320AB

Sector Protect

Verification

L

H

X

V_ID

L

H

L

C2H

X

L

A7H 22h(word)

X (byte)

X

A8H 22h(word)

X (byte)

SA

X

H

01h(1),

or 00h

99h(2),

or 19h

X

Security Sector

Indicater

H

X

Bit (Q7)

Notes:

1.Code=00h means unprotected, or code=01h protected.

2.Code=99 means factory locked, or code=19h not factory locked.

P/N:PM1008

REV. 1.1, MAY 28, 2004

10

MX29LV320AT/B

REQUIREMENTS FOR READING ARRAY

DATA

ACCELERATED PROGRAM OPERATION

The device offers accelerated program operations through

the WP/ACC function. If the system asserts V_HHon ACC

pin, the device will provide the fast programming time to

user. This function is primarily intended to allow faster

manufacturing throughput during production. Removing

V_HHfrom the WP/ACC pin returns the device to normal

operation. Note that the WP/ACC pin must not be at V_HH

for operations other than accelerated programming, or

device damage may result.

To read array data from the outputs, the system must

drive the CE and OE pins toVIL.CE is the power control

and selects the device. OE is the output control and gates

array data to the output pins. WE should remain at VIH.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory content

occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address on

the device address inputs produce valid data on the device

data outputs.The device remains enabled for read access

until the command register contents are altered.

STANDBY MODE

MX29LV320AT/B can be set into Standby mode with two

different approaches. One is using both CE and RESET

pins and the other one is using RESET pin only.

When using both pins of CE and RESET, a CMOS

Standby mode is achieved with both pins held at Vcc ±

0.3V. Under this condition, the current consumed is less

than 0.2uA (typ.). If both of the CE and RESET are held

atVIH, but not within the range ofVCC ± 0.3V, the device

will still be in the standby mode, but the standby current

will be larger. During Auto Algorithm operation, Vcc ac-

tive current (ICC2) is required even CE = "H" until the

operation is completed.The device can be read with stan-

dard access time (tCE) from either of these standby

modes.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory

, the system must drive WE and CE to VIL, and OE to

VIH.

An erase operation can erase one sector, multiple sectors

, or the entire device.Table 1 indicates the address space

that each sector occupies. A "sector address" consists

of the address bits required to uniquely select a sector.

Writing specific address and data commands or

sequences into the command register initiates device

operations. Table 3 defines the valid register command

sequences.Writing incorrect address and data values or

writing them in the improper sequence resets the device

to reading array data. Section has details on erasing a

sector or the entire chip, or suspending/resuming the erase

operation.

When using only RESET, a CMOS standby mode is

achieved with RESET input held at Vss ± 0.3V, Under

this condition the current is consumed less than 1uA

(typ.). Once the RESET pin is taken high, the device is

back to active without recovery delay.

In the standby mode the outputs are in the high imped-

ance state, independent of the OE input.

After the system writes the Automatic Select command

sequence, the device enters the Automatic Select mode.

The system can then read Automatic Select codes from

the internal register (which is separate from the memory

array) on Q7-Q0. Standard read cycle timings apply in

this mode. Refer to the Automatic Select Mode and

Automatic Select Command Sequence section for more

information.

MX29LV320AT/B is capable to provide the Automatic

Standby Mode to restrain power consumption during read-

out of data. This mode can be used effectively with an

application requested low power consumption such as

handy terminals.

To active this mode, MX29LV320AT/B automatically

switch themselves to low power mode when

MX29LV320AT/B addresses remain stable during access

time of tACC+30ns. It is not necessary to control CE,

WE, and OE on the mode. Under the mode, the current

consumed is typically 0.2uA (CMOS level).

ICC2 in the DC Characteristics table represents the active

current specification for the write mode. The "AC

Characteristics" section contains timing specification

table and timing diagrams for write operations.

P/N:PM1008

REV. 1.1, MAY 28, 2004

11

MX29LV320AT/B

The primary method requires VID on the RESET only.

This method can be implemented either in-system or via

programming equipment. This method uses standard

microprocessor bus cycle timing. Refer to Figure 13 for

timing diagram and Figure 14 illustrates the algorithm for

the sector group protection operation.

OUTPUT DISABLE

With the OE input at a logic high level (VIH), output from

the devices are disabled.This will cause the output pins

to be in a high impedance state.

The alternate method intended only for programming

equipment, must force VID on address pin A9 and con-

trol pin OE, (suggest VID = 12V) A6 = VIL and CE =

VIL(seeTable 2). Programming of the protection circuitry

begins on the falling edge of the WE pulse and is termi-

nated on the rising edge. Contact MXIC for details.

RESET OPERATION

The RESET pin provides a hardware method of resetting

the device to reading array data.When the RESET pin is

driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write

commands for the duration of the RESET pulse. The

device also resets the internal state machine to reading

array data.The operation that was interrupted should be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

To verify programming of the protection circuitry, the pro-

gramming equipment must force V_IDon address pin A9 (

with CE and OE at VIL and WE at VIH). When A1=1, it

will produce a logical "1" code at device output Q0 for a

protected sector. Otherwise the device will produce 00H

for the unprotected sector. In this mode, the addresses,

except for A1, are don't care. Address locations with

A1= VIL are reserved to read manufacturer and device

codes.(Read Silicon ID)

Current is reduced for the duration of the RESET pulse.

When RESET is held at VSS±0.3V, the device draws

CMOS standby current (ICC4). If RESET is held at VIL

but not within VSS±0.3V, the standby current will be

greater.

It is also possible to determine if the group is protected

in the system by writing a Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

a logical "1" at Q0 for the protected sector.

The RESET pin may be tied to system reset circuitry. A

system reset would that also reset the Flash memory,

enabling the system to read the boot-up firm-ware from

the Flash memory.

CHIP UNPROTECT OPERATION

If RESET is asserted during a program or erase

operation, the RY/BY pin remains a "0" (busy) until the

internal reset operation is complete, which requires a time

of tREADY (during Embedded Algorithms).The system

can thus monitor RY/BY to determine whether the reset

operation is complete. If RESET is asserted when a

program or erase operation is not executing (RY/BY pin

is "1"), the reset operation is completed within a time of

tREADY (not during Embedded Algorithms).The system

can read data tRH after the RESET pin returns to VIH.

The MX29LV320AT/B also features the chip unprotect

mode, so that all sectors are unprotected after chip

unprotect is completed to incorporate any changes in

the code. It is recommended to protect all sectors before

activating chip unprotect mode.

The primary method requires VID on the RESET only.

This method can be implemented either in-system or via

programming equipment. This method uses standard

microprocessor bus cycle timing. Refer to Figure 13 for

timing diagram and Figure 14 illustrates the algorithm for

the sector group protection operation.

Refer to the AC Characteristics tables for RESET

parameters and to Figure 14 for the timing diagram.

The alternate method intended only for programming

equipment, must force VID on address pin A9 and con-

trol pin OE, (suggest VID = 12V) A6 = VIL and CE =

VIL(seeTable 2). Programming of the protection circuitry

begins on the falling edge of the WE pulse and is termi-

nated on the rising edge. Contact MXIC for details.

SECTOR GROUP PROTECT OPERATION

The MX29LV320AT/B features hardware sector group

protection. This feature will disable both program and

erase operations for these sector group protected. Sec-

tor protection can be implemented via two methods.

P/N:PM1008

REV. 1.1, MAY 28, 2004

12

MX29LV320AT/B

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs(Q0-Q7) for an unprotected sector.It

is noted that all sectors are unprotected after the chip

unprotect algorithm is completed.

AUTOMATIC SELECT OPERATION

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design prac-

tice.

TEMPORARY SECTOR GROUP UNPROTECT

OPERATION

MX29LV320AT/B provides hardware method to access

the Automatic Select operation.This method requiresV_ID

on A9 pin, VIL on CE, OE, A6, and A1 pins.When apply-

ing VIL on A0 pin, the device will output MXIC's manu-

facture code of C2H. When applying VIH on A0 pin, the

device will output MX29LV320AT/B device code of 22A7h

and 22A8h.

This feature allows temporary unprotection of previously

protected sector to change data in-system.The Tempo-

rary Sector Unprotect mode is activated by setting the

RESET pin to V_ID(11.5V-12.5V). During this mode, for-

merly protected sectors can be programmed or erased

as un-protected sector. Once V_IDis remove from the

RESET pin, all the previously protected sectors are pro-

tected again.

VERIFY SECTOR GROUP PROTECT STATUS

OPERATION

WRITE PROTECT (WP)

MX29LV320AT/B provides hardware method for sector

group protect status verify. This method requires V_IDon

A9 pin, VIH on WE and A1 pins, VIL on CE, OE, A6, and

A0 pins, and sector address on A12 to A20 pins. When

the identified sector is protected, the device will output

01H.When the identified sector is not protect, the device

will output 00H.

The write protect function provides a hardware method

to protect boot sectors without using V_ID.

If the system asserts VIL on the WP/ACC pin, the de-

vice disables program and erase functions in the two

"outermost" 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected

using the method described in Sector/Sector Group Pro-

tection and Chip Unprotection". The two outermost 8

Kbyte boot sectors are the two sectors containing the

lowest addresses in a bottom-boot-configured device, or

the two sectors containing the highest addresses in a

top-boot-configured device.

SECURITY SECTOR FLASH MEMORY REGION

The Security Sector (Security Sector) feature provides a

Flash memory region that enables permanent part iden-

tification through an Electronic Serial Number (ESN).The

Security Sector is 64 Kbytes (32 Kwords) in length, and

uses a Security Sector Indicator Bit (Q7) to indicate

whether or not the Security Sector is locked when shipped

from the factory. This bit is per-manently set at the fac-

tory and cannot be changed, which prevents cloning of a

factory locked part.This ensures the security of the ESN

once the product is shipped to the field.

If the system asserts VIH on the WP/ACC pin, the de-

vice reverts to whether the two outermost 8K Byte boot

sectors were last set to be protected or unprotected.That

is, sector protection or unprotection for these two sec-

tors depends on whether they were last protected or un-

protected using the method described in "Sector/Sector

Group Protection and Chip Unprotection".

MXIC offers the device with the Security Sector either

factory locked or customer lockable. The factory-locked

version is always protected when shipped from the fac-

tory, and has the Security on Silicon Sector (Security

Sector) Indicator Bit permanently set to a "1". The cus-

tomer-lockable version is shipped with the unprotected,

allowing customers to utilize the that sector in any man-

Note that the WP/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may

result.

P/N:PM1008

REV. 1.1, MAY 28, 2004

13

MX29LV320AT/B

ner they choose.The customer-lockable version has the

Security on Silicon Sector (Security Sector) Indicator Bit

permanently set to a "0".Thus, the Security Sector Indi-

cator Bit prevents customer-lockable devices from be-

ing used to replace devices that are factory locked.

Write the three-cycle Enter Security Region command

sequence, and then follow the in-system sector group

protect algorithm as shown in Figure 14, except that RE-

SET may be at either VIH or V_ID. This allows in-system

protection of the without raising any device pin to a high

voltage. Note that this method is only applicable to the

Security Sector.

The system accesses the Security Sector through a

command sequence (see "Enter Security Sector/Exit

Security Sector Command Sequence"). After the sys-

tem has written the Enter Security Sector command se-

quence, it may read the Security Sector by using the ad-

dresses normally occupied by the boot sectors. This

mode of operation continues until the system issues the

Exit Security Sector command sequence, or until power

is removed from the device. On power-up, or following a

hardware reset, the device reverts to sending commands

to the boot sectors.

Write the three-cycle Enter Security Region command

sequence, and then use the alternate method of sector

protection described in the "Sector/Sector Block Protec-

tion and Unprotection section.

Once the Security Sector is locked and verified, the sys-

tem must write the Exit Security Sector Region com-

mand sequence to return to reading and writing the re-

mainder of the array.

The Security Sector protection must be used with cau-

tion since, once protected, there is no procedure avail-

able for unprotecting the Security Sector area and none

of the bits in the Security Sector memory space can be

modified in any way.

Factory Locked: Security Sector Programmed

and Protected at the Factory

In a factory locked device, the Security Sector is pro-

tected when the device is shipped from the factory. The

Security Sector cannot be modified in any way. The de-

vice is available preprogrammed with one of the follow-

ing:

DATA PROTECTION

The MX29LV320AT/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transition. During power up the device automatically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorporates several features to prevent inadvertent write

cycles resulting fromVCC power-up and power-down tran-

sition or system noise.

A random, secure ESN only.

Customer code through the Express Flash service.

Both a random, secure ESN and customer code through

the Express Flash service.

In devices that have an ESN, a Bottom Boot device will

have the 16-byte (8-word) ESN in the lowest address-

able memory area starting at 00000h and ending at

0000Fh (00007h). In the Top Boot device the starting

address of the ESN will be at the bottom of the lowest 8

Kbyte (4 Kword) boot sector starting at 3F0000h

(1F8000h) and ending at 3F000Fh (1F8007h).

LOW VCC WRITE INHIBIT

When VCC is less than VLKO the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down.The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater thanVLKO. The system must provide the proper

signals to the control pins to prevent unintentional write

whenVCC is greater thanVLKO.

Customer Lockable: Security Sector NOT Pro-

grammed or Protected at the Factory

If the security feature is not required, the Security Sec-

tor can be treated as an additional Flash memory space,

expanding the size of the available Flash array by 64

Kbytes (32 Kwords). The Security Sector can be read,

programmed, and erased as often as required.The Se-

curity Sector area can be protected using one of the

following procedures:

P/N:PM1008

REV. 1.1, MAY 28, 2004

14

MX29LV320AT/B

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns (typical) on OE, CE or WE

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE =VIL, CE =

VIH or WE = VIH. To initiate a write cycle CE and WE

must be a logical zero while OE is a logical one.

POWER-UP SEQUENCE

The MX29LV320AT/B powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

POWER-UP WRITE INHIBIT

IfWE=CE=VIL and OE=VIH during power up, the device

does not accept commands on the rising edge of WE.

The internal state machine is automatically reset to the

read mode on power-up.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

SOFTWARE COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. Table 3 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

All addresses are latched on the falling edge of WE or

CE, whichever happens later.All data are latched on ris-

ing edge of WE or CE, whichever happens first.

P/N:PM1008

REV. 1.1, MAY 28, 2004

15

MX29LV320AT/B

TABLE 3. MX29LV320AT/B COMMAND DEFINITIONS

First Bus

Cycle

Second Bus Third Bus

Cycle Cycle

Fourth Bus

Cycle

Fifth Bus Sixth Bus

Cycle Cycle

Command

Bus

Cycles Addr Data Addr Data Addr Data Addr

Data Addr Data Addr Data

Read(Note 5)

1

RA

RD

Reset(Note 4)

XXX F0

Automatic Select(Note 5)

Manufacturer ID

Word

Byte

4

3

4

6

1

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

555 AA

AAA AA

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

2AA 55

555 55

555 90

AAA 90

555 90

AAA 90

555 90

AAA 90

555 90

AAA 90

555 88

AAA 88

555 90

AAA 90

555 A0

AAA A0

555 80

AAA 80

555 80

AAA 80

X00

X01

X02

X03

X06

C2H

ID

Device ID

Word

Byte

Security Sector Factory Word

Protect Verify (Note 6) Byte

Sector Protect Verify Word

99/19

(SA)X02 00/01

(SA)X04

(Note 7)

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Word

Byte

Enter Security Sector

Region

Exit Security Sector

XXX

PA

00

Program

PD

AA

PA

Chip Erase

555

AAA

555

AAA

2AA 55 555 10

555 55 AAA 10

2AA 55 SA 30

555 55 SA 30

Sector Erase

CFI Query (Note 8)

55

98

B0

30

AA

SA

Erase Suspend(Note 9)

Erase Resume(Note 10)

Legend:

X=Don't care

RA=Address of the memory location to be read.

PD=Data to be programmed at location PA. Data is latched

on the rising edge of WE or CE pulse.

RD=Data read from location RA during read operation.

PA=Address of the memory location to be programmed.

Addresses are latched on the falling edge of the WE or CE

pulse.

SA=Address of the sector to be erased or verified. Address

bits A20-A12 uniquely select any sector.

ID=22A7h(Top), 22A8h(Bottom)

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or Automatic Select data, all bus cycles are write operation.

4. The Reset command is required to return to the read mode when the device is in the Automatic Select mode or if Q5 goes

high.

5. The fourth cycle of the Automatic Select command sequence is a read cycle.

6. The data is 99h for factory locked and 19h for not factory locked.

7. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third cycle of the

command sequence, address bit A20=0 to verify sectors 0~31, A20=1 to verify sectors 32~70 for Top Boot device.

8. Command is valid when device is ready to read array data or when device is in Automatic Select mode.

9. The system may read and program functions in non-erasing sectors, or enter the Automatic Select mode, when in the erase

Suspend mode. The Erase Suspend command is valid only during a sector erase operation.

10. The Erase Resume command is valid only during the Erase Suspend mode.

P/N:PM1008

REV. 1.1, MAY 28, 2004

16

MX29LV320AT/B

READING ARRAY DATA

AUTOMATIC SELECT COMMAND SEQUENCE

The Automatic Select command sequence allows the

host system to access the manufacturer and device

codes, and determine whether or not a sector is pro-

tected.Table 2 shows the address and data requirements.

This method is an alternative to that shown in Table 3,

which is intended for EPROM programmers and requires

V^IDon address bit A9.

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data.The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data. After

completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See Erase Suspend/Erase

Resume Commands” for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high

during an active program or erase operation, or while in

the Automatic Select mode. See the "Reset Command"

section, next.

The Automatic Select command sequence is initiated

by writ-ing two unlock cycles, followed by the Automatic

Select command. The device then enters the Automatic

Select mode, and the system may read at any address

any number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address XX01h in

word mode (or xx02h in byte mode) returns the device

code. A read cycle containing a sector address (SA) and

the address 02h on A7-A0 in word mode (or the address

04h on A6-A-1 in byte mode) returns 01h if that sector is

protected, or 00h if it is unprotected. Refer to Table 1 for

valid sector addresses.

The system must write the reset command to exit the

Automatic Select mode and return to reading array data.

RESET COMMAND

Writing the reset command to the device resets the

device to reading array data. Address bits are don't care

for this command.

ENTER SECURITY SECTOR & EXIT SECURITY

SECTOR COMMAND SEQUENCE

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ignores

reset commands until the operation is complete.

The Security Sector provides a secured area which con-

tains a random, sixteen-byte electronic serial

number.(ESN)

The system can access the Security Sector area by is-

suing the three-cycle "Enter Security Sector command

sequence. The device continues to access the security

section area until the system issues the four-cycle Exit

Security Sector command sequence. The Exit Security

Sector command sequence returns the device to normal

operation.

The reset command may be written between the se-

quence cycles in a program command sequence before

programming begins. This resets the device to reading

array data (also applies to programming in Erase Suspend

mode). Once programming begins, however, the device

ignores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in an Automatic Select command

sequence. Once in the Automatic Select mode, the reset

command must be written to return to reading array data

(also applies to Automatic Select during Erase Suspend).

BYTE/WORD PROGRAM COMMAND SEQUENCE

The device programs one byte/word of data for each

program operation. The command sequence requires four

bus cycles, and is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in turn

initiate the Embedded Program algorithm. The system is

not required to provide further controls or timings. The

device automatically generates the program pulses and

If Q5 goes high during a program or erase operation,

writing the reset command returns the device to read-ing

array data (also applies during Erase Suspend).

P/N:PM1008

REV. 1.1, MAY 28, 2004

17

MX29LV320AT/B

verifies the programmed cell margin. Table 3 shows the

address and data requirements for the byte/word program

command sequence.

However, a succeeding read will show that the data is

still "0". Only erase operations can convert a "0" to a

"1".

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses

are no longer latched. The system can determine the

status of the program operation by using Q7, Q6, or RY/

BY. See "Write Operation Status" for information on these

status bits.

SETUP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H, or

the sector erase command 30H.

Any commands written to the device during the Em-

bedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming

operation. The Byte/Word Program command sequence

should be reinitiated once the device has reset to reading

array data, to ensure data integrity.

The MX29LV320AT/B contains a Silicon-ID-Read opera-

tion to supplement traditional PROM programming meth-

odology. The operation is initiated by writing the read

silicon ID command sequence into the command regis-

ter. Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of A7H/A8H for MX29LV320AT/B.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may cause the

device to set Q5 to "1" ,” or cause the Data Polling

algorithm to indicate the operation was successful.

TABLE 4. SILICON ID CODE

Pins

A0 A1 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacturecode

VIL VIL

VIH VIL

1

0

1

0

1

0

1

0

1

0

1

0

C2H

Device code for MX29LV320AT

Device code for MX29LV320AB

22A7H

22A8H

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

AUTOMATIC CHIP/SECTOR ERASE COMMAND

The device does not require the system to preprogram

prior to erase.The Automatic Erase algorithm automati-

cally preprograms and verifies the entire memory for an

all zero data pattern prior to electrical erase.The system

is not required to provide any controls or timings during

these operations. Table 3 shows the address and data

requirements for the chip erase command sequence.

The system can determine the status of the erase op-

eration by using Q7, Q6, Q2, or RY/BY. See "Write Op-

eration Status" for information on these status bits.When

the Automatic Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched.

Any commands written to the chip during the Automatic

Erase algorithm are ignored. Note that a hard-ware reset

during the chip erase operation immediately terminates

the operation.The Chip Erase command sequence should

Figure 5 illustrates the algorithm for the erase opera-tion.

See the Erase/Program Operations tables in "AC Char-

acteristics" for parameters, and to Figure 4 for timing

diagrams.

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18

MX29LV320AT/B

Sector Erase operation. When the Erase Suspend com-

mand is issued during the sector erase operation, the

device requires a maximum 20us to suspend the sector

erase operation.However,When the Erase Suspend com-

mand is written during the sector erase time-out, the

device immediately terminates the time-out period and

suspends the erase operation. After this command has

been executed, the command register will initiate erase

suspend mode. The state machine will return to read

mode automatically after suspend is ready. At this time,

state machine only allows the command register to re-

spond to the Erase Resume, program data to, or read

data from any sector not selected for erasure. The sys-

tem can use Q7, or Q6 and Q2 together, to determine if

a sector is actively erasing or is erase-suspended.

SECTOR ERASE COMMANDS

The device does not require the system to entirely

pre-program prior to executing the Automatic Set-up

Sector Erase command and Automatic Sector Erase

command. Upon executing the Automatic Sector

Erase command, the device will automatically

program and verify the sector(s) memory for an all-

zero data pattern. The system is not required to

provide any control or timing during these operations.

When the sector(s) is automatically verified to

contain an all-zero pattern, a self-timed sector erase

and verify begin. The erase and verify operations are

complete when the data on Q7 is "1" and the data on

Q6 stops toggling for two consecutive read cycles, at

which time the device returns to the Read mode. The

system is not required to provide any control or timing

during these operations.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended blocks.

When using the Automatic Sector Erase algorithm,

note that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array (no erase verification command is

required). Sector erase is a six-bus cycle operation.

There are two "unlock" write cycles. These are

followed by writing the set-up command 80H. Two

more "unlock" write cycles are then followed by the

sector erase command 30H. The sector address is

latched on the falling edge of WE or CE, whichever

happens later , while the command(data) is latched on

the rising edge of WE or CE, whichever happens first.

Sector addresses selected are loaded into internal

register on the sixth falling edge of WE or CE,

whichever happens later. Each successive sector

load cycle started by the falling edge of WE or CE,

whichever happens later must begin within 50us from

the rising edge of the preceding WE or CE, whichever

happens first. Otherwise, the loading period ends and

internal auto sector erase cycle starts. (Monitor Q3 to

determine if the sector erase timer window is still

open, see section Q3, Sector Erase Timer.) Any

command other than Sector Erase(30H) or Erase

Suspend(B0H) during the time-out period resets the

device to read mode.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation,

and therefore will only be responded during Automatic

P/N:PM1008

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19

MX29LV320AT/B

WRITE OPERATION STATUS

The device provides several bits to determine the sta-

tus of a write operation:Q2, Q3, Q5, Q6, Q7, and RY/BY.

Table 5 and the following subsections describe the func-

tions of these bits. Q7, RY/BY, and Q6 each offer a

method for determining whether a program or erase op-

eration is complete or in progress. These three bits are

discussed first.

Table 5. Write Operation Status

Status

Q7

Q6

Q5

Q3

Q2 RY/BY

Note1

Note2

Byte/Word Program in Auto Program Algorithm

Auto Erase Algorithm

Q7

Toggle

0

N/A

1

No

0

Toggle

0

1

0

Toggle

0

1

Erase Suspend Read

(Erase Suspended Sector)

No

Toggle

N/A Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

Q7

Data Data Data Data

1

0

(Non-Erase Suspended Sector)

Erase Suspend Program

Toggle

0

1

N/A N/A

Byte/Word Program in Auto Program Algorithm

Q7

N/A

1

No

Toggle

Exceeded

Time Limits Auto Erase Algorithm

0

Toggle

1

Toggle

0

Erase Suspend Program

Q7

N/A N/A

Notes:

1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2. Performing successive read operations from any address will cause Q6 to toggle.

3. Reading the byte/word address being programmed while in the erase-suspend program mode will indicate logic "1"

at the Q2 bit.

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

P/N:PM1008

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20

MX29LV320AT/B

after the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

Q7: Data Polling

The Data Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend. Data

Polling is valid after the rising edge of the final WE pulse

in the program or erase command sequence.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE or CE to con-

trol the read cycles.When the operation is complete, Q6

stops toggling.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7.This Q7 status also applies to programming dur-

ing Erase Suspend.When the Automatic Program algo-

rithm is complete, the device outputs the datum pro-

grammed to Q7.The system must provide the program

address to read valid status information on Q7. If a pro-

gram address falls within a protected sector, Data Poll-

ing on Q7 is active for approximately 1 us, then the de-

vice returns to reading array data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles for

100us and returns to reading array data. If not all se-

lected sectors are protected, the Automatic Erase algo-

rithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase suspended.

When the device is actively erasing (that is, the Auto-

matic Erase algorithm is in progress), Q6 toggling.When

the device enters the Erase Suspend mode, Q6 stops

toggling. However, the system must also use Q2 to de-

termine which sectors are erasing or erase-suspended.

Alternatively, the system can use Q7.

During the Automatic Erase algorithm, Data Polling pro-

duces a "0" on Q7.When the Automatic Erase algorithm

is complete, or if the device enters the Erase Suspend

mode, Data Polling produces a "1" on Q7.This is analo-

gous to the complement/true datum out-put described

for the Automatic Program algorithm: the erase function

changes all the bits in a sector to "1" prior to this, the

device outputs the "complement,” or "0".” The system

must provide an address within any of the sectors se-

lected for erasure to read valid status information on Q7.

If a program address falls within a protected sector, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data Polling on

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

Table 5 shows the outputs for Toggle Bit I on Q6.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output Enable

(OE) is asserted low.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit II is valid

after the rising edge of the final WE or CE, whichever

happens first pulse in the command sequence.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE or CE to control the read

P/N:PM1008

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21

MX29LV320AT/B

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 5 to compare outputs for Q2 and Q6.

only operating functions of the device under this condi-

tion.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte/word pro-

gramming operation, it specifies that the entire sector

containing that byte/word is bad and this sector maynot

be reused, (other sectors are still functional and can be

reused).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

The Q5 failure condition may appear if the system tries

to program a "1" to a location that is previously pro-

grammed to "0". Only an erase operation can change a

"0" back to a "1".” Under this condition, the device halts

the operation, and when the operation has exceeded the

timing limits, Q5 produces a "1".

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it returns to determine the status of the

operation.

Q3:Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

Q5:Program/Erase Timing

Q5 will indicate if the program or erase time has exceeded

the specified limits(internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data Polling andToggle Bit are the

If Data Polling or the Toggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

P/N:PM1008

REV. 1.1, MAY 28, 2004

22

MX29LV320AT/B

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

operation is completed as indicated by Data Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept addi-

tional sector erase commands. To insure the command

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been accepted.

lect mode. The command is valid only when the device

is in the CFI mode.

If the time between additional erase commands from the

system can be less than 50us, the system need not to

monitor Q3.

RY/BY:READY/BUSY OUTPUT

The RY/BY is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in progress

or complete. The RY/BY status is valid after the rising

edge of the final WE pulse in the command sequence.

Since RY/BY is an open-drain output, several RY/BY pins

can be tied together in parallel with a pull-up resistor to

VCC .

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device

is ready to read array data (includ-ing during the Erase

Suspend mode), or is in the standby mode.

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE

MX29LV320AT/B is capable of operating in the CFI mode.

This mode all the host system to determine the manu-

facturer of the device such as operating parameters and

configuration.Two commands are required in CFI mode.

Query command of CFI mode is placed first, then the

Reset command exits CFI mode.These are described in

Table 3.

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Standby mode, and Automatic Select mode; however, it

is ignored otherwise.

The Reset command exits from the CFI mode to the

Read mode, or Erase Suspend mode, or Automatic Se-

P/N:PM1008

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MX29LV320AT/B

Table 6-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Address(h)

Address(h) Data(h)

(WordMode)

(ByteMode)

Query-unique ASCII string "QRY"

10

11

12

13

14

15

16

17

18

19

1A

20

22

24

26

28

2A

2C

2E

30

32

34

0051

0052

0059

0002

0000

0040

0000

Primary vendor command set and control interface ID code

Address for primary algorithm extended query table

Alternate vendor command set and control interface ID code (none)

Address for secondary algorithm extended query table (none)

Table 6-2. CFI Mode: System Interface Data Values

Description

Address(h)

Address(h) Data(h)

(WordMode) (ByteMode)

VCC supply, minimum (2.7V)

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

36

38

3A

3C

3E

40

42

44

46

48

4A

4C

0027

0036

0000

0004

0000

000A

0000

0005

0000

0004

0000

VCC supply, maximum (3.6V)

VPP supply, minimum (none)

VPP supply, maximum (none)

Typical timeout for single word/byte write (2^Nus)

Typical timeout for maximum size buffer write (2^Nus) (not supported)

Typical timeout for individual sector erase (2^Nms)

Typical timeout for full chip erase (2^Nms)

Maximum timeout for single word/byte write times (2^NX Typ)

Maximum timeout for maximum size buffer write times (2^NX Typ)

Maximum timeout for individual sector erase times (2^NX Typ)

Maximum timeout for full chip erase times (not supported)

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MX29LV320AT/B

Table 6-3. CFI Mode: Device Geometry Data Values

Description

Address(h)

Address(h) Data(h)

(WordMode) (ByteMode)

Device size (2^Nbytes)

27

28

29

2A

2B

2C

2D

2E

2F

30

31

32

33

34

35

36

37

38

39

3A

3B

3C

4E

50

52

54

56

58

5A

5C

5E

60

62

64

66

68

6A

6C

6E

70

72

74

76

78

0016

0002

0000

0002

0007

0000

0020

0000

003E

0000

0001

0000

Flash device interface code (02=asynchronous x8/x16)

Maximum number of bytes in multi-byte write (not supported)

Number of erase sector regions

Erase Sector Region 1 Information

[2E,2D] = # of same-size sectors in region 1-1

[30, 2F] = sector size in multiples of 256-bytes

Erase Sector Region 2 Information

Erase Sector Region 3 Information

Erase Sector Region 4 Information

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MX29LV320AT/B

Table 6-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

Description

Address(h)

Address(h) Data(h)

(WordMode) (ByteMode)

Query-unique ASCII string "PRI"

40

41

42

43

44

45

46

47

48

49

4A

4B

4C

4D

80

82

84

86

88

8A

8C

8E

90

92

94

96

98

9A

0050

0052

0049

0031

0000

0002

0004

0001

0004

0000

00B5

Major version number, ASCII

Minor version number, ASCII

Address sensitive unlock (0=required, 1= not required)

Erase suspend (2= to read and write)

Sector protect (N= # of sectors/group)

Temporarysectorunprotect(1=supported)

Sector protect/Chip unprotect scheme

SimultaneousR/Woperation(0=notsupported)

Burst mode type (0=not supported)

Page mode type (0=not supported)

ACC (Acceleration) Supply Minimum

(0=notsupported,D7-D4:Volt,D3-D0:100mV

ACC (Acceleration) Supply Maximum

(0=notsupported,D7-D4:Volt,D3-D0:100mV

Top/Bottom Boot Sector Flag

4E

4F

9C

9E

00C5

000X

02h=Bottom Boot Device, 03h=Top Boot Device

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MX29LV320AT/B

OPERATING RATINGS

ABSOLUTE MAXIMUM RATINGS

StorageTemperature

Commercial (C) Devices

Plastic Packages . . . . . . . . . . . . . ..... -65^oC to +150^oC

Ambient Temperature (T^A). . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

AmbientTemperature

with Power Applied. . . . . . . . . . . . . .... -65^oC to +125^oC

Voltage with Respect to Ground

Ambient Temperature (T^A). . . . . . . . . . -40°C to +85° C

V^CCSupply Voltages

V^CCfor full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE, and

Operating ranges define those limits between which the

functionality of the device is guaranteed.

RESET (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20ns. Maxi-

mum DC voltage on input or I/O pins is VCC +0.5 V.

During voltage transitions, input or I/O pins may over-

shoot to VCC +2.0 V for periods up to 20 ns.

2. Minimum DC input voltage on pins A9, OE, and

RESET is -0.5 V. During voltage transitions, A9, OE,

and RESET may overshoot VSS to -2.0 V for periods

of up to 20 ns. Maximum DC input voltage on pin A9

is +12.5 V which may overshoot to 14.0 V for periods

up to 20 ns.

3.No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

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MX29LV320AT/B

DC CHARACTERISTICS VCC=2.7V~3.6V

Para- Description

meter

Test Conditions

TA=0°C to 70°C

Min Typ Max

±1.0

TA=-40° C to 85° C

Min Typ Max Unit

±1.0 uA

ILI

Input Load Current

(Note 1)

ILIT A9 Input Load Current

VIN = VSS to VCC,

VCC = VCC max

VCC = VCC max,

A9=12.5V

35

45

uA

ILO

Output Leakage Current

VOUT = VSS to VCC ,

VCC = VCC max

CE= VIL, 5 MHz

OE = VIH 1 MHz

CE= VIL , OE = VIH,

WE=VIL

±1.0

±1.0 uA

ICC1 VCC Active Read Current

(Notes 2, 3)

10

2

16

4

10

2

16

4

mA

ICC2 VCC ActiveWrite Current

(Notes 2, 4, 6)

15

30

15

30

ICC3 VCC Standby Current

(Note 2)

CE, RESET,

0.2

15

0.2

15

uA

WP/ACC = VCC±0.3V

RESET = VSS ± 0.3V,

WP/ACC= VCC ±0.3V

VIH = VCC ± 0.3V;

VIL = VSS ± 0.3V,

WP/ACC=VCC±0.3V

ICC4 VCC Reset Current (Note 2)

ICC5 Automatic Sleep Mode

(Notes 2,5)

IACC WP/ACC Accelerated Program CE=VIL, WP/ACC pin

5

10

30

5

10

30

mA

V

Current, Word or Byte

Input LowVoltage

OE=VIH VCC pin

15

VIL

-0.5

0.7xVcc

11.5

0.8

-0.5

0.8

VIH Input HighVoltage

VHH Voltage for WP/ACC Sector

Protect/Unprotect and

Vcc+0.3 0.7xVcc

Vcc+0.3 V

VCC = 3.0 V ±10%

12.5

0.45

11.5

12.5

0.45

V

Program Acceleration

VID Voltage for Automatic Select VCC = 3.0 V ±10%

11.5

V

andTemporary Sector

Unprotect

VOL Output LowVoltage

VOH1 Output HighVoltage

VOH2

IOL=4.0mA,

V

VCC=VCC min

IOH=-2.0mA,

VCC=VCC min

IOH=-100uA,

VCC = VCC min

0.85Vcc

Vcc-0.4

1.4

0.85Vcc

Vcc-0.4

1.4

VLKO LowVCC Lock-OutVoltage

(Note 6)

2.1

Notes:

1. On the WP/ACC pin only, the maximum input load current when WP/ACC = VIL is ±5.0uA / VIH is ±3.0uA.

2. Maximum ICC specifications are tested with VCC = VCC max.

3.The ICC current listed is typically is less than 2 mA/MHz, with OE atVIH.Typical specifications are for VCC = 3.0V.

4. ICC active while Embedded Erase or Embedded Program is in progress.

5.Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.Typical sleep

mode current is 200 nA.

6. Not 100% tested.

P/N:PM1008

REV. 1.1, MAY 28, 2004

28

MX29LV320AT/B

SWITCHINGTEST CIRCUITS

TEST SPECIFICATIONS

Test Condition

70

30

90

1TTL gate

100

Unit

pF

Output Load

DEVICE UNDER

TEST

1.6K ohm

+3.3V

Output Load Capacitance,CL

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

5

ns

V

CL

0.0-3.0

1.5

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

Input timing measurement

reference levels

V

Output timing measurement

reference levels

1.5

V

KEYTO SWITCHINGWAVEFORMS

WAVEFORM INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State(High Z)

SWITCHINGTEST WAVEFORMS

3.0V

0.0V

1.5V

Measurement Level

1.5V

INPUT

OUTPUT

P/N:PM1008

REV. 1.1, MAY 28, 2004

29

MX29LV320AT/B

AC CHARACTERISTICS TA=-40°C to 85° C, VCC=2.7V~3.6V

Symbol DESCRIPTION

CONDITION

70

90

Unit

tACC

Address to output delay

CE=VIL

MAX

70

90

ns

OE=VIL

tCE

tOE

tDF

tOH

Chip enable to output delay

Output enable to output delay

OE High to output float(Note1)

Output hold time of from the rising edge of

Address, CE or OE whichever happens first

Read cycle time (Note 1)

Write cycle time (Note 1)

Command write cycle time(Note 1)

Address setup time

MAX

MIN

70

40

30

0

90

40

30

0

ns

tRC

MIN

70

0

90

0

ns

tWC

tCWC

tAS

tAH

Address hold time

45

0

45

0

tDS

Data setup time

tDH

Data hold time

tVCS

tCS

Vcc setup time(Note 1)

Chip enable setup time

Chip enable hold time

50

0

50

0

tCH

0

tOES

tOEH

Output enable setup time (Note 1)

Output enable hold time (Note 1) Read

Toggle &

0

10

Data Polling

tWES

tWEH

tCEP

WE setup time

MIN

MAX

MIN

TYP

0

ns

us

WE hold time

CE pulse width

45

30

45

30

90

0

45

30

45

30

90

0

tCEPH

tWP

CE pulse width high

WE pulse width

tWPH

tBUSY

tGHWL

tGHEL

WE pulse width high

Program/Erase valid to RY/BY delay

Read recovery time before write

0

tWHWH1 Programming operation

BYTE

9

WORD

11

7

11

7

Accelerated programming operation word or

byte

tWHWH2 Sector erase operation

tBAL Sector address hold time

TYP

0.9

50

0.9

50

sec

us

MAX

Note: 1.Not 100%Tested

2.tr = tf = 5ns

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REV. 1.1, MAY 28, 2004

30

MX29LV320AT/B

Fig 1. COMMAND WRITE OPERATION

VCC

3V

VIH

Addresses

ADD Valid

VIL

tAH

tAS

VIH

VIL

WE

tOES

tWPH

tWP

tCWC

VIH

VIL

CE

OE

tCS

tCH

tDH

VIH

VIL

tDS

VIH

VIL

Data

DIN

P/N:PM1008

REV. 1.1, MAY 28, 2004

31

MX29LV320AT/B

READ/RESET OPERATION

Fig 2. READ TIMING WAVEFORMS

tRC

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE

VIL

VIH

WE

tDF

VIL

tOEH

tOE

VIH

OE

VIL

tOH

tACC

HIGH Z

VOH

VOL

Outputs

DATA Valid

P/N:PM1008

REV. 1.1, MAY 28, 2004

32

MX29LV320AT/B

AC CHARACTERISTICS

Parameter

Description

Test Setup All Speed Options Unit

tREADY1

RESET PIN Low (During Automatic Algorithms)

to Read or Write (See Note)

MAX

MIN

20

us

tREADY2

RESET PIN Low (NOT During Automatic

Algorithms) to Read or Write (See Note)

RESET Pulse Width (During Automatic Algorithms)

500

ns

tRP1

tRP2

tRH

10

500

70

0

us

ns

RESET Pulse Width (NOT During Automatic Algorithms) MIN

RESET HighTime Before Read(See Note)

RY/BY Recovery Time(to CE, OE go low)

RY/BY RecoveryTime(to WE go low)

MIN

tRB1

tRB2

50

Note:Not 100% tested

Fig 3. RESET TIMING WAVEFORM

RY/BY

tRH

CE, OE

RESET

tRP2

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY

CE, OE

WE

tRB1

tRB2

RESET

tRP1

Reset Timing during Automatic Algorithms

P/N:PM1008

REV. 1.1, MAY 28, 2004

33

MX29LV320AT/B

ERASE/PROGRAM OPERATION

Fig 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

tWC

tAS

VA

2AAh

SA

Address

555h for chip erase

tAH

CE

tCH

tGHWL

OE

tWHWH2

tWP

WE

tCS

tWPH

tDS tDH

In

Progress

55h

10h

Complete

Data

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

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REV. 1.1, MAY 28, 2004

34

MX29LV320AT/B

Fig 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data Poll

from system

YES

No

DATA = FFh ?

YES

Auto Erase Completed

P/N:PM1008

REV. 1.1, MAY 28, 2004

35

MX29LV320AT/B

Fig 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

tWC

tAS

Sector

Address n

VA

2AAh

Address

Address 0

Address 1

tAH

CE

tCH

tGHWL

OE

tWHWH2

tBAL

tWP

WE

tCS

tWPH

tDS tDH

In

Progress

55h

30h

Complete

Data

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

P/N:PM1008

REV. 1.1, MAY 28, 2004

36

MX29LV320AT/B

Fig 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Last Sector

to Erase ?

YES

Data Poll from System

NO

Data=FFh?

YES

Auto Sector Erase Completed

P/N:PM1008

REV. 1.1, MAY 28, 2004

37

MX29LV320AT/B

Fig 8. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

ERASE SUSPEND

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

ERASE RESUME

Continue Erase

Another

NO

Erase Suspend ?

YES

P/N:PM1008

REV. 1.1, MAY 28, 2004

38

MX29LV320AT/B

Fig 9. AUTOMATIC PROGRAM TIMING WAVEFORMS

Program Command Sequence(last two cycle)

Read Status Data (last two cycle)

tWC

tAS

PA

555h

PA

Address

tAH

CE

tCH

tGHWL

OE

tWHWH1

tWP

WE

tCS

tWPH

tDS tDH

Status

A0h

PD

DOUT

Data

tBUSY

tRB

RY/BY

tVCS

VCC

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

Fig 10. Accelerated Program Timing Diagram

(11.5V ~ 12.5V)

VHH

WP/ACC

VIL or VIH

tVHH

P/N:PM1008

REV. 1.1, MAY 28, 2004

39

MX29LV320AT/B

Fig 11. CE CONTROLLED WRITE TIMING WAVEFORM

PA for program

555 for program

2AA for erase

SA for sector erase

555 for chip erase

Data Polling

Address

PA

tWC

tWH

tAS

tAH

WE

OE

tGHEL

tCP

tWHWH1 or 2

CE

tWS

tDS

tCPH

tBUSY

tDH

DOUT

Q7

Data

PD for program

30 for sector erase

10 for chip erase

A0 for program

55 for erase

tRH

RESET

RY/BY

NOTES:

1. PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.

2. Figure indicates the last two bus cycles of the command sequence.

P/N:PM1008

REV. 1.1, MAY 28, 2004

40

MX29LV320AT/B

Fig 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Data Poll

Increment

Address

from system

No

Verify Data OK ?

YES

Last Address ?

YES

Auto Program Completed

P/N:PM1008

REV. 1.1, MAY 28, 2004

41

MX29LV320AT/B

SECTOR GROUP PROTECT/CHIP UNPROTECT

Fig 13. Sector Group Protect/Chip Unprotect Waveform (RESET Control)

VID

VIH

RESET

SA, A6

A1, A0

Valid (note2)

Status

Sector Group Protect or Chip Unprotect

Verify

40h

Data

60h

Sector Group Protect: 150us

Chip Unprotect: 15ms

1us

CE

WE

OE

Note:

1. For sector group protect A6=0, A1=1, A0=0 ; for chip unprotect A6=1, A1=1, A0=0

P/N:PM1008

REV. 1.1, MAY 28, 2004

42

MX29LV320AT/B

Fig 14. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH RESET=VID

START

Protect all sectors:

PLSCNT=1

The indicated portion of

PLSCNT=1

the sector protect algorithm

must be performed

RESET=VID

for all unprotected sectors

RESET=VID

prior to issuing the first

sector unprotect address

Wait 1us

No

First Write

Temporary Sector

Unprotect Mode

Cycle=60h?

First Write

No

Temporary Sector

Unprotect Mode

Cycle=60h?

Yes

Set up sector address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6=0, A1=1, A0=0

Yes

Set up first sector address

Wait 150us

Chip Unprotect:

Write 60h to sector

address with

Verify Sector Protect:

Write 40h to sector

address with

Reset

PLSCNT=1

A6=1, A1=1, A0=0

A6=0, A1=1, A0=0

Increment PLSCNT

Wait 15ms

Read from

sector address

with

A6=0, A1=1, A0=0

Verify Sector Unprotect:

Write 40h to sector

address with

No

Increment PLSCNT

A6=1, A1=1, A0=0

No

Data=01h?

Yes

PLSCNT=25?

Read from

sector address

with

Yes

A6=1, A1=1, A0=0

No

Device failed

Reset

Yes

Protect another

sector?

PLSCNT=1

No

PLSCNT=1000?

Data=00h?

Yes

No

Sector Protect

Algorithm

Yes

Remove VID from RESET

Device failed

No

Last sector

verified?

Write reset command

Yes

Chip Unprotect

Algorithm

Sector Protect complete

Remove VID from RESET

Write reset command

Chip Unprotect complete

P/N:PM1008

REV. 1.1, MAY 28, 2004

43

MX29LV320AT/B

Table 7. TEMPORARY SECTOR GROUP UNPROTECT

Parameter Std. Description

Test Setup All Speed Options Unit

tVIDR

tRSP

VID Rise and Fall Time (See Note)

Min

500

4

ns

us

RESET Setup Time for Temporary Sector Unprotect

Note:

Not 100% tested

Fig 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS

12V

RESET

0 or 3V

VIL or VIH

tVIDR

Program or Erase Command Sequence

CE

WE

tRSP

RY/BY

P/N:PM1008

REV. 1.1, MAY 28, 2004

44

MX29LV320AT/B

Fig 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART

Start

RESET = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET = VIH

Temporary Sector Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected. VID=11.5V~12.5V.

(if WP/ACC=VIL, outermost boot sectors will remain protected)

2. All previously protected sectors are protected again.

P/N:PM1008

REV. 1.1, MAY 28, 2004

45

MX29LV320AT/B

Fig 17. SILICON ID READ TIMING WAVEFORM

VCC

3V

VID

ADD

A9

VIH

VIL

VIH

VIL

ADD

A0

tACC

VIH

VIL

A1

VIH

VIL

ADD

CE

VIH

VIL

VIH

VIL

tCE

WE

OE

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q7

DATA OUT

C2H

DATA OUT

A7H (TOP boot)

A8H (Bottom boot)

P/N:PM1008

REV. 1.1, MAY 28, 2004

46

MX29LV320AT/B

WRITE OPERATION STATUS

Fig 18. DATA POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE

tACC

tCE

tCH

tOE

OE

tOEH

tDF

WE

tOH

High Z

Complement

Status Data

True

Valid Data

Q7

Q0-Q6

tBUSY

RY/BY

NOTES:

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.

P/N:PM1008

REV. 1.1, MAY 28, 2004

47

MX29LV320AT/B

Fig 19. Data Polling Algorithm

START

Read Q7~Q0

Add. = VA (1)

Yes

Q7 = Data ?

No

Q5 = 1 ?

Yes

Read Q7~Q0

Add. = VA

Yes

Q7 = Data ?

(2)

No

PASS

FAIL

Notes:

1.VA=valid address for programming or erasure.

2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.

P/N:PM1008

REV. 1.1, MAY 28, 2004

48

MX29LV320AT/B

Fig 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE

tACC

tCE

tCH

tOE

OE

tOEH

tDF

WE

tOH

Valid Status

(second read)

Valid Status

(first read)

Valid Data

Q6/Q2

(stops toggling)

tBUSY

RY/BY

NOTES:

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and

array data read cycle.

P/N:PM1008

REV. 1.1, MAY 28, 2004

49

MX29LV320AT/B

Fig 21. Toggle Bit Algorithm

START

Read Q7~Q0

(Note 1)

NO

Toggle Bit Q6

=Toggle?

YES

NO

Q5=1?

YES

(Note 1,2)

Read Q7~Q0 Twice

Toggle Bit Q6=

Toggle?

YES

Program/Erase Operation Not

Program/Erase Operation Complete

Complete, Write Reset Command

Note:

1. Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".

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REV. 1.1, MAY 28, 2004

50

MX29LV320AT/B

Fig 22. Q6 versus Q2

Enter Embedded

Erasing

Erase

Enter Erase

Erase

Suspend

Suspend Program

Resume

Erase

Erase Suspend

Read

Erase

Erase Suspend

Read

Erase

WE

Q6

Suspend

Program

Complete

Q2

NOTES:

The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

P/N:PM1008

REV. 1.1, MAY 28, 2004

51

MX29LV320AT/B

AC CHARACTERISTICS

WORD/BYTE CONFIGURATION (BYTE)

Parameter

Description

Speed Options

Unit

JEDEC Std

-70

-90

tELFL/tELFH CE to BYTE Switching Low or High

Max

Min

5

ns

tFLQZ

tFHQV

BYTE Switching Low to Output HIGH Z

BYTE Switching High to Output Active

25

70

30

90

Figure 23. BYTE TIMING WAVEFORM FOR READ OPERATIONS (BYTE switching from byte

mode to word mode)

CE

OE

tELFH

BYTE

DOUT

(Q0-Q7)

DOUT

(Q0-Q14)

Q0~Q14

Q15/A-1

DOUT

(Q15)

VA

tFHQV

P/N:PM1008

REV. 1.1, MAY 28, 2004

52

MX29LV320AT/B

ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.

15

UNITS

sec

us

Sector Erase Time

Chip Erase Time

0.9

35

9

50

Byte Programming Time

Word Program Time

Chip Programming Time

300

360

108

72

11

36

24

7

us

Byte Mode

Word Mode

sec

us

Accelerated Byte/Word Program Time

Erase/Program Cycles

210

100,000

Cycles

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25°C,3.3V.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

VCC Current

12.5V

Vcc + 1.0V

+100mA

-1.0V

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter Symbol

Parameter Description

Input Capacitance

Test Set

VIN=0

TYP

MAX

7.5

12

UNIT

pF

CIN

6

COUT

CIN2

Output Capacitance

Control Pin Capacitance

VOUT=0

VIN=0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2.Test conditions TA=25°C, f=1.0MHz

P/N:PM1008

REV. 1.1, MAY 28, 2004

53

MX29LV320AT/B

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS TIME

Ball Pitch/

Ball Size

-

PACKAGE

Remark

(ns)

70

90

70

90

MX29LV320ATTC-70

MX29LV320ABTC-70

MX29LV320ATTI-70

MX29LV320ABTI-70

MX29LV320ATTC-90

MX29LV320ABTC-90

MX29LV320ATTI-90

MX29LV320ABTI-90

MX29LV320ATXBC-70

MX29LV320ABXBC-70

MX29LV320ATXEC-70

MX29LV320ABXEC-70

MX29LV320ATXBI-70

MX29LV320ABXBI-70

MX29LV320ATXEI-70

MX29LV320ABXEI-70

MX29LV320ATXBC-90

MX29LV320ABXBC-90

MX29LV320ATXEC-90

MX29LV320ABXEC-90

MX29LV320ATXBI-90

MX29LV320ABXBI-90

MX29LV320ATXEI-90

MX29LV320ABXEI-90

48 Pin TSOP

48-Ball CSP

-

0.8mm/0.3mm

0.8mm/0.4mm

0.8mm/0.3mm

0.8mm/0.4mm

0.8mm/0.3mm

0.8mm/0.4mm

0.8mm/0.3mm

0.8mm/0.4mm

P/N:PM1008

REV. 1.1, MAY 28, 2004

54

MX29LV320AT/B

PART NO.

ACCESS TIME

Ball Pitch/

Ball Size

-

PACKAGE

Remark

(ns)

70

90

MX29LV320ATTC-70G

MX29LV320ABTC-70G

MX29LV320ATTI-70G

MX29LV320ABTI-70G

MX29LV320ATTC-90G

MX29LV320ABTC-90G

MX29LV320ATTI-90G

MX29LV320ABTI-90G

48 Pin TSOP

48-Ball CSP

Pb-free

-

MX29LV320ATXBC-70G

MX29LV320ABXBC-70G

MX29LV320ATXEC-70G

MX29LV320ABXEC-70G

MX29LV320ATXBI-70G

MX29LV320ABXBI-70G

MX29LV320ATXEI-70G

MX29LV320ABXEI-70G

MX29LV320ATXBC-90G

MX29LV320ABXBC-90G

MX29LV320ATXEC-90G

MX29LV320ABXEC-90G

MX29LV320ATXBI-90G

MX29LV320ABXBI-90G

MX29LV320ATXEI-90G

MX29LV320ABXEI-90G

70

90

0.8mm/0.3mm

0.8mm/0.4mm

0.8mm/0.3mm

0.8mm/0.4mm

0.8mm/0.3mm

0.8mm/0.4mm

0.8mm/0.3mm

0.8mm/0.4mm

P/N:PM1008

REV. 1.1, MAY 28, 2004

55

MX29LV320AT/B

PACKAGE INFORMATION

P/N:PM1008

REV. 1.1, MAY 28, 2004

56

MX29LV320AT/B

P/N:PM1008

REV. 1.1, MAY 28, 2004

57

MX29LV320AT/B

P/N:PM1008

REV. 1.1, MAY 28, 2004

58

MX29LV320AT/B

REVISION HISTORY

Revision No. Description

Page

P1

P53

Date

JAN/30/2004

MAY/28/2004

1.0

1.1

1. Removed "Advanced Information" on page 1

1. To removed data retention information

P/N:PM1008

REV. 1.1, MAY 28, 2004

59

MX29LV320AT/B

MACRONIX INTERNATIONALCO., LTD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX29LV320ABTI-70
厂家：	MACRONIX INTERNATIONAL
描述：	32M-BIT [4M x 8 / 2M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY 32M - BIT [ 4M ×8 / 2M ×16 ]单电压3V仅限于Flash存储器存储
文件：	总60页 (文件大小：604K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29LV320ABTI-70 [Macronix]

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