MX29LV640BUTI-90_技术文档

MX29LV640BU

64M-BIT[4Mx16]CMOSEQUALSECTORFLASHMEMORY

FEATURES

GENERAL FEATURES

SOFTWARE FEATURES

• 4,194,304 x 16 byte structure

• Support Common Flash Interface (CFI)

• One hundred twenty-eight Equal Sectors with 32K

word each

- Flash device parameters stored on the device and

provide the host system to access.

• Erase Suspend/ Erase Resume

- Any combination of sectors can be erased with erase

suspend/resume function

• Sector Protection/Chip Unprotect

- Provides sector group protect function to prevent

program or erase operation in the protected sector

group

- Suspends sector erase operation to read data from

or program data to another sector which is not being

erased

• Status Reply

- Data# polling & Toggle bits provide detection of pro-

gram and erase operation completion

- Provides chip unprotect function to allow code

changes

- Provides temporary sector group unprotect function

for code changes in previously protected sector groups

• Secured Silicon Sector

- Provides a 128-word area for code or data that can

be permanently protected.

- Once this sector is protected, it is prohibited to pro-

gram or erase within the sector again.

• Single Power Supply Operation

HARDWARE FEATURES

• Ready/Busy (RY/BY#) Output

- Provides a hardware method of detecting program

and erase operation completion

• Hardware Reset (RESET#) Input

- Provides a hardware method to reset the internal

state machine to read mode

• ACC input pin

- Provides accelerated program capability

• WP# pin

- 2.7 to 3.6 volt for read, erase, and program opera-

tions

• Latch-up protected to 250mA from -1V to Vcc + 1V

• Low Vcc write inhibit is equal to or less than 1.5V

• Compatible with JEDEC standard

- Pinout and software compatible to single power sup-

ply Flash

- At V_IL, allows protection of first sector, regardless of

sector protection/unprotected status

- At V_IH, allows removal of protection

PACKAGE

PERFORMANCE

• 48-pinTSOP

• 63-ball CSP

• High Performance

- Access time: 90/120ns

- Program time:11us/word, 45s/chip (typical)

- Erase time: 0.9s/sector, 45s/chip (typical)

• Low Power Consumption

- Low active read current: 9mA (typical) at 5MHz

- Low standby current: 0.2uA(typ.)

• Minimum 100,000 erase/program cycle

• 20-year data retention

GENERAL DESCRIPTION

The standard MX29LV640BU offers access time as fast

as 90ns, allowing operation of high-speed microproces-

sors without wait states. To eliminate bus contention,

the MX29LV640BU has separate chip enable (CE#) and

output enable (OE#) controls.

The MX29LV640BU is a 64-mega bit Flash memory or-

ganized as 4M bytes of 16 bits. MXIC's Flash memories

offer the most cost-effective and reliable read/write non-

volatile random access memory. The MX29LV640BU is

packaged in 48-pinTSOP and 63-ball CSP. It is designed

to be reprogrammed and erased in system or in standard

EPROM programmers.

MXIC's Flash memories augment EPROM functionality

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MX29LV640BU

with in-circuit electrical erasure and programming. The

MX29LV640BU uses a command register to manage this

functionality.

controlled internally within the device.

AUTOMATIC SECTOR ERASE

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and program

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and programming operations produces reliable

cycling. The MX29LV640BU uses a 2.7V to 3.6V VCC

supply to perform the High Reliability Erase and auto

Program/Erase algorithms.

The MX29LV640BU is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically pro-

grams the specified sector(s) prior to electrical erase.

The timing and verification of electrical erase are con-

trolled internally within the device.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stand-

ard microprocessor write timings. The device will auto-

matically preprogram and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

AUTOMATIC PROGRAMMING

The MX29LV640BU is word programmable using the Au-

tomatic Programming algorithm. The Automatic Program-

ming algorithm makes the external system do not need

to have time out sequence nor to verify the data pro-

grammed. The typical chip programming time at room

temperature of the MX29LV640BU is less than 48 sec-

onds.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE# .

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm require the user

to only write program set-up commands (including 2 un-

lock write cycle and A0H) and a program command (pro-

gram data and address). The device automatically times

the programming pulse width, provides the program veri-

fication, and counts the number of sequences. A status

bit similar to DATA# polling and a status bit toggling be-

tween consecutive read cycles, provide feedback to the

user as to the status of the programming operation.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, relia-

bility, and cost effectiveness. The MX29LV640BU elec-

trically erases all bits simultaneously using Fowler-Nord-

heim tunneling. The words are programmed by using

the EPROM programming mechanism of hot electron in-

jection.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command. After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 50 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 45 seconds. The Automatic Erase algorithm

automatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

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MX29LV640BU

PIN CONFIGURATION

48 TSOP

A15

A14

A13

A12

A11

A10

A9

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

V I/O

GND

Q15

Q7

Q14

Q6

Q13

Q5

A8

A21

A20

WE#

RESET#

ACC

WP#

A19

A18

A17

A7

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Q12

Q4

V

CC

MX29LV640BU

Q11

Q3

Q10

Q2

Q9

Q1

Q8

Q0

OE#

GND

CE#

A0

A6

A5

A4

A3

A2

A1

63 Ball CSP (TopView, Ball Down)

12.0 mm

8

7

6

5

4

3

2

1

NC

NC*

NC

NC*

A13

A12

A14

A15

A16

V I/O

Q15

GND

Q6

NC*

A9

A8

RESET

ACC

A17

A10

A21

A11

A19

Q7

Q5

Q14

Q12

Q13

WE

VCC

Q4

11.0 mm

RY/BY

A7

A18

A6

A20

A5

Q2

Q0

A0

Q10

Q8

Q11

Q9

Q3

Q1

NC*

A3

A4

A2

A1

CE

OE

GND

NC*

B

NC*

M

NC*

L

A

C

D

E

F

G

H

J

K

* Ball are shorted together via the substrate but not connected to the die.

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MX29LV640BU

PIN DESCRIPTION

LOGIC SYMBOL

SYMBOL

A0~A21

Q0~Q15

CE#

PIN NAME

22

Address Input

16

A0-A21

8 Data Inputs/Outputs

Chip Enable Input

Q0-Q15

WE#

Write Enable Input

OE#

Output Enable Input

CE#

OE#

WE#

RESET#

WP#

Hardware Reset Pin, Active Low

HardwareWrite Protect Input

Read/Busy Output

RY/BY#

VCC

+3.0V single power supply

Hardware Acceleration Pin

Device Ground

ACC

RESET#

WP#

GND

RY/BY#

NC

Pin Not Connected Internally

Input/Output buffer (2.7V~3.6V) this

input should be tied directly to VCC

V I/O

ACC

V I/O

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MX29LV640BU

BLOCK DIAGRAM

CE#

OE#

WRITE

STATE

CONTROL

INPUT

PROGRAM/ERASE

HIGH VOLTAGE

WE#

RESET#

WP#

MACHINE

(WSM)

LOGIC

ACC

STATE

MX29LV640BU

FLASH

ADDRESS

LATCH

REGISTER

ARRAY

A0-A21

AND

SOURCE

HV

BUFFER

Y-PASS GATE

COMMAND

DATA

DECODER

PGM

SENSE

DATA

HV

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

Q0-Q15

I/O BUFFER

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MX29LV640BU

SECTOR (GROUP) STRUCTURE

Sector

A21

A20

A19

A18

A17

A16

A15

16-bit Address Range

(in hexadecimal)

000000-007FFF

008000-00FFFF

010000-017FFF

018000-01FFFF

020000-027FFF

028000-02FFFF

030000-037FFF

038000-03FFFF

040000-047FFF

048000-04FFFF

050000-057FFF

058000-05FFFF

060000-067FFF

068000-06FFFF

070000-077FFF

078000-07FFFF

080000-087FFF

088000-08FFFF

090000-097FFF

098000-09FFFF

0A0000-0A7FFF

0A8000-0AFFFF

0B0000-0B7FFF

0B8000-0BFFFF

0C0000-0C7FFF

0C8000-0CFFFF

0D0000-0D7FFF

0D8000-0DFFFF

0E0000-0E7FFF

0E8000-0EFFFF

0F0000-0F7FFF

0F8000-0FFFFF

100000-10FFFF

108000-10FFFF

110000-117FFF

118000-11FFFF

120000-127FFF

128000-12FFFF

SA0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

SA11

SA12

SA13

SA14

SA15

SA16

SA17

SA18

SA19

SA20

SA21

SA22

SA23

SA24

SA25

SA26

SA27

SA28

SA29

SA30

SA31

SA32

SA33

SA34

SA35

SA36

SA37

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MX29LV640BU

Sector

A21

A20

A19

A18

A17

A16

A15

16-bit Address Range

(in hexadecimal)

130000-137FFF

138000-13FFFF

140000-147FFF

148000-14FFFF

150000-157FFF

158000-15FFFF

160000-167FFF

168000-16FFFF

170000-177FFF

178000-17FFFF

180000-187FFF

188000-18FFFF

190000-197FFF

198000-19FFFF

1A0000-1A7FFF

1A8000-1AFFFF

1B0000-1B7FFF

1B8000-1BFFFF

1C0000-1C7FFF

1C8000-1CFFFF

1D0000-1D7FFF

1D8000-1DFFFF

1E0000-1E7FFF

1E8000-1EFFFF

1F0000-1F7FFF

1F8000-1FFFFF

200000-207FFF

208000-20FFFF

210000-217FFF

218000-21FFFF

220000-227FFF

228000-22FFFF

230000-237FFF

238000-23FFFF

240000-247FFF

248000-24FFFF

250000-257FFF

258000-25FFFF

260000-267FFF

268000-26FFFF

SA38

SA39

SA40

SA41

SA42

SA43

SA44

SA45

SA46

SA47

SA48

SA49

SA50

SA51

SA52

SA53

SA54

SA55

SA56

SA57

SA58

SA59

SA60

SA61

SA62

SA63

SA64

SA65

SA66

SA67

SA68

SA69

SA70

SA71

SA72

SA73

SA74

SA75

SA76

SA77

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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MX29LV640BU

Sector

A21

A20

A19

A18

A17

A16

A15

16-bit Address Range

(in hexadecimal)

270000-277FFF

278000-27FFFF

280000-287FFF

288000-28FFFF

290000-297FFF

298000-29FFFF

2A0000-2A7FFF

2A8000-2AFFFF

2B0000-2B7FFF

2B8000-2BFFFF

2C0000-2C7FFF

2C8000-2CFFFF

2D0000-2D7FFF

2D8000-2DFFFF

2E0000-2E7FFF

2E8000-2EFFFF

2F0000-2F7FFF

2F8000-2FFFFF

300000-307FFF

308000-30FFFF

310000-317FFF

318000-31FFFF

320000-327FFF

328000-32FFFF

330000-337FFF

338000-33FFFF

340000-347FFF

348000-34FFFF

350000-357FFF

358000-35FFFF

360000-367FFF

368000-36FFFF

370000-377FFF

378000-37FFFF

380000-387FFF

388000-38FFFF

390000-397FFF

398000-39FFFF

3A0000-3A7FFF

3A8000-3AFFFF

SA78

SA79

SA80

SA81

SA82

SA83

SA84

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

SA85

SA86

SA87

SA88

SA89

SA90

SA91

SA92

SA93

SA94

SA95

SA96

SA97

SA98

SA99

SA100

SA101

SA102

SA103

SA104

SA105

SA106

SA107

SA108

SA109

SA110

SA111

SA112

SA113

SA114

SA115

SA116

SA117

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MX29LV640BU

Sector

A21

A20

A19

A18

A17

A16

A15

16-bit Address Range

(in hexadecimal)

3B0000-3B7FFF

3B8000-3BFFFF

3C0000-3C7FFF

3C8000-3CFFFF

3D0000-3D7FFF

3D8000-3DFFFF

3E0000-3E7FFF

3E8000-3EFFFF

3F0000-3F7FFF

3F8000-3FFFFF

SA118

SA119

SA120

SA121

SA122

SA123

SA124

SA125

SA126

SA127

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

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MX29LV640BU

Sector Group Protection/Unprotected Address Table

Sector Group

SA0-SA3

A21-A17

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

SA4-SA7

SA8-SA11

SA12-SA15

SA16-SA19

SA20-SA23

SA24-SA27

SA28-SA31

SA32-SA35

SA36-SA39

SA40-SA43

SA44-SA47

SA48-SA51

SA52-SA55

SA56-SA59

SA60-SA63

SA64-SA65

SA66-SA69

SA70-SA73

SA74-SA79

SA80-SA83

SA84-SA87

SA88-SA91

SA92-SA95

SA96-SA99

SA100-SA103

SA104-SA107

SA108-SA111

SA112-SA115

SA116-SA119

SA120-SA123

SA124-SA127

Note: All sector groups are 128K words in size.

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MX29LV640BU

Table 1. BUS OPERATION (1)

Operation

CE# OE# WE# RESET# WP#

ACC

X

Address (Note 2) Q15~Q0

Read

L

H

X

H

L

H

X

A_IN

X

D_OUT

Write (Program/Erase)

Accelerated Program

Standby

L

(Note 2)

X

(Note 3)

High-Z

L

VCC±

0.3V

L

H

V_HH

H

X

VCC±

0.3V

H

Output Disable

Reset

H

X

H

X

L

X

H

X

High-Z

X

L

Sector Group Protect

(Note 1)

L

V_ID

Sector Addresses, (Note 3)

A6=L, A1=H, A0=L

Chip

L

H

X

L

V_ID

H

X

Sector Addresses, (Note 3)

A6=H, A1=H, A0=L

Unprotect (Note 1)

Temporary Sector Group

Unprotect

X

A_IN

(Note 3)

Legend:

L=Logic LOW=V_IL,H=Logic High=V_IH,V_ID=12.0±0.5V, X=Don't Care, A_IN=Address IN, D_IN=Data IN, D_OUT=Data OUT

Notes:

1. The sector group protect and chip unprotect functions may also be implemented via programming equipment. See

the "Sector Group Protection and Chip Unprotect" section.

2. If WP#=VIL, the first sector remains protected. If WP#=VIH, the first sector will be protected or unprotected as

determined by the method described in "Sector Group Protection and Unprotect". All sectors are unprotected when

shipped from the factory (The Secured Silicon Sector may be factory protected depending on version ordered).

3. D_INor D_OUTas required by command sequence, Data# polling or sector protect algorithm (see Figure 14).

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MX29LV640BU

Table 2. AUTOMATIC SELECT CODES (High Voltage Method)

Operation

CE# OE# WE# A0 A1 A5 A6 A8 A9 A14 A15

Q0~Q15

to

A2

X

to

A7

X

to

A10 A21

Read

Manufactures Code

L

H

L

V_ID

X

C2H

Silicon Device Code

ID

H

X

22D7H

Sector Protect Verify

Secured Silicon Sector

Indicator Bit(Q7)

with WP# Protects

highest Address Sector

Secured Silicon Sector

Indicator Bit(Q7)

with WP# Protects

lowest Address Sector

L

H

L

H

X

L

X

V_ID

X

SA

X

Code(1)

xx98h

H

(factory locked)

xx18h

(non-factory locked)

xx88h

L

H

X

L

X

V_ID

X

(factory locked)

xx08h

(non-factory locked)

Notes:

1.code=xx00h means unprotected, or code=xx01h means protected, SA=Sector Address, X=Don't care.

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MX29LV640BU

REQUIREMENTS FOR READING ARRAY

DATA

ACCELERATED PROGRAM OPERATION

The device offers accelerated program operations through

the ACC function. This is one of two functions provided

by the ACC pin. This function is primarily intended to

allow faster manufacturing throughput at the factory.

To read array data from the outputs, the system must

drive the CE# and OE# pins to VIL. CE# is the power

control and selects the device. OE# is the output control

and gates array data to the output pins.WE# should re-

main at VIH.

If the system asserts VHH on this pin, the device auto-

matically enters the aforementioned accelerated program

mode, temporarily unprotects any protected sectors, and

uses the higher voltage on the pin to reduce the time

required for program operations.RemovingVHH from the

ACC pin must not be at VHH for operations other than

accelerated programming, or device damage may result.

The internal state machine is set for reading array data

upon device power-up, or after a hardware reset. This

ensures that no spurious alteration of the memory con-

tent occurs during the power transition. No command is

necessary in this mode to obtain array data. Standard

microprocessor read cycles that assert valid address on

the device address inputs produce valid data on the de-

vice data outputs. The device remains enabled for read

access until the command register contents are altered.

STANDBY MODE

MX29LV640BU can be set into Standby mode with two

different approaches. One is using both CE# and RE-

SET# pins and the other one is using RESET# pin only.

WRITE COMMANDS/COMMAND SEQUENCES

To program data to the device or erase sectors of memory

, the system must drive WE# and CE# to VIL, and OE#

to VIH.

When using both pins of CE# and RESET#, a CMOS

Standby mode is achieved with both pins held at Vcc ±

0.3V. Under this condition, the current consumed is less

than 0.2uA (typ.). If both of the CE# and RESET# are

held at VIH, but not within the range of VCC ± 0.3V, the

device will still be in the standby mode, but the standby

current will be larger. During Auto Algorithm operation,

Vcc active current (Icc2) is required even CE# = "H"

until the operation is completed.The device can be read

with standard access time (tCE) from either of these

standby modes.

An erase operation can erase one sector, multiple sec-

tors , or the entire device. Table indicates the address

space that each sector occupies. A "sector address"

consists of the address bits required to uniquely select a

sector.The "Writing specific address and data commands

or sequences into the command register initiates device

operations. Table 1 defines the valid register command

sequences.Writing incorrect address and data values or

writing them in the improper sequence resets the device

to reading array data". Section has details on erasing a

sector or the entire chip, or suspending/resuming the erase

operation.

When using only RESET#, a CMOS standby mode is

achieved with RESET# input held at Vss ± 0.3V, Under

this condition the current is consumed less than 1uA (typ.).

Once the RESET# pin is taken high, the device is back

to active without recovery delay.

After the system writes the Automatic Select command

sequence, the device enters the Automatic Select mode.

The system can then read Automatic Select codes from

the internal register (which is separate from the memory

array) on Q7-Q0. Standard read cycle timings apply in

this mode. Refer to the Automatic Select Mode and Au-

tomatic Select Command Sequence section for more in-

formation.

In the standby mode the outputs are in the high imped-

ance state, independent of the OE# input.

MX29LV640BU is capable to provide the Automatic

Standby Mode to restrain power consumption during read-

out of data. This mode can be used effectively with an

application requested low power consumption such as

handy terminals.

ICC2 in the DC Characteristics table represents the ac-

tive current specification for the write mode. The "AC

Characteristics" section contains timing specification table

and timing diagrams for write operations.

To active this mode, MX29LV640BU automatically switch

themselves to low power mode when MX29LV640BU ad-

dresses remain stable during access time of tACC+30ns.

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MX29LV640BU

It is not necessary to control CE#, WE#, and OE# on the

mode. Under the mode, the current consumed is typi-

cally 0.2uA (CMOS level).

internal reset operation is complete, which requires a time

of tREADY. The system can thus monitor RY/BY# to

determine whether the reset operation is complete. If

RESET# is asserted when a program or erase operation

is completed within a time of tREADY. The system can

read data tRH after the RESET# pin returns to VIH.

AUTOMATIC SLEEP MODE

Refer to the AC Characteristics tables for RESET#

parameters and to Figure 3 for the timing diagram.

The automatic sleep mode minimizes Flash device en-

ergy consumption.The device automatically enables this

mode when address remain stable for tACC+30ns. The

automatic sleep mode is independent of the CE#, WE#,

and OE# control signals. Standard address access tim-

ings provide new data when addresses are changed.While

in sleep mode, output data is latched and always avail-

able to the system. ICC4 in the DC Characteristics table

represents the automatic sleep mode current specifica-

tion.

SECTOR GROUP PROTECT OPERATION

The MX29LV640BU features hardware sector group pro-

tection. This feature will disable both program and erase

operations for these sector group protected. In this de-

vice, a sector group consists of four adjacent sectors

which are protected or unprotected at the same time.To

activate this mode, the programming equipment must

force VID on address pin A9 and control pin OE#, (sug-

gest VID = 12V) A6 = VIL and CE# = VIL. (see Table 2)

Programming of the protection circuitry begins on the

falling edge of the WE# pulse and is terminated on the

rising edge. Please refer to sector group protect algo-

rithm and waveform.

OUTPUT DISABLE

With the OE# input at a logic high level (VIH), output

from the devices are disabled.This will cause the output

pins to be in a high impedance state.

MX29LV640BU also provides another method.Which re-

quiresVID on the RESET# only.This method can be imple-

mented either in-system or via programming equipment.

This method uses standard microprocessor bus cycle

timing.

RESET# OPERATION

The RESET# pin provides a hardware method of resetting

the device to reading array data.When the RESET# pin

is driven low for at least a period of tRP, the device

immediately terminates any operation in progress,

tristates all output pins, and ignores all read/write

commands for the duration of the RESET# pulse. The

device also resets the internal state machine to reading

array data.The operation that was interrupted should be

reinitiated once the device is ready to accept another

command sequence, to ensure data integrity

To verify programming of the protection circuitry, the pro-

gramming equipment must forceVID on address pin A9

( with CE# and OE# at VIL and WE# at VIH). When

A1=1, it will produce a logical "1" code at device output

Q0 for a protected sector. Otherwise the device will pro-

duce 00H for the unprotected sector. In this mode, the

addresses, except for A1, are don't care. Address loca-

tions with A1 = VIL are reserved to read manufacturer

and device codes. (Read Silicon ID)

Current is reduced for the duration of the RESET# pulse.

When RESET# is held at VSS±0.3V, the device draws

CMOS standby current (ICC4).If RESET# is held atVIL

but not within VSS±0.3V, the standby current will be

greater.

It is also possible to determine if the group is protected

in the system by writing a Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

a logical "1" at Q0 for the protected sector.

The RESET# pin may be tied to system reset circuitry.

A system reset would that also reset the Flash memory,

enabling the system to read the boot-up firmware from

the Flash memory.

CHIP UNPROTECT OPERATION

The MX29LV640BU also features the chip unprotected

mode, so that all sectors are unprotected after chip

If RESET# is asserted during a program or erase

operation, the RY/BY# pin remains a "0" (busy) until the

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MX29LV640BU

unprotected is completed to incorporate any changes in

the code. It is recommended to protect all sectors before

activating chip unprotect mode.

SET# pin, all the previously protected sectors are pro-

tected again.

To activate this mode, the programming equipment must

force VID on control pin OE# and address pin A9. The

CE# pins must be set at VIL. Pins A6 must be set to

VIH. (see Table 2) Refer to chip unprotected algorithm

and waveform for the chip unprotected algorithm. The

unprotected mechanism begins on the falling edge of the

WE# pulse and is terminated on the rising edge.

SILICON ID READ OPERATION

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design prac-

tice.

MX29LV640BU also provides another method.Which re-

quiresVID on the RESET# only.This method can be imple-

mented either in-system or via programming equipment.

This method uses standard microprocessor bus cycle

timing.

MX29LV640BU provides hardware method to access the

silicon ID read operation.Which method requiresVID on

A9 pin, VIL on CE#, OE#, A6, and A1 pins.Which apply

VIL on A0 pin, the device will output MXIC's manufac-

ture code of C2H.Which applyVIH on A0 pin, the device

will output MX29LV640BU device code of 22D7H.

It is also possible to determine if the chip is unprotected

in the system by writing the Read Silicon ID command.

Performing a read operation with A1=VIH, it will produce

00H at data outputs (Q0-Q15) for an unprotected sector.

It is noted that all sectors are unprotected after the chip

unprotected algorithm is completed.

VERIFY SECTOR GROUP PROTECT STATUS

OPERATION

MX29LV640BU provides hardware method for sector group

protect status verify. Which method requires VID on A9

pin, VIH on WE# and A1 pins, VIL on CE#, OE#, A6, and

A0 pins, and sector address on A16 to A21 pins. Which

the identified sector is protected, the device will output

01H.Which the identified sector is not protect, the device

will output 00H.

WRITE PROTECT (WP#)

This Write Protect function provides a hardware protec-

tion method on the first sector without using VID.

If the system asserts VIL on the WP# pin, the device

disable program and erase function in the first sector in-

dependently of whether those sectors were protected or

unprotect using the method described in "Sector Group

Protection and Unprotect".

DATA PROTECTION

The MX29LV640BU is designed to offer protection against

accidental erasure or programming caused by spurious

system level signals that may exist during power transi-

tion. During power up the device automatically resets

the state machine in the Read mode. In addition, with its

control register architecture, alteration of the memory

contents only occurs after successful completion of spe-

cific command sequences. The device also incorporates

several features to prevent inadvertent write cycles re-

sulting fromVCC power-up and power-down transition or

system noise.

If the system asserts VIH on the WP# pin, the device

reverts to whether the first sector was previously set to

be protected or unprotected using the method described

in "Sector Group Protection and Unprotect".

TEMPORARY SECTOR GROUP UNPROTECT

OPERATION

This feature allows temporary unprotect of previously pro-

tected sector to change data in-system.The Temporary

Sector Unprotect mode is activated by setting the RE-

SET# pin to VID(11.5V-12.5V). During this mode, for-

merly protected sectors can be programmed or erased

as unprotected sector.OnceVID is remove from the RE-

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MX29LV640BU

the system issues the Exit Secured Silicon Sector com-

mand sequence, or until power is removed from the de-

vice. On power-up, or following a hardware reset, the

device reverts to sending command to sector SA0.

SECURED SILICON SECTOR

The MX29LV640BU features a OTP region where the sys-

tem may access through a command sequence to cre-

ate a permanent part identification as so called Elec-

tronic Serial Number (ESN) in the device. Once this re-

gion is programmed, any further modification on the re-

gion is impossible. The secured silicon sector is a 128

words in length, and uses a Secured Silicon Sector Indi-

cator Bit (Q7) to indicate whether or not the Secured

Silicon Sector is locked when shipped from the factory.

This bit is permanently set at the factory and cannot be

changed, which prevent duplication of a factory locked

part.This ensures the security of the ESN once the prod-

uct is shipped to the field.

FACTORY LOCKED:Secured Silicon Sector

Programmed and Protected At the Factory

In device with an ESN, the Secured Silicon Sector is

protected when the device is shipped from the factory.

The Secured Silicon Sector cannot be modified in any

way.A factory locked device has an 8-word random ESN

at address 000000h-000007h.

The MX29LV640BU offers the device with Secured Sili-

con Sector either factory locked or customer lockable.

The factory-locked version is always protected when

shipped from the factory , and has the Secured Silicon

Sector Indicator Bit permanently set to a "1". The cus-

tomer-lockable version is shipped with the Secured Sili-

con Sector unprotected, allowing customs to utilize that

sector in any form they prefer. The customer-lockable

version has the secured sector Indicator Bit permanently

set to a "0". Therefore, the Secured Silicon Sector Indi-

cator Bit permanently set to a "0". Therefore, the Sec-

ond Silicon Sector Indicator Bit prevents customer, lock-

able device from being used to replace devices that are

factory locked.

CUSTOMER LOCKABLE:Secured Silicon

Sector NOT Programmed or Protected At the

Factory

As an alternative to the factory-locked version, the device

may be ordered such that the customer may program

and protect the 128-word Secured Silicon Sector.

Programming and protected the Secured Silicon Sector

must be used with caution since, once protected, there

is no procedure available for unprotecting the Secured

Silicon Sector area and none of the bits in the Secured

Silicon Sector memory space can be modified in any

way.

The secured silicon sector address space in this device

is allocated as follows.

The Secured Silicon Sector area can be protected using

one of the following procedures:

Write the three-cycle Enter Secured Silicon Sector Region

command sequence, and then follow the in-system

sector protect algorithm as shown in Figure 14, except

that RESET# may be at eitherVIH orVID.This allows in-

system protection of the Secured Silicon Sector without

raising any device pin to a high voltage. Note that method

is only applicable to the Secured Silicon Sector.

Secured Silicon Standard Express Flash Customer

Sector Address Factory

Factory

Lockable

Range

Locked

000000h-

000007h

ESN

ESN or

Determined

by Customer

Determined

by

000008h-

00007Fh

Unavailable Determined

by Customer

Customer

Write the three-cycle Enter Secured Silicon Sector Region

command sequence, and then alternate method of sector

protection described in the :Sector Group Protection and

Unprotect" section.

The system access the Secured Silicon Sector through

a command sequence (refer to "Enter Secured Silicon/

Exit Secured Silicon Sector command Sequence). After

the system has written the Enter Secured Silicon Sector

command sequence, it may read the Secured Silicon

Sector by using the address normally occupied by the

first sector (SA0).This mode of operation continues until

Once the Secured Silicon Sector is programmed, locked

and verified, the system must write the Exit Secured

Silicon Sector Region command sequence to return to

reading and writing the remainder of the array.

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MX29LV640BU

LOW VCC WRITE INHIBIT

When VCC is less than VLKO the device does not ac-

cept any write cycles. This protects data during VCC

power-up and power-down.The command register and

all internal program/erase circuits are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater thanVLKO. The system must provide the proper

signals to the control pins to prevent unintentional write

whenVCC is greater thanVLKO.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# orWE# will

not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# =VIL, CE#

= VIH or WE# = VIH. To initiate a write cycle CE# and

WE# must be a logical zero while OE# is a logical one.

POWER-UP SEQUENCE

The MX29LV640BU powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

POWER-UP WRITE INHIBIT

If WE#=CE#=VIL and OE#=VIH during power up, the

device does not accept commands on the rising edge of

WE#. The internal state machine is automatically reset

to the read mode on power-up.

POWER SUPPLY DE COUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

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MX29LV640BU

Erase Resume (30H) commands are valid only while the

Sector Erase operation is in progress. Either of the two

reset command sequences will reset the device (when

applicable).

SOFTWARE COMMAND DEFINITIONS

Device operations are selected by writing specific ad-

dress and data sequences into the command register.

Writing incorrect address and data values or writing them

in the improper sequence will reset the device to the

read mode. Table 3 defines the valid register command

sequences. Note that the Erase Suspend (B0H) and

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data are latched on

rising edge of WE# or CE#, whichever happens first.

TABLE 3. MX29LV640BU COMMAND DEFINITIONS

First Bus

Cycle

Addr

Second Bus Third Bus

Cycle Cycle

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Bus

Cycle

1

Data Addr Data Addr

Data Addr Data

Addr Data Addr Data

Read(Note 5)

RA

RD

F0

Reset(Note 6)

1

XXX

Automatic Select(Note 7)

Manufacturer ID

Device ID

4

555

AA

2AA

55

555

90

X00 C2

AA

X01 22D7

X03 see

Secured Sector Factory

Protect (Note 9)

Sector Group Protect

Verify (Note 8)

Note10

xx00

X02 xx01

4

3

555

AA

2AA

55

555

90

88

SA

Enter Secured Silicon

Sector

Exit Secured Silicon

Sector

4

555

AA

2AA

55

555

90

xxx

PA

00

Program

4

6

1

555

55

AA

B0

30

98

2AA

55

555

A0

80

PD

Chip Erase

555 AA

2AA 55

555 10

SA 30

Sector Erase

Erase Suspend(Note 10)

Erase Resume(Note 11)

CFI Query (Note 12)

Legend:

X=Don't care

RA=Address of the memory location to be read.

PD=Data to be programmed at location PA.Data is latched

on the rising edge of WE# or CE# pulse.

RD=Data read from location RA during read operation.

PA=Address of the memory location to be programmed.

SA=Address of the sector to be erased or verified.

Address bits A21-A16 uniquely select any sector.

Addresses are latched on the falling edge of the WE# or

CE# pulse.

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MX29LV640BU

Notes:

1. See Table 1 for descriptions of bus operations.

2. All values are in hexadecimal.

3. Except when reading array or Automatic Select data, all bus cycles are write operation.

4. Address bits are don't care for unlock and command cycles, except when PA or SA is required.

5. No unlock or command cycles required when device is in read mode.

6. The Reset command is required to return to the read mode when the device is in the Automatic Select mode or if

Q5 goes high.

7. The fourth cycle of the Automatic Select command sequence is a read cycle.

8. The data is 00h for an unprotected sector/sector block and 01h for a protected sector/sector block. In the third

cycle of the command sequence, address bit A21=0 to verify sectors 0~63, A21=1 to verify sectors 64.

9. If WP# protects the highest address sectors, the data is 98h for factory locked and 18h for factory. If WP# protects

the lowest address sector, the data is 88h for factory locked and 08h for not factory locked.

10.The system may read and program functions in non-erasing sectors, or enter the Automatic Select mode, when in

the erase Suspend mode.The Erase Suspend command is valid only during a sector erase operation.

11.The Erase Resume command is valid only during the Erase Suspend mode.

12.Command is valid when device is ready to read array data or when device is in Automatic Select mode.

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

READING ARRAY DATA

data. Once erasure begins, however, the device ignores

reset commands until the operation is complete.

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data.The device is also ready to read array data

after completing an Automatic Program or Automatic

Erase algorithm.

The reset command may be written between the se-

quence cycles in a program command sequence before

programming begins. This resets the device to reading

array data (also applies to programming in Erase Suspend

mode). Once programming begins, however, the device

ignores reset commands until the operation is complete.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The system

can read array data using the standard read timings,

except that if it reads at an address within erase-

suspended sectors, the device outputs status data. After

completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See "Erase Suspend/Erase

Resume Commands" for more information on this mode.

The system must issue the reset command to re-en-

able the device for reading array data if Q5 goes high, or

while in the Automatic Select mode. See the "Reset

Command" section, next.

The reset command may be written between the

sequence cycles in an SILICON ID READ command

sequence. Once in the SILICON ID READ mode, the

reset command must be written to return to reading array

data (also applies to SILICON ID READ during Erase

Suspend).

If Q5 goes high during a program or erase operation,

writing the reset command returns the device to reading

array data (also applies during Erase Suspend).

RESET COMMAND

SILICON ID READ COMMAND SEQUENCE

Writing the reset command to the device resets the

device to reading array data. Address bits are don't care

for this command.

The SILICON ID READ command sequence allows the

host system to access the manufacturer and devices

codes, and determine whether or not a sector is protected.

Table 3 shows the address and data requirements.

The reset command may be written between the se-

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MX29LV640BU

This method is an alternative to that shown in Table 1,

which is intended for PROM programmers and requires

V^IDon address bit A9.

SETUP AUTOMATIC CHIP/SECTOR ERASE

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cycles

are then followed by the chip erase command 10H, or the

sector erase command 30H.

The SILICON ID READ command sequence is initiated

by writing two unlock cycles, followed by the SILICON

ID READ command. The device then enters the SILICON

ID READ mode, and the system may read at any address

any number of times, without initiating another command

sequence. A read cycle at address XX00h retrieves the

manufacturer code. A read cycle at address XX01h

returns the device code. A read cycle containing a sector

address (SA) and the address 02h returns 01h if that

sector is protected, or 00h if it is unprotected. Refer to

Table for valid sector addresses.

The MX29LV640BU contains a Silicon-ID-Read operation

to supplement traditional PROM programming methodol-

ogy. The operation is initiated by writing the read silicon

ID command sequence into the command register. Fol-

lowing the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H.

A read cycle with A1=VIL, A0=VIH returns the device

code of 22D7H for MX29LV640BU.

The system must write the reset command to exit the

Automatic Select mode and return to reading array data.

AUTOMATIC

COMMAND

CHIP/SECTOR

ERASE

WORD PROGRAM COMMAND SEQUENCE

The device does not require the system to preprogram

prior to erase.The Automatic Erase algorithm automati-

cally pre-program and verifies the entire memory for an

all zero data pattern prior to electrical erase.The system

is not required to provide any controls or timings during

these operations. Table 3 shows the address and data

requirements for the chip erase command sequence.

The command sequence requires four bus cycles, and is

initiated by writing two unlock write cycles, followed by

the program set-up command. The program address and

data are written next, which in turn initiate the Embedded

Program algorithm. The system is not required to provide

further controls or timings. The device automatically

generates the program pulses and verifies the

programmed cell margin. Table 3 shows the address and

data requirements for the word program command

sequence.

Any commands written to the chip during the Automatic

Erase algorithm are ignored.Note that a hardware reset

during the chip erase operation immediately terminates

the operation.The Chip Erase command sequence should

be reinitiated once the device has returned to reading

array data, to ensure data integrity.

When the Embedded Program algorithm is complete, the

device then returns to reading array data and addresses

are no longer latched. The system can determine the

status of the program operation by using Q7, Q6, or RY/

BY#.See "Write Operation Status" for information on these

status bits.

The system can determine the status of the erase opera-

tion by using Q7, Q6, Q2, or RY/BY#.See "Write Opera-

tion Status" for information on these status bits. When

the Automatic Erase algorithm is complete, the device

returns to reading array data and addresses are no longer

latched.

Any commands written to the device during the

Embedded Program Algorithm are ignored. Note that a

hardware reset immediately terminates the programming

operation. The Word Program command sequence should

be reinitiated once the device has reset to reading array

data, to ensure data integrity.

Figure 5 illustrates the algorithm for the erase operation.

See the Erase/Program Operations tables in "AC Char-

acteristics" for parameters, and to Figure 4 for timing

diagrams.

Programming is allowed in any sequence and across

sector boundaries. A bit cannot be programmed from a

"0" back to a "1". Attempting to do so may halt the

operation and set Q5 to "1" ,” or cause the Data# Polling

algorithm to indicate the operation was successful.

However, a succeeding read will show that the data is

still "0". Only erase operations can convert a "0" to a

"1".

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MX29LV640BU

SECTOR ERASE COMMANDS

therefore will only be responded during Automatic Sector

Erase operation. When the Erase Suspend command is

issued during the sector erase operation, the device re-

quires a maximum 20us to suspend the sector erase

operation.However, When the Erase Suspend command

is written during the sector erase time-out, the device

immediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mode. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to the

Erase Resume, program data to, or read data from any

sector not selected for erasure.

The Automatic Sector Erase does not require the

device to be entirely pre-programmed prior to

executing the Automatic Set-up Sector Erase

command and Automatic Sector Erase command.

Upon executing the Automatic Sector Erase

command, the device will automatically program and

verify the sector(s) memory for an all-zero data

pattern. The system is not required to provide any

control or timing during these operations.

When the sector(s) is automatically verified to

contain an all-zero pattern, a self-timed sector erase

and verify begin. The erase and verify operations are

complete when the data on Q7 is "1" and the data on

Q6 stops toggling for two consecutive read cycles, at

which time the device returns to the Read mode. The

system is not required to provide any control or timing

during these operations.

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation. After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended blocks.

When using the Automatic Sector Erase algorithm,

note that the erase automatically terminates when

adequate erase margin has been achieved for the

memory array (no erase verification command is

required). Sector erase is a six-bus cycle operation.

There are two "unlock" write cycles. These are

followed by writing the set-up command 80H. Two

more "unlock" write cycles are then followed by the

sector erase command 30H. The sector address is

latched on the falling edge of WE# or CE#, whichever

happens later , while the command (data) is latched

on the rising edge of WE# or CE#, whichever happens

first. Sector addresses selected are loaded into

internal register on the sixth falling edge of WE# or

CE#, whichever happens later. Each successive

sector load cycle started by the falling edge of WE#

or CE#, whichever happens later must begin within

50us from the rising edge of the preceding WE# or

CE#, whichever happens first. Otherwise, the loading

period ends and internal auto sector erase cycle

starts. (Monitor Q3 to determine if the sector erase

timer window is still open, see section Q3, Sector

Erase Timer.) Any command other than Sector Erase

(30H) or Erase Suspend (B0H) during the time-out

period resets the device to read mode.

ERASE RESUME

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions. Another Erase Suspend command can

be written after the chip has resumed erasing.

QUERY COMMAND AND COMMON FLASH

INTERFACE (CFI) MODE

MX29LV640BU is capable of operating in the CFI mode.

This mode all the host system to determine the manu-

facturer of the device such as operating parameters and

configuration.Two commands are required in CFI mode.

Query command of CFI mode is placed first, then the

Reset command exits CFI mode.These are described in

Table 3.

The single cycle Query command is valid only when the

device is in the Read mode, including Erase Suspend,

Standby mode, and Read ID mode;however, it is ignored

otherwise.

ERASE SUSPEND

The Reset command exits from the CFI mode to the Read

mode, or Erase Suspend mode, or read ID mode. The

command is valid only when the device is in the CFI

mode.

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation, and

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MX29LV640BU

Table 4-1. CFI mode: Identification Data Values

(All values in these tables are in hexadecimal)

Description

Addressh

Datah

0051

0052

0059

0002

0000

0040

0000

Query-unique ASCII string "QRY"

10

11

12

13

14

15

16

17

18

19

1A

Primary vendor command set and control interface ID code

Address for primary algorithm extended query table

Alternate vendor command set and control interface ID code (none)

Address for secondary algorithm extended query table (none)

Table 4-2. CFI Mode: System Interface Data Values

Description

Addressh

Datah

0027

0036

0000

0004

0000

000A

0000

0005

0000

0004

0000

VCC supply, minimum (2.7V)

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

VCC supply, maximum (3.6V)

VPP supply, minimum (none)

VPP supply, maximum (none)

Typical timeout for single word/byte write (2^Nus)

Typical timeout for maximum size buffer write (2^Nus)

Typical timeout for individual block erase (2^Nms)

Typical timeout for full chip erase (2^Nms)

Maximum timeout for single word/byte write times (2^NX Typ)

Maximum timeout for maximum size buffer write times (2^NX Typ)

Maximum timeout for individual block erase times (2^NX Typ)

Maximum timeout for full chip erase times (not supported)

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MX29LV640BU

Table 4-3. CFI Mode: Device Geometry Data Values

Description

Device size (2ⁿbytes)

Addressh

27

Datah

0017

Flash device interface code (02=asynchronous x8/x16)

28

0001

29

0000

Maximum number of bytes in multi-byte write (not supported)

2A

0000

2B

0000

Number of erase block regions

2C

0001

Erase block region 1 information

[2E,2D] = # of blocks in region -1

[30, 2F] = size in multiples of 256-bytes

2D

2E

2F

007F

0000

30

0001

31h

32h

33h

34h

35h

36h

37h

38h

39h

3Ah

3Bh

3Ch

0000h

Erase Block Region 2 Information (refer to CFI publication 100)

Erase Block Region 3 Information (refer to CFI publication 100)

Erase Block Region 4 Information (refer to CFI publication 100)

Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values

Description

Addressh

Datah

0050

0052

0049

0031

0033

0000

0002

0004

0001

0004

0000

00B5

Query-unique ASCII string "PRI"

40

41

42

Major version number, ASCII

43

Minor version number, ASCII

44

Address sensitive unlock (0=required, 1= not required)

Erase suspend (2= to read and write)

45

46

Sector protect (N= # of sectors/group)

Temporarysectorunprotected(1=supported)

Sectorprotect/unprotectedscheme(04=29LV800mode)

SimultaneousR/Woperation(0=notsupported)

Burst mode type (0=not supported)

47

48

49

4A

4B

4C

4Dh

Page mode type (0=not supported)

ACC (Acceleration) Supply Minimum

00h=NotSupported,D7-D4:Volt,D3-D0:100mV

ACC (Acceleration) Supply Maximum

00h=NotSupported,D7-D4:Volt,D3-D0:100mV

Top/Bottom Boot Sector Flag

4Eh

4Fh

00C5

0000h

02h=Bottom Boot Device, 03h=Top BootnDevice

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MX29LV640BU

WRITE OPERATION STATUS

The device provides several bits to determine the status

of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/BY#.

Table 5 and the following subsections describe the func-

tions of these bits. Q7, RY/BY#, and Q6 each offer a

method for determining whether a program or erase op-

eration is complete or in progress. These three bits are

discussed first.

Table 5. Write Operation Status

Status

Q7#

Q6

Q5

Q3

Q2 RY/BY#

Note1

Note2

Word Program in Auto Program Algorithm

Auto Erase Algorithm

Q7# Toggle

0

N/A

1

No

0

Toggle

0

1

Toggle

0

Toggle

0

1

Erase Suspend Read

(Erase Suspended Sector)

No

Toggle

N/A Toggle

In Progress

Erase Suspended Mode Erase Suspend Read

(Non-Erase Suspended Sector)

Data

Data Data Data

1

0

Erase Suspend Program

Q7# Toggle

0

1

N/A N/A

Word Program in Auto Program Algorithm

N/A

1

No

Toggle

Exceeded

Time Limits Auto Erase Algorithm

0

Toggle

1

Toggle

0

Erase Suspend Program

Q7# Toggle

N/A N/A

Notes:

1. Performing successive read operations from the erase-suspended sector will cause Q2 to toggle.

2. Performing successive read operations from any address will cause Q6 to toggle.

3. Reading the word address being programmed while in the erase-suspend program mode will indicate logic "1" at the

Q2 bit.

However, successive reads from the erase-suspended sector will cause Q2 to toggle.

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MX29LV640BU

after the rising edge of the final WE# or CE#, whichever

happens first pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

Q7: Data# Polling

The Data# Polling bit, Q7, indicates to the host system

whether an Automatic Algorithm is in progress or com-

pleted, or whether the device is in Erase Suspend.Data#

Polling is valid after the rising edge of the finalWE# pulse

in the program or erase command sequence.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

control the read cycles.When the operation is complete,

Q6 stops toggling.

During the Automatic Program algorithm, the device out-

puts on Q7 the complement of the datum programmed

to Q7.This Q7 status also applies to programming dur-

ing Erase Suspend.When the Automatic Program algo-

rithm is complete, the device outputs the datum pro-

grammed to Q7.The system must provide the program

address to read valid status information on Q7. If a pro-

gram address falls within a protected sector, Data# Poll-

ing on Q7 is active for approximately 1 us, then the de-

vice returns to reading array data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles for

100us and returns to reading array data. If not all se-

lected sectors are protected, the Automatic Erase algo-

rithm erases the unprotected sectors, and ignores the

selected sectors that are protected.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase suspended.

When the device is actively erasing (that is, the Auto-

matic Erase algorithm is in progress), Q6 toggling.When

the device enters the Erase Suspend mode, Q6 stops

toggling. However, the system must also use Q2 to de-

termine which sectors are erasing or erase-suspended.

Alternatively, the system can use Q7.

During the Automatic Erase algorithm, Data# Polling pro-

duces a "0" on Q7.When the Automatic Erase algorithm

is complete, or if the device enters the Erase Suspend

mode, Data# Polling produces a "1" on Q7.This is analo-

gous to the complement/true datum output described for

the Automatic Program algorithm: the erase function

changes all the bits in a sector to "1" prior to this, the

device outputs the "complement,” or "0".” The system

must provide an address within any of the sectors se-

lected for erasure to read valid status information on Q7.

If a program address falls within a protected sector, Q6

toggles for approximately 2us after the program com-

mand sequence is written, then returns to reading array

data.

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Data# Polling on

Q7 is active for approximately 100 us, then the device

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algo-

rithm is complete.

Table 5 shows the outputs for Toggle Bit I on Q6.

When the system detects Q7 has changed from the

complement to true data, it can read valid data at Q7-Q0

on the following read cycles. This is because Q7 may

change asynchronously with Q0-Q6 while Output Enable

(OE#) is asserted low.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit II is valid

after the rising edge of the final WE# or CE#, whichever

happens first pulse in the command sequence.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE# or CE# to control the read

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MX29LV640BU

cycles.) But Q2 cannot distinguish whether the sector is

actively erasing or is erase-suspended. Q6, by compari-

son, indicates whether the device is actively erasing, or

is in Erase Suspend, but cannot distinguish which sec-

tors are selected for erasure. Thus, both status bits are

required for sectors and mode information. Refer toTable

5 to compare outputs for Q2 and Q6.

the only operating functions of the device under this con-

dition.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

Reading Toggle Bits Q6/ Q2

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has

completed the program or erase operation. The system

can read array data on Q7-Q0 on the following read cycle.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the word program-

ming operation, it specifies that the entire sector con-

taining that word is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

The time-out condition may also appear if a user tries to

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

The Q5 failure condition may appear if the system tries

to program a to a "1" location that is previously pro-

grammed to "0". Only an erase operation can change a

"0" back to a "1".” Under this condition, the device halts

the operation, and when the operation has exceeded the

timing limits, Q5 produces a "1".

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it returns to determine the status of the

operation.

Q3:Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data# Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

Q5:Program/Erase Timing

Q5 will indicate if the program or erase time has exceeded

the specified limits (internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data# Polling and Toggle Bit are

If Data# Polling or theToggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

P/N:PM1081

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MX29LV640BU

still open. If Q3 is high ("1") the internally controlled erase

cycle has begun;attempts to write subsequent commands

to the device will be ignored until the erase operation is

completed as indicated by Data Polling or Toggle Bit. If

Q3 is low ("0"), the device will accept additional sector

erase commands. To insure the command has been ac-

cepted, the system software should check the status of

Q3 prior to and following each subsequent sector erase

command. If Q3 were high on the second status check,

the command may not have been accepted.

If the time between additional erase commands from the

system can be less than 50us, the system need not to

monitor Q3.

RY/BY#:READY/BUSY# OUTPUT

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Embedded Algorithm is in progress

or complete. The RY/BY# status is valid after the rising

edge of the final WE# pulse in the command sequence.

Since RY/BY# is an open-drain output, several RY/BY#

pins can be tied together in parallel with a pull-up resistor

to VCC .

If the output is low (Busy), the device is actively erasing

or programming. (This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device

is ready to read array data (including during the Erase

Suspend mode), or is in the standby mode.

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MX29LV640BU

OPERATING RATINGS

ABSOLUTE MAXIMUM RATINGS

StorageTemperature

Commercial (C) Devices

Plastic Packages . . . . . . . . . . . . . ..... -65^oC to +150^oC

Ambient Temperature (T^A). . . . . . . . . . . . 0°C to +70°C

Industrial (I) Devices

AmbientTemperature

with Power Applied. . . . . . . . . . . . . .... -65^oC to +125^oC

Voltage with Respect to Ground

Ambient Temperature (T^A). . . . . . . . . . -40°C to +85° C

V^CCSupply Voltages

V^CCfor full voltage range. . . . . . . . . . . +2.7 V to 3.6 V

VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V

A9, OE#, ACC and

Operating ranges define those limits between which the

functionality of the device is guaranteed.

RESET# (Note 2) . . . . . . . . . . . ....-0.5 V to +12.5 V

All other pins (Note 1) . . . . . . . -0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is -0.5 V.

During voltage transitions, input or I/O pins may over-

shoot VSS to -2.0 V for periods of up to 20 ns. Maxi-

mum DC voltage on input or I/O pins is VCC +0.5 V.

During voltage transitions, input or I/O pins may over-

shoot to VCC +2.0 V for periods up to 20 ns.

2. Minimum DC input voltage on pins A9, OE#, and RE-

SET# is -0.5 V. During voltage transitions, A9, OE#,

and RESET# may overshootVSS to -2.0V for periods

of up to 20 ns.Maximum DC input voltage on pin A9 is

+12.5 V which may overshoot to 14.0 V for periods up

to 20 ns.

3.No more than one output may be shorted to ground at

a time. Duration of the short circuit should not be

greater than one second.

Stresses above those listed under "Absolute Maximum

Ratings" may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device at these or any other conditions above those in-

dicated in the operational sections of this data sheet is

not implied. Exposure of the device to absolute maxi-

mum rating conditions for extended periods may affect

device reliability.

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MX29LV640BU

DC CHARACTERISTICS

TA=-40°C to 85°C, VCC=2.7V~3.6V

Para-

meter Description

Test Conditions

Min

Typ

Max

Unit

I LI

Input Load Current (Note 1)

VIN = VSS to VCC ,

VCC = VCC max

±1.0

uA

I LIT

I LO

A9,ACC Input Load Current

Output Leakage Current

VCC=VCC max; A9 = 12.5V

VOUT = VSS to VCC ,

VCC= VCC max

35

uA

±1.0

ICC1 VCC Active Read Current

(Notes 2,3)

CE#= VIL,

OE# = VIH

5 MHz

1 MHz

9

2

16

4

mA

ICC2 VCC Active Write Current

(Notes 2,4,6)

CE#= V IL , OE# = V IH

26

30

ICC3 VCC Standby Current

(Note 2)

CE#,RESET#,ACC=VCC±0.3V

WP#=VIH

0.2

15

uA

ICC4 VCC Reset Current

(Note 2)

RESET=VSS±0.3V

WP#=VIH

ICC5 Automatic Sleep Mode

(Note 2,5)

VIL = V SS ±0.3 V,

VIH = VCC ±0.3 V,

ACC = VCC ±0.3 V, WP#=VIH

CE#=VIL, OE#=VIH ACC pin

VCC pin

IACC ACC Accelerated Program

Current, Word or Byte

5

10

30

mA

V

15

VIL

Input Low Voltage

Input High Voltage

-0.5

0.7xVcc

11.5

0.8

VIH

Vcc+0.3

12.5

V

VHH Voltage for ACC Program

Acceleration

VCC = 3.0 V ± 10%

V

VID

Voltage for Automatic Select

11.5

12.5

0.45

V

and Temporary Sector Unprotect

VOL Output Low Voltage

VOH1 Output High Voltage

VOH2

IOL= 4.0mA,VCC=VCC min

IOH=-2.0mA,VCC=VCC min

IOH=-100uA,VCC=VCC min

V

0.85VCC

VCC-0.4

1.5

VLKO Low VCC Lock-Out Voltage

(Note 4)

Notes:

1. On the WP# pin only, the maximum input load current when WP# = VIL is ±5.0uA.

2. Maximum ICC specifications are tested with VCC = VCC max.

3. The ICC current listed is typically is less than 2 mA/MHz, with OE# at VIH . Typical specifications are for VCC =

3.0V.

4. ICC active while Embedded Erase or Embedded Program is in progress.

5. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns.Typical sleep

mode current is 200 nA.

6. Not 100% tested.

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MX29LV640BU

SWITCHINGTEST CIRCUITS

TEST SPECIFICATIONS

Test Condition

Output Load

90

1TTL gate

100

120

Unit

pF

DEVICE UNDER

TEST

2.7K ohm

Output Load Capacitance, CL 30

(including jig capacitance)

Input Rise and Fall Times

Input Pulse Levels

3.3V

5

ns

V

0.0-3.0

1.5

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

Input timing measurement

reference levels

V

Output timing measurement

reference levels

1.5

V

KEYTO SWITCHINGWAVEFORMS

WAVEFORM

INPUTS

OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don't Care, Any Change Permitted

Does Not Apply

Changing, State Unknown

Center Line is High Impedance State (High Z)

SWITCHINGTEST WAVEFORMS

3.0V

0.0V

Measurement Level

1.5V

INPUT

OUTPUT

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MX29LV640BU

AC CHARACTERISTICS

Read-Only Operations

Parameter

Speed Options

Std.

tRC

tACC

tCE

tOE

tDF

Description

Test Setup

90

35

30

120 Unit

Read CycleTime (Note 1)

Min

CE#, OE#=VIL Max

120

50

ns

Address to Output Delay

Chip Enable to Output Delay

Output Enable to Output Delay

Chip Enable to Output High Z (Note 1)

Output Enable to Output High Z (Note 1)

Output HoldTime From Address, CE#

or OE#, whichever Occurs First

Read

OE#=VIL

Max

Min

30

tDF

30

tOH

0

Min

0

ns

tOEH

Output Enable HoldTime Toggle and

10

(Note 1)

Data# Polling

Notes:

1. Not 100% tested.

2. See SWITCHING TEST CIRCUITS and TEST SPECIFICATIONS TABLE for test specifications.

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MX29LV640BU

Figure 1. COMMAND WRITE OPERATION

VCC

3V

VIH

Addresses

ADD Valid

VIL

tAH

tAS

VIH

WE#

VIL

tWPH

tWP

tCWC

VIH

CE#

VIL

tCS

tCH

tDH

VIH

OE#

VIL

tDS

VIH

VIL

Data

DIN

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MX29LV640BU

READ/RESET OPERATION

Figure 2. READ TIMING WAVEFORMS

tRC

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE#

tRH

VIL

tRH

VIH

WE#

tDF

VIL

VIH

VIL

tOEH

tOE

OE#

tOH

tACC

HIGH Z

VOH

VOL

Outputs

DATA Valid

VIH

VIL

RESET#

RY/BY#

0V

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MX29LV640BU

AC CHARACTERISTICS

Parameter

Description

Test Setup All Speed Options Unit

tREADY1

RESET# PIN Low (During Automatic Algorithms)

to Read or Write (See Note)

MAX

20

us

tREADY2

RESET# PIN Low (NOT During Automatic

Algorithms) to Read or Write (See Note)

MAX

500

ns

tRP

RESET# Pulse Width (NOT During Automatic Algorithms) MIN

500

50

0

ns

us

tRH

RESET# HighTime Before Read (See Note)

RY/BY# Recovery Time (to CE#, OE# go low)

RESET# Low to Standby Mode

MIN

tRB

tRPD

20

Note:Not 100% tested

Figure 3. RESET# TIMING WAVEFORM

RY/BY#

CE#, OE#

tRH

RESET#

tRP

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY#

tRB

CE#, OE#

RESET#

tRP

Reset Timing during Automatic Algorithms

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MX29LV640BU

ERASE/PROGRAM OPERATION

Figure 4. AUTOMATIC CHIP/SECTOR ERASE TIMING WAVEFORM

Erase Command Sequence(last two cycle)

Read Status Data

VA

tWC

tAS

VA

2AAh

SA

Address

CE#

555h for chip erase

tAH

tCH

OE#

WE#

tWHWH2

tWP

tCS

tWPH

tDS tDH

In

Progress

55h

30h

Complete

Data

10 for Chip Erase

tBUSY

tRB

RY/BY#

tVCS

VCC

NOTES:

1.SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").

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MX29LV640BU

Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

Data Poll

from system

YES

No

DATA = FFh ?

YES

Auto Erase Completed

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MX29LV640BU

Figure 6. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Last Sector

to Erase ?

YES

Data Poll from System

NO

Data=FFh?

YES

Auto Sector Erase Completed

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MX29LV640BU

Figure 7. ERASE SUSPEND/RESUME FLOWCHART

START

Write Data B0H

ERASE SUSPEND

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Continue Erase

ERASE RESUME

Another

NO

Erase Suspend ?

YES

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MX29LV640BU

Figure 8. SECURED SILICON SECTOR PROTECTED ALGORITHMS FLOWCHART

START

Enter Secured Silicon Sector

Wait 1us

First Wait Cycle Data=60h

Second Wait Cycle Data=60h

A6=0, A1=1, A0=0

Wait 300us

No

Data = 01h ?

Yes

Device Failed

Write Reset Command

Secured Sector Protect Complete

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MX29LV640BU

AC CHARACTERISTICS

Erase and Program Operations

Parameter

Speed Options

Std.

tWC

tCWC

tAS

Description

90

120

Unit

ns

Write CycleTime (Note 1)

CommandWrite CycleTime (Note 1)

Address SetupTime

Min

ns

0

ns

tASO

tAH

Address SetupTime to OE# low during toggle bit polling

Address HoldTime

15

ns

45

50

ns

tAHT

Address HoldTime From CE# or OE# high during toggle

bit polling

0

ns

tDS

Data SetupTime

Min

ns

tDH

Data HoldTime

0

20

0

tOEPH

tGHWL

Output Enable High during toggle bit polling

Read RecoveryTime Before Write

(OE# High to WE# Low)

tGHEL

tCS

Read RecoveryTime Before Write

CE# SetupTime

Min

Typ

Min

0

ns

us

sec

ns

us

ns

tCH

CE# HoldTime

tWP

Write Pulse Width

35

50

tWPH

tWHWH1

tWHWH2

tVHH

tVCS

tRB

Write PulseWidth High

30

11

1.6

250

50

0

Word Programming Operation (Note 2)

Sector Erase Operation (Note 2)

VHH Rise and FallTime (Note 1)

VCC SetupTime (Note 1)

Write RecoveryTime from RY/BY#

Program/EraseValid to RY/BY# Delay

tBUSY

90

Notes:

1. Not 100% tested.

2. See the "Erase And Programming Performance" section for more information.

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MX29LV640BU

Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS

Program Command Sequence(last two cycle)

Read Status Data (last two cycle)

tWC

tAS

PA

555h

PA

Address

CE#

tAH

tCH

tGHWL

OE#

WE#

tWHWH1

tWP

tCS

tWPH

tDS tDH

Status

A0h

PD

DOUT

Data

tBUSY

tRB

RY/BY#

tVCS

VCC

NOTES:

1.PA=Program Address, PD=Program Data, DOUT is the true data the program address

Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM

VHH

ACC

VIL or VIH

tVHH

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MX29LV640BU

AC CHARACTERISTICS

Alternate CE# Controlled Erase and Program Operations

Parameter

Speed Options

Std.

tWC

tAS

Description

90

120 Unit

Write Cycle Time (Note 1)

Address SetupTime

Address HoldTime

Min

90

120

ns

0

tAH

45

50

tDS

Data SetupTime

tDH

Data HoldTime

0

tGHEL

Read RecoveryTime BeforeWrite

(OE# High to WE# Low)

WE# SetupTime

tWS

Min

Typ

0

ns

tWH

WE# HoldTime

tCP

CE# PulseWidth

45

50

ns

tCPH

CE# Pulse Width High

Word Programming Operation (Note 2)

Sector Erase Operation (Note 2)

30

11

ns

tWHWH1

tWHWH2

us

1.6

sec

Notes:

1. Not 100% tested.

2. See the "Erase And Programming Performance" section for more information.

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MX29LV640BU

Figure 11. CE# CONTROLLED PROGRAM TIMING WAVEFORM

PA for program

555 for program

2AA for erase

SA for sector erase

555 for chip erase

Data# Polling

Address

PA

tWC

tWH

tAS

tAH

WE#

OE#

tGHEL

tCP

tWHWH1 or 2

CE#

Data

tWS

tDS

tCPH

tBUSY

tDH

DOUT

Q7

PD for program

30 for sector erase

10 for chip erase

A0 for program

55 for erase

tRH

RESET #

RY/BY#

NOTES:

1.PA=Program Address, PD=Program Data, DOUT=Data Out, Q7=complement of data written to device.

2.Figure indicates the last two bus cycles of the command sequence.

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MX29LV640BU

Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

Data Poll

Increment

Address

from system

No

Verify Word Ok ?

YES

Last Address ?

YES

Auto Program Completed

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MX29LV640BU

SECTOR GROUP PROTECT/CHIP UNPROTECT

Figure 13. Sector Group Protect / Chip Unprotect Waveform (RESET# Control)

VID

VIH

RESET#

SA, A6

A1, A0

Valid*

Sector Group Protect or Chip Unprotect

Verify

40h

Status

Data

60h

Sector Group Protect:150us

Chip Unprotect:15ms

1us

CE#

WE#

OE#

Note: For sector group protect A6=0, A1=1, A0=0. For sector group unprotect A6=1, A1=1, A0=0

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MX29LV640BU

Figure 14. IN-SYSTEM SECTOR GROUP PROTECT/CHIP UNPROTECT ALGORITHMS WITH

RESET#=VID

START

Protect all sectors:

PLSCNT=1

The indicated portion of

PLSCNT=1

the sector protect algorithm

must be performed

RESET#=VID

for all unprotected sectors

RESET#=VID

prior to issuing the first

sector unprotect address

Wait 1us

No

First Write

Temporary Sector

Unprotect Mode

Cycle=60h?

First Write

No

Temporary Sector

Unprotect Mode

Cycle=60h?

Yes

Set up sector address

No

All sectors

protected?

Sector Protect:

Write 60h to sector

address with

A6=0, A1=1, A0=0

Yes

Set up first sector address

Wait 150us

Chip Unprotect:

Write 60h to sector

address with

Verify Sector Protect:

Write 40h to sector

address with

Reset

PLSCNT=1

A6=1, A1=1, A0=0

A6=0, A1=1, A0=0

Increment PLSCNT

Wait 15 ms

Read from

sector address

with

A6=0, A1=1, A0=0

Verify Chip Unprotect:

Write 40h to sector

address with

No

Increment PLSCNT

A6=1, A1=1, A0=0

No

Data=01h?

Yes

PLSCNT=25?

Read from

sector address

with

Yes

A6=1, A1=1, A0=0

No

Device failed

Reset

Yes

Protect another

sector?

PLSCNT=1

No

PLSCNT=1000?

Data=00h?

Yes

No

Sector Protect

Algorithm

Yes

Remove VID from RESET#

Device failed

No

Last sector

verified?

Write reset command

Yes

Chip Unprotect

Algorithm

Sector Protect complete

Remove VID from RESET#

Write reset command

Chip Unprotect complete

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MX29LV640BU

AC CHARACTERISTICS

Parameter

tVLHT

Description

Test Setup

Min.

All Speed Options Unit

Voltage transition time

4

us

ns

us

tWPP1

tWPP2

tOESP

Write pulse width for sector group protect

Write pulse width for chip unprotect

OE# setup time to WE# active

Min.

100

4

Min.

Figure 15. SECTOR GROUP PROTECT TIMING WAVEFORM (A9, OE# Control)

A1

A6

12V

3V

A9

tVLHT

Verify

12V

3V

OE#

tVLHT

tWPP 1

WE#

tOESP

CE#

Data

01H

F0H

tOE

Sector Address

A21-A16

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MX29LV640BU

Figure 16. SECTOR GROUP PROTECTION ALGORITHM (A9, OE# Control)

START

Set Up Sector Addr

PLSCNT=1

OE#=VID, A9=VID, CE#=VIL

A6=VIL

Activate WE# Pulse

Time Out 150us

Set WE#=VIH, CE#=OE#=VIL

A9 should remain VID

.

Read from Sector

Addr=SA, A1=1

No

Data=01H?

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector?

Remove VID from A9

Write Reset Command

Sector Protection

Complete

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MX29LV640BU

Figure 17. CHIP UNPROTECT TIMING WAVEFORM (A9, OE# Control)

A1

12V

3V

A9

A6

tVLHT

Verify

12V

3V

OE#

tVLHT

tWPP 2

WE#

CE#

tOESP

Data

00H

F0H

tOE

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MX29LV640BU

Figure 18. CHIP UNPROTECT FLOWCHART (A9, OE# Control)

START

Protect All Sectors

PLSCNT=1

Set OE#=A9=VID

CE#=VIL,A6=1

Activate WE# Pulse

Time Out 15ms

Increment

PLSCNT

Set OE#=CE#=VIL

A9=VID,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

PLSCNT=1000?

Increment

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Remove VID from A9

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

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MX29LV640BU

AC CHARACTERISTICS

Parameter Description

Test

Setup

Min

All Speed Options Unit

tVIDR

tRSP

tRRB

VID Rise and Fall Time (see Note)

500

4

ns

us

RESET# SetupTime forTemporary Sector Unprotect

RESET# HoldTime from RY/BY# High forTemporary

Sector Group Unprotect

Min

4

Figure 19. TEMPORARY SECTOR GROUP UNPROTECTED WAVEFORMS

12V

RESET#

0 or 3V

VIL or VIH

tVIDR

Program or Erase Command Sequence

CE#

WE#

tRSP

tRRB

RY/BY#

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MX29LV640BU

Figure 20. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART

Start

RESET# = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET# = VIH

Temporary Sector Unprotect Completed(Note 2)

Note :

1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

2. All previously protected sectors are protected again.

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MX29LV640BU

Figure 21. SILICON ID READ TIMING WAVEFORM

VCC

3V

VID

ADD

A9

VIH

VIL

VIH

VIL

ADD

A0

tACC

VIH

VIL

A1

VIH

VIL

ADD

CE#

VIH

VIL

VIH

VIL

tCE

WE#

OE#

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q15

DATA OUT

00C2H

DATA OUT

22D7

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MX29LV640BU

WRITE OPERATION STATUS

Figure 22. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE#

tACC

tCE

tCH

tOE

OE#

WE#

tOEH

tDF

tOH

High Z

Complement

Status Data

True

Valid Data

Q7

Q0-Q6

True

tBUSY

RY/BY#

NOTES:

VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data raed cycle.

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MX29LV640BU

Figure 23. Data# Polling Algorithm

Start

Read Q7~Q0

Add.=VA(1)

Yes

Q7 = Data ?

No

Q5 = 1 ?

Yes

Read Q7~Q0

Add.=VA

Yes

Q7 = Data ?

(2)

No

FAIL

Pass

Notes:

1.VA=valid address for programming.

2.Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.

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MX29LV640BU

Figure 24. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)

tRC

VA

Address

CE#

tACC

tCE

tCH

tOE

OE#

tOEH

tDF

WE#

tOH

tDH

Valid Status

(second read)

Valid Status

(first read)

Valid Data

Q6/Q2

Valid Status

(stops toggling)

RY/BY#

NOTES:

VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle, and

array data read cycle.

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MX29LV640BU

Figure 25. Toggle Bit Algorithm

START

Read Q7~Q0

(Note 1)

NO

Toggle Bit Q6

=Toggle?

YES

NO

Q5=1?

YES

(Note 1,2)

Read Q7~Q0 Twice

Toggle Bit Q6=

Toggle?

YES

Program/Erase Operation Not

Program/Erase Operation Complete

Complete, Write Reset Command

Note:

1. Read toggle bit twice to determine whether or not it is toggling.

2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".

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MX29LV640BU

Figure 26. Q6 versus Q2

Enter Embedded

Erasing

Erase

Enter Erase

Erase

Suspend

Suspend Program

Resume

Erase

Erase Suspend

Read

Erase

Erase Suspend

Read

Erase

WE#

Q6

Suspend

Program

Complete

Q2

NOTES:

The system can use OE# or CE# to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended

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MX29LV640BU

ERASE AND PROGRAMMING PERFORMANCE (1)

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.

15

UNITS

sec

Sector Erase Time

0.9

45

11

7

Chip Erase Time

65

sec

Word Programming Time

Accelerated Word Program Time

Chip Programming Time

Erase/Program Cycles

300

210

140

us

45

sec

100,000

Cycles

Note: 1. Not 100% Tested, Excludes external system level over head.

2.Typical program and erase times assume the following condition= 25° C,3.0V VCC.

Additionally, programming typicals assume checkerboard pattern.

LATCH-UP CHARACTERISTICS

MIN.

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

-1.0V

13.5V

Vcc + 1.0V

+100mA

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 3.0V, one pin at a time.

TSOP PIN CAPACITANCE

Parameter Symbol

Parameter Description

Input Capacitance

Test Set

VIN=0

TYP

MAX

7.5

12

UNIT

pF

CIN

6

COUT

CIN2

Output Capacitance

Control Pin Capacitance

VOUT=0

VIN=0

8.5

7.5

pF

9

pF

Notes:

1. Sampled, not 100% tested.

2.Test conditionsTA=25° C, f=1.0MHz

DATA RETENTION

Parameter

Test Conditions

Min

10

Unit

Minimum Pattern Data Retention Time

150

125

Years

20

P/N:PM1081

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59

MX29LV640BU

ORDERING INFORMATION

PLASTIC PACKAGE

PART NO.

ACCESS TIME

Ball Pitch/

Ball size

PACKAGE

Remark

(ns)

MX29LV640BUTC-90

MX29LV640BUTC-12

MX29LV640BUTI-90

MX29LV640BUTI-12

90

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

63 Ball CSP

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

48 Pin TSOP

(Normal Type)

63 Ball CSP

Commercialgrade

Industrial grade

120

90

120

MX29LV640BUXBC-90

MX29LV640BUXBC-12

MX29LV640BUXBI-90

MX29LV640BUXBI-12

MX29LV640BUTC-90G

90

120

90

0.8mm/0.3mm

Commercialgrade

Industrial grade

Commercialgrade

Pb-free

120

90

MX29LV640BUTC-12G

MX29LV640BUTI-90G

MX29LV640BUTI-12G

MX29LV640BUXBC-90G

MX29LV640BUXBC-12G

MX29LV640BUXBI-90G

MX29LV640BUXBI-12G

120

90

Commercialgrade

Pb-free

Industrial grade

Pb-free

120

90

Industrial grade

Pb-free

0.8mm/0.3mm

Commercialgrade

Pb-free

120

90

63 Ball CSP

Commercialgrade

Pb-free

Industrial grade

Pb-free

120

Industrial grade

Pb-free

P/N:PM1081

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MX29LV640BU

PACKAGE INFORMATION

P/N:PM1081

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MX29LV640BU

P/N:PM1081

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MX29LV640BU

REVISION HISTORY

Revision No. Description

Page

Date

1.0

1. Removed "Preliminary"

P1

MAR/08/2005

P/N:PM1081

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63

MX29LV640BU

MACRONIX INTERNATIONALCO., LTD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.


型号：	MX29LV640BUTI-90
厂家：	MACRONIX INTERNATIONAL
描述：	64M-BIT [4M x 16] CMOS EQUAL SECTOR FLASH MEMORY 64M - BIT [ 4M ×16 ]的CMOS EQUAL部门FLASH MEMORY
文件：	总64页 (文件大小：493K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX29LV640BUTI-90 [Macronix]

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