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MX29SL800CTXHI-90 [Macronix]

8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 1.8V ONLY FLASH MEMORY; 8M - BIT [ 1Mx8 / 512K X16 ] CMOS单电压仅1.8V闪存
MX29SL800CTXHI-90
型号： MX29SL800CTXHI-90
厂家： MACRONIX INTERNATIONAL    MACRONIX INTERNATIONAL
描述：

8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE 1.8V ONLY FLASH MEMORY
8M - BIT [ 1Mx8 / 512K X16 ] CMOS单电压仅1.8V闪存

闪存 存储 内存集成电路
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中文：  中文翻译
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MX29SL800C T/B  
8M-BIT [1Mx8/512K x16] CMOS SINGLE VOLTAGE  
1.8V ONLY FLASH MEMORY  
FEATURES  
• Ready/Busy# pin (RY/BY#)  
• Extendedsingle-supplyvoltagerange1.65Vto2.2V  
• 1,048,576 x 8/524,288 x 16 switchable  
• Singlepowersupplyoperation  
- 1.8V only operation for read, erase and program  
operation  
• Fast access time: 90ns  
-Providesahardwaremethodofdetectingprogramor  
eraseoperationcompletion  
• Hardwareresetpin(RESET#)  
-Hardwaremethodtoresetthedevicetoreadingarray  
data  
• Sectorprotection  
• Lowpowerconsumption  
- Hardware method to disable any combination of  
sectors from program or erase operations  
-Temporarysectorunprotectedallowscodechanges  
in previously locked sectors  
- 12mA maximum active current (10MHz)  
- 1uA typical standby current  
• Commandregisterarchitecture  
- Byte/word Programming (12us/18us typical)  
- Sector Erase (Sector structure 16K-Bytex1,  
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)  
• Auto Erase (chip & sector) and Auto Program  
-Automaticallyeraseanycombinationofsectorswith  
Erase Suspend capability.  
• CFI (Common Flash Interface) compliant  
- Flash device parameters stored on the device and  
provide the host system to access  
• 100,000minimumerase/programcycles  
• Latch-up protected to 100mA from -1V to VCC+1V  
• Boot Sector Architecture  
- T = Top Boot Sector  
- B = Bottom Boot Sector  
• Package type:  
- Automatically program and verify data at specified  
address  
• Erasesuspend/EraseResume  
- Suspends sector erase operation to read data from,  
orprogramdatato,any sectorthatisnotbeingerased,  
then resumes the erase  
- 48-pin TSOP  
- 48-ball CSP  
- All Pb-free devices are RoHS Compliant  
• Compatibility with JEDEC standard  
- Pinout and software compatible with single-power  
supply Flash  
• Status Reply  
- Data# polling & Toggle bit for detection of program  
anderaseoperationcompletion  
• 10 years data retention  
GENERAL DESCRIPTION  
The MX29SL800C T/B is a 8-mega bit Flash memory  
organized as 1M bytes of 8 bits or 512K words of 16 bits.  
MXIC's Flash memories offer the most cost-effective and  
reliable read/write non-volatile random access memory.  
The MX29SL800CT/B is packaged in 48-pinTSOP and  
48-ball CSP. It is designed to be reprogrammed and  
erased in system or in standard EPROM programmers.  
TTL level control inputs and fixed power supply levels  
during erase and programming, while maintaining maxi-  
mum EPROM compatibility.  
MXIC Flash technology reliably stores memory contents  
even after 100,000 erase and program cycles. The MXIC  
cell is designed to optimize the erase and programming  
mechanisms. In addition, the combination of advanced  
tunnel oxide processing and low internal electric fields  
for erase and program operations produces reliable cy-  
cling. The MX29SL800C T/B uses a 1.65V~2.2V VCC  
supply to perform the High Reliability Erase and auto  
Program/Erase algorithms.  
The standard MX29SL800C T/B offers access time as  
fast as 90ns, allowing operation of high-speed micropro-  
cessors without wait states. To eliminate bus conten-  
tion, the MX29SL800C T/B has separate chip enable  
(CE#) and output enable (OE#) controls.  
MXIC's Flash memories augment EPROM functionality  
with in-circuit electrical erasure and programming. The  
MX29SL800CT/B uses a command register to manage  
this functionality. The command register allows for 100%  
The highest degree of latch-up protection is achieved  
with MXIC's proprietary non-epi process. Latch-up pro-  
tection is proved for stresses up to 100 milliamperes on  
address and data pin from -1V to VCC + 1V.  
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MX29SL800C T/B  
PIN CONFIGURATIONS  
PIN DESCRIPTION  
SYMBOL PIN NAME  
48 TSOP (Standard Type) (12mm x 20mm)  
A0~A18  
Address Input  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
A16  
BYTE#  
GND  
Q15/A-1  
Q7  
2
Q0~Q14 Data Input/Output  
3
4
Q15/A-1  
Q15 (data input/output, word mode)/  
5
6
Q14  
Q6  
A-1(LSB address input, byte mode)  
Chip Enable Input  
7
A8  
8
Q13  
Q5  
CE#  
NC  
9
NC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Q12  
Q4  
WE#  
Write Enable Input  
WE#  
RESET#  
NC  
VCC  
Q11  
Q3  
MX29SL800C T/B  
BYTE#  
Word/Byte Selection input  
NC  
RESET# Hardware Reset Pin  
RY/BY#  
A18  
A17  
A7  
Q10  
Q2  
OE#  
Output Enable Input  
Ready/Busy Output  
Power Supply Pin (1.65V~2.2V)  
Ground Pin  
Q9  
Q1  
RY/BY#  
VCC  
A6  
Q8  
A5  
Q0  
A4  
OE#  
GND  
CE#  
A0  
A3  
A2  
GND  
A1  
48-Ball CSP( Ball Pitch = 0.5 mm),Top View, Balls Facing Down  
6
5
4
3
2
1
A2  
A1  
A0  
A4  
A3  
A5  
A6  
A7  
A17  
NC  
NC  
NC  
WE#  
NC  
NC  
A9  
A10  
A8  
A11  
A13  
A12  
A14  
A15  
A18  
CE#  
Q8  
OE#  
Q0  
Q10  
Q9  
Q4  
Q5  
Q11  
Q6  
A16  
Q7  
GND  
NC  
Q2  
NC  
Q1  
Q3  
VCC  
Q12  
Q13  
Q14  
Q15  
GND  
A
B
C
D
E
F
G
H
J
K
L
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MX29SL800C T/B  
48-Ball CSP( Ball Pitch = 0.8 mm),Top View, Balls Facing Down  
Q15/  
A-1  
6
5
4
3
2
1
A13  
A9  
A12  
A8  
A14  
A10  
A15  
A11  
A16  
Q7  
BYTE#  
Q14  
GND  
Q6  
Q13  
RE-  
SET#  
WE#  
NC  
NC  
Q5  
Q12  
VCC  
Q4  
RY/BY#  
A7  
NC  
A17  
A4  
A18  
A6  
NC  
A5  
A1  
Q2  
Q0  
A0  
Q10  
Q8  
Q11  
Q9  
Q3  
Q1  
A3  
A2  
CE#  
OE#  
GND  
A
B
C
D
E
F
G
H
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MX29SL800C T/B  
BLOCK STRUCTURE  
TABLE 1: MX29SL800CT SECTOR ARCHITECTURE  
Sector  
Sector Size  
Address range  
Sector Address  
Byte Mode Word Mode Byte Mode (x8)  
Word Mode (x16) A18 A17 A16 A15 A14 A13 A12  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
00000h-0FFFFh  
10000h-1FFFFh  
20000h-2FFFFh  
30000h-3FFFFh  
40000h-4FFFFh  
50000h-5FFFFh  
60000h-6FFFFh  
70000h-7FFFFh  
80000h-8FFFFh  
90000h-9FFFFh  
A0000h-AFFFFh  
B0000h-BFFFFh  
C0000h-CFFFFh  
D0000h-DFFFFh  
E0000h-EFFFFh  
F0000h-F7FFFh  
F8000h-F9FFFh  
FA000h-FBFFFh  
FC000h-FFFFFh  
00000h-07FFFh  
08000h-0FFFFh  
10000h-17FFFh  
18000h-1FFFFh  
20000h-27FFFh  
28000h-2FFFFh  
30000h-37FFFh  
38000h-3FFFFh  
40000h-47FFFh  
48000h-4FFFFh  
50000h-57FFFh  
58000h-5FFFFh  
60000h-67FFFh  
68000h-6FFFFh  
70000h-77FFFh  
78000h-7BFFFh  
7C000h-7CFFFh  
7D000h-7DFFFh  
7E000h-7FFFFh  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
SA10 64Kbytes 32Kwords  
SA11 64Kbytes 32Kwords  
SA12 64Kbytes 32Kwords  
SA13 64Kbytes 32Kwords  
SA14 64Kbytes 32Kwords  
SA15 32Kbytes 16Kwords  
SA16  
SA17  
8Kbytes  
8Kbytes  
4Kwords  
4Kwords  
8Kwords  
1
1
0
1
SA18 16Kbytes  
1
1
X
Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.  
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MX29SL800C T/B  
TABLE 2: MX29SL800CB SECTOR ARCHITECTURE  
Sector  
Sector Size  
Address range  
Sector Address  
Byte Mode Word Mode Byte Mode (x8)  
Word Mode (x16) A18 A17 A16 A15 A14 A13 A12  
SA0  
SA1  
SA2  
SA3  
SA4  
SA5  
SA6  
SA7  
SA8  
SA9  
16Kbytes  
8Kbytes  
8Kbytes  
8Kwords  
4Kwords  
4Kwords  
00000h-03FFFh  
04000h-05FFFh  
06000h-07FFFh  
08000h-0FFFFh  
10000h-1FFFFh  
20000h-2FFFFh  
30000h-3FFFFh  
40000h-4FFFFh  
50000h-5FFFFh  
60000h-6FFFFh  
70000h-7FFFFh  
80000h-8FFFFh  
90000h-9FFFFh  
A0000h-AFFFFh  
B0000h-BFFFFh  
C0000h-CFFFFh  
D0000h-DFFFFh  
E0000h-EFFFFh  
F0000h-FFFFFh  
00000h-01FFFh  
02000h-02FFFh  
03000h-03FFFh  
04000h-07FFFh  
08000h-0FFFFh  
10000h-17FFFh  
18000h-1FFFFh  
20000h-27FFFh  
28000h-2FFFFh  
30000h-37FFFh  
38000h-3FFFFh  
40000h-47FFFh  
48000h-4FFFFh  
50000h-57FFFh  
58000h-5FFFFh  
60000h-67FFFh  
68000h-6FFFFh  
70000h-77FFFh  
78000h-7FFFFh  
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
1
X
0
0
1
1
32Kbytes 16Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
64Kbytes 32Kwords  
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SA10 64Kbytes 32Kwords  
SA11 64Kbytes 32Kwords  
SA12 64Kbytes 32Kwords  
SA13 64Kbytes 32Kwords  
SA14 64Kbytes 32Kwords  
SA15 64Kbytes 32Kwords  
SA16 64Kbytes 32Kwords  
SA17 64Kbytes 32Kwords  
SA18 64Kbytes 32Kwords  
Note: Byte mode:address range A18:A-1, word mode:address range A18:A0.  
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MX29SL800C T/B  
BLOCK DIAGRAM  
WRITE  
CE#  
OE#  
WE#  
CONTROL  
INPUT  
PROGRAM/ERASE  
STATE  
MACHINE  
(WSM)  
HIGH VOLTAGE  
LOGIC  
RESET#  
STATE  
REGISTER  
FLASH  
ARRAY  
ADDRESS  
LATCH  
ARRAY  
A0-A18  
SOURCE  
HV  
AND  
COMMAND  
DATA  
BUFFER  
Y-PASS GATE  
DECODER  
PGM  
SENSE  
DATA  
COMMAND  
DATA LATCH  
AMPLIFIER  
HV  
PROGRAM  
DATA LATCH  
I/O BUFFER  
Q0-Q15/A-1  
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MX29SL800C T/B  
write commands to the command register using stan-  
dard microprocessor write timings. The device will auto-  
matically pre-program and verify the entire array. Then  
the device automatically times the erase pulse width,  
provides the erase verification, and counts the number  
of sequences. A status bit toggling between consecu-  
tive read cycles provides feedback to the user as to the  
status of the erasing operation.  
AUTOMATIC PROGRAMMING  
The MX29SL800CT/B is byte programmable using the  
Automatic Programming algorithm. The Automatic Pro-  
gramming algorithm makes the external system do not  
need to have time out sequence nor to verify the data  
programmed. The typical chip programming time at room  
temperature of the MX29SL800C T/B is less than 9.6  
seconds.  
Register contents serve as inputs to an internal state-  
machine which controls the erase and programming cir-  
cuitry. During write cycles, the command register inter-  
nally latches address and data needed for the program-  
ming and erase operations. During a system write cycle,  
addresses are latched on the falling edge of WE# or  
CE#, whichever happens last, and data are latched on  
the rising edge of WE# or CE#, whichever happens first.  
AUTOMATIC PROGRAMMING ALGORITHM  
MXIC's Automatic Programming algorithm requires the  
user to only write program set-up commands (including  
2 unlock write cycle and A0H) and a program command  
(program data and address). The device automatically  
times the programming pulse width, provides the pro-  
gram verification, and counts the number of sequences.  
A status bit similar to DATA# polling and a status bit  
toggling between consecutive read cycles, provide feed-  
back to the user as to the status of the programming  
operation.Refer to write operation status, table 8, for more  
information on these status bits.  
MXIC's Flash technology combines years of EPROM  
experience to produce the highest levels of quality, reli-  
ability, and cost effectiveness. The MX29SL800C T/B  
electrically erases all bits simultaneously using Fowler-  
Nordheim tunneling. The bytes are programmed by us-  
ing the EPROM programming mechanism of hot elec-  
tron injection.  
During a program cycle, the state-machine will control  
the program sequences and command register will not  
respond to any command set. During a Sector Erase  
cycle, the command register will only respond to Erase  
Suspend command. After Erase Suspend is completed,  
the device stays in read mode. After the state machine  
has completed its task, it will allow the command regis-  
ter to respond to its full command set.  
AUTOMATIC CHIP ERASE  
The entire chip is bulk erased using 10 ms erase pulses  
according to MXIC's Automatic Chip Erase algorithm.  
Typical erasure at room temperature is accomplished in  
less than 14 second. The Automatic Erase algorithm  
automatically programs the entire array prior to electrical  
erase. The timing and verification of electrical erase are  
controlled internally within the device.  
AUTOMATIC SELECT  
AUTOMATIC SECTOR ERASE  
The auto select mode provides manufacturer and de-  
vice identification, and sector protection verification,  
through identifier codes output on Q7~Q0.This mode is  
mainly adapted for programming equipment on the de-  
vice to be programmed with its programming algorithm.  
When programming by high voltage method, automatic  
select mode requires VID (10V to 11V) on address pin  
A9 and other address pin A6, A1 and A0 as referring to  
Table 3.In addition, to access the automatic select codes  
in-system, the host can issue the automatic select com-  
mand through the command register without requiringVID,  
as shown in table 5.  
The MX29SL800CT/B is sector(s) erasable using MXIC's  
Auto Sector Erase algorithm. The Automatic Sector  
Erase algorithm automatically programs the specified  
sector(s) prior to electrical erase. The timing and verifi-  
cation of electrical erase are controlled internally within  
the device. An erase operation can erase one sector,  
multiple sectors, or the entire device.  
AUTOMATIC ERASE ALGORITHM  
MXIC's Automatic Erase algorithm requires the user to  
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MX29SL800C T/B  
To verify whether or not sector being protected, the sec-  
tor address must appear on the appropriate highest order  
address bit (seeTable 1 andTable 2).The rest of address  
bits, as shown in table 3, are don't care. Once all neces-  
sary bits have been set as required, the programming  
equipment may read the corresponding identifier code on  
Q7~Q0.  
TABLE 3. MX29SL800C T/B AUTO SELECT MODE OPERATION  
A18 A11 A9 A8 A6 A5 A1 A0  
Description  
Mode CE# OE# WE#  
|
|
|
A7  
X
|
A2  
X
Q15~Q0  
A12 A10  
Manufacturer Code  
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
VID  
VID  
VID  
VID  
VID  
L
L
L
L
L
L
L
L
L
L
L
C2H  
22EAH  
Read Device ID  
Word  
Byte  
Word  
X
X
H
H
H
H
Silicon (Top Boot Block)  
X
X
XXEAH  
226BH  
ID  
Device ID  
X
X
(Bottom Boot Block) Byte  
X
X
XX6BH  
XX01H  
Sector Protection  
Verification  
L
L
H
SA  
X
VID  
X
L
X
H
L
(protected)  
XX00H  
(unprotected)  
NOTE:SA=Sector Address, X=Don't Care, L=Logic Low, H=Logic High  
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MX29SL800C T/B  
QUERY COMMAND AND COMMON FLASH  
INTERFACE (CFI) MODE  
The single cycle Query command is valid only when the  
device is in the Read mode, including Erase Suspend,  
Standby mode, and Read ID mode; however, it is ig-  
nored otherwise.  
MX29SL800CT/B is capable of operating in the CFI mode.  
This mode all the host system to determine the manu-  
facturer of the device such as operating parameters and  
configuration.Two commands are required in CFI mode.  
Query command of CFI mode is placed first, then the  
Reset command exits CFI mode.These are described in  
Table 6.  
The Reset command exits from the CFI mode to the  
Read mode, or Erase Suspend mode.The command is  
valid only when the device is in the CFI mode.  
TABLE 4-1. CFI mode: Identification Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
Address  
Data  
(ByteMode)  
(WordMode)  
Query-unique ASCII string "QRY"  
20  
22  
24  
26  
28  
2A  
2C  
2E  
30  
32  
34  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
1A  
0051  
0052  
0059  
0002  
0000  
0040  
0000  
0000  
0000  
0000  
0000  
Primary vendor command set and control interface ID code  
Address for primary algorithm extended query table  
Alternate vendor command set and control interface ID code (none)  
Address for secondary algorithm extended query table (none)  
TABLE 4-2. CFI Mode: System Interface Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
Address  
Data  
(ByteMode)  
(WordMode)  
VCC supply, minimum (1.65V)  
36  
38  
3A  
3C  
3E  
40  
42  
44  
46  
48  
4A  
4C  
1B  
1C  
1D  
1E  
1F  
20  
21  
22  
23  
24  
25  
26  
0016  
0022  
0000  
0000  
0004  
0000  
000A  
0000  
0005  
0000  
0004  
0000  
VCC supply, maximum (2.2V)  
VPP supply, minimum (none)  
VPP supply, maximum (none)  
Typical timeout for single word/byte write (2N us)  
Typical timeout for Minimum size buffer write (2N us)  
Typical timeout for individual block erase (2N ms)  
Typical timeout for full chip erase (2N ms)  
Maximum timeout for single word/byte write times (2N X Typ)  
Maximum timeout for buffer write times (2N X Typ)  
Maximum timeout for individual block erase times (2N X Typ)  
Maximum timeout for full chip erase times (not supported)  
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MX29SL800C T/B  
TABLE 4-3. CFI Mode: Device Geometry Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
Address  
Data  
(ByteMode)  
(WordMode)  
Device size (2N bytes)  
4E  
50  
52  
54  
56  
58  
5A  
5C  
5E  
60  
62  
64  
66  
68  
6A  
6C  
6E  
70  
72  
74  
76  
78  
27  
28  
29  
2A  
2B  
2C  
2D  
2E  
2F  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
3A  
3B  
3C  
0014  
0002  
0000  
0000  
0000  
0004  
0000  
0000  
0040  
0000  
0001  
0000  
0020  
0000  
0000  
0000  
0080  
0000  
000E  
0000  
0000  
0001  
Flash device interface code (refer to the CFI publication 100)  
Maximum number of bytes in multi-byte write (not supported)  
Number of erase block regions  
Erase block region 1 information (refer to the CFI publication 100)  
Erase block region 2 information  
Erase block region 3 information  
Erase block region 4 information  
TABLE 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values  
(All values in these tables are in hexadecimal)  
Description  
Address  
Address  
Data  
(ByteMode)  
(WordMode)  
Query-unique ASCII string "PRI"  
80  
82  
84  
86  
88  
8A  
8C  
8E  
90  
92  
94  
96  
98  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
4A  
4B  
4C  
0050  
0052  
0049  
0031  
0030  
0000  
0002  
0001  
0001  
0004  
0000  
0000  
0000  
Major version number, ASCII  
Minor version number, ASCII  
Address sensitive unlock (0=required, 1= not required)  
Erase suspend (2= to read and write)  
Sector protect (N= # of sectors/group)  
Temporarysectorunprotected(1=supported)  
Sectorprotect/unprotectedscheme  
SimultaneousR/Woperation(0=notsupported)  
Burst mode type (0=not supported)  
Page mode type (0=not supported)  
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MX29SL800C T/B  
TABLE 5. MX29SL800C T/B COMMAND DEFINITIONS  
First Bus  
Bus Cycle  
Second Bus Third Bus  
Fourth Bus  
Cycle  
Fifth Bus  
Cycle  
Sixth Bus  
Cycle  
Command  
Cycle  
Cycle  
Cycle Addr Data Addr  
Data Addr  
Data Addr Data Addr  
Data Addr Data  
Reset  
1
1
4
4
4
XXXH F0H  
RA RD  
Read  
Read Silicon ID Word  
Byte  
555H AAH 2AAH 55H 555H 90H ADI  
AAAH AAH 555H 55H AAAH 90H ADI  
DDI  
DDI  
Sector Protect  
Verify  
Word  
555H AAH 2AAH 55H 555H 90H (SA) XX00H  
x02H XX01H  
Byte  
4
AAAH AAH 555H 55H AAAH 90H (SA) 00H  
x04H 01H  
Program  
Word  
Byte  
Word  
Byte  
Word  
Byte  
4
4
6
6
6
6
1
1
1
1
4
4
555H AAH 2AAH 55H 555H A0H PA  
AAAH AAH 555H 55H AAAH A0H PA  
PD  
PD  
Chip Erase  
Sector Erase  
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H  
555H 10H  
AAAH 10H  
AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H  
555H AAH 2AAH 55H 555H 80H 555H AAH 2AAH 55H  
SA  
SA  
30H  
30H  
AAAH AAH 555H 55H AAAH 80H AAAH AAH 555H 55H  
Sector Erase Suspend  
Sector Erase Resume  
XXXH B0H  
XXXH 30H  
55H 98  
AAH 98  
CFI Query  
Word  
Byte  
Sector Protect  
(Note 6,7)  
Note:  
Word  
Byte  
XXXH 60H SPA  
XXXH 60H SPA  
60H SPA  
60H SPA  
40H SPA SD  
40H SPA SD  
1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacturer code,A1=0, A0 = 1 for device code. A2-A18=do not care.  
(Refer to table 3)  
DDI = Data of Device identifier : C2H for manufacture code, 22EAH/EAH(Top), and 226BH/6BH(Bottom) for device code.  
X = X can be VIL or VIH  
RA=Address of memory location to be read.  
RD=Data to be read at location RA.  
2. PA = Address of memory location to be programmed.  
PD = Data to be programmed at location PA.  
SA = Address of the sector.  
3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or  
555H to Address A10~A-1 in byte mode.  
Address bit A11~A18=X=Don't care for all address commands except for Program Address (PA) and Sector Address (SA).  
Write Sequence may be initiated with A11~A18 in either state.  
4. For Sector Protect Verify operation: If read out data is 01H, it means the sector has been protected. If read out data is 00H,  
it means the sector is still not being protected.  
5. Any number of CFI data read cycle are permitted.  
6. Set sector address (SA) with (A6, A1, A0)=(0,1,0).  
7. This command is valid while RESET#=VID.  
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MX29SL800C T/B  
COMMAND DEFINITIONS  
sequences. Note that the Erase Suspend (B0H) and  
Erase Resume (30H) commands are valid only while the  
Sector Erase operation is in progress.  
Device operations are selected by writing specific ad-  
dress and data sequences into the command register.  
Writing incorrect address and data values or writing them  
in the improper sequence will reset the device to the  
read mode. Table 5 defines the valid register command  
TABLE 6. MX29SL800C T/B BUS OPERATION  
ADDRESS  
CE# OE# WE#RESET# A18 A10 A9 A8 A6 A5 A1 A0 Q0~Q7 BYTE#  
Q8~Q15  
BYTE#=VIL  
Q8~Q14 Q15/A-1  
DESCRIPTION  
A12 A11  
A7  
A2  
=VIH  
Read  
L
L
H
H
AIN  
Dout  
Dout Q8~Q14  
A-1  
=High Z  
DIN  
Write  
L
H
X
L
H
L
AIN  
X
DIN(3)  
Reset  
X
X
High Z High Z High Z  
DIN DIN High Z  
X
X
Temporary sector  
Unprotection  
X
X
X
VID  
AIN  
Output Disable  
Standby  
L
VCC±  
0.3V  
L
H
X
H
X
H
VCC±  
0.3V  
VID  
VID  
H
X
X
High Z High Z High Z  
High Z High Z High Z  
X
X
Sector Protect  
Chip Unprotected  
Sector Protection Verify  
NOTES:  
H
H
L
L
L
SA  
X
X
X
X
X
X
X
X
X
L
H
L
X
X
X
H
H
H
L
L
L
DIN  
DIN  
X
X
X
X
X
X
L
X
L
L
L
H
SA  
VID  
CODE(5)  
1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer to Table 5.  
2. VID is the Silicon-ID-Read high voltage, 10V to 11V.  
3. Refer to Table 5 for valid Data-In during a write operation.  
4. X can be VIL or VIH.  
5. Code=00H/XX00H means unprotected.  
Code=01H/XX01H means protected.  
6. A18~A12=Sector address for sector protect.  
7. The sector protect and chip unprotected functions may also be implemented via programming equipment.  
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MX29SL800C T/B  
REQUIREMENTS FOR READING ARRAY  
DATA  
STANDBY MODE  
When using both pins of CE# and RESET#, the device  
enter CMOS Standby with both pins held at Vcc ± 0.3V.  
If CE# and RESET# are held at VIH, but not within the  
range of VCC ± 0.3V, the device will still be in the standby  
mode, but the standby current will be larger.During Auto  
Algorithm operation,Vcc active current (Icc2) is required  
even CE# = "H" until the operation is completed. The  
device can be read with standard access time (tCE) from  
either of these standby modes, before it is ready to read  
data.  
To read array data from the outputs, the system must  
drive the CE# and OE# pins to VIL. CE# is the power  
control and selects the device. OE# is the output control  
and gates array data to the output pins. WE# should  
remain atVIH.  
The internal state machine is set for reading array data  
upon device power-up, or after a hardware reset. This  
ensures that no spurious alteration of the memory  
content occurs during the power transition. No command  
is necessary in this mode to obtain array data. Standard  
microprocessor read cycles that assert valid address  
on the device address inputs produce valid data on the  
device data outputs.The device remains enabled for read  
access until the command register contents are altered.  
OUTPUT DISABLE  
With the OE# input at a logic high level (VIH), output  
from the devices are disabled.This will cause the output  
pins to be in a high impedance state.  
WRITE COMMANDS/COMMAND SEQUENCES  
RESET# OPERATION  
To program data to the device or erase sectors of memory  
, the system must drive WE# and CE# to VIL, and OE#  
to VIH.  
The RESET# pin provides a hardware method of resetting  
the device to reading array data.When the RESET# pin  
is driven low for at least a period of tRP, the device  
immediately terminates any operation in progress, tri-  
states all output pins, and ignores all read/write  
commands for the duration of the RESET# pulse. The  
device also resets the internal state machine to reading  
array data.The operation that was interrupted should be  
reinitiated once the device is ready to accept another  
command sequence, to ensure data integrity  
An erase operation can erase one sector, multiple sectors  
, or the entire device.Table indicates the address space  
that each sector occupies. A "sector address" consists  
of the address bits required to uniquely select a sector.  
The "Writing specific address and data commands or  
sequences into the command register initiates device  
operations. Table 1 defines the valid register command  
sequences.Writing incorrect address and data values or  
writing them in the improper sequence resets the device  
to reading array data. Section has details on erasing a  
sector or the entire chip, or suspending/resuming the  
erase operation.  
Current is reduced for the duration of the RESET# pulse.  
When RESET# is held at VSS±0.3V, the device draws  
CMOS standby current (ICC4).If RESET# is held atVIL  
but not within VSS±0.3V, the standby current will be  
greater.  
After the system writes the autoselect command  
sequence, the device enters the autoselect mode. The  
system can then read autoselect codes from the internal  
register (which is separate from the memory array) on  
Q7-Q0. Standard read cycle timings apply in this mode.  
Refer to the Autoselect Mode and Autoselect Command  
Sequence section for more information.  
The RESET# pin may be tied to system reset circuitry.  
A system reset would that also reset the Flash memory,  
enabling the system to read the boot-up firmware from  
the Flash memory.  
If RESET# is asserted during a program or erase  
operation, the RY/BY# pin remains a "0" (busy) until the  
internal reset operation is complete, which requires a  
time of tREADY (during Embedded Algorithms). The  
system can thus monitor RY/BY# to determine whether  
the reset operation is complete. If RESET# is asserted  
when a program or erase operation is completed within a  
ICC2 in the DC Characteristics table represents the  
active current specification for the write mode.The "AC  
Characteristics" section contains timing specification  
table and timing diagrams for write operations.  
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MX29SL800C T/B  
The Automatic Chip Erase does not require the device to  
be entirely pre-programmed prior to executing the Auto-  
matic Chip Erase. Upon executing the Automatic Chip  
Erase, the device will automatically program and verify  
the entire memory for an all-zero data pattern. When the  
device is automatically verified to contain an all-zero pat-  
tern, a self-timed chip erase and verify begin. The erase  
and verify operations are completed when the data on Q7  
is "1" at which time the device returns to the Read mode.  
The system is not required to provide any control or tim-  
ing during these operations.  
time of tREADY (not during Embedded Algorithms).The  
system can read data tRH after the RESET# pin returns  
to VIH.  
Refer to the AC Characteristics tables for RESET#  
parameters and to Figure 22 for the timing diagram.  
READ/RESET COMMAND  
The read or reset operation is initiated by writing the read/  
reset command sequence into the command register.  
Microprocessor read cycles retrieve array data. The de-  
vice remains enabled for reads until the command regis-  
ter contents are altered.  
When using the Automatic Chip Erase algorithm, note  
that the erase automatically terminates when adequate  
erase margin has been achieved for the memory array  
(no erase verification command is required).  
If program-fail or erase-fail happen, the write of F0H will  
reset the device to abort the operation. A valid com-  
mand must then be written to place the device in the  
desired state.  
If the Erase operation was unsuccessful, the data on Q5  
is "1" (see Table 8), indicating the erase operation ex-  
ceed internal timing limit.  
The automatic erase begins on the rising edge of the last  
WE# or CE# pulse, whichever happens first in the com-  
mand sequence and terminates when the data on Q7 is  
"1" at which time the device returns to the Read mode,  
or the data on Q6 stops toggling for two consecutive read  
cycles at which time the device returns to the Read mode.  
SILICON-ID READ COMMAND  
Flash memories are intended for use in applications where  
the local CPU alters memory contents. As such, manu-  
facturer and device codes must be accessible while the  
device resides in the target system. PROM program-  
mers typically access signature codes by raising A9 to  
a high voltage (VID). However, multiplexing high voltage  
onto address lines is not generally desired system de-  
sign practice.  
The MX29SL800C T/B contains a Silicon-ID-Read op-  
eration to supple traditional PROM programming meth-  
odology. The operation is initiated by writing the read  
silicon ID command sequence into the command regis-  
ter. Following the command write, a read cycle with  
A1=VIL, A0=VIL retrieves the manufacturer code of C2H/  
00C2H. A read cycle with A1=VIL, A0=VIH returns the  
device code of EAH/22EAH for MX29SL800CT, 6BH/  
226BH for MX29SL800CB.  
SET-UP AUTOMATIC CHIP/SECTOR ERASE  
COMMANDS  
Chip erase is a six-bus cycle operation. There are two  
"unlock" write cycles. These are followed by writing the  
"set-up" command 80H. Two more "unlock" write cycles  
are then followed by the chip erase command 10H or  
sector erase command 30H.  
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MX29SL800C T/B  
TABLE 7. SILICON ID CODE  
Pins  
A0  
A1 Q15~Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Code (Hex)  
Manufacture code Word VIL VIL 00H  
Byte VIL VIL  
Word VIH VIL 22H  
for MX29SL800CT Byte VIH VIL  
Device code Word VIH VIL 22H  
for MX29SL800CB Byte VIH VIL  
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
00C2H  
X
C2H  
Device code  
22EAH  
X
EAH  
226BH  
X
6BH  
Sector Protection Word X  
Verification Byte X  
VIH X  
VIH X  
01H (Protected)  
00H (Unprotected)  
READING ARRAY DATA  
RESET COMMAND  
The device is automatically set to reading array data  
after device power-up. No commands are required to re-  
trieve data.The device is also ready to read array data  
after completing an Automatic Program or Automatic  
Erase algorithm.  
Writing the reset command to the device resets the de-  
vice to reading array data. Address bits are don't care  
for this command.  
The reset command may be written between the se-  
quence cycles in an erase command sequence before  
erasing begins. This resets the device to reading array  
data.Once erasure begins, however, the device ignores  
reset commands until the operation is complete.  
After the device accepts an Erase Suspend command,  
the device enters the Erase Suspend mode. The sys-  
tem can read array data using the standard read tim-  
ings, except that if it reads at an address within erase-  
suspended sectors, the device outputs status data. Af-  
ter completing a programming operation in the Erase  
Suspend mode, the system may once again read array  
data with the same exception. See Erase Suspend/Erase  
Resume Commands” for more information on this mode.  
The system must issue the reset command to re-en-  
able the device for reading array data if Q5 goes high, or  
while in the autoselect mode. See the "Reset Command"  
section, next.  
The reset command may be written between the se-  
quence cycles in a program command sequence before  
programming begins. This resets the device to reading  
array data (also applies to programming in Erase Sus-  
pend mode). Once programming begins, however, the  
device ignores reset commands until the operation is  
complete.  
The reset command may be written between the se-  
quence cycles in an SILICON ID READ command se-  
quence. Once in the SILICON ID READ mode, the reset  
command must be written to return to reading array data  
(also applies to SILICON ID READ during Erase Sus-  
pend).  
If Q5 goes high during a program or erase operation,  
writing the reset command returns the device to read-  
ing array data (also applies during Erase Suspend).  
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MX29SL800C T/B  
device requires a maximum 20us to suspend the sector  
erase operation.However, when the Erase Suspend com-  
mand is written during the sector erase time-out, the  
device immediately terminates the time-out period and  
suspends the erase operation. After this command has  
been executed, the command register will initiate erase  
suspend mode. The state machine will return to read  
mode automatically after suspend is ready. At this time,  
state machine only allows the command register to re-  
spond to Erase Resume, program data to , or read data  
from any sector not selected for erasure.  
SECTOR ERASE COMMANDS  
The Automatic Sector Erase does not require the de-  
vice to be entirely pre-programmed prior to executing  
the Automatic Sector Erase Set-up command and Au-  
tomatic Sector Erase command. Upon executing the  
Automatic Sector Erase command, the device will auto-  
matically program and verify the sector(s) memory for  
an all-zero data pattern. The system is not required to  
provide any control or timing during these operations.  
When the sector(s) is automatically verified to contain  
an all-zero pattern, a self-timed sector erase and verify  
begin. The erase and verify operations are complete  
when either the data on Q7 is "1" at which time the de-  
vice returns to the Read mode, or the data on Q6 stops  
toggling for two consecutive read cycles at which time  
the device returns to the Read mode. The system is not  
required to provide any control or timing during these  
operations.  
The system can determine the status of the program  
operation using the Q7 or Q6 status bits, just as in the  
standard program operation. After an erase-suspend pro-  
gram operation is complete, the system can once again  
read array data within non-suspended sectors.  
ERASE RESUME  
When using the Automatic sector Erase algorithm, note  
that the erase automatically terminates when adequate  
erase margin has been achieved for the memory array  
(no erase verification command is required). Sector  
erase is a six-bus cycle operation. There are two "un-  
lock" write cycles. These are followed by writing the  
set-up command 80H. Two more "unlock" write cycles  
are then followed by the sector erase command 30H.  
The sector address is latched on the falling edge of WE#  
or CE#, whichever happens later, while the command  
(data) is latched on the rising edge of WE# or CE#,  
whichever happens first. Sector addresses selected are  
loaded into internal register on the sixth falling edge of  
WE# or CE#, whichever happens later. Each succes-  
sive sector load cycle started by the falling edge of WE#  
or CE#, whichever happens later must begin within 50us  
from the rising edge of the preceding WE# or CE#, which-  
ever happens first. Otherwise, the loading period ends  
and internal auto sector erase cycle starts. (Monitor Q3  
to determine if the sector erase timer window is still open,  
see section Q3, Sector EraseTimer.) Any command other  
than Sector Erase (30H) or Erase Suspend (B0H) during  
the time-out period resets the device to read mode.  
This command will cause the command register to clear  
the suspend state and return back to Sector Erase mode  
but only if an Erase Suspend command was previously  
issued. Erase Resume will not have any effect in all  
other conditions. Another Erase Suspend command can  
be written after the chip has resumed erasing.However,  
a delay time must be required after the erase resume  
command (500us for MX29SL800C T/B), if the system  
implements an endless erase suspend/resume loop, or  
the number of erase suspend/resume is exceeded 1024  
times. The erase times will be expended if the erase  
behavior always be suspended. (Please refer to MXIC  
Flash Application Note for details.)  
WORD/BYTE PROGRAM COMMAND SEQUENCE  
The device programs one word/byte of data for each  
program operation.The command sequence requires four  
bus cycles, and is initiated by writing two unlock write  
cycles, followed by the program set-up command. The  
program address and data are written next, which in turn  
initiate the Embedded Program algorithm. The system is  
not required to provide further controls or timings. The  
device automatically generates the program pulses and  
verifies the programmed cell margin. Table 1 shows the  
address and data requirements for the byte program  
command sequence.  
ERASE SUSPEND  
This command only has meaning while the state ma-  
chine is executing Automatic Sector Erase operation,  
and therefore will only be responded during Automatic  
Sector Erase operation. When the Erase Suspend Com-  
mand is issued during the sector erase operation, the  
When the Embedded Program algorithm is complete,  
the device then returns to reading array data and  
addresses are no longer latched. The system can  
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MX29SL800C T/B  
determine the status of the program operation by using  
Q7, Q6, or RY/BY#. See "Write Operation Status" for  
information on these status bits.  
rithm is complete, or if the device enters the Erase Sus-  
pend mode, DATA# polling produces a "1" on Q7.This is  
analogous to the complement/true datum out-put de-  
scribed for the Automatic Program algorithm: the erase  
function changes all the bits in a sector to "1" prior to  
this, the device outputs the "complement," or "0". The  
system must provide an address within any of the sec-  
tors selected for erasure to read valid status information  
on Q7.  
Any commands written to the device during the Em-  
bedded Program Algorithm are ignored. Note that a  
hardware reset immediately terminates the programming  
operation. The Byte Program command sequence should  
be reinitiated once the device has reset to reading array  
data, to ensure data integrity.  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, DATA# polling on  
Q7 is active for approximately 100 us, then the device  
returns to reading array data. If not all selected sectors  
are protected, the Automatic Erase algorithm erases the  
unprotected sectors, and ignores the selected sectors  
that are protected.  
Programming is allowed in any sequence and across  
sector boundaries. A bit cannot be programmed from a  
"0" back to a "1". Attempting to do so may halt the  
operation and set Q5 to "1" , or cause the DATA# polling  
algorithm to indicate the operation was successful.  
However, a succeeding read will show that the data is  
still "0". Only erase operations can convert a "0" to a  
"1".  
When the system detects Q7 has changed from the  
complement to true data, it can read valid data at Q7-Q0  
on the following read cycles. This is because Q7 may  
change asynchronously with Q0-Q6 while Output En-  
able (OE#) is asserted low.  
WRITE OPERATION STATUS  
The device provides several bits to determine the sta-  
tus of a write operation: Q2, Q3, Q5, Q6, Q7, and RY/  
BY#. Table 10 and the following subsections describe  
the functions of these bits. Q7, RY/BY#, and Q6 each  
offer a method for determining whether a program or erase  
operation is complete or in progress. These three bits  
are discussed first.  
RY/BY# : Ready/Busy  
The RY/BY# is a dedicated, open-drain output pin that  
indicates whether an Automatic Erase/Program algorithm  
is in progress or complete. The RY/BY# status is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence.Since RY/BY#  
is an open-drain output, several RY/BY# pins can be  
tied together in parallel with a pull-up resistor to VCC.  
Q7: Data# Polling  
The DATA# polling bit, Q7, indicates to the host system  
whether an Automatic Algorithm is in progress or com-  
pleted, or whether the device is in Erase Suspend.DATA#  
polling is valid after the rising edge of the finalWE# pulse  
in the program or erase command sequence.  
If the output is low (Busy), the device is actively erasing  
or programming. (This includes programming in the Erase  
Suspend mode.) If the output is high (Ready), the de-  
vice is ready to read array data (including during the  
Erase Suspend mode), or is in the standby mode.  
During the Automatic Program algorithm, the device out-  
puts on Q7 the complement of the datum programmed  
to Q7.This Q7 status also applies to programming dur-  
ing Erase Suspend.When the Automatic Program algo-  
rithm is complete, the device outputs the datum pro-  
grammed to Q7.The system must provide the program  
address to read valid status information on Q7. If a pro-  
gram address falls within a protected sector, DATA# poll-  
ing on Q7 is active for approximately 2 us, then the de-  
vice returns to reading array data.  
Table 8 shows the outputs for RY/BY# during write op-  
eration.  
Q6:Toggle BIT I  
Toggle Bit I on Q6 indicates whether an Automatic Pro-  
gram or Erase algorithm is in progress or complete, or  
whether the device has entered the Erase Suspend mode.  
Toggle Bit I may be read at any address, and is valid  
after the rising edge of the final WE# or CE#, whichever  
During the Automatic Erase algorithm, DATA# polling pro-  
duces a "0" on Q7. When the Automatic Erase algo-  
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happens first, in the command sequence (prior to the  
program or erase operation), and during the sector time-  
out.  
parison, indicates whether the device is actively eras-  
ing, or is in Erase Suspend, but cannot distinguish which  
sectors are selected for erasure. Thus, both status bits  
are required for sectors and mode information. Refer to  
Table 8 to compare outputs for Q2 and Q6.  
During an Automatic Program or Erase algorithm opera-  
tion, successive read cycles to any address cause Q6  
to toggle. The system may use either OE# or CE# to  
control the read cycles.When the operation is complete,  
Q6 stops toggling.  
Reading Toggle Bits Q6/ Q2  
Whenever the system initially begins reading toggle bit  
status, it must read Q7-Q0 at least twice in a row to  
determine whether a toggle bit is toggling. Typically, the  
system would note and store the value of the toggle bit  
after the first read. After the second read, the system  
would compare the new value of the toggle bit with the  
first. If the toggle bit is not toggling, the device has  
completed the program or erase operation. The system  
can read array data on Q7-Q0 on the following read cycle.  
After an erase command sequence is written, if all sec-  
tors selected for erasing are protected, Q6 toggles and  
returns to reading array data. If not all selected sectors  
are protected, the Automatic Erase algorithm erases the  
unprotected sectors, and ignores the selected sectors  
that are protected.  
The system can use Q6 and Q2 together to determine  
whether a sector is actively erasing or is erase sus-  
pended.When the device is actively erasing (that is, the  
Automatic Erase algorithm is in progress), Q6 toggling.  
When the device enters the Erase Suspend mode, Q6  
stops toggling. However, the system must also use Q2  
to determine which sectors are erasing or erase-sus-  
pended. Alternatively, the system can use Q7.  
However, if after the initial two read cycles, the system  
determines that the toggle bit is still toggling, the sys-  
tem also should note whether the value of Q5 is high  
(see the section on Q5). If it is, the system should then  
determine again whether the toggle bit is toggling, since  
the toggle bit may have stopped toggling just as Q5 went  
high. If the toggle bit is no longer toggling, the device  
has successfully completed the program or erase op-  
eration. If it is still toggling, the device did not complete  
the operation successfully, and the system must write  
the reset command to return to reading array data.  
If a program address falls within a protected sector, Q6  
toggles for approximately 2 us after the program com-  
mand sequence is written, then returns to reading array  
data.  
Q6 also toggles during the erase-suspend-program mode,  
and stops toggling once the Automatic Program algo-  
rithm is complete.  
The remaining scenario is that system initially determines  
that the toggle bit is toggling and Q5 has not gone high.  
The system may continue to monitor the toggle bit and  
Q5 through successive read cycles, determining the sta-  
tus as described in the previous paragraph. Alterna-  
tively, it may choose to perform other system tasks. In  
this case, the system must start at the beginning of the  
algorithm when it returns to determine the status of the  
operation.  
Table 8 shows the outputs for Toggle Bit I on Q6.  
Q2:Toggle Bit II  
The "Toggle Bit II" on Q2, when used with Q6, indicates  
whether a particular sector is actively erasing (that is,  
the Automatic Erase algorithm is in process), or whether  
that sector is erase-suspended. Toggle Bit II is valid  
after the rising edge of the final WE# or CE#, whichever  
happens first, in the command sequence.  
Q5  
ExceededTiming Limits  
Q5 will indicate if the program or erase time has ex-  
ceeded the specified limits (internal pulse count). Under  
these conditions Q5 will produce a "1". This time-out  
condition indicates that the program or erase cycle was  
not successfully completed. Data# Polling and Toggle  
Bit are the only operating functions of the device under  
this condition.  
Q2 toggles when the system reads at addresses within  
those sectors that have been selected for erasure. (The  
system may use either OE# or CE# to control the read  
cycles.) But Q2 cannot distinguish whether the sector  
is actively erasing or is erase-suspended. Q6, by com-  
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If this time-out condition occurs during sector erase op-  
eration, it specifies that a particular sector is bad and it  
may not be reused. However, other sectors are still func-  
tional and may be used for the program or erase opera-  
tion. The device must be reset to use other sectors.  
Write the Reset command sequence to the device, and  
then execute program or erase command sequence. This  
allows the system to continue to use the other active  
sectors in the device.  
If this time-out condition occurs during the byte program-  
ming operation, it specifies that the entire sector con-  
taining that byte is bad and this sector may not be re-  
used, (other sectors are still functional and can be re-  
used).  
The time-out condition will not appear if a user tries to  
program a non blank location without erasing. Please  
note that this is not a device failure condition since the  
device was incorrectly used.  
If this time-out condition occurs during the chip erase  
operation, it specifies that the entire chip is bad or com-  
bination of sectors are bad.  
TABLE 8. WRITE OPERATION STATUS  
Status  
Q7  
Q6  
Q5  
Q3  
Q2 RY/BY#  
(Note1)  
(Note2)  
Word/Byte Program in Auto Program Algorithm  
Auto Erase Algorithm  
Q7# Toggle  
0
0
1
0
0
1
Toggle  
1
0
0
1
0
Toggle  
Toggle  
0
1
Erase Suspend Read  
(Erase Suspended Sector)  
In Progress  
Erase Suspended Mode  
Erase Suspend Read  
Data  
Data Data Data Data  
1
0
(Non-Erase Suspended Sector)  
Erase Suspend Program  
(Non-Erase Suspended Sector)  
Q7# Toggle  
Q7# Toggle  
0
1
0
0
1
1
Word/Byte Program in Auto Program Algorithm  
0
Exceeded  
Time Limits Auto Erase Algorithm  
0
Toggle  
1
1
1
0
N/A  
N/A  
0
0
Erase Suspend Program  
(Non-Erase Suspended Sector)  
Q7# Toggle  
Note:  
1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.  
2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.  
See "Q5:Exceeded Timing Limits " for more information.  
3. Successive reads from the erasing or erase-suspend sector causes Q2 to toggle.  
4. Reading from non-erase suspended sector address will indicate logic "1" at the Q2 bit.  
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Q3  
POWER SUPPLY DECOUPLING  
Sector Erase Timer  
In order to reduce power switching effect, each device  
should have a 0.1uF ceramic capacitor connected be-  
tween itsVCC and GND.  
After the completion of the initial sector erase command  
sequence, the sector erase time-out will begin. Q3 will  
remain low until the time-out is complete. DATA# polling  
andToggle Bit are valid after the initial sector erase com-  
mand sequence.  
POWER-UP SEQUENCE  
The MX29SL800CT/B powers up in the Read only mode.  
In addition, the memory contents may only be altered  
after successful completion of the predefined command  
sequences.  
If DATA# polling or the Toggle Bit indicates the device  
has been written with a valid erase command, Q3 may  
be used to determine if the sector erase timer window is  
still open. If Q3 is high ("1") the internally controlled  
erase cycle has begun; attempts to write subsequent  
commands to the device will be ignored until the erase  
operation is completed as indicated by DATA# polling or  
Toggle Bit. If Q3 is low ("0"), the device will accept  
additional sector erase commands. To insure the com-  
mand has been accepted, the system software should  
check the status of Q3 prior to and following each sub-  
sequent sector erase command. If Q3 were high on the  
second status check, the command may not have been  
accepted.  
TEMPORARY SECTOR UNPROTECTED  
This feature allows temporary unprotected of previously  
protected sector to change data in-system.TheTempo-  
rary Sector Unprotected mode is activated by setting  
the RESET# pin to VID (10V-11V). During this mode,  
formerly protected sectors can be programmed or erased  
as un-protected sector. Once VID is remove from the  
RESET# pin, all the previously protected sectors are  
protected again.  
DATA PROTECTION  
SECTOR PROTECTION  
The MX29SL800C T/B is designed to offer protection  
against accidental erasure or programming caused by  
spurious system level signals that may exist during power  
transition. During power up the device automatically re-  
sets the state machine in the Read mode. In addition,  
with its control register architecture, alteration of the  
memory contents only occurs after successful comple-  
tion of specific command sequences. The device also  
incorporates several features to prevent inadvertent write  
cycles resulting fromVCC power-up and power-down tran-  
sition or system noise.  
The MX29SL800CT/B features hardware sector protec-  
tion. This feature will disable both program and erase  
operations for these sectors protected. To activate this  
mode, the programming equipment must force VID on  
address pin A9 and OE#. Programming of the protection  
circuitry begins on the falling edge of theWE# pulse and  
is terminated on the rising edge. Please refer to sector  
protect algorithm and waveform.  
To verify programming of the protection circuitry, the pro-  
gramming equipment must forceVID on address pin A9  
( with CE# and OE# at VIL and WE# at VIH). When  
A1=VIH, A0=VIL, A6=VIL, it will produce a logical "1"  
code at device output Q0 for a protected sector. Other-  
wise the device will produce 00H for the unprotected  
sector. In this mode, the addresses, except for A1, are  
don't care. Address locations with A1 =VIL are reserved  
to read manufacturer and device codes. (Read Silicon  
ID)  
WRITE PULSE "GLITCH" PROTECTION  
Noise pulses of less than 5ns(typical) on CE# or WE#  
will not initiate a write cycle.  
LOGICAL INHIBIT  
Writing is inhibited by holding any one of OE# = VIL,  
CE# = VIH or WE# = VIH. To initiate a write cycle CE#  
and WE# must be a logical zero while OE# is a logical  
one.  
It is also possible to determine if the sector is protected  
in the system by writing a Read Silicon ID command.  
Performing a read operation with A1=VIH, it will produce  
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a logical "1" at Q0 for the protected sector.  
CHIP UNPROTECTED  
The MX29SL800CT/B also features the chip unprotected  
mode, so that all sectors are unprotected after chip un-  
protected is completed to incorporate any changes in the  
code. It is recommended to protect all sectors before  
activating chip unprotected mode.  
To activate this mode, the programming equipment must  
force VID on control pin OE# and address pin A9. The  
CE# pins must be set at VIL. Pins A6 must be set to  
VIH. Refer to chip unprotected algorithm and waveform  
for the chip unprotected algorithm. The unprotection  
mechanism begins on the falling edge of the WE# pulse  
and is terminated on the rising edge.  
It is also possible to determine if the chip is unprotected  
in the system by writing the Read Silicon ID command.  
Performing a read operation with A1=VIH, it will produce  
00H at data outputs (Q0-Q7) for an unprotected sector.  
It is noted that all sectors are unprotected after the chip  
unprotected algorithm is completed.  
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ABSOLUTE MAXIMUM RATINGS  
OPERATING RATINGS  
StorageTemperature  
Plastic Packages . . . . . . . . . . . . . ..... -55oC to +125oC  
Commercial (C) Devices  
Ambient Temperature (TA ). . . . . . . . . . . . 0°C to +70°C  
Industrial (I) Devices  
AmbientTemperature  
with Power Applied. . . . . . . . . . . . . .... -40oC to +85oC  
Voltage with Respect to Ground  
Ambient Temperature (TA ). . . . . . . . . . -40°C to +85°C  
VCC Supply Voltages  
VCC for full voltage range. . . . . . . . . . . +1.65 V to 2.2 V  
VCC (Note 1) . . . . . . . . . . . . . . . . . -0.5 V to +3.0 V  
A9, OE#, and  
Operating ranges define those limits between which the  
functionality of the device is guaranteed.  
RESET# (Note 2) . . . . . . . . . . . ....-0.3 V to +11.5 V  
All other pins (Note 1) . . . . . . . -0.3 V to VCC +0.5 V  
Output Short Circuit Current (Note 3) . . . . . . 200 mA  
Notes:  
1. Minimum DC voltage on input or I/O pins is -0.3 V.  
During voltage transitions, input or I/O pins may over-  
shoot VSS to -2.0 V for periods of up to 20 ns. See  
Figure 6. Maximum DC voltage on input or I/O pins is  
VCC +0.5 V. During voltage transitions, input or I/O  
pins may overshoot to VCC +2.0 V for periods up to  
20 ns.  
2. Minimum DC input voltage on pins A9, OE#, and  
RESET# is -0.3V.During voltage transitions, A9, OE#,  
and RESET# may overshoot VSS to -2.0 V for peri-  
ods of up to 20 ns. See Figure 6. Maximum DC input  
voltage on pin A9 is +11.5 V which may overshoot to  
12.5 V for periods up to 20 ns.  
3.No more than one output may be shorted to ground at  
a time. Duration of the short circuit should not be  
greater than one second.  
Stresses above those listed under "Absolute Maximum  
Ratings" may cause permanent damage to the device.  
This is a stress rating only; functional operation of the  
device at these or any other conditions above those in-  
dicated in the operational sections of this data sheet is  
not implied. Exposure of the device to absolute maxi-  
mum rating conditions for extended periods may affect  
device reliability.  
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TABLE 9. DC CHARACTERISTICS TA = -40oC to 85oC, VCC = 1.65V~2.2V  
Symbol PARAMETER  
MIN.  
TYP  
MAX.  
± 1  
UNIT  
uA  
CONDITIONS  
ILI  
Input Leakage Current  
VIN = VSS to VCC, VCC=VCC max  
VCC=VCC max;  
ILIT  
A9, OE#, RESET# Input  
Leakage Current  
35  
uA  
A9, OE#, RESET#=11V  
VOUT = VSS to VCC, VCC=VCC max  
CE#=VIL, OE#=VIH @10MHz  
ILO  
Output Leakage Current  
VCC Active Read Current  
± 1  
12  
6
uA  
mA  
mA  
mA  
mA  
mA  
uA  
ICC1  
(Byte Mode)  
@5MHz  
12  
6
CE#=VIL, OE#=VIH @10MHz  
(Word Mode)  
@5MHz  
ICC2  
ICC3  
VCC Active write Current  
VCC Standby Current  
15  
1
25  
5
CE#=VIL, OE#=VIH  
VCC=VCC max;  
CE#, RESET#= VCC ± 0.3V  
RESET#= VSS ± 0.3V  
ICC4  
ICC5  
VCC Standby Current  
During Reset  
1
1
5
5
uA  
uA  
Automatic sleep mode  
VCC=VCC max;  
CE#=VSS ± 0.3V;  
RESET#=VCC ± 0.3V;  
VIH=VCC ± 0.3V;  
VIL=VSS ± 0.3V  
VIL  
VIH  
VID  
Input Low Voltage(Note 1)  
Input High Voltage  
-0.5  
0.2xVCC  
VCC+ 0.3  
V
V
0.7xVCC  
Voltage for Automatic  
Select, Sector protection  
and Temporary  
10  
10.5  
11  
V
Sector Unprotected  
Output Low Voltage  
VOL  
0.25  
0.1  
V
V
IOL = 2.0mA, VCC= VCC min  
IOL = 100uA, VCC= VCC min  
IOH = -2mA, VCC=VCC min  
IOH = -100uA, VCC=VCC min  
VOH1  
VOH2  
Output High Voltage(TTL)  
0.85xVCC  
Output High Voltage(CMOS) VCC-0.1  
NOTES:  
1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.  
VIL min. = -2.0V for pulse width is equal to or less than 20 ns.  
2. Automatic sleep mode enable the low power mode when addresses remain stable for tACC +30ns.  
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AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 1.65V~2.2V  
TABLE 10. READ OPERATIONS  
29SL800CT/B-90  
SYMBOL PARAMETER  
MIN.  
MAX.  
UNIT  
ns  
CONDITIONS  
tRC  
tACC  
tCE  
Read Cycle Time (Note 1)  
Address to Output Delay  
CE# to Output Delay  
90  
90  
90  
35  
30  
ns  
CE#=OE#=VIL  
OE#=VIL  
ns  
tOE  
OE# to Output Delay  
ns  
CE#=VIL  
tDF  
OE# High to Output Float (Note1)  
Output Enable Read  
0
ns  
CE#=VIL  
tOEH  
0
ns  
Hold Time  
Toggle and  
10  
ns  
Data# Polling  
tOH  
Address to Output hold  
0
ns  
CE#=OE#=VIL  
NOTES:  
1. Not 100% tested.  
2. tDF is defined as the time at which the output achieves  
the open circuit condition and data is no longer driven.  
TEST CONDITIONS:  
• Input pulse levels: 0V or VCC  
• Input rise and fall times is equal to or less than 5ns.  
• Output load: 1 TTL gate + 30pF  
• Reference levels for measuring timing: VCC/2  
CAPACITANCE TA = 25oC, f = 1.0 MHz  
SYMBOL  
CIN1  
PARAMETER  
MIN.  
TYP  
MAX.  
8
UNIT  
pF  
CONDITIONS  
VIN = 0V  
Input Capacitance  
Control Pin Capacitance  
Output Capacitance  
CIN2  
12  
pF  
VIN = 0V  
COUT  
12  
pF  
VOUT = 0V  
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SWITCHING TEST CIRCUITS  
DEVICE UNDER  
TEST  
2.7K ohm  
VCC  
CL  
6.2K ohm  
DIODES=IN3064  
OR EQUIVALENT  
CL= 30pF Including jig capacitance  
SWITCHING TEST WAVEFORMS  
VCC  
TEST POINTS  
0V  
INPUT  
OUTPUT  
AC TESTING: Inputs are driven at VCC for a logic "1" and 0V for a logic "0".  
Input pulse rise and fall times are < 5ns.  
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FIGURE 1. READ TIMING WAVEFORMS  
tRC  
VIH  
ADD Valid  
Addresses  
VIL  
tACC  
tCE  
VIH  
CE#  
VIL  
VIH  
WE#  
VIL  
tOE  
tDF  
tOEH  
VIH  
OE#  
VIL  
tACC  
tOH  
HIGH Z  
HIGH Z  
VOH  
VOL  
Outputs  
DATA Valid  
VIH  
VIL  
RESET#  
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AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 1.65V~2.2V  
TABLE 11. Erase/Program Operations  
Parameter  
Speed Options  
Std.  
tWC  
tAS  
Description  
90  
Unit  
ns  
Write Cycle Time (Note 1)  
Address Setup Time  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
90  
0
45  
45  
0
ns  
tAH  
Address Hold Time  
ns  
tDS  
Data Setup Time  
ns  
tDH  
Data Hold Time  
ns  
tOES  
tGHWL  
Output Enable Setup Time  
Read Recovery Time Before Write  
(OE# High to WE# Low)  
CE# Setup Time  
0
ns  
0
ns  
tCS  
Min  
Min  
Min  
Min  
Typ  
Typ  
Typ  
Min  
Min  
Max  
Min  
Typ  
Min  
Typ  
Max  
0
0
ns  
ns  
ns  
ns  
us  
us  
sec  
us  
ns  
ns  
ns  
us  
ns  
ms  
us  
tCH  
CE# Hold Time  
tWP  
Write Pulse Width  
45  
30  
12  
18  
1.3  
50  
0
tWPH  
tWHWH1  
Write Pulse Width High  
ProgrammingOperation(Note2)  
(Byte/Wordprogramtime)  
Sector Erase Operation (Note 2)  
VCC Setup Time (Note 1)  
Recovery Time from RY/BY#  
Program/Erase Valid to RY/BY# Delay  
Write Pulse Width for Sector Protect  
(A9, OE#Control)  
Byte  
Word  
tWHWH2  
tVCS  
tRB  
tBUSY  
tWPP1  
90  
100  
10  
100  
12  
50  
tWPP2  
tBAL  
Write Pulse Width for Chip Unprotected  
(A9, OE#Control)  
Sector Address Load Time  
NOTES:  
1. Not 100% tested.  
2. See the "Erase and Programming Performance" section for more information.  
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AC CHARACTERISTICS TA = -40oC to 85oC, VCC = 1.65V~2.2V  
TABLE 12. Alternate CE# Controlled Erase/Program Operations  
Parameter  
Speed Options  
Std.  
Description  
90  
90  
0
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
us  
us  
sec  
tWC  
Write CycleTime (Note 1)  
Address SetupTime  
Address HoldTime  
Data SetupTime  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Min  
Typ  
Typ  
Typ  
tAS  
tAH  
45  
45  
0
tDS  
tDH  
Data HoldTime  
tOES  
tGHEL  
tWS  
Output Enable SetupTime  
Read RecoveryTime BeforeWrite  
WE# SetupTime  
0
0
0
tWH  
WE# HoldTime  
0
tCP  
CE# PulseWidth  
45  
30  
12  
18  
1.3  
tCPH  
tWHWH1  
CE# Pulse Width High  
Programming  
Byte  
Word  
Operation(note2)  
tWHWH2  
Sector Erase Operation (note2)  
NOTE:  
1. Not 100% tested.  
2. See the "Erase and Programming Performance" section for more information.  
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FIGURE 2. COMMAND WRITE TIMING WAVEFORM  
VCC  
1.8V  
VIH  
Addresses  
ADD Valid  
VIL  
tAH  
tAS  
VIH  
VIL  
WE#  
CE#  
tWPH  
tCWC  
tOES  
tWP  
VIH  
VIL  
tCS  
tCH  
tDH  
VIH  
VIL  
OE#  
Data  
tDS  
VIH  
VIL  
DIN  
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AUTOMATIC PROGRAMMING TIMING WAVEFORM  
ing after automatic programming starts. Device outputs  
DATA# during programming and DATA# after program-  
ming on Q7. (Q6 is for toggle bit; see toggle bit, DATA#  
polling, timing waveform)  
One byte data is programmed. Verify in fast algorithm  
and additional verification by external control are not re-  
quired because these operations are executed automati-  
cally by internal control circuit. Programming comple-  
tion can be verified by DATA# polling and toggle bit check-  
FIGURE 3. AUTOMATIC PROGRAMMING TIMING WAVEFORM  
Program Command Sequence(last two cycle)  
Read Status Data (last two cycle)  
tWC  
tAS  
PA  
PA  
555h  
PA  
Address  
CE#  
tAH  
tCH  
tGHWL  
OE#  
WE#  
tWHWH1  
tWP  
tCS  
tWPH  
tDS tDH  
Status  
A0h  
PD  
DOUT  
Data  
tBUSY  
tRB  
RY/BY#  
tVCS  
VCC  
NOTES:  
1.PA=Program Address, PD=Program Data, DOUT is the true data the program address  
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FIGURE 4. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART  
START  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data A0H Address 555H  
Write Program Data/Address  
Data Poll  
Increment  
Address  
from system  
No  
No  
Verify Word Ok ?  
YES  
Last Address ?  
YES  
Auto Program Completed  
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FIGURE 5. CE# CONTROLLED PROGRAM TIMING WAVEFORM  
PA for program  
555 for program  
2AA for erase  
SA for sector erase  
555 for chip erase  
Data Polling  
Address  
PA  
tWC  
tWH  
tAS  
tAH  
WE#  
OE#  
tGHEL  
tCP  
tWHWH1 or 2  
CE#  
Data  
tWS  
tDS  
tCPH  
tBUSY  
tDH  
DOUT  
DQ7  
PD for program  
30 for sector erase  
10 for chip erase  
A0 for program  
55 for erase  
tRH  
RESET#  
RY/BY#  
NOTES:  
1.PA=Program Address, PD=Program Data, DOUT=Data Out, DQ7=complement of data written to device.  
2.Figure indicates the last two bus cycles of the command sequence.  
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AUTOMATIC CHIP ERASE TIMING WAVEFORM  
All data in chip are erased. External erase verification is  
not required because data is verified automatically by  
internal control circuit. Erasure completion can be veri-  
fied by DATA# polling and toggle bit checking after auto-  
matic erase starts. Device outputs 0 during erasure  
and 1 after erasure on Q7. (Q6 is for toggle bit; see toggle  
bit, DATA# polling, timing waveform)  
FIGURE 6. AUTOMATIC CHIP ERASE TIMING WAVEFORM  
Erase Command Sequence(last two cycle)  
Read Status Data  
VA  
tWC  
tAS  
VA  
2AAh  
555h  
Address  
CE#  
tAH  
tCH  
tGHWL  
OE#  
WE#  
tWHWH2  
tWP  
tCS  
tWPH  
tDS tDH  
In  
Progress  
55h  
10h  
Complete  
Data  
tBUSY  
tRB  
RY/BY#  
tVCS  
VCC  
NOTES:  
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").  
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FIGURE 7. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART  
START  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 80H Address 555H  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 10H Address 555H  
Data Pall from System  
NO  
Data=FFh ?  
YES  
Auto Chip Erase Completed  
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AUTOMATIC SECTOR ERASE TIMING WAVEFORM  
Sector indicated by A12 to A18 are erased. External  
erase verify is not required because data are verified  
automatically by internal control circuit. Erasure comple-  
tion can be verified by DATA# polling and toggle bit check-  
ing after automatic erase starts. Device outputs 0 dur-  
ing erasure and 1 after erasure on Q7. (Q6 is for toggle  
bit; see toggle bit, DATA# polling, timing waveform)  
FIGURE 8. AUTOMATIC SECTOR ERASE TIMING WAVEFORM  
Erase Command Sequence(last two cycle)  
Read Status Data  
VA  
tWC  
tAS  
Sector  
Sector  
Sector  
VA  
2AAh  
Address  
CE#  
Address 0  
Address 1  
Address n  
tAH  
tCH  
tGHWL  
OE#  
WE#  
tWHWH2  
tBAL  
tWP  
tCS  
tWPH  
tDS tDH  
In  
Progress  
55h  
30h  
30h  
30h  
Complete  
Data  
tBUSY  
tRB  
RY/BY#  
tVCS  
VCC  
NOTES:  
SA=sector address(for Sector Erase), VA=Valid Address for reading status data(see "Write Operation Status").  
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FIGURE 9. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART  
START  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 80H Address 555H  
Write Data AAH Address 555H  
Write Data 55H Address 2AAH  
Write Data 30H Sector Address  
NO  
Last Sector  
to Erase  
YES  
Data Poll from System  
NO  
Data=FFh  
YES  
Auto Sector Erase Completed  
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FIGURE 10. ERASE SUSPEND/ERASE RESUME FLOWCHART  
START  
Write Data B0H  
ERASE SUSPEND  
NO  
Toggle Bit checking Q6  
not toggled  
YES  
Read Array or  
Program  
Reading or  
NO  
Programming End  
YES  
Write Data 30H  
Delay Time (Note 2)  
Continue Erase  
ERASE RESUME  
Another  
NO  
Erase Suspend ?  
YES  
Note:  
1. If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is  
exceeded 1024 times, then the delay time must be put into consideration.  
2. Delay timing: 1.5ms for MX29SL800C T/B.  
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FIGURE 11. IN-SYSTEM SECTOR PROTECT/UNPROTECTEDTIMINGWAVEFORM (RESET# Control)  
VID  
VIH  
RESET#  
SA, A6  
A1, A0  
Valid*  
Valid*  
Valid*  
Sector Protect or Chip Unprotect  
Verify  
40h  
Status  
Data  
60h  
60h  
Sector Protect =150us  
Chip Unprotect =15ms  
1us  
CE#  
WE#  
OE#  
Note: When sector protect, A6=0, A1=1, A0=0. When chip unprotect, A6=1, A1=1, A0=0.  
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FIGURE 12. SECTOR PROTECT TIMING WAVEFORM (A9, OE# Control)  
A1  
A6  
10.5V  
3V  
A9  
tVLHT  
tVLHT  
Verify  
10.5V  
3V  
OE#  
tVLHT  
tWPP 1  
WE#  
CE#  
tOESP  
Data  
01H  
F0H  
tOE  
Sector Address  
A18-A12  
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FIGURE 13. SECTOR PROTECTION ALGORITHM (A9, OE# Control)  
START  
Set Up Sector Addr  
PLSCNT=1  
OE#=VID, A9=VID, CE#=VIL  
A6=VIL  
Activate WE# Pulse  
Time Out 150us  
Set WE#=VIH, CE#=OE#=VIL  
A9 should remain VID  
.
Read from Sector  
Addr=SA, A1=1  
No  
No  
Data=01H?  
PLSCNT=32?  
Yes  
Device Failed  
Yes  
Protect Another  
Sector?  
Remove VID from A9  
Write Reset Command  
Sector Protection  
Complete  
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FIGURE 14. IN-SYSTEM SECTOR PROTECTION ALGORITHM WITH RESET#=VID  
START  
PLSCNT=1  
RESET#=VID  
Wait 1us  
No  
Temporary Sector  
Unprotect Mode  
First Write  
Cycle=60H  
Yes  
Set up sector address  
Write 60H to sector address  
with A6=0, A1=1, A0=0  
Wait 150us  
Verify sector protect :  
write 40H with A6=0,  
A1=1, A0=0  
Increment PLSCNT  
Reset PLSCNT=1  
Read from sector address  
No  
No  
PLSCNT=25?  
Data=01H ?  
Yes  
Yes  
Device failed  
Yes  
Protect another  
sector?  
No  
Remove VID from RESET#  
Write reset command  
Sector protect complete  
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FIGURE 15. IN-SYSTEM CHIP UNPROTECTION ALGORITHM WITH RESET#=VID  
START  
PLSCNT=1  
RESET#=VID  
Wait 1us  
No  
No  
Temporary Sector  
Unprotect Mode  
First Write  
Cycle=60H ?  
Yes  
All sector  
Protect all sectors  
protected?  
Yes  
Set up first sector address  
Chip unprotect :  
write 60H with  
A6=1, A1=1, A0=0  
Wait 50ms  
Verify chip unprotect  
write 40H to sector address  
with A6=1, A1=1, A0=0  
Increment PLSCNT  
Read from sector address  
with A6=1, A1=1, A0=0  
No  
No  
Set up next sector address  
PLSCNT=1000?  
Data=00H ?  
Yes  
Yes  
Device failed  
Yes  
Last sector  
verified?  
No  
Remove VID from RESET#  
Write reset command  
Chip unprotect complete  
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FIGURE 16. TIMING WAVEFORM FOR CHIP UNPROTECTION (A9, OE# Control)  
A1  
10.5V  
VCC  
A9  
A6  
tVLHT  
Verify  
10.5V  
VCC  
OE#  
tVLHT  
tVLHT  
tWPP 2  
WE#  
CE#  
tOESP  
Data  
00H  
F0H  
tOE  
A18-A12  
Sector Address  
Notes: tVLHT (Voltage transition time)=4us min.  
tWPP1 (Write pulse width for sector protect)=100ns min, 10us(Typ.)  
tWPP2 (Write pulse width for chip unprotected)=100ns min, 12ms(Typ.)  
tOESP (OE# setup time to WE# active)=4us min.  
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FIGURE 17. CHIP UNPROTECTION ALGORITHM (A9, OE# Control)  
START  
Protect All Sectors  
PLSCNT=1  
Set OE#=A9=VID  
CE#=VIL,A6=1  
Activate WE# Pulse  
Time Out 50ms  
Increment  
PLSCNT  
Set OE#=CE#=VIL  
A9=VID,A1=1  
Set Up First Sector Addr  
Read Data from Device  
No  
No  
Data=00H?  
Yes  
PLSCNT=1000?  
Increment  
Sector Addr  
Yes  
Device Failed  
No  
All sectors have  
been verified?  
Yes  
Remove VID from A9  
Write Reset Command  
Chip Unprotect  
Complete  
* It is recommended before unprotect whole chip, all sectors should be protected in advance.  
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WRITE OPERATION STATUS  
FIGURE 18. DATA# POLLING ALGORITHM  
Start  
Read Q7~Q0  
Add.=VA(1)  
Yes  
Q7 = Data ?  
No  
No  
Q5 = 1 ?  
Yes  
Read Q7~Q0  
Add.=VA  
Yes  
(2)  
Q7 = Data ?  
No  
FAIL  
Pass  
NOTE : 1.VA=Valid address for programming  
2.Q7 should be re-checked even Q5="1" because Q7 may change  
simultaneously with Q5.  
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FIGURE 19. TOGGLE BIT ALGORITHM  
Start  
Read Q7-Q0  
Read Q7-Q0  
(Note 1)  
NO  
Toggle Bit Q6 =  
Toggle ?  
YES  
NO  
Q5= 1?  
YES  
Read Q7~Q0 Twice  
(Note 1,2)  
NO  
Toggle bit Q6=  
Toggle?  
YES  
Program/Erase Operation  
Not Complete,Write  
Reset Command  
Program/Erase  
operation Complete  
Note:1.Read toggle bit twice to determine whether or not it is toggling.  
2. Recheck toggle bit because it may stop toggling as Q5 change to "1".  
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FIGURE 20. DATA# Polling Timings (During Automatic Algorithms)  
tRC  
VA  
VA  
VA  
Address  
CE#  
tACC  
tCE  
tCH  
tOE  
OE#  
WE#  
tOEH  
tDF  
tOH  
High Z  
High Z  
Complement  
Status Data  
Complement  
Status Data  
True  
True  
Valid Data  
Valid Data  
DQ7  
Q0-Q6  
tBUSY  
RY/BY#  
NOTES:  
1. VA=Valid address. Figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle.  
2. CE# must be toggled when DATA# polling.  
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FIGURE 21. Toggle Bit Timings (During Automatic Algorithms)  
tRC  
VA  
VA  
VA  
VA  
Address  
CE#  
tACC  
tCE  
tCH  
tOE  
OE#  
tDF  
tOEH  
WE#  
tOH  
High Z  
Valid Status  
(second read)  
Valid Status  
(first read)  
Valid Data  
Valid Data  
Q6/Q2  
(stops toggling)  
tBUSY  
RY/BY#  
NOTES:  
1. VA=Valid address; not required for Q6. Figure shows first two status cycle after command sequence, last status read cycle,  
and array data read cycle.  
2. CE# must be toggled when toggle bit toggling.  
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TABLE 13. AC CHARACTERISTICS  
Parameter Std Description  
Test Setup All Speed Options Unit  
tREADY1  
RESET# PIN Low (During Automatic Algorithms)  
MAX  
20  
us  
to Read or Write (See Note)  
tREADY2  
RESET# PIN Low (NOT During Automatic  
Algorithms) to Read or Write (See Note)  
RESET# Pulse Width (During Automatic Algorithms)  
RESET# HighTime Before Read (See Note)  
RY/BY# Recovery Time (to CE#, OE# go low)  
MAX  
500  
ns  
tRP  
tRH  
tRB  
MIN  
MIN  
MIN  
500  
200  
0
ns  
ns  
ns  
Note: Not 100% tested  
FIGURE 22. RESET# TIMING WAVEFORM  
RY/BY#  
CE#, OE#  
tRH  
RESET#  
tRP  
tReady2  
Reset Timing NOT during Automatic Algorithms  
tReady1  
RY/BY#  
tRB  
CE#, OE#  
RESET#  
tRP  
Reset Timing during Automatic Algorithms  
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AC CHARACTERISTICS  
TABLE 14. WORD/BYTE CONFIGURATION (BYTE#)  
Parameter  
Std  
Description  
Speed OptionsUnit JEDEC  
-90  
tELFL/tELFH CE# to BYTE# Switching Low or High  
Max  
Max  
Min  
5
30  
90  
ns  
ns  
ns  
tFLQZ  
tFHQV  
BYTE# Switching Low to Output HIGH Z  
BYTE# Switching High to Output Active  
FIGURE 23. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte  
mode to word mode)  
CE#  
OE#  
tELFH  
BYTE#  
DOUT  
(Q0-Q7)  
DOUT  
(Q0-Q14)  
Q0~Q14  
Q15/A-1  
DOUT  
(Q15)  
VA  
tFHQV  
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FIGURE 24. BYTE# TIMINGWAVEFORM FOR READ OPERATIONS (BYTE# switching from word  
mode to byte mode)  
CE#  
OE#  
tELFH  
BYTE#  
DOUT  
(Q0-Q14)  
DOUT  
(Q0-Q7)  
Q0~Q14  
Q15/A-1  
DOUT  
(Q15)  
VA  
tFLQZ  
FIGURE 25. BYTE# TIMING WAVEFORM FOR PROGRAM OPERATIONS  
CE#  
The falling edge of the last WE# signal  
WE#  
BYTE#  
tAS  
tAH  
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TABLE 15. TEMPORARY SECTOR UNPROTECTED  
Parameter Std. Description  
Test Setup All Speed Options Unit  
tVIDR  
tRSP  
VID Rise and Fall Time (See Note)  
Min  
Min  
500  
4
ns  
us  
RESET# Setup Time for Temporary Sector Unprotected  
Note:  
Not 100% tested  
FIGURE 26. TEMPORARY SECTOR UNPROTECTED TIMING DIAGRAM  
10.5V  
RESET#  
0 or VCC  
0 or VCC  
Program or Erase Command Sequence  
tVIDR  
tVIDR  
CE#  
WE#  
tRSP  
RY/BY#  
FIGURE 27. Q6 vs Q2 for Erase and Erase Suspend Operations  
Enter Embedded  
Erasing  
Erase  
Enter Erase  
Erase  
Suspend  
Suspend Program  
Resume  
Erase  
Erase  
Erase Suspend  
Read  
Erase  
Erase  
WE#  
Q6  
Suspend  
Program  
Complete  
Q2  
NOTES:  
The system can use OE or CE to toggle Q2/Q6, Q2 toggles only when read at an address within an erase-suspended  
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FIGURE 28. TEMPORARY SECTOR UNPROTECTED ALGORITHM  
Start  
RESET# = VID (Note 1)  
Perform Erase or Program Operation  
Operation Completed  
RESET# = VIH  
Temporary Sector Unprotect Completed(Note 2)  
Note :  
1. All protected sectors are temporary unprotected.  
VID=10V~11V  
2. All previously protected sectors are protected again.  
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FIGURE 29. ID CODE READ TIMING WAVEFORM  
VCC  
1.8V  
VID  
ADD  
A9  
VIH  
VIL  
VIH  
VIL  
ADD  
A0  
tACC  
tACC  
VIH  
VIL  
A1  
ADD  
A2-A8  
VIH  
A10-A18 VIL  
CE#  
VIH  
VIL  
VIH  
VIL  
tCE  
WE#  
OE#  
tOE  
VIH  
VIL  
tDF  
tOH  
tOH  
VIH  
VIL  
DATA  
Q0-Q15  
DATA OUT  
DATA OUT  
EAH/6BH (Byte)  
C2H/00C2H  
22EAH/226BH (Word)  
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RECOMMENDED OPERATING CONDITIONS  
At Device Power-Up  
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up.  
If the timing in the figure is ignored, the device may not operate correctly.  
VCC(min)  
VCC  
GND  
tVR  
tACC  
tR or tF  
tR or tF  
VIH  
VIL  
Valid  
ADDRESS  
CE#  
Address  
tF  
tCE  
tR  
VIH  
VIL  
VIH  
VIL  
WE#  
tF  
tOE  
tR  
VIH  
VIL  
OE#  
VIH  
VIL  
WP#/ACC  
DATA  
VOH  
VOL  
High Z  
Valid  
Ouput  
Figure A. ACTiming at Device Power-Up  
Notes  
Symbol  
Parameter  
Min.  
Max.  
Unit  
us/V  
us/V  
us/V  
tVR  
tR  
VCC RiseTime  
1
20  
500000  
20  
Input Signal RiseTime  
Input Signal Fall Time  
1,2  
1,2  
tF  
20  
Notes :  
1. Sampled, not 100% tested.  
2. This specification is applied for not only the device power-up but also the normal operations.  
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TABLE 16. ERASE AND PROGRAMMING PERFORMANCE (1)  
LIMITS  
TYP.(2)  
1.3  
PARAMETER  
MIN.  
MAX.(3)  
UNITS  
sec  
Sector Erase Time  
Chip Erase Time  
15  
18  
sec  
Byte Programming Time  
Word Programming Time  
Chip Programming Time  
12  
72  
us  
18  
108  
us  
Byte Mode  
Word Mode  
12.6  
9.6  
sec  
sec  
Erase/Program Cycles  
100,000  
Cycles  
Note: 1. Not 100% Tested, Excludes external system level over head.  
2.Typical values measured at 25°C, 1.8V.  
3. Maximum values measured at 90°C, 1.65V, 100K cycles.  
TABLE 17. LATCH-UP CHARACTERISTICS  
MIN.  
-1.0V  
MAX.  
Input Voltage with respect to GND on OE#, RESET#, A9  
Input Voltage with respect to GND on all power pins, Address pins, CE# and WE#  
Input Voltage with respect to GND on all I/O pins  
11V  
-1.0V  
2xVCC  
-1.0V  
VCC + 1.0V  
+100mA  
Current  
-100mA  
Includes all pins except VCC. Test conditions: VCC = 1.8V, one pin at a time.  
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ORDERING INFORMATION  
PART NO.  
ACCESS  
OPERATING  
STANDBY  
PACKAGE  
Remark  
TIME (ns) Current MAX. (mA) Current MAX. (uA)  
MX29SL800CTTC-90  
MX29SL800CBTC-90  
MX29SL800CTXBC-90  
MX29SL800CBXBC-90  
MX29SL800CTXEC-90  
MX29SL800CBXEC-90  
MX29SL800CTXHC-90  
90  
90  
90  
90  
90  
90  
90  
12  
12  
12  
12  
12  
12  
12  
5
5
5
5
5
5
5
48-PinTSOP  
(NormalType)  
48-PinTSOP  
(NormalType)  
48-ball CSP  
(Ball Size:0.3mm)  
48-ball CSP  
(Ball Size:0.3mm)  
48-ball CSP  
(Ball Size:0.4mm)  
48-ball CSP  
(Ball Size:0.4mm)  
48-ball CSP  
(Ball Pitch:0.5mm,  
Ball Size:0.3mm)  
48-ball CSP  
MX29SL800CBXHC-90  
90  
12  
5
(Ball Pitch:0.5mm,  
Ball Size:0.3mm)  
48-PinTSOP  
MX29SL800CTTI-90  
MX29SL800CBTI-90  
MX29SL800CTXBI-90  
MX29SL800CBXBI-90  
MX29SL800CTXEI-90  
MX29SL800CBXEI-90  
MX29SL800CTXHI-90  
90  
90  
90  
90  
90  
90  
90  
12  
12  
12  
12  
12  
12  
12  
5
5
5
5
5
5
5
(NormalType)  
48-PinTSOP  
(NormalType)  
48-ball CSP  
(Ball Size:0.3mm)  
48-ball CSP  
(Ball Size:0.3mm)  
48-ball CSP  
(Ball Size:0.4mm)  
48-ball CSP  
(Ball Size:0.4mm)  
48-ball CSP  
(Ball Pitch:0.5mm,  
Ball Size:0.3mm)  
48-ball CSP  
MX29SL800CBXHI-90  
90  
12  
5
(Ball Pitch:0.5mm,  
Ball Size:0.3mm)  
P/N:PM1224  
REV. 1.0, APR. 20, 2006  
57  
MX29SL800C T/B  
PART NAME DESCRIPTION  
MX 29 SL 800 C T T C 90 G  
OPTION:  
G: Lead-free package  
blank: normal  
SPEED:  
90: 90ns  
TEMPERATURE RANGE:  
C: Commercial (0˚C to 70˚C)  
I: Industrial (-40˚C to 85˚C)  
PACKAGE:  
T: TSOP  
XB: CSP (0.8mm ball pitch, 0.3mm ball size)  
XE: CSP (0.8mm ball pitch, 0.4mm ball size)  
XH: CSP (0.5mm ball pitch, 0.3mm ball size)  
BOOT BLOCK TYPE:  
T: Top Boot  
B: Bottom Boot  
REVISION:  
C
DENSITY & MODE:  
800: 8M, x8/x16 Boot Block  
TYPE:  
SL: 1.8V  
DEVICE:  
29: Flash  
P/N:PM1224  
REV. 1.0, APR. 20, 2006  
58  
MX29SL800C T/B  
PACKAGE INFORMATION  
P/N:PM1224  
REV. 1.0, APR. 20, 2006  
59  
MX29SL800C T/B  
P/N:PM1224  
REV. 1.0, APR. 20, 2006  
60  
MX29SL800C T/B  
P/N:PM1224  
REV. 1.0, APR. 20, 2006  
61  
MX29SL800C T/B  
P/N:PM1224  
REV. 1.0, APR. 20, 2006  
62  
MX29SL800C T/B  
REVISION HISTORY  
Revision No. Description  
Page  
Date  
1.0  
1. Removed "Preliminary" title  
P1  
APR/20/2006  
P/N:PM1224  
REV. 1.0, APR. 20, 2006  
63  
MX29SL800C T/B  
MACRONIX INTERNATIONALCO., LTD.  
Headquarters:  
TEL:+886-3-578-6688  
FAX:+886-3-563-2888  
Europe Office :  
TEL:+32-2-456-8020  
FAX:+32-2-456-8021  
Hong Kong Office :  
TEL:+86-755-834-335-79  
FAX:+86-755-834-380-78  
Japan Office :  
Kawasaki Office :  
TEL:+81-44-246-9100  
FAX:+81-44-246-9105  
Osaka Office :  
TEL:+81-6-4807-5460  
FAX:+81-6-4807-5461  
Singapore Office :  
TEL:+65-6346-5505  
FAX:+65-6348-8096  
Taipei Office :  
TEL:+886-2-2509-3300  
FAX:+886-2-2509-2200  
MACRONIX AMERICA, INC.  
TEL:+1-408-262-8887  
FAX:+1-408-262-8810  
http : //www.macronix.com  
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.  

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