MX66L51235FXDI-10G_技术文档

MX66L51235F

3V, 512M-BIT [x 1/x 2/x 4]

CMOS MXSMIO^®(SERIAL MULTI I/O)

FLASH MEMORY

Key Features

• Multi I/O Support - Single I/O, Dual I/O, and Quad I/O

• Quad Peripheral Interface (QPI)

• Program/Erase Suspend and Resume operation

P/N: PM1832

MX66L51235F

Contents

1. FEATURES ..............................................................................................................................................................5

2. GENERAL DESCRIPTION .....................................................................................................................................6

Table 1. Read performance Comparison ....................................................................................................6

3. PIN CONFIGURATIONS .........................................................................................................................................7

4. PIN DESCRIPTION..................................................................................................................................................7

5. BLOCK DIAGRAM...................................................................................................................................................8

6. DATA PROTECTION................................................................................................................................................9

Table 2. Protected Area Sizes...................................................................................................................10

Table 3. 4K-bit Secured OTP Deﬁnition ....................................................................................................11

7. Memory Organization...........................................................................................................................................12

Table 4. Memory Organization ..................................................................................................................12

8. DEVICE OPERATION............................................................................................................................................13

8-1. Address Protocol ..................................................................................................................................... 15

8-2. Quad Peripheral Interface (QPI) Read Mode .......................................................................................... 17

9. COMMAND DESCRIPTION...................................................................................................................................18

Table 5. Command Set..............................................................................................................................18

9-1. Write Enable (WREN).............................................................................................................................. 23

9-2. Write Disable (WRDI)............................................................................................................................... 24

9-3. Read Identiﬁcation (RDID)....................................................................................................................... 25

9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES) ........................................... 26

9-5. Read Electronic Manufacturer ID & Device ID (REMS)........................................................................... 28

9-6. QPI ID Read (QPIID) ............................................................................................................................... 29

Table 6. ID Deﬁnitions ..............................................................................................................................29

9-7. Read Status Register (RDSR)................................................................................................................. 30

9-8. Read Conﬁguration Register (RDCR)...................................................................................................... 31

9-9. Write Status Register (WRSR)................................................................................................................. 37

Table 7. Protection Modes.........................................................................................................................38

9-10. Enter 4-byte mode (EN4B) ...................................................................................................................... 41

9-11. Exit 4-byte mode (EX4B) ......................................................................................................................... 41

9-12. Read Data Bytes (READ) ........................................................................................................................ 42

9-13. Read Data Bytes at Higher Speed (FAST_READ) .................................................................................. 43

9-14. Dual Output Read Mode (DREAD).......................................................................................................... 44

9-15. 2 x I/O Read Mode (2READ) ................................................................................................................... 45

9-16. Quad Read Mode (QREAD) .................................................................................................................... 46

9-17. 4 x I/O Read Mode (4READ) ................................................................................................................... 47

9-18. 4 Byte Address Command Set................................................................................................................. 49

9-19. Burst Read............................................................................................................................................... 51

9-20. Performance Enhance Mode................................................................................................................... 52

9-21. Fast Boot ................................................................................................................................................. 55

Table 8. Fast Boot Register (FBR) ............................................................................................................55

9-22. Sector Erase (SE).................................................................................................................................... 58

9-23. Block Erase (BE32K)............................................................................................................................... 59

P/N: PM1832

Rev. 1.1, August 02, 2016

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MX66L51235F

9-24. Block Erase (BE) ..................................................................................................................................... 60

9-25. Chip Erase (CE)....................................................................................................................................... 61

9-26. Page Program (PP) ................................................................................................................................. 62

9-27. 4 x I/O Page Program (4PP).................................................................................................................... 64

9-28. Deep Power-down (DP)........................................................................................................................... 65

9-29. Enter Secured OTP (ENSO).................................................................................................................... 66

9-30. Exit Secured OTP (EXSO)....................................................................................................................... 66

9-31. Read Security Register (RDSCUR)......................................................................................................... 66

9-32. Write Security Register (WRSCUR)......................................................................................................... 66

Table 9. Security Register Deﬁnition .........................................................................................................67

9-33. Write Protection Selection (WPSEL)........................................................................................................ 68

9-34. Advanced Sector Protection .................................................................................................................... 70

9-35. Program/Erase Suspend/Resume........................................................................................................... 78

9-36. Erase Suspend ........................................................................................................................................ 78

9-37. Program Suspend.................................................................................................................................... 78

9-38. Write-Resume.......................................................................................................................................... 80

9-39. No Operation (NOP) ................................................................................................................................ 80

9-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST)) ................................................................... 80

9-41. Read SFDP Mode (RDSFDP).................................................................................................................. 82

Table 9. Signature and Parameter Identiﬁcation Data Values ..................................................................83

Table 10. Parameter Table (0): JEDEC Flash Parameter Tables..............................................................84

Table 11. Parameter Table (1): Macronix Flash Parameter Tables............................................................86

10. RESET..................................................................................................................................................................88

Table 12. Reset Timing-(Power On)..........................................................................................................88

Table 13. Reset Timing-(Other Operation) ................................................................................................88

11. POWER-ON STATE .............................................................................................................................................89

12. ELECTRICAL SPECIFICATIONS........................................................................................................................90

Table 14. ABSOLUTE MAXIMUM RATINGS ............................................................................................90

Table 15. CAPACITANCE TA = 25°C, f = 1.0 MHz....................................................................................90

Table 16. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 2.7V - 3.6V) ........................92

°

Table 17. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 2.7V - 3.6V) .......................93

°

13. OPERATING CONDITIONS.................................................................................................................................94

Table 18. Power-Up/Down Voltage and Timing ........................................................................................96

13-1. INITIAL DELIVERY STATE...................................................................................................................... 96

14. ERASE AND PROGRAMMING PERFORMANCE..............................................................................................97

15. DATA RETENTION ..............................................................................................................................................97

16. LATCH-UP CHARACTERISTICS........................................................................................................................97

17. ORDERING INFORMATION................................................................................................................................98

18. PART NAME DESCRIPTION...............................................................................................................................99

19. PACKAGE INFORMATION................................................................................................................................100

20. REVISION HISTORY .........................................................................................................................................103

P/N: PM1832

Rev. 1.1, August 02, 2016

3

MX66L51235F

Figures

Figure 1. Serial Modes Supported...............................................................................................................................................13

Figure 2. Serial Input Timing........................................................................................................................................................14

Figure 3. Output Timing ...............................................................................................................................................................14

Figure 4. EAR Operation Segments ............................................................................................................................................16

Figure 5. Enable QPI Sequence..................................................................................................................................................17

Figure 6. Reset QPI Mode...........................................................................................................................................................17

Figure 7. Write Enable (WREN) Sequence (SPI Mode) ..............................................................................................................23

Figure 8. Write Enable (WREN) Sequence (QPI Mode)..............................................................................................................23

Figure 9. Write Disable (WRDI) Sequence (SPI Mode)...............................................................................................................24

Figure 10. Write Disable (WRDI) Sequence (QPI Mode).............................................................................................................25

Figure 11. Read Identiﬁcation (RDID) Sequence (SPI mode only)..............................................................................................25

Figure 12. Read Electronic Signature (RES) Sequence (SPI Mode)...........................................................................................26

Figure 13. Read Electronic Signature (RES) Sequence (QPI Mode) .........................................................................................27

Figure 14. Release from Deep Power-down (RDP) Sequence (SPI Mode) ................................................................................27

Figure 15. Release from Deep Power-down (RDP) Sequence (QPI Mode)................................................................................27

Figure 16. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only) ......................................................28

Figure 17. Read Status Register (RDSR) Sequence (SPI Mode) ...............................................................................................30

Figure 18. Read Status Register (RDSR) Sequence (QPI Mode)...............................................................................................30

Figure 19. Read Conﬁguration Register (RDCR) Sequence (SPI Mode)....................................................................................31

Figure 20. Read Conﬁguration Register (RDCR) Sequence (QPI Mode)....................................................................................31

Figure 21. Program/Erase ﬂow with read array data ...................................................................................................................32

Figure 22. Program/Erase ﬂow without read array data (read P_FAIL/E_FAIL ﬂag) ...................................................................33

Figure 23. Write Status Register (WRSR) Sequence (SPI Mode)..............................................................................................37

Figure 24. Write Status Register (WRSR) Sequence (QPI Mode)..............................................................................................37

Figure 25. WRSR ﬂow .................................................................................................................................................................39

Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1 ..........................................................................40

Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)...............................................................................................42

Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode) ...................................................................................43

Figure 29. Dual Read Mode Sequence .......................................................................................................................................44

Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only) .........................................................................................................45

Figure 31. Quad Read Mode Sequence......................................................................................................................................46

Figure 32. 4 x I/O Read Mode Sequence (SPI Mode).................................................................................................................48

Figure 33. 4 x I/O Read Mode Sequence (QPI Mode).................................................................................................................48

Figure 34. Read Data Bytes using 4 Byte Address Sequence (READ4B)...................................................................................49

Figure 35. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (FASTREAD4B)...............................................49

Figure 36. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B)................................................................................50

Figure 37. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B)...................................................................................50

Figure 38. SPI Mode....................................................................................................................................................................51

Figure 39. QPI Mode ...................................................................................................................................................................51

Figure 40. 4 x I/O Read performance enhance Mode Sequence (SPI Mode) ............................................................................53

Figure 41. 4 x I/O Read performance enhance Mode Sequence (QPI Mode) ............................................................................54

Figure 42. Fast Boot Sequence (QE Bit=0).................................................................................................................................56

Figure 43. Fast Boot Sequence (QE Bit=1).................................................................................................................................56

Figure 44. Read Fast Boot Register (RDFBR) Sequence ...........................................................................................................57

Figure 45. Write Fast Boot Register (WRFBR) Sequence...........................................................................................................57

Figure 46. Erase Fast Boot Register (ESFBR) Sequence...........................................................................................................57

Figure 47. Sector Erase (SE) Sequence (SPI Mode) ..................................................................................................................58

Figure 48. Sector Erase (SE) Sequence (QPI Mode)..................................................................................................................58

Figure 49. Block Erase 32KB (BE32K) Sequence (SPI Mode)....................................................................................................59

Figure 50. Block Erase 32KB (BE32K) Sequence (QPI Mode) ...................................................................................................59

Figure 51. Block Erase (BE) Sequence (SPI Mode)....................................................................................................................60

Figure 52. Block Erase (BE) Sequence (QPI Mode) ...................................................................................................................60

Figure 53. Chip Erase (CE) Sequence (SPI Mode).....................................................................................................................61

Figure 54. Chip Erase (CE) Sequence (QPI Mode).....................................................................................................................61

Figure 55. Page Program (PP) Sequence (SPI Mode)................................................................................................................63

Figure 56. Page Program (PP) Sequence (QPI Mode) ...............................................................................................................63

Figure 57. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)...........................................................................................64

Figure 58. Deep Power-down (DP) Sequence (SPI Mode) .........................................................................................................65

Figure 59. Deep Power-down (DP) Sequence (QPI Mode)........................................................................................................65

Figure 60. WPSEL Flow...............................................................................................................................................................69

Figure 61. Advanced Sector Protection Overview .......................................................................................................................70

Figure 63. Read Lock Register (RDLR) Sequence......................................................................................................................71

Figure 62. Write Lock Register (WRLR) Sequence (SPI Mode)..................................................................................................71

Figure 64. SPB Lock Bit Set (SPBLK) Sequence........................................................................................................................72

Figure 65. Read SPB Lock Register (RDSPBLK) Sequence ......................................................................................................72

Figure 66. Read SPB Status (RDSPB) Sequence.......................................................................................................................74

Figure 67. SPB Erase (ESSPB) Sequence .................................................................................................................................74

Figure 68. SPB Program (WRSPB) Sequence............................................................................................................................74

Figure 69. Read DPB Register (RDDPB) Sequence...................................................................................................................75

Figure 70. Write DPB Register (WRDPB) Sequence...................................................................................................................75

Figure 71. Suspend to Read Latency ..........................................................................................................................................79

Figure 72. Resume to Read Latency...........................................................................................................................................79

Figure 73. Resume to Suspend Latency .....................................................................................................................................79

Figure 74. Software Reset Recovery...........................................................................................................................................81

Figure 75. Reset Sequence (SPI mode)......................................................................................................................................81

Figure 76. Reset Sequence (QPI mode) .....................................................................................................................................81

Figure 77. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence............................................................................82

Figure 78. RESET Timing............................................................................................................................................................88

Figure 79. Maximum Negative Overshoot Waveform..................................................................................................................90

Figure 80. Maximum Positive Overshoot Waveform....................................................................................................................90

Figure 81. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL.....................................................................................91

Figure 82. OUTPUT LOADING...................................................................................................................................................91

Figure 83. AC Timing at Device Power-Up ..................................................................................................................................94

Figure 84. Power-Down Sequence..............................................................................................................................................95

Figure 85. Power-up Timing.........................................................................................................................................................95

Figure 86. Power Up/Down and Voltage Drop.............................................................................................................................96

P/N: PM1832

Rev. 1.1, August 02, 2016

4

MX66L51235F

3V 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO^®(SERIAL MULTI I/O)

FLASH MEMORY

1. FEATURES

GENERAL

•

Command Reset

•

Supports Serial Peripheral Interface -- Mode 0 and

Mode 3

Program/Erase Suspend and Resume operation

Electronic Identiﬁcation

•

Single Power Supply Operation

- 2.7 to 3.6 volt for read, erase, and program opera-

tions

JEDEC 1-byte manufacturer ID and 2-byte device

ID

-

- RES command for 1-byte Device ID

- REMS command for 1-byte manufacturer ID and

1-byte device ID

Support Serial Flash Discoverable Parameters

(SFDP) mode

•

536,870,912 x 1 bit structure or 268,435,456 x 2 bits

(two I/O mode) structure or 134,217,728 x 4 bits (four

I/O mode) structure

•

Protocol Support

- Single I/O, Dual I/O and Quad I/O

Latch-up protected to 100mA from -1V to Vcc +1V

Low Vcc write inhibit is from 2.3V to 2.5V

Fast read for SPI mode

HARDWARE FEATURES

•

SCLK Input

- Serial clock input

•

SI/SIO0

- Support clock frequency up to 133MHz for all

protocols

- Serial Data Input or Serial Data Input/Output for 2

x I/O read mode and 4 x I/O read mode

SO/SIO1

- Serial Data Output or Serial Data Input/Output for

2 x I/O read mode and 4 x I/O read mode

WP#/SIO2

- Hardware write protection or serial data Input/Out-

put for 4 x I/O read mode

DNU/SIO3

- Support Fast Read, 2READ, DREAD, 4READ,

QREAD instructions.

- Conﬁgurable dummy cycle number for fast read

operation

Quad Peripheral Interface (QPI) available

Equal Sectors with 4K byte each, or Equal Blocks

with 32K byte each or Equal Blocks with 64K byte

each

•

- Do not use or serial data Input/Output for 4 x I/O

read mode

- Any Block can be erased individually

Programming :

•

RESET#

- Hardware Reset pin

PACKAGE

- 256byte page buffer

- Quad Input/Output page program(4PP) to enhance

program performance

-16-pin SOP (300mil)

-8-land WSON (8x6mm)

•

Typical 100,000 erase/program cycles

20 years data retention

-24-Ball BGA (5x5 ball array)

-All devices are RoHS Compliant and Halogen-

free

SOFTWARE FEATURES

•

Input Data Format

- 1-byte Command code

•

Advanced Security Features

- Block lock protection

The BP0-BP3 and T/B status bits deﬁne the size of

the area to be protected against program and erase

instructions

- Advanced sector protection function (Solid and

Password Protect)

•

Additional 4K bit security OTP

Features unique identiﬁer

factory locked identiﬁable, and customer lockable

-

P/N: PM1832

Rev. 1.1, August 02, 2016

5

MX66L51235F

2. GENERAL DESCRIPTION

MX66L51235F is 512Mb bits Serial NOR Flash memory, which is conﬁgured as 67,108,864 x 8 internally. When it is

in two or four I/O mode, the structure becomes 268,435,456 bits x 2 or 134,217,728 bits x 4.

MX66L51235F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire

bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a

serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits

input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0

pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX66L51235F MXSMIO^®(Serial Multi I/O) provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the

speciﬁed page or sector/block locations will be executed. Program command is executed on byte basis, or page (256

bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte),

or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read

command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for

more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX66L51235F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after

100,000 program and erase cycles.

Table 1. Read performance Comparison

Dual Output

Fast Read

(MHz)

Quad Output

Fast Read

(MHz)

Dual IO

Fast Read

(MHz)

Quad IO

Fast Read

(MHz)

Numbers of

Dummy Cycles

Fast Read

(MHz)

4

6

-

84*

104

133

70

104

104*

133

104

104*

133

84

84*

104

133

8

104*

133

10

Note: * mean default status

P/N: PM1832

Rev. 1.1, August 02, 2016

6

MX66L51235F

4. PIN DESCRIPTION

3. PIN CONFIGURATIONS

16-PIN SOP (300mil)

SYMBOL

DESCRIPTION

CS#

Chip Select

1

2

3

4

5

6

7

8

SCLK

SI/SIO0

NC

DNU/SIO3

VCC

16

15

14

13

12

11

10

9

Serial Data Input (for 1 x I/O)/ Serial

Data Input & Output (for 2xI/O or

4xI/O read mode)

Serial Data Output (for 1 x I/O)/

Serial Data Input & Output (for 2xI/O

or 4xI/O read mode)

SI/SIO0

RESET#

NC

GND

WP#/SIO2

CS#

SO/SIO1

SCLK

SO/SIO1

Clock Input

Write protection: connect to GND or

Serial Data Input & Output (for 4xI/O

read mode)

WP#/SIO2

8-WSON (8x6mm)

Hardware Reset Pin Active low or

Serial Data Input & Output (for 4xI/O

read mode)^N₁^ote

RESET#/SIO3

(8WSON)

1

VCC

CS#

SO/SIO1

WP#/SIO2

GND

8

7

6

5

2

3

4

RESET#/SIO3

SCLK

DNU/SIO3 ^{Note 2}Do Not Use or Serial Data Input &

(16SOP, 24BGA) Output (for 4xI/O read mode)

SI/SIO0

VCC

+ 3V Power Supply

GND

Ground

Notes:

(1). RESET# pin has internal pull up.

(2). When using 1 I/O or 2 I/O (QE bit not enabled), the

DNU/SIO3 pin of 16SOP & 24BGA can not connect

to GND. We suggest user to connect this pin to

VCC or ﬂoating.

24-BALL BGA (5x5 ball array)

5

NC

4

3

2

1

DNU/SIO3

RESET#

VCC

WP#/SIO2

NC

GND

NC

SI/SIO0

NC

SCLK

NC

SO/SIO1

NC

CS#

NC

A

B

C

D

E

P/N: PM1832

Rev. 1.1, August 02, 2016

7

MX66L51235F

5. BLOCK DIAGRAM

Address

Generator

Memory Array

Page Buffer

Data

Register

SI/SIO0

Y-Decoder

SRAM

Buffer

Sense

Amplifier

CS#

WP#/SIO2

Reset#/SIO3*⁽¹⁾

DNU/SIO3*⁽²⁾

Mode

Logic

State

Machine

HV

Generator

SCLK

Clock Generator

Output

Buffer

SO/SIO1

Notes:

(1). For 8WSON.

(2). For 16SOP or 24BGA.

P/N: PM1832

Rev. 1.1, August 02, 2016

8

MX66L51235F

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after speciﬁc command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

•

Deep Power Down Mode: By entering deep power down mode, the ﬂash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic

Signature command (RES), and softreset command.

Advanced Security Features: there are some protection and security features which protect content from

inadvertent write and hostile access.

I. Block lock protection

- The Software Protected Mode (SPM) use (BP3, BP2, BP1, BP0 and T/B) bits to allow part of memory to be

protected as read only. The protected area deﬁnition is shown as Table 2 Protected Area Sizes, the protected

areas are more ﬂexible which may protect various area by setting value of BP0-BP3 bits.

- The Hardware Proteced Mode (HPM) use WP#/SIO2 to protect the (BP3, BP2, BP1, BP0) bits and Status

Register Write Protect bit.

- In four I/O and QPI mode, the feature of HPM will be disabled.

P/N: PM1832

Rev. 1.1, August 02, 2016

9

MX66L51235F

Table 2. Protected Area Sizes

Protected Area Sizes (T/B bit = 0)

Status bit

Protect Level

512Mb

BP3

0

BP2

0

BP1

0

BP0

0

0 (none)

0

1

1 (1 block, protected block 1023rd)

0

1

0

2 (2 blocks, protected block 1022nd~1023rd)

3 (4 blocks, protected block 1020th~1023rd)

4 (8 blocks, protected block 1016th~1023rd)

5 (16 blocks, protected block 1008th~1023rd)

6 (32 blocks, protected block 992nd~1023rd)

7 (64 blocks, protected block 960th~1023rd)

8 (128 blocks, protected block 896th~1023rd)

9 (256 blocks, protected block 768th~1023rd)

10 (512 blocks, protected block 512nd~1023rd)

11 (1024 blocks, protected all)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

12 (1024 blocks, protected all)

1

0

1

13 (1024 blocks, protected all)

1

0

14 (1024 blocks, protected all)

1

15 (1024 blocks, protected all)

Protected Area Sizes (T/B bit = 1)

Status bit

Protect Level

512Mb

BP3

0

BP2

0

BP1

0

BP0

0

0 (none)

0

1

1 (1 block, protected block 0th)

2 (2 blocks, protected block 0th~1th)

3 (4 blocks, protected block 0th~3rd)

4 (8 blocks, protected block 0th~7th)

5 (16 blocks, protected block 0th~15th)

6 (32 blocks, protected block 0th~31st)

7 (64 blocks, protected block 0th~63rd)

8 (128 blocks, protected block 0th~127th)

9 (256 blocks, protected block 0th~255th)

10 (512 blocks, protected block 0th~511st)

11 (1024 blocks, protected all)

12 (1024 blocks, protected all)

13 (1024 blocks, protected all)

14 (1024 blocks, protected all)

15 (1024 blocks, protected all)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P/N: PM1832

Rev. 1.1, August 02, 2016

10

MX66L51235F

II. Additional 4K-bit secured OTP for unique identiﬁer: to provide 4K-bit one-time program area for setting

device unique serial number - Which may be set by factory or system customer.

- Security register bit 0 indicates whether the chip is locked by factory or not.

- To program the 4K-bit secured OTP by entering 4K-bit secured OTP mode (with Enter Security OTP command),

and going through normal program procedure, and then exiting 4K-bit secured OTP mode by writing Exit Security

OTP command.

- Customer may lock-down the customer lockable secured OTP by writing WRSCUR(write security register)

command to set customer lock-down bit1 as "1". Please refer to "Table 9. Security Register Deﬁnition" for

security register bit deﬁnition and "Table 3. 4K-bit Secured OTP Deﬁnition" for address range deﬁnition.

- Note: Once lock-down whatever by factory or customer, it cannot be changed any more. While in 4K-bit secured

OTP mode, array access is not allowed.

Table 3. 4K-bit Secured OTP Deﬁnition

Address range

xxx000~xxx00F

xxx010~xxx1FF

Size

Standard Factory Lock

ESN (electrical serial number)

N/A

Customer Lock

128-bit

3968-bit

Determined by customer

P/N: PM1832

Rev. 1.1, August 02, 2016

11

MX66L51235F

7. Memory Organization

Table 4. Memory Organization

Block(64K-byte) Block(32K-byte)

Sector

16383

Address Range

3FFF000h

3FFFFFFh

2047

individual 16 sectors

lock/unlock unit:4K-byte

16376

16375

3FF8000h

3FF7000h

3FF8FFFh

3FF7FFFh

1023

2046

2045

2044

2043

2042

16368

16367

3FF0000h

3FEF000h

3FF0FFFh

3FEFFFFh

16360

16359

3FE8000h

3FE7000h

3FE8FFFh

3FE7FFFh

1022

individual block

lock/unlock unit:64K-byte

16352

16351

3FE0000h

3FDF000h

3FE0FFFh

3FDFFFFh

16344

16343

3FD8000h

3FD7000h

3FD8FFFh

3FD7FFFh

1021

16336

3FD0000h

3FD0FFFh

individual block

lock/unlock unit:64K-byte

47

002F000h

002FFFFh

5

4

3

2

1

0

40

39

0028000h

027000h

0028FFFh

0027FFFh

2

1

individual block

lock/unlock unit:64K-byte

32

31

0020000h

001F000h

0020FFFh

001FFFFh

24

23

0018000h

0017000h

0018FFFh

0017FFFh

16

15

0010000h

000F000h

0010FFFh

000FFFFh

individual 16 sectors

lock/unlock unit:4K-byte

8

7

0008000h

0007000h

0008FFFh

0007FFFh

0

0000000h

0000FFFh

P/N: PM1832

Rev. 1.1, August 02, 2016

12

MX66L51235F

8. DEVICE OPERATION

1. Before a command is issued, status register should be checked to ensure device is ready for the intended

operation.

2. When incorrect command is inputted to this device, this device becomes standby mode and keeps the standby

mode until next CS# falling edge. In standby mode, SO pin of this device should be High-Z.

3. When correct command is inputted to this device, this device becomes active mode and keeps the active mode

until next CS# rising edge.

4. Input data is latched on the rising edge of Serial Clock (SCLK) and data shifts out on the falling edge of SCLK.

The difference of Serial mode 0 and mode 3 is shown as "Serial Modes Supported".

5. For the following instructions: RDID, RDSR, RDSCUR, READ/READ4B, FAST_READ/FAST_READ4B,

2READ/2READ4B, DREAD/DREAD4B, 4READ/4READ4B, QREAD/QREAD4B, RDSFDP, RES, REMS, QPIID,

RDDPB, RDSPB, RDPASS, RDLR, RDEAR, RDFBR, RDSPBLK, RDCR, the shifted-in instruction sequence is

followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following

instructions: WREN, WRDI, WRSR, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, PP/PP4B, 4PP/4PP4B, DP,

ENSO, EXSO, WRSCUR, EN4B, EX4B, WPSEL, GBLK, GBULK, SPBLK, SUSPEND, RESUME, NOP, RSTEN,

RST, EQIO, RSTQIO the CS# must go high exactly at the byte boundary; otherwise, the instruction will be

rejected and not executed.

6. During the progress of Write Status Register, Program, Erase operation, to access the memory array is

neglected and not affect the current operation of Write Status Register, Program, Erase.

Figure 1. Serial Modes Supported

CPOL CPHA

shift in

shift out

SCLK

(Serial mode 0)

(Serial mode 3)

0

1

0

1

SI

MSB

SO

MSB

Note:

CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not

transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is

supported.

P/N: PM1832

Rev. 1.1, August 02, 2016

13

MX66L51235F

Figure 2. Serial Input Timing

tSHSL

tSHCH

tCHCL

CS#

tCHSL

tSLCH

tCHSH

SCLK

tDVCH

tCHDX

tCLCH

MSB

LSB

SI

High-Z

SO

Figure 3. Output Timing

CS#

tCH

SCLK

tCLQV

tCL

tSHQZ

tCLQX

SO

tCLQX

LSB

ADDR.LSB IN

SI

P/N: PM1832

Rev. 1.1, August 02, 2016

14

MX66L51235F

8-1. Address Protocol

The original 24 bit address protocol of serial Flash can only access density size below 128Mb. For the memory

above 128Mb, the 32bit address is requested for access higher memory size. The MX66L51235F has three different

methods ot access the whole density:

(1)Command entry 4-byte address mode

(2)Extended Address Register (EAR)

(3)4-byte Address Command Set

Enter 4-Byte Address Mode

In 4-byte Address mode, all instructions are 32-bits address clock cycles. Two dedicated instructions are available

to enter/exit this modality:

● Enter 4-byte address mode (EN4B)

● Exit 4-byte address mode (EX4B)

When 4-byte address mode is enabled, the EAR<1-0> becomes "don't care" for all instructions requiring 4-byte

address.

Extended Address Register (Conﬁgurable)

The device provides an 8-bit volatile register for extended Address Register: it indentiﬁes the extended address

(A31~A24) above 128Mb density by using original 3-byte address.

Extended Address Register (EAR)

Bit 7

A31

Bit 6

A30

Bit 5

A29

Bit 4

A28

Bit 3

A27

Bit 2

A26

Bit 1

A25

Bit 0

A24

For the MX66L51235F the A31 to A26 are Don’t Care. During EAR, reading these bits will read as 0. The bit <1-0>

is default as "0".

P/N: PM1832

Rev. 1.1, August 02, 2016

15

MX66L51235F

Figure 4. EAR Operation Segments

03FFFFFFh

EAR<1-0>= 11

03000000h

02FFFFFFh

EAR<1-0>= 10

EAR<1-0>= 01

02000000h

01FFFFFFh

01000000h

00FFFFFFh

EAR<1-0>= 00

00000000h

When under EAR mode, Read, Program, Erase operates in the selected segment by using 3-byte address mode.

For the read operation, the whole array data can be continually read out with one command. Data output starts from

the selected 128Mb, but it can cross the boundary. When the last byte of the segment is reached, the next byte (in

a continuous reading) is the ﬁrst byte of the next segment. However, the EAR (Extended Address Register) value

does not change. The random access reading can only be operated in the selected segment.

The Chip erase command will erase the whole chip and is not limited by EAR selected segment.

P/N: PM1832

Rev. 1.1, August 02, 2016

16

MX66L51235F

8-2. Quad Peripheral Interface (QPI) Read Mode

QPI protocol enables user to take full advantage of Quad I/O Serial Flash by providing the Quad I/O interface in

command cycles, address cycles and as well as data output cycles.

Enable QPI mode

By issuing 35H command, the QPI mode is enable. After QPI mode is enabled, the device enters quad mode (4-4-4)

without QE bit status changed.

Figure 5. Enable QPI Sequence

CS#

MODE 3

MODE 0

2

3

4

5

6

7

0

1

SCLK

SIO0

35h

SIO[3:1]

Reset QPI (RSTQIO)

To reset the QPI mode, the RSTQIO (F5H) command is required. After the RSTQIO command is issued, the device

returns from QPI mode (4 I/O interface in command cycles) to SPI mode (1 I/O interface in command cycles).

Note: For EQIO and RSTQIO commands, CS# high width has to follow "write spec" tSHSL for next instruction.

Figure 6. Reset QPI Mode

CS#

SCLK

SIO[3:0]

F5h

P/N: PM1832

Rev. 1.1, August 02, 2016

17

MX66L51235F

9. COMMAND DESCRIPTION

Table 5. Command Set

Read/Write Array Commands

2READ

(2 x I/O read

command)

Command

(byte)

READ

(normal read)

FAST READ

(fast read data)

DREAD

(1I 2O read)

QREAD

(1I 4O read)

4READ

Mode

Address Bytes

1st byte

SPI

3/4

SPI

3/4

SPI

3/4

SPI

3/4

SPI/QPI

3/4

SPI

3/4

03 (hex)

ADD1

ADD2

ADD3

0B (hex)

ADD1

ADD2

ADD3

Dummy*

BB (hex)

ADD1

ADD2

ADD3

Dummy*

3B (hex)

ADD1

ADD2

ADD3

Dummy*

EB (hex)

ADD1

6B (hex)

ADD1

ADD2

ADD3

Dummy*

2nd byte

3rd byte

ADD2

4th byte

ADD3

5th byte

Dummy*

Data Cycles

n bytes read out n bytes read out n bytes read out n bytes read out

Quad I/O read

with 6 dummy

cycles

n bytes read out

by Quad output

until CS# goes

high

until CS# goes

high

until CS# goes

high

by 2 x I/O until

CS# goes high

by Dual output

until CS# goes

high

Action

4PP

(quad page

program)

BE 32K

(block erase

32KB)

BE

Command

(byte)

PP

SE

CE

(chip erase)

(block erase

64KB)

(page program)

(sector erase)

Mode

Address Bytes

1st byte

SPI/QPI

3/4

SPI

3/4

SPI/QPI

3/4

SPI/QPI

3/4

SPI/QPI

3/4

SPI/QPI

0

02 (hex)

38 (hex)

ADD1

ADD2

ADD3

20 (hex)

ADD1

ADD2

ADD3

52 (hex)

ADD1

ADD2

ADD3

D8 (hex)

ADD1

ADD2

ADD3

60 or C7 (hex)

2nd byte

3rd byte

4th byte

5th byte

1-256

Data Cycles

to program the

selected page

quad input to

program the

selected page

to erase the

selected sector

to erase the

selected 32K

block

to erase the

selected block

to erase whole

chip

Action

* Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in conﬁguration register.

P/N: PM1832

Rev. 1.1, August 02, 2016

18

MX66L51235F

Read/Write Array Commands (4 Byte Address Command Set)

Command

(byte)

READ4B

FAST READ4B

2READ4B

DREAD4B

4READ4B

QREAD4B

Mode

SPI

4

SPI

4

SPI

4

SPI

4

SPI/QPI

4

SPI

4

Address Bytes

1st byte

2nd byte

3rd byte

13 (hex)

0C (hex)

BC (hex)

3C (hex)

EC (hex)

6C (hex)

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

Dummy

ADD1

ADD2

ADD3

ADD4

Dummy

ADD1

ADD2

ADD3

ADD4

Dummy

ADD1

ADD2

ADD3

ADD4

Dummy

ADD1

ADD2

ADD3

ADD4

Dummy

4th byte

5th byte

6th byte

Data Cycles

read data byte by read data byte by read data byte by Read data byte by read data byte by Read data byte by

Action

4 byte address

4 byte address 2 x I/O with 4 byte Dual Output with 4 x I/O with 4 byte Quad Output with

address

4 byte address

address

4 byte address

BE4B

(block erase

64KB)

BE32K4B

(block erase

32KB)

SE4B

(Sector erase

4KB)

Command

(byte)

PP4B

4PP4B

Mode

SPI/QPI

4

SPI

4

SPI/QPI

4

SPI/QPI

4

SPI/QPI

4

Address Bytes

1st byte

2nd byte

3rd byte

12 (hex)

3E (hex)

DC (hex)

5C (hex)

21 (hex)

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

ADD1

ADD2

ADD3

ADD4

4th byte

5th byte

6th byte

Data Cycles

1-256

to program the

selected page

with 4byte

Quad input to

program the

selected page

with 4byte

to erase the

selected (64KB) selected (32KB) selected (4KB)

block with 4byte block with 4byte sector with 4byte

Action

address

P/N: PM1832

Rev. 1.1, August 02, 2016

19

MX66L51235F

Register/Setting Commands

RDCR

(read

WRSR

RDEAR

WREAR

RDSR

(read status

register)

Command

(byte)

WREN

WRDI

(write status/ (read extended (write extended

(write enable) (write disable)

conﬁguration conﬁguration

address

register)

address

register)

SPI/QPI

15 (hex)

register)

SPI/QPI

01 (hex)

Values

Mode

1st byte

SPI/QPI

06 (hex)

SPI/QPI

04 (hex)

SPI/QPI

05 (hex)

SPI/QPI

C8 (hex)

SPI/QPI

C5 (hex)

2nd byte

3rd byte

4th byte

Values

5th byte

Data Cycles

1-2

1

sets the (WEL)

write enable

latch bit

resets the

(WEL) write

enable latch bit status register conﬁguration

to read out the to read out the to write new read extended write extended

values of the values of the values of the

address

register

address

register

status/

conﬁguration

register

Action

register

PGM/ERS

Suspend

(Suspends

Program/

Erase)

PGM/ERS

Resume

(Resumes

Program/

Erase)

WPSEL

(Write Protect

Selection)

EN4B

(enter 4-byte

mode)

EX4B

(exit 4-byte

mode)

Command

(byte)

EQIO

(Enable QPI)

RSTQIO

(Reset QPI)

Mode

1st byte

SPI/QPI

68 (hex)

SPI

QPI

SPI/QPI

B7 (hex)

SPI/QPI

E9 (hex)

SPI/QPI

35 (hex)

F5 (hex)

B0 (hex)

30 (hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

to enter and

Entering the Exiting the QPI to enter 4-byte to exit 4-byte

enable individal QPI mode

block protect

mode

mode and set mode and clear

4BYTE bit as 4BYTE bit to

Action

mode

"1"

be "0"

RDP (Release

DP (Deep

SBL

RDFBR

WRFBR

ESFBR

Command

(byte)

from deep

(Set Burst

Length)

SPI/QPI

(read fast boot (write fast boot (erase fast

power down)

register)

SPI

register)

SPI

boot register)

Mode

1st byte

SPI/QPI

B9 (hex)

SPI/QPI

AB (hex)

SPI

C0 (hex)

16(hex)

17(hex)

18(hex)

2nd byte

3rd byte

4th byte

5th byte

Data Cycles

1-4

4

enters deep

power down

mode

release from

deep power

down mode

to set Burst

length

Action

P/N: PM1832

Rev. 1.1, August 02, 2016

20

MX66L51235F

ID/Security Commands

REMS

(read electronic

manufacturer & (QPI ID Read)

device ID)

RDID

RES

ENSO

EXSO

Command

(byte)

QPIID

(read identiﬁc- (read electronic

RDSFDP

(enter secured (exit secured

ation)

ID)

OTP)

Mode

Address Bytes

SPI

0

SPI/QPI

0

SPI

0

QPI

0

SPI/QPI

3

SPI/QPI

0

SPI/QPI

0

1st byte

2nd byte

3rd byte

4th byte

5th byte

9F (hex)

AB (hex)

90 (hex)

AF (hex)

5A (hex)

B1 (hex)

C1 (hex)

x

ADD1

ADD2

x

ADD1 ^{(Note 1)}

ADD3

Dummy (8)

outputs JEDEC to read out

output the

ID in QPI

interface

Read SFDP

mode

to enter the

4K-bit secured 4K-bit secured

OTP mode

to exit the

ID: 1-byte

Manufacturer

ID & 2-byte

Device ID

1-byte Device Manufacturer

ID

ID & Device ID

OTP mode

Action

WRSCUR

(write

security

register)

SPI/QPI

WRPASS

(write

password

register)

SPI

RDPASS

(read

password

register)

SPI

RDSCUR

(read security

register)

GBLK

GBULK

WRLR

RDLR

Command

(byte)

(gang block (gang block (write Lock (read Lock

lock)

unlock)

register)

Mode

SPI/QPI

0

SPI/QPI

0

SPI/QPI

0

SPI

0

SPI

0

Address Bytes

0

1st byte

2nd byte

3rd byte

2B (hex)

2F (hex)

7E (hex)

98 (hex)

2C (hex)

2D (hex)

28 (hex)

27 (hex)

4th byte

5th byte

Data Cycles

2

1-8

to read value to set the

whole chip whole chip

of security lock-down bit write protect unprotect

register

as "1" (once

lock-down,

cannot be

updated)

Action

PASSULK

(password

unlock)

SPI

WRSPB

(SPB bit

program)

SPI

ESSPB

(all SPB bit (read SPB

erase)

SPI

0

RDSPB

SPBLK

(SPB lock

set)

RDSPBLK

(SPB lock

register read) register)

WRDPB

(write DPB

RDDPB

(read DPB

register)

SPI

Command

(byte)

status)

SPI

4

Mode

SPI

0

SPI

4

Address Bytes

0

4

0

4

1st byte

2nd byte

3rd byte

29 (hex)

E3 (hex)

ADD1

ADD2

ADD3

ADD4

E4 (hex)

E2 (hex)

ADD1

ADD2

ADD3

ADD4

1

A6 (hex)

A7 (hex)

E1 (hex)

ADD1

ADD2

ADD3

ADD4

1

E0 (hex)

ADD1

ADD2

ADD3

ADD4

1

4th byte

5th byte

Data Cycles

8

2

Action

P/N: PM1832

Rev. 1.1, August 02, 2016

21

MX66L51235F

Reset Commands

RST

(Reset

Memory)

Command

(byte)

NOP

RSTEN

(No Operation) (Reset Enable)

Mode

SPI/QPI

00 (hex)

SPI/QPI

66 (hex)

SPI/QPI

99 (hex)

1st byte

2nd byte

3rd byte

4th byte

5th byte

Action

Note 1: The count base is 4-bit for ADD(2) and Dummy(2) because of 2 x I/O. And the MSB is on SO/SIO1 which is different

from 1 x I/O condition.

Note 2: ADD=00H will output the manufacturer ID ﬁrst and AD=01H will output device ID ﬁrst.

Note 3: It is not recommended to adopt any other code not in the command deﬁnition table, which will potentially enter the hid-

den mode.

Note 4: Before executing RST command, RSTEN command must be executed. If there is any other command to interfere, the

reset operation will be disabled.

Note 5: The number in parentheses after "ADD" or "Data" stands for how many clock cycles it has. For example, "Data(8)"

represents there are 8 clock cycles for the data in. Please note the number after "ADD" are based on 3-byte address

mode, for 4-byte address mode, which will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

22

MX66L51235F

9-1. Write Enable (WREN)

The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP/

PP4B, 4PP/4PP4B, SE/SE4B, BE32K/BE32K4B, BE/BE4B, CE, and WRSR, which are intended to change the

device content WEL bit should be set every time after the WREN instruction setting the WEL bit.

The sequence of issuing WREN instruction is: CS# goes low→sending WREN instruction code→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

Figure 7. Write Enable (WREN) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

06h

SI

High-Z

SO

Figure 8. Write Enable (WREN) Sequence (QPI Mode)

CS#

0

1

Mode 3

SCLK

Mode 0

Command

SIO[3:0]

06h

P/N: PM1832

Rev. 1.1, August 02, 2016

23

MX66L51235F

9-2. Write Disable (WRDI)

The Write Disable (WRDI) instruction is to reset Write Enable Latch (WEL) bit.

The sequence of issuing WRDI instruction is: CS# goes low→sending WRDI instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care in

SPI mode.

The WEL bit is reset by following situations:

- Power-up

- Reset# pin driven low

- WRDI command completion

- WRSR command completion

- PP/PP4B command completion

- 4PP/4PP4B command completion

- SE/SE4B command completion

- BE32K/BE32K4B command completion

- BE/BE4B command completion

- CE command completion

- PGM/ERS Suspend command completion

- Reset command completion

- WRSCUR command completion

- WPSEL command completion

- GBLK command completion

- GBULK command completion

- WREAR command completion

- WRLR command completion

- WRPASS command completion

- PASSULK command completion

- SPBLK command completion

- WRSPB command completion

- ESSPB command completion

- WRDPB command completion

- WRFBR command completion

- ESFBR command completion

Figure 9. Write Disable (WRDI) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

Command

04h

SI

High-Z

SO

P/N: PM1832

Rev. 1.1, August 02, 2016

24

MX66L51235F

Figure 10. Write Disable (WRDI) Sequence (QPI Mode)

CS#

0

1

Mode 3

SCLK

Mode 0

Command

SIO[3:0]

04h

9-3. Read Identiﬁcation (RDID)

The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-byte. The Macronix

Manufacturer ID and Device ID are listed as Table 6 ID Deﬁnitions.

The sequence of issuing RDID instruction is: CS# goes low→ sending RDID instruction code→24-bits ID data out

on SO→ to end RDID operation can drive CS# to high at any time during data out.

While Program/Erase operation is in progress, it will not decode the RDID instruction, therefore there's no effect on

the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at standby

stage.

Figure 11. Read Identiﬁcation (RDID) Sequence (SPI mode only)

CS#

0

1

2

3

4

5

6

7

8

9

10

13 14 15 16 17 18

28 29 30 31

Mode 3

Mode 0

SCLK

SI

Command

9Fh

Manufacturer Identification

Device Identification

High-Z

SO

7

6

5

2

1

0

15 14 13

MSB

3

2

1

0

MSB

P/N: PM1832

Rev. 1.1, August 02, 2016

25

MX66L51235F

9-4. Release from Deep Power-down (RDP), Read Electronic Signature (RES)

The Release from Deep Power-down (RDP) instruction is completed by driving Chip Select (CS#) High. When Chip

Select (CS#) is driven High, the device is put in the Stand-by Power mode. If the device was not previously in the

Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was previously in

the Deep Power-down mode, though, the transition to the Stand-by Power mode is delayed by tRES2, and Chip

Select (CS#) must remain High for at least tRES2(max), as speciﬁed in Table 17 AC Characteristics. Once in the

Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. The

RDP instruction is only for releasing from Deep Power Down Mode. Reset# pin goes low will release the Flash from

deep power down mode.

RES instruction is for reading out the old style of 8-bit Electronic Signature, whose values are shown as Table 6 ID

Deﬁnitions. This is not the same as RDID instruction. It is not recommended to use for new design. For new design,

please use RDID instruction.

Even in Deep power-down mode, the RDP and RES are also allowed to be executed, only except the device is in

progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The RES instruction is ended by CS# goes high after the ID been read out at least once. The ID outputs repeatedly

if continuously send the additional clock cycles on SCLK while CS# is at low. If the device was not previously in

Deep Power-down mode, the device transition to standby mode is immediate. If the device was previously in Deep

Power-down mode, there's a delay of tRES2 to transit to standby mode, and CS# must remain to high at least

tRES2(max). Once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute

instruction.

Figure 12. Read Electronic Signature (RES) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38

SCLK

Command

ABh

t

3 Dummy Bytes

RES2

SI

23 22 21

MSB

3

2

1

0

Electronic Signature Out

High-Z

7

6

5

4

3

2

0

1

SO

MSB

Deep Power-down Mode

Stand-by Mode

P/N: PM1832

Rev. 1.1, August 02, 2016

26

MX66L51235F

Figure 13. Read Electronic Signature (RES) Sequence (QPI Mode)

CS#

MODE 3

0

1

2

3

4

5

6

7

SCLK

MODE 0

3 Dummy Bytes

Command

ABh

SIO[3:0]

X

H0 L0

MSB LSB

Data Out

Data In

Stand-by Mode

Deep Power-down Mode

Figure 14. Release from Deep Power-down (RDP) Sequence (SPI Mode)

CS#

t

RES1

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

SI

Command

ABh

High-Z

SO

Deep Power-down Mode

Stand-by Mode

Figure 15. Release from Deep Power-down (RDP) Sequence (QPI Mode)

CS#

t

RES1

Mode 3

Mode 0

0

1

SCLK

Command

SIO[3:0]

ABh

Deep Power-down Mode

Stand-by Mode

P/N: PM1832

Rev. 1.1, August 02, 2016

27

MX66L51235F

9-5. Read Electronic Manufacturer ID & Device ID (REMS)

The REMS instruction is an alternative to the Release from Power-down/Device ID instruction that provides both the

JEDEC assigned manufacturer ID and the speciﬁc device ID.

The REMS instruction is very similar to the Release from Power-down/Device ID instruction. The instruction is

initiated by driving the CS# pin low and shift the instruction code "90h" followed by two dummy bytes and one

bytes address (A7~A0). After which, the Manufacturer ID for Macronix (C2h) and the Device ID are shifted out

on the falling edge of SCLK with most signiﬁcant bit (MSB) ﬁrst. The Device ID values are listed in Table 6 of ID

Deﬁnitions. If the one-byte address is initially set to 01h, then the device ID will be read ﬁrst and then followed by the

Manufacturer ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The

instruction is completed by driving CS# high.

Figure 16. Read Electronic Manufacturer & Device ID (REMS) Sequence (SPI Mode only)

CS#

0

1

2

3

4

5

6

7

8

9 10

Mode 3

Mode 0

SCLK

Command

90h

2 Dummy Bytes

SI

15 14 13

3

2

1

0

High-Z

SO

CS#

47

28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

ADD (1)

7

6

5

4

3

2

0

1

SI

Manufacturer ID

Device ID

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Notes:

(1) ADD=00H will output the manufacturer's ID ﬁrst and ADD=01H will output device ID ﬁrst.

P/N: PM1832

Rev. 1.1, August 02, 2016

28

MX66L51235F

9-6. QPI ID Read (QPIID)

User can execute this QPIID Read instruction to identify the Device ID and Manufacturer ID. The sequence of issue

QPIID instruction is CS# goes low→sending QPI ID instruction→Data out on SO→CS# goes high. Most signiﬁcant

bit (MSB) ﬁrst.

After the command cycle, the device will immediately output data on the falling edge of SCLK. The manufacturer ID,

memory type, and device ID data byte will be output continuously, until the CS# goes high.

Table 6. ID Deﬁnitions

Command Type

MX66L51235F

Manufactory ID

C2

Memory type

Memory density

1A

RDID

RES

9Fh

20

Electronic ID

19

Device ID

19

ABh

90h

AFh

Manufactory ID

REMS

QPIID

C2

Manufactory ID

C2

Memory type

20

Memory density

1A

P/N: PM1832

Rev. 1.1, August 02, 2016

29

MX66L51235F

9-7. Read Status Register (RDSR)

The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even

in program/erase/write status register condition). It is recommended to check the Write in Progress (WIP) bit before

sending a new instruction when a program, erase, or write status register operation is in progress.

The sequence of issuing RDSR instruction is: CS# goes low→ sending RDSR instruction code→ Status Register data

out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 17. Read Status Register (RDSR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

05h

Status Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 18. Read Status Register (RDSR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

N

SCLK

SIO[3:0]

05h

H0 L0 H0 L0 H0 L0

H0 L0

MSB

LSB

Status Byte Status Byte Status Byte

Status Byte

P/N: PM1832

Rev. 1.1, August 02, 2016

30

MX66L51235F

9-8. Read Conﬁguration Register (RDCR)

The RDCR instruction is for reading Conﬁguration Register Bits. The Read Conﬁguration Register can be read at

any time (even in program/erase/write conﬁguration register condition). It is recommended to check the Write in

Progress (WIP) bit before sending a new instruction when a program, erase, or write conﬁguration register operation

is in progress.

The sequence of issuing RDCR instruction is: CS# goes low→ sending RDCR instruction code→ Conﬁguration

Register data out on SO.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Figure 19. Read Conﬁguration Register (RDCR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

15h

Configuration register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Figure 20. Read Conﬁguration Register (RDCR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

N

0

1

2

3

4

5

6

7

SCLK

SIO[3:0]

15h

H0 L0 H0 L0 H0 L0

H0 L0

MSB

LSB

Config. Byte Config. Byte Config. Byte

Config. Byte

P/N: PM1832

Rev. 1.1, August 02, 2016

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MX66L51235F

For user to check if Program/Erase operation is ﬁnished or not, RDSR instruction ﬂow are shown as follows:

Figure 21. Program/Erase ﬂow with read array data

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

Read array data

(same address of PGM/ERS)

No

Verify OK?

Yes

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

No

Program/erase completed

P/N: PM1832

Rev. 1.1, August 02, 2016

32

MX66L51235F

Figure 22. Program/Erase ﬂow without read array data (read P_FAIL/E_FAIL ﬂag)

start

WREN command

RDSR command*

No

WEL=1?

Yes

Program/erase command

Write program data/address

(Write erase address)

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

RDSCUR command

P_FAIL/E_FAIL =1 ?

Yes

No

Program/erase successfully

Program/erase fail

Yes

Program/erase

another block?

* Issue RDSR to check BP[3:0].

* If WPSEL = 1, issue RDSPB and RDDPB to check the block status.

No

Program/erase completed

P/N: PM1832

Rev. 1.1, August 02, 2016

33

MX66L51235F

Status Register

The deﬁnition of the status register bits is as below:

WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase/write

status register progress. When WIP bit sets to 1, which means the device is busy in program/erase/write status

register progress. When WIP bit sets to 0, which means the device is not in progress of program/erase/write status

register cycle.

WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable

latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/

erase/write status register instruction. When WEL bit sets to 0, which means no internal write enable latch; the

device will not accept program/erase/write status register instruction. The program/erase command will be ignored

if it is applied to a protected memory area. To ensure both WIP bit & WEL bit are both set to 0 and available for next

program/erase/operations, WIP bit needs to be conﬁrm to be 0 before polling WEL bit. After WIP bit conﬁrmed, WEL

bit needs to be conﬁrm to be 0.

BP3, BP2, BP1, BP0 bits. The Block Protect (BP3, BP2, BP1, BP0) bits, non-volatile bits, indicate the protected area

(as deﬁned in Table 2) of the device to against the program/erase instruction without hardware protection mode being

set. To write the Block Protect (BP3, BP2, BP1, BP0) bits requires the Write Status Register (WRSR) instruction to

be executed. Those bits deﬁne the protected area of the memory to against Page Program (PP), Sector Erase (SE),

Block Erase 32KB (BE32K), Block Erase (BE) and Chip Erase (CE) instructions (only if Block Protect bits (BP3:BP0)

set to 0, the CE instruction can be executed). The BP3, BP2, BP1, BP0 bits are "0" as default. Which is unprotected.

QE bit. The Quad Enable (QE) bit, non-volatile bit, while it is "0" (factory default), it performs non-Quad and WP#,

RESET# are enable. While QE is "1", it performs Quad I/O mode and WP#, RESET# are disabled. In the other

word, if the system goes into four I/O mode (QE=1), the feature of HPM and RESET# will be disabled.

SRWD bit. The Status Register Write Disable (SRWD) bit, non-volatile bit, is operated together with Write Protection

(WP#/SIO2) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and

WP#/SIO2 pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is

no longer accepted for execution and the SRWD bit and Block Protect bits (BP3, BP2, BP1, BP0) are read only. The

SRWD bit defaults to be "0".

Status Register

bit7

bit6

bit5

BP3

(level of

protected

block)

bit4

BP2

(level of

protected

block)

bit3

BP1

(level of

protected

block)

bit2

BP0

(level of

protected

block)

bit1

bit0

SRWD (status

register write

protect)

QE

(Quad

Enable)

WEL

(write enable

latch)

WIP

(write in

progress bit)

1=Quad

Enable

0=not Quad

Enable

1=write

enable

0=not write 0=not in write

1=write

operation

1=status

register write

disable

(note 1)

enable

operation

Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile Non-volatile

bit bit bit bit bit bit

volatile bit

Note 1: see the Table 2 "Protected Area Size".

P/N: PM1832

Rev. 1.1, August 02, 2016

34

MX66L51235F

Conﬁguration Register

The Conﬁguration Register is able to change the default status of Flash memory. Flash memory will be conﬁgured

after the CR bit is set.

ODS bit

The output driver strength (ODS2, ODS1, ODS0) bits are volatile bits, which indicate the output driver level (as

deﬁned in "Output Driver Strength Table") of the device. The Output Driver Strength is defaulted as 30 Ohms when

delivered from factory. To write the ODS bits requires the Write Status Register (WRSR) instruction to be executed.

TB bit

The Top/Bottom (TB) bit is a non-volatile OTP bit. The Top/Bottom (TB) bit is used to conﬁgure the Block Protect

area by BP bit (BP3, BP2, BP1, BP0), starting from TOP or Bottom of the memory array. The TB bit is defaulted as

“0”, which means Top area protect. When it is set as “1”, the protect area will change to Bottom area of the memory

device. To write the TB bits requires the Write Status Register (WRSR) instruction to be executed.

4BYTE Indicator bit

By writing EN4B instruction, the 4BYTE bit may be set as "1" to access the address length of 32-bit for memory area

of higher density (large than 128Mb). The default state is "0" as the 24-bit address mode. The 4BYTE bit may be

cleared by power-off or writing EX4B instruction to reset the state to be "0".

Conﬁguration Register

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

DC1

DC0

TB

ODS 2

ODS 1

ODS 0

(Dummy

cycle 1)

(Dummy

cycle 0)

4 BYTE

Reserved

(top/bottom (output driver (output driver (output driver

selected)

strength)

0=3-byte

address

mode

0=Top area

protect

(note 2)

1=4-byte

address

mode

x

1=Bottom

area protect

(Default=0)

(note 1)

(Default=0)

volatile bit

OTP

volatile bit

Note 1: see "Output Driver Strength Table"

Note 2: see "Dummy Cycle and Frequency Table (MHz)"

P/N: PM1832

Rev. 1.1, August 02, 2016

35

MX66L51235F

Output Driver Strength Table

ODS2

ODS1

ODS0

Description

Reserved

90 Ohms

60 Ohms

45 Ohms

Note

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Impedance at VCC/2

Reserved

20 Ohms

15 Ohms

30 Ohms (Default)

Dummy Cycle and Frequency Table (MHz)

Numbers of Dummy

Dual Output Fast

Quad Output Fast

DC[1:0]

Fast Read

clock cycles

Read

104

133

Read

104

84

104

133

00 (default)

8

6

8

104

133

01

10

11

10

Numbers of Dummy

DC[1:0]

Dual IO Fast Read

clock cycles

00 (default)

4

6

8

84

01

10

11

104

133

10

Numbers of Dummy

DC[1:0]

Quad IO Fast Read

clock cycles

00 (default)

6

4

8

84

70

104

133

01

10

11

10

P/N: PM1832

Rev. 1.1, August 02, 2016

36

MX66L51235F

9-9. Write Status Register (WRSR)

The WRSR instruction is for changing the values of Status Register Bits and Conﬁguration Register Bits. Before

sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write

Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP3, BP2, BP1,

BP0) bits to deﬁne the protected area of memory (as shown in Table 2). The WRSR also can set or reset the Quad

enable (QE) bit and set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#/

SIO2) pin signal, but has no effect on bit1(WEL) and bit0 (WIP) of the status register. The WRSR instruction cannot

be executed once the Hardware Protected Mode (HPM) is entered.

The sequence of issuing WRSR instruction is: CS# goes low→ sending WRSR instruction code→ Status Register

data on SI→CS# goes high.

The CS# must go high exactly at the 8 bits or 16 bits data boundary; otherwise, the instruction will be rejected and

not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes

high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress.

The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write

Enable Latch (WEL) bit is reset.

Figure 23. Write Status Register (WRSR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

SCLK

command

01h

Status

Register In

Configuration

Register In

SI

4

15 14

13

12 11

10 9

8

2

1

0

7

6

5

3

MSB

High-Z

SO

Note : The CS# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command.

Figure 24. Write Status Register (WRSR) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

SCLK

CR in

SR in

Command

01h

H0 L0 H1 L1

SIO[3:0]

P/N: PM1832

Rev. 1.1, August 02, 2016

37

MX66L51235F

Software Protected Mode (SPM):

-

When SRWD bit=0, no matter WP#/SIO2 is low or high, the WREN instruction may set the WEL bit and can

change the values of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1,

BP0 and T/B bit, is at software protected mode (SPM).

-

When SRWD bit=1 and WP#/SIO2 is high, the WREN instruction may set the WEL bit can change the values

of SRWD, BP3, BP2, BP1, BP0. The protected area, which is deﬁned by BP3, BP2, BP1, BP0 and T/B bit, is at

software protected mode (SPM)

Note:

If SRWD bit=1 but WP#/SIO2 is low, it is impossible to write the Status Register even if the WEL bit has previously

been set. It is rejected to write the Status Register and not be executed.

Hardware Protected Mode (HPM):

-

When SRWD bit=1, and then WP#/SIO2 is low (or WP#/SIO2 is low before SRWD bit=1), it enters the hardware

protected mode (HPM). The data of the protected area is protected by software protected mode by BP3, BP2,

BP1, BP0 and T/B bit and hardware protected mode by the WP#/SIO2 to against data modiﬁcation.

Note:

To exit the hardware protected mode requires WP#/SIO2 driving high once the hardware protected mode is entered.

If the WP#/SIO2 pin is permanently connected to high, the hardware protected mode can never be entered; only

can use software protected mode via BP3, BP2, BP1, BP0 and T/B bit.

If the system enter QPI or set QE=1, the feature of HPM will be disabled.

Table 7. Protection Modes

Mode

Status register condition

WP# and SRWD bit status

Memory

Status register can be written

in (WEL bit is set to "1") and

the SRWD, BP0-BP3

Software protection

mode (SPM)

WP#=1 and SRWD bit=0, or

WP#=0 and SRWD bit=0, or

WP#=1 and SRWD=1

The protected area

cannot

be program or erase.

bits can be changed

The SRWD, BP0-BP3 of

status register bits cannot be

changed

The protected area

cannot

be program or erase.

Hardware protection

mode (HPM)

WP#=0, SRWD bit=1

Note:

1. As deﬁned by the values in the Block Protect (BP3, BP2, BP1, BP0) bits of the Status Register, as shown in

Table 2.

P/N: PM1832

Rev. 1.1, August 02, 2016

38

MX66L51235F

Figure 25. WRSR ﬂow

start

WREN command

RDSR command

No

WEL=1?

Yes

WRSR command

Write status register data

RDSR command

No

WIP=0?

Yes

RDSR command

Read WEL=0, BP[3:0], QE,

and SRWD data

No

Verify OK?

Yes

WRSR successfully

WRSR fail

P/N: PM1832

Rev. 1.1, August 02, 2016

39

MX66L51235F

Figure 26. WP# Setup Timing and Hold Timing during WRSR when SRWD=1

WP#

CS#

tSHWL

tWHSL

0

1

2

3

4

5

6

7

8

9

10 11 12

13 14

15

SCLK

01h

SI

High-Z

SO

Note: WP# must be kept high until the embedded operation ﬁnish.

P/N: PM1832

Rev. 1.1, August 02, 2016

40

MX66L51235F

9-10. Enter 4-byte mode (EN4B)

The EN4B instruction enables accessing the address length of 32-bit for the memory area of higher density (larger

than 128Mb). The device default is in 24-bit address mode; after sending out the EN4B instruction, the bit5 (4BYTE

bit) of security register will be automatically set to "1" to indicate the 4-byte address mode has been enabled. Once

the 4-byte address mode is enabled, the address length becomes 32-bit instead of the default 24-bit. There are

three methods to exit the 4-byte mode: writing exit 4-byte mode (EX4B) instruction, Reset or power-off.

All instructions are accepted normally, and just the address bit is changed from 24-bit to 32-bit.

The following command don't support 4bye address: RDSFDP, RES and REMS.

The sequence of issuing EN4B instruction is: CS# goes low → sending EN4B instruction to enter 4-byte mode(

automatically set 4BYTE bit as "1") → CS# goes high.

9-11. Exit 4-byte mode (EX4B)

The EX4B instruction is executed to exit the 4-byte address mode and return to the default 3-bytes address mode.

After sending out the EX4B instruction, the bit5 (4BYTE bit) of Conﬁguration register will be cleared to be "0" to

indicate the exit of the 4-byte address mode. Once exiting the 4-byte address mode, the address length will return to

24-bit.

The sequence of issuing EX4B instruction is: CS# goes low → sending EX4B instruction to exit 4-byte mode

(automatically clear the 4BYTE bit to be "0") → CS# goes high.

P/N: PM1832

Rev. 1.1, August 02, 2016

41

MX66L51235F

9-12. Read Data Bytes (READ)

The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on

the falling edge of SCLK at a maximum frequency fR. The ﬁrst address can't be any location if the device is still in

3-Byte mode. The address is automatically increased to the next higher address after each byte data is shifted out,

so the whole memory can be read out at a single READ instruction. The address counter rolls over to 0 when the

highest address has been reached.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing READ instruction is: CS# goes low→sending READ instruction code→ 3-byte or 4-byte

address on SI→ data out on SO→to end READ operation can use CS# to high at any time during data out.

Figure 27. Read Data Bytes (READ) Sequence (SPI Mode only)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

command

03h

24-Bit Address

(Note)

23 22 21

MSB

3

2

1

0

SI

Data Out 1

Data Out 2

High-Z

2

7

6

5

4

3

1

7

0

SO

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

42

MX66L51235F

9-13. Read Data Bytes at Higher Speed (FAST_READ)

The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and

data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The ﬁrst address can't be any

location if the device is still in 3-Byte mode. The address is automatically increased to the next higher address

after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The

address counter rolls over to 0 when the highest address has been reached.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

Read on SPI Mode The sequence of issuing FAST_READ instruction is: CS# goes low→ sending FAST_READ

instruction code→ 3-byte or 4-byte address on SI→ 8 dummy cycles (default)→ data out on SO→ to end FAST_

READ operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any

impact on the Program/Erase/Write Status Register current cycle.

Figure 28. Read at Higher Speed (FAST_READ) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

Mode 3

Mode 0

SCLK

Command

0Bh

24-Bit Address

(Note)

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Configurable

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

43

MX66L51235F

9-14. Dual Output Read Mode (DREAD)

The DREAD instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fT. The ﬁrst address can't be any location if the device is still in 3-Byte mode. The address is

automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single DREAD instruction. The address counter rolls over to 0 when the highest address has been

reached. Once writing DREAD instruction, the following data out will perform as 2-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing DREAD instruction is: CS# goes low

sending DREAD instruction 3-byte or 4-byte

→

address on SIO0 8 dummy cycles (default) on SIO0

data out interleave on SIO1 & SIO0

to end DREAD

→

operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, DREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 29. Dual Read Mode Sequence

CS#

30 31 32

39 40 41 42 43 44 45

0

1

2

3

4

5

6

7

8

9

SCLK

…

Data Out

1

Configurable

Dummy Cycle

Command

24 ADD Cycle

2

…

A23 A22

A1 A0

D4 D2

D6 D4

D7 D5

3B

D6

D7

D0

SI/SIO0

High Impedance

D1

D5 D3

SO/SIO1

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

44

MX66L51235F

9-15. 2 x I/O Read Mode (2READ)

The 2READ instruction enable double throughput of Serial Flash in read mode. The address is latched on rising

edge of SCLK, and data of every two bits (interleave on 2 I/O pins) shift out on the falling edge of SCLK at a

maximum frequency fT. The ﬁrst address can't be any location if the device is still in 3-Byte mode. The address is

automatically increased to the next higher address after each byte data is shifted out, so the whole memory can

be read out at a single 2READ instruction. The address counter rolls over to 0 when the highest address has been

reached. Once writing 2READ instruction, the following address/dummy/data out will perform as 2-bit instead of

previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing 2READ instruction is: CS# goes low sending 2READ instruction 3-byte or 4-byte

→

address interleave on SIO1 & SIO0 4 dummy cycles (default) on SIO1 & SIO0 data out interleave on SIO1 &

→

SIO0 to end 2READ operation can use CS# to high at any time during data out.

→

While Program/Erase/Write Status Register cycle is in progress, 2READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 30. 2 x I/O Read Mode Sequence (SPI Mode only)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

17 18 19 20 21 22 23 24 25 26 27 28 29 30

SCLK

Data

Configurable

Dummy Cycle

12 ADD Cycles

(Note)

Command

Out 1

Out 2

D6 D4 D2 D0 D6 D4 D2 D0

A22 A20 A18

A4 A2 A0

BBh

SI/SIO0

D7 D5 D3 D1 D7 D5 D3 D1

A23 A21 A19

A5 A3 A1

SO/SIO1

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

45

MX66L51235F

9-16. Quad Read Mode (QREAD)

The QREAD instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status

Register must be set to "1" before sending the QREAD instruction. The address is latched on rising edge of SCLK,

and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fQ. The ﬁrst address can't be any location if the device is still in 3-Byte mode. The address is automatically

increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a

single QREAD instruction. The address counter rolls over to 0 when the highest address has been reached. Once

writing QREAD instruction, the following data out will perform as 4-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

The sequence of issuing QREAD instruction is: CS# goes low

sending QREAD instruction → 3-byte or 4-byte

→

address on SI

8 dummy cycle (Default)

data out interleave on SO3, SO2, SO1 & SO0

to end QREAD

→

operation can use CS# to high at any time during data out.

While Program/Erase/Write Status Register cycle is in progress, QREAD instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

Figure 31. Quad Read Mode Sequence

CS#

29 30 31 32 33

38 39 40 41 42

0

1

2

3

4

5

6

7

8

9

SCLK

…

Configurable

dummy cycles

Data

Out 1

Data Data

Out 2 Out 3

Command

6B

24 ADD Cycles

…

A23A22

A2 A1 A0

D4 D0 D4 D0 D4

SIO0

SIO1

SIO2

SIO3

High Impedance

D5 D1 D5 D1 D5

D6 D2 D6 D2 D6

D7 D3 D7 D3 D7

Notes:

1. Please note the above address cycles are base on 3-byte address mode, for 4-byte address mode, the address

cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

46

MX66L51235F

9-17. 4 x I/O Read Mode (4READ)

The 4READ instruction enable quad throughput of Serial Flash in read mode. A Quad Enable (QE) bit of status

Register must be set to "1" before sending the 4READ instruction. The address is latched on rising edge of SCLK,

and data of every four bits (interleave on 4 I/O pins) shift out on the falling edge of SCLK at a maximum frequency

fQ. The ﬁrst address can't be any location if the device is still in 3-Byte mode. The address is automatically

increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a

single 4READ instruction. The address counter rolls over to 0 when the highest address has been reached. Once

writing 4READ instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte mode, please refer to the enter 4-byte mode (EN4B)

Mode section.

4 x I/O Read on SPI Mode (4READ) The sequence of issuing 4READ instruction is: CS# goes low sending

→

4READ instruction 3-byte or 4-byte address interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default)

→

data out interleave on SIO3, SIO2, SIO1 & SIO0 to end 4READ operation can use CS# to high at any time

→

during data out.

4 x I/O Read on QPI Mode (4READ) The 4READ instruction also support on QPI command mode. The sequence

of issuing 4READ instruction QPI mode is: CS# goes low sending 4READ instruction 3-byte or 4-byte address

→

interleave on SIO3, SIO2, SIO1 & SIO0 6 dummy cycles (Default) data out interleave on SIO3, SIO2, SIO1 &

→

SIO0 to end 4READ operation can use CS# to high at any time during data out.

→

While Program/Erase/Write Status Register cycle is in progress, 4READ instruction is rejected without any impact

on the Program/Erase/Write Status Register current cycle.

P/N: PM1832

Rev. 1.1, August 02, 2016

47

MX66L51235F

Figure 32. 4 x I/O Read Mode Sequence (SPI Mode)

CS#

23 24

10 11 12 13 14 15 16 17 18 19 20 21 22

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

SCLK

Data

Command

6 ADD Cycles

Performance

enhance

Out 1

Out 2 Out 3

indicator (Note 1)

Configurable

Dummy Cycle (Note 3)

A20 A16 A12 A8 A4 A0

D4 D0 D4 D0 D4 D0

P4 P0

EBh

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3 D7 D3

P7 P3

Notes:

1. Hi-impedance is inhibited for the two clock cycles.

2. P7≠P3, P6≠P2, P5≠P1 & P4≠P0 (Toggling) is inhibited.

3. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

Figure 33. 4 x I/O Read Mode Sequence (QPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

MODE 3

MODE 0

MODE 3

MODE 0

SCLK

EB

SIO[3:0]

H0 L0 H1 L1 H2 L2 H3 L3

A5 A4 A3 A2 A1 A0

X

MSB

Data Out

24-bit Address

(Note)

Configurable

Dummy Cycle

Data In

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

48

MX66L51235F

9-18. 4 Byte Address Command Set

The operation of 4-byte address command set was very similar to original 3-byte address command set. The

only different is all the 4-byte command set request 4-byte address (A31-A0) followed by instruction code. The

command set support 4-byte address including: READ4B, Fast_Read4B, DREAD4B, 2READ4B, QREAD4B,

4READ4B, PP4B, 4PP4B, SE4B, BE32K4B, BE4B. Please note that it is not necessary to issue EN4B command

before issuing any of 4-byte command set.

Figure 34. Read Data Bytes using 4 Byte Address Sequence (READ4B)

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39 40 41 42 43 44 45 46 47

SCLK

Command

13h

32-bit address

31 30 29

MSB

3

2

1

0

SI

DataOut 1

DataOut 2

7

High Impedance

2

SO

7

6

5

4

3

1

0

MSB

Figure 35. Read Data Bytes at Higher Speed using 4 Byte Address Sequence (FASTREAD4B)

CS#

0

1

2

3

4

5

6

7

8

9

10

36 37 38 39

SCLK

Command

0Ch

32-bit address

31 30 29

3

2

1

0

SI

High Impedance

SO

CS#

55

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

SCLK

Configurable

Dummy cycles

SI

7

6

5

4

3

2

0

1

DATAOUT2

DATAOUT1

7

6

5

4

3

2

1

0

7

SO

7

6

5

4

3

2

0

1

MSB

P/N: PM1832

Rev. 1.1, August 02, 2016

49

MX66L51235F

Figure 36. 2 x I/O Fast Read using 4 Byte Address Sequence (2READ4B)

CS#

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

21 22 23 24 25 26 27 28 29 30 31 32 33 34

SCLK

Configurable

Dummy Cycle

(Note)

Data

Out 1

Data

Out 2

16 ADD Cycles

Command

D6 D4 D2 D0 D6 D4 D2 D0

A30 A28 A26

A31 A29 A27

A4 A2 A0

BCh

SI/SIO0

D7 D5 D3 D1 D7 D5 D3 D1

A5 A3 A1

SO/SIO1

Note: Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

Figure 37. 4 I/O Fast Read using 4 Byte Address sequence (4READ4B)

CS#

23 24 25 26

Mode 3

Mode 0

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

SCLK

Command

8 ADD Cycles

Performance

Data

Out 1

Data

Out 2

Data

Out 3

enhance

indicator

Configurable

Dummy Cycle

(Note)

A16

A12 A8 A4 A0

D4 D0 D4 D0 D4 D0

A28 A24

A29 A25

A20

P4 P0

ECh

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

P5 P1

P6 P2

P7 P3

D5 D1 D5 D1 D5 D1

D6 D2 D6 D2 D6 D2

A30 A26 A22 A18 A14 A10 A6 A2

A31 A27

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3 D7 D3

Note: Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM1832

Rev. 1.1, August 02, 2016

50

MX66L51235F

9-19. Burst Read

The Burst Read feature allows applications to ﬁll a cache line with a ﬁxed length of data without using multiple read

commands. Burst Read is disabled by default at power-up or reset. Burst Read is enabled by setting the Burst

Length. When the Burst Length is set, reads will wrap on the selected boundary (8/16/32/64-bytes) containing the

initial target address. For example if an 8-byte Wrap Depth is selected, reads will wrap on the 8-byte-page-aligned

boundary containing the initial read address.

To set the Burst Length, drive CS# low → send SET BURST LENGTH instruction code → send WRAP CODE

→drive CS# high. Refer to the table below for valid 8-bit Wrap Codes and their corresponding Wrap Depth.

Data

00h

01h

02h

03h

1xh

Wrap Around

Wrap Depth

8-byte

Yes

No

16-byte

32-byte

64-byte

X

Once Burst Read is enabled, it will remain enabled until the device is power-cycled or reset. The SPI and QPI mode

4READ and 4READ4B read commands support the wrap around feature after Burst Read is enabled. To change

the wrap depth, resend the Burst Read instruction with the appropriate Wrap Code. To disable Burst Read, send the

Burst Read instruction with Wrap Code 1xh. “EBh” supports wrap around feature after wrap around is enabled. Both

SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this instruction. The SIO[3:1] are don't care

during SPI mode.

Figure 38. Burst Read - SPI Mode

CS#

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

SCLK

SIO

D7

D6

D5

D4

D3

D2

D1

D0

C0h

Figure 39. Burst Read - QPI Mode

CS#

0

1

2

3

Mode 3

Mode 0

SCLK

C0h

H0

L0

SIO[3:0]

MSB LSB

Note: MSB=Most Signiﬁcant Bit

LSB=Least Signiﬁcant Bit

P/N: PM1832

Rev. 1.1, August 02, 2016

51

MX66L51235F

9-20. Performance Enhance Mode

The device could waive the command cycle bits if the two cycle bits after address cycle toggles.

Performance enhance mode is supported in both SPI and QPI mode.

In QPI mode, “EBh” "ECh" and SPI “EBh” "ECh" commands support enhance mode. The performance enhance

mode is not supported in dual I/O mode.

To enter performance-enhancing mode, P[7:4] must be toggling with P[3:0]; likewise P[7:0]=A5h, 5Ah, F0h or 0Fh

can make this mode continue and skip the next 4READ instruction. To leave enhance mode, P[7:4] is no longer

toggling with P[3:0]; likewise P[7:0]=FFh, 00h, AAh or 55h along with CS# is afterwards raised and then lowered.

Issuing ”FFh” data cycle can also exit enhance mode. The system then will leave performance enhance mode and

return to normal operation.

After entering enhance mode, following CS# go high, the device will stay in the read mode and treat CS# go low of

the ﬁrst clock as address instead of command cycle.

This sequence of issuing 4READ instruction especially useful in random access: CS# goes low→send 4READ

instruction→3-bytes or 4-bytes address interleave on SIO3, SIO2, SIO1 & SIO0→performance enhance toggling

bit P[7:0]→ 4 dummy cycles (Default) →data out until CS# goes high → CS# goes low (the following 4READ

instruction is ignored) → 3-bytes or 4-bytes random access address.

To conduct the Performance Enhance Mode Reset operation in SPI mode, FFh data cycle(8 clocks in 3-byte

address mode)/3FFh data cycle(10 clocks in 4-byte address mode), should be issued in 1I/O sequence. In QPI

Mode, FFFFFFFFh data cycle(8 clocks in 3-byte address mode)/FFFFFFFFFFh data cycle (10 clocks in 4-byte

address mode), in 4I/O should be issued.

If the system controller is being Reset during operation, the ﬂash device will return to the standard SPI operation.

P/N: PM1832

Rev. 1.1, August 02, 2016

52

MX66L51235F

Figure 40. 4 x I/O Read Performance Enhance Mode Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22

n

SCLK

Data

Out 2

Data

Out n

Command

6 ADD Cycles

(Note 2)

Performance

enhance

Out 1

indicator (Note 1)

Configurable

Dummy Cycle (Note 2)

P4 P0

D4 D0 D4 D0

D4 D0

A20 A16 A12 A8 A4 A0

EBh

SIO0

SIO1

SIO2

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

P5 P1

P6 P2

A23 A19 A15 A11 A7 A3

D7 D3 D7 D3

D7 D3

P7 P3

SIO3

CS#

n+1

...........

n+7......n+9 ........... n+13

...........

Mode 3

Mode 0

SCLK

Data

Out 1

Data

Out 2

Data

Out n

6 ADD Cycles

(Note 2)

Performance

enhance

indicator (Note 1)

Configurable

Dummy Cycle (Note 2)

D4 D0 D4 D0

D4 D0

P4 P0

A20 A16 A12 A8 A4 A0

SIO0

SIO1

SIO2

SIO3

D5 D1 D5 D1

D6 D2 D6 D2

D5 D1

D6 D2

A21 A17 A13 A9 A5 A1

A22 A18 A14 A10 A6 A2

P5 P1

P6 P2

D7 D3 D7 D3

D7 D3

A23 A19 A15 A11 A7 A3

P7 P3

Notes:

1. If not using performance enhance recommend to keep 1 or 0 in performance enhance indicator.

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

2. Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

P/N: PM1832

Rev. 1.1, August 02, 2016

53

MX66L51235F

Figure 41. 4 x I/O Read Performance Enhance Mode Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SCLK

EBh

SIO[3:0]

X

H0 L0 H1 L1

MSB LSB MSB LSB

A5 A4 A3 A2 A1 A0

P(7:4)P(3:0)

Data In

Data Out

performance

enhance

indicator

Configurable

Dummy Cycle (Note 1)

CS#

SCLK

n+1 .............

Mode 0

SIO[3:0]

X

H0 L0 H1 L1

MSB LSB MSB LSB

A5 A4 A3 A2 A1 A0

P(7:4)P(3:0)

Data Out

6 Address cycles

(Note)

performance

enhance

indicator

Configurable

Dummy Cycle (Note 1)

Notes:

1.

Conﬁguration Dummy cycle numbers will be different depending on the bit6 & bit 7 (DC0 & DC1) setting in

conﬁguration register.

2.

Reset the performance enhance mode, if P7=P3 or P6=P2 or P5=P1 or P4=P0, ex: AA, 00, FF.

P/N: PM1832

Rev. 1.1, August 02, 2016

54

MX66L51235F

9-21. Fast Boot

The Fast Boot Feature provides the ability to automatically execute read operation after power on cycle or reset

without any read instruction.

A Fast Boot Register is provided on this device. It can enable the Fast Boot function and also deﬁne the number of

delay cycles and start address (where boot code being transferred). Instruction WRFBR (write fast boot register) and

ESFBR (erase fast boot register) can be used for the status conﬁguration or alternation of the Fast Boot Register

bit. RDFBR (read fast boot register) can be used to verify the program state of the Fast Boot Register. The default

number of delay cycles is 13 cycles, and there is a 16bytes boundary address for the start of boot code access.

When CS# starts to go low, data begins to output from default address after the delay cycles (default as 13 cycles).

After CS# returns to go high, the device will go back to standard SPI mode and user can start to input command. In

the fast boot data out process from CS# goes low to CS# goes high, a minimum of one byte must be output.

Once Fast Boot feature has been enabled, the device will automatically start a read operation after power on cycle,

reset command, or hardware reset operation.

The fast Boot feature can support Single I/O and Quad I/O interface. If the QE bit of Status Register is “0”, the data

is output by Single I/O interface. If the QE bit of Status Register is set to “1”, the data is output by Quad I/O interface.

Table 8. Fast Boot Register (FBR)

Bits

Description

FBSA (FastBoot Start

Address)

Bit Status

16 bytes boundary address for the start of boot

code access.

Default State

Type

Non-

Volatile

31 to 4

FFFFFFF

Non-

Volatile

3

2 to 1

0

x

1

11

1

00: 7 delay cycles

01: 9 delay cycles

10: 11 delay cycles

11: 13 delay cycles

0=FastBoot is enabled.

1=FastBoot is not enabled.

FBSD (FastBoot Start

Delay Cycle)

Non-

Volatile

Non-

Volatile

FBE (FastBoot Enable)

Note: If FBSD = 11, the maximum clock frequency is 133 MHz

If FBSD = 10, the maximum clock frequency is 104 MHz

If FBSD = 01, the maximum clock frequency is 84 MHz

If FBSD = 00, the maximum clock frequency is 70 MHz

P/N: PM1832

Rev. 1.1, August 02, 2016

55

MX66L51235F

Figure 42. Fast Boot Sequence (QE Bit=0)

CS#

0

-

n+1

n+13 n+15

n+12 n+14

n+10n+11

Mode 3

Mode 0

-

n

n+2

n+4 n+5 n+6

n+8 n+9

n+7

n+3

SCLK

SI

Delay Cycles

Don’t care or High Impedance

Data Out 1

Data Out 2

High Impedance

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

Note: If FBSD = 11, delay cycles is 13 and n is 12.

If FBSD = 10, delay cycles is 11 and n is 10.

If FBSD = 01, delay cycles is 9 and n is 8.

If FBSD = 00, delay cycles is 7 and n is 6.

Figure 43. Fast Boot Sequence (QE Bit=1)

CS#

-

n

n+1 n+2 n+3 n+5 n+6 n+7 n+8 n+9

0

Mode 3

Mode 0

SCLK

Data

Out 1

Delay Cycles

Data

Out 3

Out 2

Out 4

High Impedance

4

0

4

0

4

0

SIO0

SIO1

SIO2

SIO3

High Impedance

5

6

7

1

5

6

7

1

5

6

1

5

6

7

1

2

3

5

6

7

2

3

2

3

2

3

7

MSB

Note: If FBSD = 11, delay cycles is 13 and n is 12.

If FBSD = 10, delay cycles is 11 and n is 10.

If FBSD = 01, delay cycles is 9 and n is 8.

If FBSD = 00, delay cycles is 7 and n is 6.

P/N: PM1832

Rev. 1.1, August 02, 2016

56

MX66L51235F

Figure 44. Read Fast Boot Register (RDFBR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

37 38 39 40 41

Mode 3

Mode 0

SCLK

Command

16h

SI

Data Out 1

Data Out 2

26 25 24 7 6

High-Z

SO

7

6

5

MSB

Figure 45. Write Fast Boot Register (WRFBR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39

Mode 3

Mode 0

10

SCLK

Command

17h

Fast Boot Register

SI

7

6

26 25 24

5

MSB

High-Z

SO

Figure 46. Erase Fast Boot Register (ESFBR) Sequence

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

18h

SI

High-Z

SO

P/N: PM1832

Rev. 1.1, August 02, 2016

57

MX66L51235F

9-22. Sector Erase (SE)

The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used

for any 4K-byte sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit

before sending the Sector Erase (SE). Any address of the sector (Please refer to "Table 4. Memory Organization")

is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the least

signiﬁcant bit of the address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. Address bits [Am-A12] (Am is the most signiﬁcant address) select

the sector address.

To enter the 4-byte address mode, please refer to the "9-10. Enter 4-byte mode (EN4B)" section.

The sequence of issuing SE instruction is: CS# goes low→ sending SE instruction code→ 3-byte or 4-byte address

on SI→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Sector Erase cycle is in progress. The WIP sets 1 during the tSE

timing, and clears when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode), the Sector Erase (SE) instruction will not be executed on the block.

Figure 47. Sector Erase (SE) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31

SCLK

24-Bit Address

(Note)

Command

20h

SI

A23 A22

A2 A1 A0

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 48. Sector Erase (SE) Sequence (QPI Mode)

CS#

Mode 3

0

1

2

3

4

5

6

7

SCLK

Mode 0

24-Bit Address

(Note)

Command

SIO[3:0]

20h A5 A4 A3 A2 A1 A0

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

58

MX66L51235F

9-23. Block Erase (BE32K)

The Block Erase (BE32K) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 32K-byte block erase operation. A Write Enable (WREN) instruction be executed to set the Write Enable Latch

(WEL) bit before sending the Block Erase (BE32K). Any address of the block (Please refer to "Table 4. Memory

Organization") is a valid address for Block Erase (BE32K) instruction. The CS# must go high exactly at the byte

boundary (the least signiﬁcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not

executed.

Address bits [Am-A15] (Am is the most signiﬁcant address) select the 32KB block address. The default read mode is

3-byte address, to access higher address (4-byte address) which requires to enter the 4-byte address read mode or

to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the "9-10. Enter 4-byte mode (EN4B)" section.

The sequence of issuing BE32K instruction is: CS# goes low→ sending BE32K instruction code→ 3-byte or 4-byte

address on SI→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE32K) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while during the Block Erase cycle is in progress. The WIP sets during the

tBE32K timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

If the Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector

Protect Mode), the Block Erase (BE32K) instruction will not be executed on the block.

Figure 49. Block Erase 32KB (BE32K) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

SCLK

Command

52h

24-Bit Address

(Note)

SI

A23 A22

A2

A0

A1

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 50. Block Erase 32KB (BE32K) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

24-Bit Address

(Note)

Command

SIO[3:0]

52h A5 A4 A3 A2 A1 A0

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

59

MX66L51235F

9-24. Block Erase (BE)

The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used

for 64K-byte block erase operation. A Write Enable (WREN) instruction must be executed to set the Write Enable

Latch (WEL) bit before sending the Block Erase (BE). Any address of the block (Please refer to "Table 4. Memory

Organization") is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the

least signiﬁcant bit of address byte been latched-in); otherwise, the instruction will be rejected and not executed.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the "9-10. Enter

4-byte mode (EN4B)" section.

The sequence of issuing BE instruction is: CS# goes low→ sending BE instruction code→ 3-byte or 4-byte address

on SI→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Block Erase cycle is in progress. The WIP sets during the tBE

timing, and clears when Block Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. If the Block

is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect Mode),

the Block Erase (BE) instruction will not be executed on the block.

Figure 51. Block Erase (BE) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

SCLK

Command

D8h

24-Bit Address

(Note)

SI

A23 A22

A2

A0

A1

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 52. Block Erase (BE) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

24-Bit Address

(Note)

Command

SIO[3:0]

D8h A5 A4 A3 A2 A1 A0

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

60

MX66L51235F

9-25. Chip Erase (CE)

The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN)

instruction must be executed to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). The CS#

must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed.

The sequence of issuing CE instruction is: CS# goes low→sending CE instruction code→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Chip Erase cycle is in progress. The WIP sets during the tCE

timing, and clears when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is cleared.

When the chip is under "Block protect (BP) Mode" (WPSEL=0). The Chip Erase (CE) instruction will not be

executed, if one (or more) sector is protected by BP3-BP0 bits. It will be only executed when BP3-BP0 all set to "0".

When the chip is under "Advanced Sector Protect Mode" (WPSEL=1). The Chip Erase (CE) instruction will be

executed on unprotected block. The protected Block will be skipped. If one (or more) 4K byte sector was protected

in top or bottom 64K byte block, the protected block will also skip the chip erase command.

Figure 53. Chip Erase (CE) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

SCLK

SI

Command

60h or C7h

Figure 54. Chip Erase (CE) Sequence (QPI Mode)

CS#

0

1

Mode 3

Mode 0

SCLK

Command

60h or C7h

SIO[3:0]

P/N: PM1832

Rev. 1.1, August 02, 2016

61

MX66L51235F

9-26. Page Program (PP)

The Page Program (PP) instruction is for programming memory bits to "0". One to 256 bytes can be sent to the

device to be programmed. A Write Enable (WREN) instruction must be executed to set the Write Enable Latch (WEL)

bit before sending the Page Program (PP). If more than 256 data bytes are sent to the device, only the last 256

data bytes will be accepted and the previous data bytes will be disregarded. The Page Program instruction requires

that all the data bytes fall within the same 256-byte page. The low order address byte A[7:0] speciﬁes the starting

address within the selected page. Bytes that will cross a page boundary will wrap to the beginning of the selected

page. The device can accept (256 minus A[7:0]) data bytes without wrapping. If 256 data bytes are going to be

programmed, A[7:0] should be set to 0.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the "9-10. Enter

4-byte mode (EN4B)" section.

The sequence of issuing PP instruction is: CS# goes low→ sending PP instruction code→ 3-byte or 4-byte address

on SI→ at least 1-byte on data on SI→ CS# goes high.

The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte

boundary( the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be

executed.

The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in

Progress (WIP) bit still can be checked while the Page Program cycle is in progress. The WIP sets during the tPP

timing, and clears when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is cleared. If the

Block is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector Protect

Mode), the Page Program (PP) instruction will not be executed.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

P/N: PM1832

Rev. 1.1, August 02, 2016

62

MX66L51235F

Figure 55. Page Program (PP) Sequence (SPI Mode)

CS#

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

SCLK

Command

02h

Data Byte 1

24-Bit Address

(Note)

23 22 21

MSB

3

2

1

0

7

6

5

4

3

2

0

1

SI

MSB

CS#

40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

SCLK

Data Byte 2

Data Byte 3

Data Byte 256

7

6

5

4

3

2

0

7

6

5

4

3

2

0

7

6

5

4

3

2

0

1

SI

MSB

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

Figure 56. Page Program (PP) Sequence (QPI Mode)

CS#

Mode 3

Mode 0

0

1

2

SCLK

Command

02h

24-Bit Address

(Note)

H255 L255

SIO[3:0]

H0 L0 H1 L1 H2 L2 H3 L3

Data Byte Data Byte Data Byte Data Byte

A5 A4 A3 A2 A1 A0

......

Data Byte

256

Data In

1

2

3

4

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

63

MX66L51235F

9-27. 4 x I/O Page Program (4PP)

The Quad Page Program (4PP) instruction is for programming the memory to be "0". A Write Enable (WREN)

instruction must be executed to set the Write Enable Latch (WEL) bit and Quad Enable (QE) bit must be set to

"1" before sending the Quad Page Program (4PP). The Quad Page Programming takes four pins: SIO0, SIO1,

SIO2, and SIO3 as address and data input, which can improve programmer performance and the effectiveness of

application. The other function descriptions are as same as standard page program.

The default read mode is 3-byte address, to access higher address (4-byte address) which requires to enter the

4-byte address read mode or to deﬁne EAR bit. To enter the 4-byte address mode, please refer to the "9-10. Enter

4-byte mode (EN4B)" section.

The sequence of issuing 4PP instruction is: CS# goes low→ sending 4PP instruction code→ 3-byte or 4-byte

address on SIO[3:0]→ at least 1-byte on data on SIO[3:0]→CS# goes high.

If the page is protected by BP bits (WPSEL=0; Block Protect Mode) or SPB/DPB (WPSEL=1; Advanced Sector

Protect Mode), the Quad Page Program (4PP) instruction will not be executed.

Figure 57. 4 x I/O Page Program (4PP) Sequence (SPI Mode only)

CS#

10 11 12 13 14 15 16 17 18 19 20 21

Data Data Data Data

0

1

2

3

4

5

6

7

8

9

Mode 3

Mode 0

SCLK

Command

38h

6 Address cycle

Byte 1 Byte 2 Byte 3 Byte 4

A16

A8 A4 A0

A12

A20

4

0

4

0

4

0

4

0

SIO0

SIO1

SIO2

SIO3

A21 A17 A13 A9 A5 A1

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

5

6

7

1

2

3

A22

A14 A10 A6 A2

A18

A7

A23 A19 A15 A11

A3

Note: Please note the address cycles above are based on 3-byte address mode. For 4-byte address mode, the

address cycles will be increased.

P/N: PM1832

Rev. 1.1, August 02, 2016

64

MX66L51235F

9-28. Deep Power-down (DP)

The Deep Power-down (DP) instruction places the device into a minimum power consumption state, Deep

Powerdown mode, in which the quiescent current is reduced from ISB1 to ISB2.

The sequence of issuing DP instruction: CS# goes low→ send DP instruction code→ CS# goes high. The CS# must

go high at the byte boundary (after exactly eighth bits of the instruction code have been latched-in); otherwise the

instruction will not be executed. Both SPI (8 clocks) and QPI (2 clocks) command cycle can be accepted by this

instruction. SIO[3:1] are "don't care".

After CS# goes high there is a delay of tDP before the device transitions from Stand-by mode to Deep Power-down

mode and before the current reduces from ISB1 to ISB2. Once in Deep Power-down mode, all instructions will be

ignored except Release from Deep Power-down (RDP).

The device exits Deep Power-down mode and returns to Stand-by mode if it receives a Release from Deep

Powerdown (RDP) instruction, power-cycle, or reset. Please refer to "Figure 14. Release from Deep Power-down (RDP)

Sequence (SPI Mode)" and "Figure 15. Release from Deep Power-down (RDP) Sequence (QPI Mode)".

Figure 58. Deep Power-down (DP) Sequence (SPI Mode)

CS#

t

DP

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

SI

Command

B9h

Stand-by Mode

Deep Power-down Mode

Figure 59. Deep Power-down (DP) Sequence (QPI Mode)

CS#

t

DP

Mode 3

Mode 0

0

1

SCLK

Command

SIO[3:0]

B9h

Stand-by Mode

Deep Power-down Mode

P/N: PM1832

Rev. 1.1, August 02, 2016

65

MX66L51235F

9-29. Enter Secured OTP (ENSO)

The ENSO instruction is for entering the additional 4K-bit secured OTP mode. While device is in 4K-bit secured

OTPmode, main array access is not available. The additional 4K-bit secured OTP is independent from main array

and may be used to store unique serial number for system identiﬁer. After entering the Secured OTP mode, follow

standard read or program procedure to read out the data or update data. The Secured OTP data cannot be updated

again once it is lock-down.

The sequence of issuing ENSO instruction is: CS# goes low→ sending ENSO instruction to enter Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

Please note that after issuing ENSO command user can only access secure OTP region with standard read or

program procedure. Furthermore, once security OTP is lock down, only read related commands are valid.

9-30. Exit Secured OTP (EXSO)

The EXSO instruction is for exiting the additional 4K-bit secured OTP mode.

The sequence of issuing EXSO instruction is: CS# goes low→ sending EXSO instruction to exit Secured OTP

mode→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-31. Read Security Register (RDSCUR)

The RDSCUR instruction is for reading the value of Security Register bits. The Read Security Register can be read

at any time (even in program/erase/write status register/write security register condition) and continuously.

The sequence of issuing RDSCUR instruction is : CS# goes low→sending RDSCUR instruction→Security Register

data out on SO→ CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-32. Write Security Register (WRSCUR)

The WRSCUR instruction sets the LDSO bit of the Security Register. The WREN (Write Enable) instruction is

required before issuing WRSCUR instruction. The WRSCUR instruction may change the values of bit1 (LDSO bit)

for customer to lock-down the 4K-bit Secured OTP area. Once the LDSO bit is set to "1", the Secured OTP area

cannot be updated any more.

The sequence of issuing WRSCUR instruction is :CS# goes low→ sending WRSCUR instruction → CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The CS# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed.

P/N: PM1832

Rev. 1.1, August 02, 2016

66

MX66L51235F

Security Register

The deﬁnition of the Security Register bits is as below:

Write Protection Selection bit. Please reference to "9-33. Write Protection Selection (WPSEL)".

Erase Fail bit. The Erase Fail bit is a status ﬂag, which shows the status of last Erase operation. It will be set to "1",

if the erase operation fails. It will be set to "0", if the last operation is successful. Please note that it will not interrupt

or stop any operation in the ﬂash memory.

Program Fail bit. The Program Fail bit is a status ﬂag, which shows the status of last Program operation. It will be

set to "1", if the program operation fails or the program region is protected. It will be set to "0", if the last operation is

successful. Please note that it will not interrupt or stop any operation in the ﬂash memory.

Erase Suspend bit. Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use

ESB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Erase Suspend command, ESB

is set to "1". ESB is cleared to "0" after erase operation resumes.

Program Suspend bit. Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may

use PSB to identify the state of ﬂash memory. After the ﬂash memory is suspended by Program Suspend command,

PSB is set to "1". PSB is cleared to "0" after program operation resumes.

Secured OTP Indicator bit. The Secured OTP indicator bit shows the Secured OTP area is locked by factory or

not. When it is "0", it indicates non-factory lock; "1" indicates factory-lock.

Lock-down Secured OTP (LDSO) bit. By writing WRSCUR instruction, the LDSO bit may be set to "1" for

customer lock-down purpose. However, once the bit is set to "1" (lock-down), the LDSO bit and the 4K-bit Secured

OTP area cannot be updated any more. While it is in 4K-bit secured OTP mode, main array access is not allowed.

Table 9. Security Register Deﬁnition

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

ESB

(Erase

PSB

(Program

LDSO

(indicate if

Secured OTP

indicator bit

WPSEL

E_FAIL

P_FAIL

Reserved

Suspend bit) Suspend bit) lock-down)

0=Block Lock

(BP) protection

mode

1=Advanced

Sector protection

mode

0=normal

Program

succeed

1=indicate

Program

failed

0 = not lock-

0=normal

Erase

succeed

1=indicate

Erase failed

(default=0)

0=Erase

is not

suspended suspended

1= Erase 1= Program

suspended suspended

0=Program

is not

down

1 = lock-down

(cannot

0 = non-

factory

lock

1 = factory

lock

-

program/

erase

OTP)

(default=0)

Non-volatile

bit

Non-volatile bit

(OTP)

Non-volatile

bit (OTP)

Volatile bit

Volatile bit Volatile bit Volatile bit

Volatile bit

(OTP)

P/N: PM1832

Rev. 1.1, August 02, 2016

67

MX66L51235F

9-33. Write Protection Selection (WPSEL)

There are two write protection methods provided on this device, (1) Block Lock (BP) protection mode (2) Advanced

Sector protection mode. If WPSEL=0, ﬂash is under BP protection mode . If WPSEL=1, ﬂash is under Advanced

Sector protection mode. The default value of WPSEL is “0”. WPSEL command can be used to set WPSEL=1.

Please note that WPSEL is an OTP bit. Once WPSEL is set to 1, there is no chance to recovery WPSEL back

to “0”. If the ﬂash is put on BP mode, the Advanced Sector protection mode is disabled. Contrarily, if ﬂash is on the

Advanced Sector protection mode, the BP mode is disabled.

Every time after the system is powered-on, and the Security Register bit 7 is checked to be WPSEL=1, all

the blocks or sectors will be write protected by Dynamic Protected Bit (DPB) in default. User may only unlock

the blocks or sectors via GBULK instruction. Program or erase functions can only be operated after the Unlock

instruction is conducted.

When WPSEL = 0: Block Lock (BP) protection mode,

Array is protected by BP3~BP0 and BP bits are protected by “SRWD=1 and WP#=0”, where SRWD is bit 7 of status

register that can be set by WRSR command.

When WPSEL =1: Advanced Sector protection mode,

Blocks are individually protected by their own SPB or DPB lock bits which are set to “1” after power up. When the

system accepts and executes WPSEL instruction, the bit 7 in security register will be set. It will activate WRLR,

RDLR, WRPASS, RDPASS, PASSULK, WRSPB, ESSPB, SPBLK, RDSPBLK, WRDPB, RDDPB, GBLK, GBULK

etc instructions to conduct block lock protection and replace the original Software Protect Mode (SPM) use (BP3~BP0)

indicated block methods. Under the Advanced Sector protection mode (WPSEL=1), hardware protection is

performed by driving WP#=0. Once WP#=0 all array blocks/sectors are protected regardless of the contents of SPB

or DPB lock bits.

The sequence of issuing WPSEL instruction is: CS# goes low → sending WPSEL instruction to enter the individual

block protect mode → CS# goes high. The WREN command must be executed before issuing the WPSEL

command.

Write Protection Selection

Start

(Default in BP Mode)

WPSEL=1

WPSEL=0

Set

WPSEL Bit

Advanced

Sector Protection

Block Protection

(BP)

Set

Bit 1 =0

Lock Register

Bit 2 =0

Password

Protection

Solid

Protection

Dynamic

Protection

P/N: PM1832

Rev. 1.1, August 02, 2016

68

MX66L51235F

Figure 60. WPSEL Flow

start

WREN command

RDSCUR command

Yes

WPSEL=1?

No

WPSEL disable,

block protected by BP[3:0]

WPSEL command

RDSR command

No

WIP=0?

Yes

RDSCUR command

No

WPSEL=1?

Yes

WPSEL set successfully

WPSEL set fail

WPSEL enable.

Block protected by Advance Sector Protection

P/N: PM1832

Rev. 1.1, August 02, 2016

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MX66L51235F

9-34. Advanced Sector Protection

There are two ways to implement software Advanced Sector Protection on this device: Password method or Solid

method. Through these two protection methods, user can disable or enable the programming or erasing operation

to any individual sector or all sectors.

There is a non-volatile (SPB) and volatile (DPB) protection bit related to the single sector in main ﬂash array. Each

of the sectors is protected from programming or erasing operation when the bit is set. The temporary unprotect solid

write protect bit (USPB) can temporarily unprotect the sectors protected by SPB.

The ﬁgure below helps describing an overview of these methods. The device is default to the Solid mode when

shipped from factory. The detail algorithm of advanced sector protection is shown as follows:

Figure 61. Advanced Sector Protection Overview

Start

Bit 1=0

Bit 2=0

Set

Lock Register ?

Solid Protection Mode

Password Protection Mode

Set 64 bit Password

Set

SPBLK = 0

SPB Lock bit locked

All SPB can not be changeable

SPB Lock Bit ?

SPBLK = 1

SPB Lock bit Unlocked

SPB is changeable

Temporary Unprotect

SPB bit (USPB)

SPB Access Register

(SPB)

Dynamic Protect Bit Register

(DPB)

Sector Array

SPB=1 Write Protect

USPB=0 SPB bit is disabled

USPB=1 SPB bit is effective

DPB=1 sector protect

SPB=0 Write Unprotect

DPB=0 sector unprotect

DPB 0

DPB 1

SA 0

SA 1

SPB 0

SPB 1

DPB 2

SA 2

SPB 2

:

USPB

DPB N-1

DPB N

SA N-1

SA N

SPB N-1

SPB N

P/N: PM1832

Rev. 1.1, August 02, 2016

70

MX66L51235F

9-34-1. Lock Register

User can choose favorite sector protecting method via setting Lock Register bits 1 and 2. Lock Register is a 16-

bit one-time programmable register. Once bit 1 or bit 2 has been programmed (cleared to "0"), they will be locked

in that mode and the others will be disabled permanently. Bit 1 and Bit 2 can not be programmed at the same time,

otherwise the device will abort the operation.

If user selects Password Protection mode, the password setting is required. User can set password by issuing

WRPASS command.

Lock Register

Bit 15-3

Bit 2

Bit 1

Bit0

Reserved

Password Protection Mode Lock Bit

0=Password Protection Mode Enable

1= Password Protection Mode not

enable (Default =1)

Solid Protection Mode Lock Bit

Reserved

0=Solid Protection Mode Enable

1= Solid Protection Mode not enable (Default =1)

x

OTP

Notes:

1. While bit 2 or bit 1 has been "0" status, other bits can't be changed any more. If set lock register program mode,

program fail will be set to "1".

2. While bit 2 and bit 1 is "1" status,other bits can be programmed, program fail will be set to "1".

Figure 63. Read Lock Register (RDLR) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

2Dh

Register Out

High-Z

SO

7

6

5

4

3

2

1

0

15 14 13 12 11 10

MSB

9

8

7

MSB

Figure 62. Write Lock Register (WRLR) Sequence (SPI Mode)

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Mode 3

Mode 0

SCLK

Command

2Ch

Lock Register In

SI

4

15 14

12 11

10

13

8

2

1

0

9

7

6

5

3

MSB

High-Z

SO

P/N: PM1832

Rev. 1.1, August 02, 2016

71

MX66L51235F

9-34-2. SPB Lock Bit (SPBLB)

The Solid Protection Bit Lock Bit (SPBLB) is assigned to control all SPB status. It is unique and volatile.

The default status of this register is determined by Lock Register bit 1 and bit 2 status. Refer to SPB Lock Register

for more SPB Lock information.

When under Solid Protect Mode, there is no software command sequence requested to unlock this bit. To clear the

SPB lock bit, just take the device through a reset or a power-up cycle. When under Password Protection Mode, in

order to prevent modiﬁcation, the SPB Lock Bit must be set after all SPBs are setting the desired status.

SPB Lock Register

Bit

7-1

Description

Reserved

Bit Status

X

Default

0000000

Type

Volatile

0= SPB bit protected

1= SPB bit unprotected

Solid protected Mode=1

Password Protected Mode=0

0

SPBLK (Lock SPB Bit)

Volatile

Figure 64. SPB Lock Bit Set (SPBLK) Sequence

CS#

0

1

2

3

4

5

6

7

Mode 3

Mode 0

SCLK

Command

A6h

SI

High-Z

SO

Figure 65. Read SPB Lock Register (RDSPBLK) Sequence

CS#

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15

Mode 3

Mode 0

SCLK

SI

command

A7h

Register Out

High-Z

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

MSB

P/N: PM1832

Rev. 1.1, August 02, 2016

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MX66L51235F

9-34-3. Solid Protection Bits

The Solid write Protection bit (SPB) is a nonvolatile bit with the same endurances as the Flash memory. It is

assigned to each sector individually.

When a SPB is set to “1”, the associated sector may be protected, preventing any program or erase operation on

this sector. The SPB bits are set individually by WRSPB command. However, it cannot be cleared individually.

Issuing the ESSPB command will erase all SPB in the same time.

To unprotect a protected sector (corresponding SPB cleared to “0”), the SPB lock bit must be unlocked ﬁrst. Under

password protection mode (lock register bit 2 set as "0"), a PASSULK command is requested before unlocking SPB

lock bit. However, while the device is under Solid Protection mode (lock register bit 1 set as "0"), just

a reset or a power-up cycle can unlock the SPB lock bit.

After the SPB lock bit unlocked, the SPB status can be changed for desired settings. To lock the Solid Protection

Bits after the modiﬁcation has ﬁnished, the SPB Lock Bit must be set once again.

To verify the programming state of the SPB for a given sector, issuing a RDSPB Command to the device is required.

Note:

1. Once SPB Lock Bit is set, its program or erase command will not be executed and time-out without programming

or erasing the SPB.

SPB Register

Bit

Description

Bit Status

Default

Type

00h= SPB for the sector address unprotected

FFh= SPB for the sector address protected

7 to 0 SPB (Solid protected Bit)

00h

Non-volatile

P/N: PM1832

Rev. 1.1, August 02, 2016

73

MX66L51235F

Figure 66. Read SPB Status (RDSPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

Mode 3

Mode 0

SCLK

Command

E2h

32-Bit Address

A31 A30

A2 A1 A0

SI

MSB

Data Out

High-Z

SO

7

6

5

4

3

2

1

0

MSB

Figure 67. SPB Erase (ESSPB) Sequence

CS#

0

1

2

3

4

5

6

7

Mode 3

SCLK

Mode 0

Command

E4h

SI

High-Z

SO

Figure 68. SPB Program (WRSPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39

Mode 3

Mode 0

SCLK

Command

E3h

32-Bit Address

A31 A30

A2 A1 A0

SI

MSB

P/N: PM1832

Rev. 1.1, August 02, 2016

74

MX66L51235F

9-34-4. Dynamic Write Protection Bits

The Dynamic Protection features a volatile type protection to each individual sector. It can protect sectors from

unintentional change, and is easy to disable when there are necessary changes.

All DPBs are default as protected (FFh) after reset or upon power up cycle. Via setting up Dynamic Protection bit (DPB)

by write DPB command (WRDPB), user can cancel the Dynamic Protection of associated sector.

The Dynamic Protection only works on those unprotected sectors whose SPBs are cleared. After the DPB state is

cleared to “0”, the sector can be modiﬁed if the SPB state is unprotected state.

DPB Register

Bit

Description

Bit Status

Default

Type

00h= DPB for the sector address unprotected

FFh= DPB for the sector address protected

7 to 0 DPB (Dynamic protected Bit)

FFh

Volatile

Figure 69. Read DPB Register (RDDPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

Mode 3

Mode 0

SCLK

Command

E0h

32-Bit Address

A31 A30

A2 A1 A0

SI

MSB

Data Out

High-Z

SO

7

6

5

4

3

2

1

0

MSB

Figure 70. Write DPB Register (WRDPB) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

37 38 39 40 41 42 43 44 45 46 47

Mode 3

Mode 0

SCLK

Command

E1h

Data Byte 1

32-Bit Address

A31 A30

A2 A1 A0

SI

7

6

5

4

3

2

1

0

MSB

P/N: PM1832

Rev. 1.1, August 02, 2016

75

MX66L51235F

9-34-5. Temporary Un-protect Solid write protect bit (USPB)

Temporary Un-protect Solid write Protect Bit is volatile bit. Software can temporarily unprotect write protect sectors

despite of SPBs' property when DPBs are cleared. While the USPB=1, all the SPBs’ property is masked.

Notes:

1. Upon power up, the USPB status is default protected. The USPB can be unprotected (to “0”) or protected (to “1”)

as often as needed. The hardware reset will reset USPB/DPB to their default values.

2. Please refer to "9-34-7. Sector Protection States Summary Table" for the sector state with the protection status of

DPB/SPB/USPB bits.

9-34-6. Gang Block Lock/Unlock (GBLK/GBULK)

These instructions are only effective after WPSEL was executed. The GBLK/GBULK instruction is a chip-based

protected or unprotected operation. It can enable or disable all DPB.

The WREN (Write Enable) instruction is required before issuing GBLK/GBULK instruction.

The sequence of issuing GBLK/GBULK instruction is: CS# goes low → send GBLK/GBULK (7Eh/98h) instruction

→CS# goes high.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

The CS# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed.

9-34-7. Sector Protection States Summary Table

Protection Status

Sector State

DPB bit

SPB bit

USPB bit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Unprotect

Protect

P/N: PM1832

Rev. 1.1, August 02, 2016

76

MX66L51235F

9-34-8. SPB Password Protection Mode

The security level of Password Protection Method is higher than the Solid protection mode. The 64 bit password is

requested before modify SPB lock bit status. When device is under password protection mode, the SPB lock bit is

cleared to “0”, after a power-up cycle or Reset Command.

A correct password is required for PASSULK command, to unlock the SPB lock bit. Await 2us is necessary

to unlocked the device after valid password is given. After that, the SPB bits are allows to be changed. The

PASSULK command are issued slower than 2 μs every time, to prevent hacker from trying all the 64-bit password

combinations.

To place the device in password protection mode, a few more steps are required. First, prior to entering the

password protection mode, it is necessary to set a 64-bit password to verify it. Password veriﬁcation is only

allowed during the password programming operation. Second, the password protection mode is then activated by

programming the Password Protection Mode Lock Bit to clear to ”0”. This operation is not reversible. Once the bit is

programmed, it cannot be erased, and the device remains permanently in password protection mode, and the 64-bit

password can neither be retrieved nor reprogrammed. Moreover, all commands to the address where the password

is stored are disabled.

The password is all “1”s when shipped from the factory, it is only capable of programming "0"s under WRPASS

command. All 64-bit password combinations are valid as a password. No special address is required for

programming the password. The password is no longer readable after the Password Protection mode is selected by

programming Lock register bit 2 to "0".

Once sector under protected status, device will ignores the program/erase command, enable status polling and

returns to read mode without contents change. The DPB, SPB and SPB lock bit status of each sector can be

veriﬁed by issuing RDDPB, RDSPB, and RDSPBLK commands.

● The unlock operation may fail if the password provided by PASSULK command does not match the previously

entered password. It causes the same result when a programming operation is performed on a protected sector.

The P_FAIL bit is set to 1 and the WIP Bit remains set.

● It is not allowed to execute the PASSULK command faster than every 100us ± 20us. The reason behind it is to

make it impossible to hack into the system by running through all the combinations of a set of 64-bit password (58

million years). To verify if the device has completed the password unlock command and is available to process

a new password command, the Read Status Register command is needed to read the WIP bit. When a valid

password is provided the password unlock command does not insert the 100us delay before returning the WIP

bit to zero.

● It is not feasible to set the SPB Lock bit if the password is missing after the Password Mode is selected.

Password Register (PASS)

Field

Name

Description

Bits

Function Type

Default State

Non-volatile OTP storage of 64 bit password. The

password is no longer readable after the password

protection mode is selected by programming Lock

register bit 2 to zero.

Hidden

Password

63 to 0 PWD

OTP FFFFFFFFFFFFFFFFh

P/N: PM1832

Rev. 1.1, August 02, 2016

77

MX66L51235F

9-35. Program/Erase Suspend/Resume

The device allow the interruption of Sector-Erase, Block-Erase or Page-Program operations and conduct other

operations.

After issue suspend command, the system can determine if the device has entered the Erase-Suspended mode

through Bit2 (PSB) and Bit3 (ESB) of security register. (please refer to "Table 9. Security Register Deﬁnition")

The latency time of erase operation :

Suspend to suspend ready timing: 20us.

Resume to another suspend timing: 1ms.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-36. Erase Suspend

Erase suspend allow the interruption of all erase operations. After the device has entered Erase-Suspended mode,

the system can read any sector(s) or Block(s) except those being erased by the suspended erase operation.

Reading the sector or Block being erase suspended is invalid.

After erase suspend, WEL bit will be clear, only read related, resume and reset command can be accepted. (including:

03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h, 66h, 99h,

00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h)

If the system issues an Erase Suspend command after the sector erase operation has already begun, the device

will not enter Erase-Suspended mode until 20us time has elapsed.

Erase Suspend Bit (ESB) indicates the status of Erase Suspend operation. Users may use ESB to identify the state

of ﬂash memory. After the ﬂash memory is suspended by Erase Suspend command, ESB is set to "1". ESB is

cleared to "0" after erase operation resumes.

9-37. Program Suspend

Program suspend allows the interruption of all program operations. After the device has entered Program-

Suspended mode, the system can read any sector(s) or Block(s) except those being programmed by the suspended

program operation. Reading the sector or Block being program suspended is invalid.

After program suspend, WEL bit will be cleared, only read related, resume and reset command can be accepted.

(including: 03h, 0Bh, 3Bh, 6Bh, BBh, EBh, 5Ah, C0h, 06h, 04h, 2Bh, 9Fh, AFh, 05h, ABh, 90h, B1h, C1h, B0h, 30h,

66h, 99h, 00h, 35h, F5h, 15h, 2Dh, 27h, A7h, E2h, E0h, 16h)

Program Suspend Bit (PSB) indicates the status of Program Suspend operation. Users may use PSB to identify the

state of ﬂash memory. After the ﬂash memory is suspended by Program Suspend command, PSB is set to "1". PSB

is cleared to "0" after program operation resumes.

P/N: PM1832

Rev. 1.1, August 02, 2016

78

MX66L51235F

Figure 71. Suspend to Read Latency

Program latency : 20us

Erase latency:20us

Suspend Command

Read Command

CS#

[B0]

Figure 72. Resume to Read Latency

TSE/TBE/TPP

Resume Command

Read Command

CS#

[30]

Figure 73. Resume to Suspend Latency

1ms

Suspend

Command

[B0]

Resume Command

CS#

[30]

P/N: PM1832

Rev. 1.1, August 02, 2016

79

MX66L51235F

9-38. Write-Resume

The Write operation is being resumed when Write-Resume instruction issued. ESB or PSB (suspend status bit) in

Status register will be changed back to “0”

The operation of Write-Resume is as follows: CS# drives low → send write resume command cycle (30h) → drive

CS# high. By polling Busy Bit in status register, the internal write operation status could be checked to be completed

or not. The user may also wait the time lag of TSE, TBE, TPP for Sector-erase, Block-erase or Page-programming.

WREN (command "06") is not required to issue before resume. Resume to another suspend operation requires

latency time of 1ms.

Please note that, if "performance enhance mode" is executed during suspend operation, the device can not

be resumed. To restart the write command, disable the "performance enhance mode" is required. After the

"performance enhance mode" is disabled, the write-resume command is effective.

9-39. No Operation (NOP)

The “No Operation” command is only able to terminate the Reset Enable (RSTEN) command and will not affect any

other command.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

9-40. Software Reset (Reset-Enable (RSTEN) and Reset (RST))

The Software Reset operation combines two instructions: Reset-Enable (RSTEN) command following a Reset (RST)

command. It returns the device to a standby mode. All the volatile bits and settings will be cleared then, which

makes the device return to the default status as power on.

To execute Reset command (RST), the Reset-Enable (RSTEN) command must be executed ﬁrst to perform the

Reset operation. If there is any other command to interrupt after the Reset-Enable command, the Reset-Enable will

be invalid.

Both SPI (8 clocks) and QPI (2 clocks) command cycle can accept by this instruction. The SIO[3:1] are don't care

when during SPI mode.

If the Reset command is executed during program or erase operation, the operation will be disabled, the data under

processing could be damaged or lost.

The reset time is different depending on the last operation. For details, please refer to "Table 13. Reset Timing-

(Other Operation)" for tREADY2.

P/N: PM1832

Rev. 1.1, August 02, 2016

80

MX66L51235F

Figure 74. Software Reset Recovery

Stand-by Mode

66

99

CS#

tReady2

Mode

Note: Refer to "Table 13. Reset Timing-(Other Operation)" for tReady2 data.

Figure 75. Reset Sequence (SPI mode)

tSHSL

CS#

Mode 3

Mode 0

Mode 3

Mode 0

SCLK

SIO0

Command

66h

Command

99h

Figure 76. Reset Sequence (QPI mode)

tSHSL

CS#

MODE 3

MODE 0

MODE 3

MODE 0

SCLK

MODE 0

Command

SIO[3:0]

66h

99h

P/N: PM1832

Rev. 1.1, August 02, 2016

81

MX66L51235F

9-41. Read SFDP Mode (RDSFDP)

The Serial Flash Discoverable Parameter (SFDP) standard provides a consistent method of describing the functional

and feature capabilities of serial ﬂash devices in a standard set of internal parameter tables. These parameter tables

can be interrogated by host system software to enable adjustments needed to accommodate divergent features

from multiple vendors. The concept is similar to the one found in the Introduction of JEDEC Standard, JESD68 on

CFI.

The sequence of issuing RDSFDP instruction is CS# goes low→send RDSFDP instruction (5Ah)→send 3 address

bytes on SI pin→send 1 dummy byte on SI pin→read SFDP code on SO→to end RDSFDP operation can use CS#

to high at any time during data out.

SFDP is a JEDEC standard, JESD216.

Figure 77. Read Serial Flash Discoverable Parameter (RDSFDP) Sequence

CS#

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

SCLK

Command

5Ah

24 BIT ADDRESS

SI

23 22 21

3

2

1

0

High-Z

SO

CS#

47

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

SCLK

Dummy Cycle

7

6

5

4

3

2

0

1

SI

DATA OUT 2

DATA OUT 1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

0

1

SO

MSB

P/N: PM1832

Rev. 1.1, August 02, 2016

82

MX66L51235F

Table 9. Signature and Parameter Identiﬁcation Data Values

SFDP Table (JESD216) below is for MX66L51235FMI-10G, MX66L51235FZ2I-10G and MX66L51235FXDI-10G

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

00h

07:00

53h

01h

02h

03h

04h

05h

15:08

23:16

31:24

07:00

15:08

46h

44h

50h

00h

01h

46h

44h

50h

00h

01h

SFDP Signature

Fixed: 50444653h

SFDP Minor Revision Number

SFDP Major Revision Number

Start from 00h

Start from 01h

This number is 0-based. Therefore,

0 indicates 1 parameter header.

Number of Parameter Headers

Unused

06h

07h

08h

09h

0Ah

0Bh

23:16

31:24

07:00

15:08

23:16

31:24

01h

FFh

00h

01h

09h

01h

FFh

00h

01h

09h

00h: it indicates a JEDEC speciﬁed

header.

ID number (JEDEC)

Parameter Table Minor Revision

Number

Parameter Table Major Revision

Number

Parameter Table Length

(in double word)

Start from 00h

Start from 01h

How many DWORDs in the

Parameter table

0Ch

0Dh

0Eh

07:00

15:08

23:16

30h

00h

30h

00h

First address of JEDEC Flash

Parameter table

Parameter Table Pointer (PTP)

Unused

0Fh

10h

11h

12h

13h

31:24

07:00

15:08

23:16

31:24

FFh

C2h

00h

01h

04h

FFh

C2h

00h

01h

04h

ID number

(Macronix manufacturer ID)

Parameter Table Minor Revision

Number

Parameter Table Major Revision

Number

it indicates Macronix manufacturer

ID

Start from 00h

Start from 01h

Parameter Table Length

(in double word)

How many DWORDs in the

Parameter table

14h

15h

16h

07:00

15:08

23:16

60h

00h

60h

00h

First address of Macronix Flash

Parameter table

Parameter Table Pointer (PTP)

Unused

17h

31:24

FFh

P/N: PM1832

Rev. 1.1, August 02, 2016

83

MX66L51235F

Table 10. Parameter Table (0): JEDEC Flash Parameter Tables

SFDP Table below is for MX66L51235FMI-10G, MX66L51235FZ2I-10G and MX66L51235FXDI-10G

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

00: Reserved, 01: 4KB erase,

10: Reserved,

11: not support 4KB erase

Block/Sector Erase sizes

Write Granularity

01:00

01b

0: 1Byte, 1: 64Byte or larger

02

03

1b

0b

Write Enable Instruction Required 0: not required

for Writing to Volatile Status

1: required 00h to be written to the

Registers

status register

30h

E5h

0: use 50h opcode,

1: use 06h opcode

Write Enable Opcode Select for

Writing to Volatile Status Registers

Note: If target ﬂash status register is

nonvolatile, then bits 3 and 4 must

be set to 00b.

04

0b

Contains 111b and can never be

changed

Unused

07:05

111b

4KB Erase Opcode

31h

32h

33h

15:08

16

20h

1b

20h

F3h

FFh

(1-1-2) Fast Read (Note2)

0=not support 1=support

Address Bytes Number used in

addressing ﬂash array

00: 3Byte only, 01: 3 or 4Byte,

10: 4Byte only, 11: Reserved

18:17

19

01b

0b

Double Transfer Rate (DTR)

Clocking

0=not support 1=support

(1-2-2) Fast Read

(1-4-4) Fast Read

(1-1-4) Fast Read

Unused

0=not support 1=support

20

21

1b

22

1b

23

1b

Unused

31:24

FFh

Flash Memory Density

37h:34h 31:00

1FFF FFFFh

(1-4-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

04:00

38h

0 0100b

states (Note3)

0 0110b: 6; 0 1000b: 8

44h

EBh

08h

6Bh

(1-4-4) Fast Read Number of

Mode Bits (Note4)

Mode Bits:

000b: Not supported; 010b: 2 bits

07:05

010b

EBh

(1-4-4) Fast Read Opcode

39h

3Ah

3Bh

15:08

20:16

(1-1-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

0 1000b

states

0 0110b: 6; 0 1000b: 8

(1-1-4) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

31:24

000b

6Bh

(1-1-4) Fast Read Opcode

P/N: PM1832

Rev. 1.1, August 02, 2016

84

MX66L51235F

SFDP Table below is for MX66L51235FMI-10G, MX66L51235FZ2I-10G and MX66L51235FXDI-10G

Add (h) DW Add Data (h/b) Data

Description

Comment

(Byte)

(Bit)

(Note1)

(h)

(1-1-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

04:00

0 1000b

states

0 0110b: 6; 0 1000b: 8

3Ch

08h

(1-1-2) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

07:05

15:08

20:16

000b

3Bh

(1-1-2) Fast Read Opcode

3Dh

3Eh

3Fh

3Bh

04h

BBh

(1-2-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

0 0100b

states

0 0110b: 6; 0 1000b: 8

(1-2-2) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

000b

(1-2-2) Fast Read Opcode

(2-2-2) Fast Read

Unused

31:24

00

BBh

0b

0=not support 1=support

03:01

04

111b

1b

40h

FEh

(4-4-4) Fast Read

Unused

07:05

111b

FFh

Unused

43h:41h 31:08

45h:44h 15:00

FFh

Unused

(2-2-2) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

20:16

46h

0 0000b

000b

states

0 0110b: 6; 0 1000b: 8

00h

(2-2-2) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

(2-2-2) Fast Read Opcode

Unused

47h

31:24

FFh

49h:48h 15:00

(4-4-4) Fast Read Number of Wait 0 0000b: Not supported; 0 0100b: 4

20:16

4Ah

0 0100b

states

0 0110b: 6; 0 1000b: 8

44h

(4-4-4) Fast Read Number of

Mode Bits

Mode Bits:

000b: Not supported; 010b: 2 bits

23:21

010b

EBh

0Ch

20h

0Fh

52h

10h

D8h

00h

FFh

(4-4-4) Fast Read Opcode

4Bh

4Ch

4Dh

4Eh

4Fh

50h

51h

52h

53h

31:24

07:00

15:08

23:16

31:24

07:00

15:08

23:16

31:24

EBh

0Ch

20h

0Fh

52h

10h

D8h

00h

FFh

Sector/block size = 2^N bytes (Note5)

0Ch: 4KB; 0Fh: 32KB; 10h: 64KB

Sector Type 1 Size

Sector Type 1 erase Opcode

Sector Type 2 Size

Sector/block size = 2^N bytes

00h: N/A; 0Fh: 32KB; 10h: 64KB

Sector Type 2 erase Opcode

Sector Type 3 Size

Sector/block size = 2^N bytes

00h: N/A; 0Fh: 32KB; 10h: 64KB

Sector Type 3 erase Opcode

Sector Type 4 Size

00h: N/A, This sector type doesn't

exist

Sector Type 4 erase Opcode

P/N: PM1832

Rev. 1.1, August 02, 2016

85

MX66L51235F

Table 11. Parameter Table (1): Macronix Flash Parameter Tables

SFDP Table below is for MX66L51235FMI-10G, MX66L51235FZ2I-10G and MX66L51235FXDI-10G

Add (h) DW Add Data (h/b) Data

Description

Comment

2000h=2.000V

2700h=2.700V

3600h=3.600V

(Byte)

(Bit)

(Note1)

(h)

07:00

15:08

00h

36h

00h

36h

Vcc Supply Maximum Voltage

61h:60h

1650h=1.650V, 1750h=1.750V

2250h=2.250V, 2300h=2.300V

2350h=2.350V, 2650h=2.650V

2700h=2.700V

23:16

31:24

00h

27h

00h

27h

Vcc Supply Minimum Voltage

63h:62h

H/W Reset# pin

H/W Hold# pin

0=not support 1=support

00

01

02

03

1b

0b

1b

Deep Power Down Mode

S/W Reset

Reset Enable (66h) should be

issued before Reset Opcode

1001 1001b

(99h)

S/W Reset Opcode

65h:64h 11:04

F99Dh

Program Suspend/Resume

Erase Suspend/Resume

Unused

0=not support 1=support

12

13

14

15

1b

Wrap-Around Read mode

Wrap-Around Read mode Opcode

0=not support 1=support

1b

66h

67h

23:16

C0h

64h

08h:support 8B wrap-around read

16h:8B&16B

32h:8B&16B&32B

Wrap-Around Read data length

31:24

64h

64h:8B&16B&32B&64B

Individual block lock

0=not support 1=support

00

01

1b

0b

Individual block lock bit

(Volatile/Nonvolatile)

0=Volatile 1=Nonvolatile

1110 0001b

(E1h)

Individual block lock Opcode

09:02

10

Individual block lock Volatile

protect bit default protect status

0=protect 1=unprotect

0b

CB85h

6Bh:68h

Secured OTP

Read Lock

Permanent Lock

Unused

0=not support 1=support

11

12

1b

0b

13

0b

15:14

31:16

11b

FFh

Unused

FFh

Unused

6Fh:6Ch 31:00

MX66L51235FMI-10G-SFDP_2016-08-02,SF10

P/N: PM1832

Rev. 1.1, August 02, 2016

86

MX66L51235F

Note 1: h/b is hexadecimal or binary.

Note 2: (x-y-z) means I/O mode nomenclature used to indicate the number of active pins used for the opcode (x),

address (y), and data (z). At the present time, the only valid Read SFDP instruction modes are: (1-1-1), (2-2-2),

and (4-4-4)

Note 3: Wait States is required dummy clock cycles after the address bits or optional mode bits.

Note 4: Mode Bits is optional control bits that follow the address bits. These bits are driven by the system controller

if they are speciﬁed. (eg,read performance enhance toggling bits)

Note 5: 4KB=2^0Ch,32KB=2^0Fh,64KB=2^10h

Note 6: All unused and undeﬁned area data is blank FFh for SFDP Tables that are deﬁned in Parameter

Identiﬁcation Header. All other areas beyond deﬁned SFDPTable are reserved by Macronix.

P/N: PM1832

Rev. 1.1, August 02, 2016

87

MX66L51235F

10. RESET

Driving the RESET# pin low for a period of tRLRH or longer will reset the device. After reset cycle, the device is at

the following states:

- Standby mode

- All the volatile bits such as WEL/WIP/SRAM lock bit will return to the default status as power on.

- 3-byte address mode

If the device is under programming or erasing, driving the RESET# pin low will also terminate the operation and data

could be lost. During the resetting cycle, the SO data becomes high impedance and the current will be reduced to

minimum.

Figure 78. RESET Timing

CS#

tRHSL

SCLK

tRH

tRS

RESET#

tRLRH

tREADY1 / tREADY2

Table 12. Reset Timing-(Power On)

Symbol Parameter

tRHSL Reset# high before CS# low

Min.

10

Typ.

Max.

Unit

us

tRS

tRH

Reset# setup time

Reset# hold time

15

ns

tRLRH Reset# low pulse width

10

us

tREADY1 Reset Recovery time

35

us

Table 13. Reset Timing-(Other Operation)

Symbol Parameter

tRHSL Reset# high before CS# low

Min.

10

Typ.

Max.

Unit

us

tRS

tRH

Reset# setup time

Reset# hold time

15

ns

tRLRH Reset# low pulse width

10

us

Reset Recovery time (During instruction decoding)

Reset Recovery time (for read operation)

40

35

us

Reset Recovery time (for program operation)

tREADY2 Reset Recovery time(for SE4KB operation)

Reset Recovery time (for BE64K/BE32KB operation)

Reset Recovery time (for Chip Erase operation)

Reset Recovery time (for WRSR operation)

310

12

25

100

40

us

ms

P/N: PM1832

Rev. 1.1, August 02, 2016

88

MX66L51235F

11. POWER-ON STATE

The device is at below states when power-up:

- Standby mode (please note it is not deep power-down mode)

- Write Enable Latch (WEL) bit is reset

The device must not be selected during power-up and power-down stage unless the VCC achieves below correct

level:

- VCC minimum at power-up stage and then after a delay of tVSL

- GND at power-down

Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level.

An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change

during power up state. When VCC is lower than VWI (POR threshold voltage value), the internal logic is reset and

the ﬂash device has no response to any command.

For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not

guaranteed. The write, erase, and program command should be sent after the below time delay:

- tVSL after VCC reached VCC minimum level

The device can accept read command after VCC reached VCC minimum and a time delay of tVSL.

Please refer to the "power-up timing".

Note:

- To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is

recommended. (generally around 0.1uF)

- At power-down stage, the VCC drops below VWI level, all operations are disable and device has no response

to any command. The data corruption might occur during the stage while a write, program, erase cycle is in

progress.

P/N: PM1832

Rev. 1.1, August 02, 2016

89

MX66L51235F

12. ELECTRICAL SPECIFICATIONS

Table 14. ABSOLUTE MAXIMUM RATINGS

RATING

VALUE

Ambient Operating Temperature

Storage Temperature

Applied Input Voltage

Applied Output Voltage

VCC to Ground Potential

Industrial grade

-40°C to 85°C

-65°C to 150°C

-0.5V to VCC+0.5V

-0.5V to 4.0V

NOTICE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage

to the device. This is stress rating only and functional operational sections of this speciﬁcation is not implied.

Exposure to absolute maximum rating conditions for extended period may affect reliability.

2. Speciﬁcations contained within the following tables are subject to change.

3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, see

Figure 79, and Figure 80.

Figure 80. Maximum Positive Overshoot Waveform

Figure 79. Maximum Negative Overshoot Waveform

20ns

Vss

Vcc + 2.0V

Vss-2.0V

Vcc

20ns

Table 15. CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Parameter Min.

Typ.

Max.

35

Unit

Conditions

VIN = 0V

CIN

Input Capacitance

pF

COUT Output Capacitance

32

VOUT = 0V

P/N: PM1832

Rev. 1.1, August 02, 2016

90

MX66L51235F

Figure 81. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL

Input timing reference level

Output timing reference level

0.8VCC

0.2VCC

0.7VCC

0.8V

AC

Measurement

Level

0.5VCC

Note: Input pulse rise and fall time are <5ns

Figure 82. OUTPUT LOADING

25K ohm

+1.8V

DEVICE UNDER

TEST

CL

25K ohm

CL=30pF Including jig capacitance

P/N: PM1832

Rev. 1.1, August 02, 2016

91

MX66L51235F

Table 16. DC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 2.7V - 3.6V)

°

Symbol Parameter

Notes

Min.

Typ.

Max.

Units Test Conditions

VCC = VCC Max,

uA

ILI

Input Load Current

Output Leakage Current

1

±4

VIN = VCC or GND

VCC = VCC Max,

uA

ILO

1

±4

100

40

VOUT = VCC or GND

VIN = VCC or GND,

CS# = VCC

ISB1 VCC Standby Current

20

4

uA

Deep Power-down

Current

VIN = VCC or GND,

CS# = VCC

ISB2

uA

f=104MHz, (4 x I/O read)

mA SCLK=0.1VCC/0.9VCC,

SO=Open

40

30

ICC1 VCC Read

1

20

f=84MHz,

mA SCLK=0.1VCC/0.9VCC,

SO=Open

VCC Program Current

Program in Progress,

CS# = VCC

ICC2

(PP)

20

40

30

mA

VCC Write Status

ICC3

Program status register in

mA

Register (WRSR) Current

progress, CS#=VCC

VCC Sector/Block (32K,

ICC4 64K) Erase Current

(SE/BE/BE32K)

Erase in Progress,

CS#=VCC

1

20

30

40

mA

VCC Chip Erase Current

Erase in Progress,

CS#=VCC

ICC5

(CE)

50

mA

VIL

VIH

VOL

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.5

0.8

V

0.7VCC

VCC+0.4

V

0.2

IOL = 100uA

IOH = -100uA

VOH Output High Voltage

Notes:

VCC-0.2

1. Typical values at VCC = 3.3V, T = 25 C. These currents are valid for all product versions (package and speeds).

°

2. Typical value is calculated by simulation.

P/N: PM1832

Rev. 1.1, August 02, 2016

92

MX66L51235F

Table 17. AC CHARACTERISTICS (Temperature = -40 C to 85 C, VCC = 2.7V - 3.6V)

°

Symbol Alt. Parameter

Min.

Typ.

Max. Unit

fSCLK

fRSCLK

fC Clock Frequency for all commands (except Read)

fR Clock Frequency for READ instructions

fT Clock Frequency for 2READ instructions

fQ Clock Frequency for 4READ instructions

D.C.

133

50

MHz

ns

84⁽⁷⁾

fTSCLK

tCH⁽¹⁾

Others (fSCLK)

3.3

9

tCLH Clock High Time

Normal Read (fRSCLK)

ns

Others (fSCLK)

Normal Read (fRSCLK)

3.3

9

0.1

3

ns

V/ns

ns

tCL⁽¹⁾

tCLL Clock Low Time

tCLCH⁽²⁾

tCHCL⁽²⁾

Clock Rise Time (peak to peak)

Clock Fall Time (peak to peak)

tSLCH tCSS CS# Active Setup Time (relative to SCLK)

tCHSL CS# Not Active Hold Time (relative to SCLK)

tDVCH tDSU Data In Setup Time

3

2

ns

tCHDX

tCHSH

tSHCH

tDH Data In Hold Time

2

3

7

ns

us

CS# Active Hold Time (relative to SCLK)

CS# Not Active Setup Time (relative to SCLK)

Read

tSHSL⁽³⁾tCSH CS# Deselect Time

Write/Erase/Program

30

tSHQZ⁽²⁾tDIS Output Disable Time

8

9

7

Loading: 30pF

Loading: 15pF

Clock Low to Output Valid

tCLQV

tV

Loading: 30pF/15pF

tHO Output Hold Time

Write Protect Setup Time

Write Protect Hold Time

tCLQX

tWHSL⁽³⁾

tSHWL⁽³⁾

tDP⁽²⁾

1

20

100

CS# High to Deep Power-down Mode

CS# High to Standby Mode without Electronic Signature

Read

CS# High to Standby Mode with Electronic Signature Read

Write Status/Conﬁguration Register Cycle Time

Write Extended Address Register

Byte-Program

10

30

tRES1⁽²⁾

us

tRES2⁽²⁾

tW

tWREAW

tBP

30

40

us

ms

ns

40

16

30

us

tPP

Page Program Cycle Time

0.5

1.5

ms

0.008+

tPP⁽⁵⁾

Page Program Cycle Time (n bytes)

(nx0.004)

1.5

ms

(6)

tSE

tBE32

tBE

Sector Erase Cycle Time

30

120

650

300

ms

s

Block Erase (32KB) Cycle Time

Block Erase (64KB) Cycle Time

Chip Erase Cycle Time

150

280

110

tCE

Notes:

1. tCH + tCL must be greater than or equal to 1/ Frequency.

2. Typical values given for TA=25 C. Not 100% tested.

°

3. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.

4. Test condition is shown as Figure 81 and Figure 82.

5. While programming consecutive bytes, Page Program instruction provides optimized timings by selecting to

program the whole 256 bytes or only a few bytes between 1~256 bytes.

6. “n”=how many bytes to program. In the formula, while n=1, byte program time=12us.

7. By default dummy cycle value. Please refer to the "Table 1. Read performance Comparison".

P/N: PM1832

Rev. 1.1, August 02, 2016

93

MX66L51235F

13. OPERATING CONDITIONS

At Device Power-Up and Power-Down

AC timing illustrated in Figure 83 and Figure 84 are for the supply voltages and the control signals at device power-

up and power-down. If the timing in the ﬁgures is ignored, the device will not operate correctly.

During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be

selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL.

Figure 83. AC Timing at Device Power-Up

VCC(min)

VCC

GND

tVR

tSHSL

CS#

tSHCH

tSLCH

tCHSL

tCHSH

SCLK

tDVCH

tCHCL

tCHDX

tCLCH

MSB IN

LSB IN

SI

High Impedance

SO

Symbol

Parameter

Notes

Min.

Max.

Unit

tVR

VCC Rise Time

1

500000

us/V

Notes:

1. Sampled, not 100% tested.

2. For AC spec tCHSL, tSLCH, tDVCH, tCHDX, tSHSL, tCHSH, tSHCH, tCHCL, tCLCH in the ﬁgure, please refer to

Table 17. AC CHARACTERISTICS.

P/N: PM1832

Rev. 1.1, August 02, 2016

94

MX66L51235F

Figure 84. Power-Down Sequence

During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation.

VCC

CS#

SCLK

Figure 85. Power-up Timing

V

CC

V

(max)

CC

Chip Selection is Not Allowed

V

(min)

CC

Device is fully accessible

tVSL

V

WI

time

P/N: PM1832

Rev. 1.1, August 02, 2016

95

MX66L51235F

Figure 86. Power Up/Down and Voltage Drop

When powering down the device, VCC must drop below V_PWDfor at least tPWD to ensure the device will initialize

correctly during power up. Please refer to "Figure 86. Power Up/Down and Voltage Drop" and "Table 18. Power-Up/

Down Voltage and Timing" below for more details.

VCC

VCC (max.)

Chip Select is not allowed

VCC (min.)

tVSL

Full Device

Access

Allowed

(max.)

V

PWD

tPWD

Time

Table 18. Power-Up/Down Voltage and Timing

Symbol Parameter

Min.

Max.

Unit

us

V

tVSL

VWI

V_PWD

VCC(min.) to device operation

Command Inhibit Voltage

800

2.3

2.5

0.9

VCC voltage needed to below V_PWDfor ensuring initialization will occur

V

tPWD The minimum duration for ensuring initialization will occur

VCC VCCPower Supply

300

2.7

us

V

3.6

Note: These parameters are characterized only.

13-1. INITIAL DELIVERY STATE

The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status

Register contains 00h (all Status Register bits are 0).

P/N: PM1832

Rev. 1.1, August 02, 2016

96

MX66L51235F

14. ERASE AND PROGRAMMING PERFORMANCE

Parameter

Min.

Typ. ⁽¹⁾

Max. ⁽²⁾

40

Unit

ms

s

Write Status Register Cycle Time

Sector Erase Cycle Time (4KB)

Block Erase Cycle Time (32KB)

Block Erase Cycle Time (64KB)

Chip Erase Cycle Time

30

0.15

0.28

110

120

0.65

300

30

s

Byte Program Time (via page program command)

Page Program Time

16

us

0.15

100,000

1.5

ms

cycles

Erase/Program Cycle

Notes:

1. Typical program and erase time assumes the following conditions: 25 C, 3.3V, and all zero pattern.

°

2. Under worst conditions of 85 C and 2.7V.

°

3. System-level overhead is the time required to execute the ﬁrst-bus-cycle sequence for the programming

command.

4. The maximum chip programming time is evaluated under the worst conditions of 0°C, VCC=3.3V, and 100K

cycle with 90% conﬁdence level.

15. DATA RETENTION

Parameter

Condition

Min.

Max.

Unit

Data retention

55˚C

20

years

16. LATCH-UP CHARACTERISTICS

Min.

Max.

Input Voltage with respect to GND on all power pins, SI, CS#

Input Voltage with respect to GND on SO

Current

-1.0V

2 VCCmax

VCC + 1.0V

+100mA

-100mA

Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time.

P/N: PM1832

Rev. 1.1, August 02, 2016

97

MX66L51235F

17. ORDERING INFORMATION

PART NO.

CLOCK (MHz) TEMPERATURE

PACKAGE

Remark

MX66L51235FMI-10G

MX66L51235FZ2I-10G

MX66L51235FXDI-10G

104

-40 C to 85 C

16-SOP (300mil)

8-WSON (8x6mm)

°

-40 C to 85 C

°

24-Ball BGA

-40 C to 85 C

°

(5x5 ball array)

P/N: PM1832

Rev. 1.1, August 02, 2016

98

MX66L51235F

18. PART NAME DESCRIPTION

MX 66 51235F Z2

L

I

10 G

OPTION:

G: RoHS Compliant & Halogen-free

SPEED:

10: 104MHz

TEMPERATURE RANGE:

I: Industrial (-40°C to 85°C)

PACKAGE:

M: 16-SOP (300mil)

Z2: 8-WSON (8x6mm)

XD: 24-Ball BGA (5x5 ball array)

DENSITY & MODE:

51235F: 512Mb

TYPE:

L: 3V

DEVICE:

66: Serial NOR Flash

P/N: PM1832

Rev. 1.1, August 02, 2016

99

MX66L51235F

19. PACKAGE INFORMATION

P/N: PM1832

Rev. 1.1, August 02, 2016

100

MX66L51235F

P/N: PM1832

Rev. 1.1, August 02, 2016

101

MX66L51235F

P/N: PM1832

Rev. 1.1, August 02, 2016

102

MX66L51235F

20. REVISION HISTORY

Revision No. Description

Page

Date

1.0

1. Corrected content error

P5,7,8,24,32,33, JUN/06/2013

39,41,43,58-59,65,

P

71,76,78,80-81,93,96

P

2. Removed "Advanced Information"

3. Added USPB information.

4. Modiﬁed Reset timing deﬁnition.

5. Added Power Up/Down and Voltage Drop information

6. Added note on WP# setup

P4

P73,79

P84,91

P99

P40

7. Modiﬁed maximum CIN and COUT.

P93

"Figure 81. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL"

8. Modiﬁed

. P94

P92-93

1.1

1. Updated parameters for DC/AC Characteristics

2. Updated Erase and Programming Performance

3. Content correction

AUG/02/2016

P97

P51-52,62,65,

67,70-77,96

P90

P102

P100

4. Modiﬁed VCC to Ground Potential parameter

5. Updated 24-Ball BGA (5x5 ball array) package outline

6. Updated 16-pin SOP (300mil) package outline

7. Updated 8-land WSON (8x6mm) package outline

8. Added Key features

P101

P1

9. Updated tVR descriptions

P94,96

P46

P52-54

P87

10. Revised "9-16. Quad Read Mode (QREAD)" descriptions

11. Revised Performance Enhance Mode Reset descriptions

12. Revised Note 6 of SFDP Tables

P/N: PM1832

Rev. 1.1, August 02, 2016

103

MX66L51235F

Except for customized products which has been expressly identiﬁed in the applicable agreement, Macronix's

products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or

household applications only, and not for use in any applications which may, directly or indirectly, cause death,

personal injury, or severe property damages. In the event Macronix products are used in contradicted to their

target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualiﬁed for its

actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or

distributors shall be released from any and all liability arisen therefrom.

tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit,

NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC,

Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich Audio, Rich Book, Rich TV, and FitCAM. The names

and brands of third party referred thereto (if any) are for identiﬁcation purposes only.

For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and speciﬁcations without notice.

104


型号：	MX66L51235FXDI-10G
厂家：	MACRONIX INTERNATIONAL
描述：	3V, 512M-BIT [x 1/x 2/x 4] CMOS MXSMIOÂ® (SERIAL MULTI I/O) FLASH MEMORY 时钟内存集成电路
文件：	总104页 (文件大小：1762K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MX66L51235FXDI-10G [Macronix]

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