MX8335 [Macronix]
RAMBUS CLOCK GENERATOR; RAMBUS时钟发生器
| 型号： | MX8335 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | RAMBUS CLOCK GENERATOR |
| 文件： | 总6页 (文件大小：43K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INDEX
PRELIMINARY
MMX8 3 3 5
RAMBUS CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
• Clock generator for RambusTM Channel
• Provide two Rambus interface-level outputs with
frequency from 200MHz to 267MHz
• Multiplication ratio 40/3 allows low cost crystal used
as frequency reference
• Provide chip output enable pin (EN) for tri-state
control
• 3.0V~3.6V power supply range
The MX8335 is a clock synthesizer chip for Rambus
channel. With an advanced phase locked loop technol-
ogy, the MX8335 provides two clock outputs (CLKOUT)
with frequency ranging from 200MHz to 267MHz. The
desired high speed clock is the 40/3 Multiplication ratio
of a reference input clock. The reference clock could
be supplied by an external crystal ranging from 15MHz
to 20MHz.
• 8-pin SOP (150mil) package
PIN DESCRIPTION
PIN CONFIGURATIONS
8-PIN SOP
SYMBOL PIN TYPE PIN NUMBER DESCRIPTION
EN
I
1
When high, CLKOUTs are
enabled.
EN
XO
1
2
3
4
8
7
6
5
VDD
When low, CLKOUTs are
tristate.
CLKOUT
GND
XI
With an internal pull high
resistor.
GND
CLKOUT
XO
O
I
2
3
4
5
6
7
8
Crystal output pin.
Crystal input pin.
Ground.
XI
GND
CLKOUT
GND
CLKOUT
VDD
O
O
200-267Mhz output.
Ground.
200-267Mhz output.
Power supply.
BLOCK DIAGRAM
DIVIDER
÷40
200MHz~267MHz
200MHz~267MHz
XO
XI
CHARGE
PUMP
DIVIDER
÷3
15MHz~20MHz
VCO
PFC
OSC
VDD
LOOP
FILTER
EN
Rambus and
are trademarks of Rambus Inc.
REV. 1.4, APR. 15, 1996
P/N: PM0334
1
INDEX
MX8 3 3 5
FUNCTIONAL DESCRIPTION
OUTPUT CIRCUITRY
TheRambusclockgeneratorisanintegratedcircuitofthe
phase locked loop frequency synthesizer. It provides two
clock outputs for dual Rambus channel systems.
The clock source output is an open drain NMOS transis-
tor. The MX8335 enables and disables the NMOS
transistor alternately to drive the output load. The biasing
circuity for the MX8335 is shown in Fig. 1.
As shown in the block diagram, a phase locked loop
consists of dividers, phase frequency comparator(PFC),
charge pump, voltage controlled oscillator(VCO), and
loop filter. All components for PLL are integrated inside
the chip.
Output high voltage is determined by the Vt voltage. To
set a value for output low voltage, we must determine the
Rs and Rt values. Rt is determined by system operating
conditions, which may be ranging from 25 Ohms to 50
Ohms. Rs can be acquired by following equation:
Rs=(Rt x Vt/Vs)-(Rt+Ro)
The dividers provide a fixed multiplication ratio 40/3.
When a reference clock, ranging from 15MHz to 20MHz
and either coming from crystal or external system refer-
ence, provides to PLL, the clock outputs should fall in the
rangeof200-266.67MHz. Followingexamplesshowsthe
relationship between input and output frequencies:
Ro=On resistor of NMOS transistor
Vs=Signal Swing
For a system with Vt=2.5V, Rt=25 Ohms, Vs=1.4V, and
the MX8335's Ro=10 Ohms
Rs=(25 x 2.5/1.4)-(25+10)=9.6 Ohms
Reference Frequency Output Frequency
15MHz
200MHz
18.75MHz
20MHz
250MHz
266.67MHz
Cx capacitor can help equalize rising and falling rate. Rx
resistor helps decrease the rising time. Both Rx and Cx
depend on Rt+Rs and PCB layout. Typical values of Rx
and Cx for 25 Ohms line impedance are ∞ Ohms and 4pF
respectively. For 50 Ohms line impedance, Rx is about
100 Ohms, and Cx is about 2pF. Special care must be
taken during physical design of the output bias circuits
and the Rambus channel.
FREQUENCY REFERENCE
The internal reference oscillator includes all passive
components required. A proper resonant crystal should
be connected between XO and XI. To minimize the noise
pick up, maintain short lead lengths between the crystal
and the MX8335 by soldering the crystal to the ground
plane. The lead length of the capacitor should be kept to
minimum to reduce noise suscepibility. The reference
clockcanalsobesuppliedbyexternalclocksignal. Inthis
case, the reference clock should connected to XI and XO
should be unconnected.
Rx, Cx, and Rs should be as close to the MX8335 as
possible, and are prefered to use SMD devices. The
signal path must be built using controlled impedence
transmission line technique.
POWER SUPPLY CONDITIONING
Clock jittering is the undesirable variations in frequency
andphaseofaclocksource. InPLL,therearemanyclock
jitter sources, such as flicker and thermal noise in elec-
tronic element, electromagnetic coupling, power supply
noise, signal reflection, ground bounce, physical
vibration and variation in temperature and humidity.
Among these noise factors, the power supply noise and
ground bounce are most crucial and should be given
special care. To eliminate the supply noise, it is judicious
to decouple the power noise as shown in Fig. 1, where
C1=0.01uF, C2=0.1uF, and C3=47uF.
2
INDEX
MX8 3 3 5
FIG. 1 INTERFACE CIRCUITRY
C1 C2 C3
Vdd
1
8
2
3
7
6
For anther Rambus Channel or floating
Rx
Vt
4
5
Rambus Channel ZI
Rs
Rt=ZI
Cx
NOTICE:
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under ABSOLUTE MAXI-
MUM RATINGS may cause permanent damage to the device.
Thisisastressratingonlyandfunctionaloperationofthedevice
at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Expo-
suretoabsolutemaximumratingconditionsforextendedperiod
may affect reliability.
RATING
VALUE
Storage Temperature
Applied Input Voltage
Applied Output Voltage
Supply Voltage
-85oC to 150oC
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
-0.5V to 5V
NOTICE:
Specifications contained within the following tables are subject
to change.
Operating Temperature
Power Dissipation
0 to 70oC
0.5Watts
DC CHARACTERISTICS TA = 0oC to 70oC, VDD = 3.0 V to 3.6 V
SYMBOL PARAMETER
MIN.
TYP.
MAX.
UNIT
V
CONDITIONS
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
VDD Current
0.8
2.4
V
-5
uA
IIH
5
uA
IVDD
CI
30
35
40
10
50
2.7
10
mA
pF
Input Capacitance
Line Impedence
ZL
25
2.2
-10
40
5
Ohm
V
Rambus Level
Rambus Level
CLKOUT
VLT
IOH
IOL
Ro
Line Termination Voltage
Output High Current
Output Low Current
Output Resistance
uA
50
10
mA
Ohm
VOL=0.4V, CLKOUT
CLKOUT
15
3
INDEX
MX8 3 3 5
AC CHARACTERISTICS TA = 0oC to 70oC, VDD = 3.0 V to 3.6 V, Note 1
SYMBOL PARAMETER
MIN.
TYP.
MAX.
UNIT CONDITIONS
Dt
Duty Cycle
50
%
CLKOUT
Tj
Jitter (peak to peak)
Rise/Fall Time
Clock stabilization
150
0.5
pS
nS
mS
CLKOUT, over 3 clock cycles
CLKOUT
Tr/Tf
Tst
0.3
5
1. After power is stable
2. Frequency from 0 to 266.67MHz
Aco
Tsk
Ouput asymmetry
TBD
Output skew between two channels
50ps
Equal loading
Note1: The MX8335 parts are tested under 266.67MHz and triggered at falling edge.
ORDERING INFORMATION
PART NO.
MX8335MC
PACKAGE
8-PIN SOP
WAVE FROMS
Vh
CLKOUT
80%
20%
VI
Tf
Tr
Tcycle
Tch
CLKOUT1
CLKOUT2
50%
Tch
Dt=
Tcycle
50%
Tj
Tsk
4
INDEX
MX8 3 3 5
PACKAGE INFORMATION
8-PIN PLASTIC SOP (150 mil)
8
5
ITEM MILLIMETER INCHES
A
B
C
D
E
F
G
H
I
4.95 MAX.
.53 [REF]
1.27 [TP]
.41 [TYP.]
.10 MIN.
1.73 MAX.
1.45 ± .13
5.99 ± .3
3.91 ± .13
1.02
.195 MAX.
.021 [REF]
.050 [TP]
.016 [TYP.]
.004 MIN.
.068 MAX.
.057 ± .005
.236 ± .012
.154 ± .005
.040
1
4
A
J
H
I
K
L
.20 [TYP.]
.76
.008 [TYP.]
.030
J
NOTE:Eachleadcenterlineislocatedwithin.25
mm[.01 inch] of its true position [TP] at
maximum material condition.
G
F
K
E
B
D
L
C
5
INDEX
MX8 3 3 5
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