MX93111FC [Macronix]
Consumer Circuit, CMOS, PQFP128, PLASTIC, QFP-128;
| 型号： | MX93111FC |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | Consumer Circuit, CMOS, PQFP128, PLASTIC, QFP-128 商用集成电路 |
| 文件： | 总98页 (文件大小：1719K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MX93111
MX93111 DATA SHEET
CONTENT
1 INTRODUCTION
1.1 FEATURE
2
3
1.2 DIFFERENCE BETWEEN MX93011C AND MX93111
2 PIN
2.1 PIN OUT FOR 128 PIN PQFP MX93111
2.2 PIN DESCRIPTIONS
4
6
2.3 PIN TYPE ABBREVIATION
2.4 PINS SUMMARY BY PIN TYPE
2.5 MULTIPLEX PINS
9
9
10
3 ARCHITECTURE
3.1 DATA UNIT
13
18
23
28
3.2 MEMORY MAP AND ADDRESSING MODES
3.3 PROGRAM FLOW CONTROL UNIT
3.4 APPLICATION INTERFACE UNIT
4 REGISTERS
4.1 I/O MAPPED REGISTERS SUMMARY
4.2 NON I/O MAPPED REGISTER SUMMARY
4.3 I/O MAPPED REGISTERS DESCRIPTION
4.4 NON I/O MAPPED REGISTER DESCRIPTION
34
35
36
44
5 INSTRUCTIONS
5.1 INSTRUCTION SET SUMMARY
5.2 ACRONYMS AND NOTATIONS
5.3 INSTRUCTION SET DESCRIPTION
47
49
50
6 PCM CODEC
6.1 PCM CODEC OVERVIEW
6.2 FUNCTIONAL DESCRIPTION
6.3 CONTROL REGISTERS DEFINITION
85
88
93
7 CHARACTERISTICS
7.1 DC CHARACTERISTICS
97
7.2 AC TIMING AND CHARACTERISTICS
102
8 PACKAGE INFORMATION
8.0 ORDERING INFORMATION
117
117
8.1 PACKAGE INFORMATION FOR 128 PIN PQFP
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MX93111
1.1 FEATURES
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»Optimized for highly integrated digital answering machine application
»Built in DRAM controller; interface with x1,x4, x8 and x16 configuration
»One 8 bits host interface
»Maximum 9 general input pins , 23 output pins and 8 programmable bi-directional I/O pins
»One external interrupt pins
»1ms internal timer interrupt
»64 K words program space, 48 K internal , in which control code and voice prompt can be built
»64 K words data space , 2.5 K words data RAM internal
»45 MHz running clock , provide 30 MIPs processing power with 40 mA active current
»Built in PLL with 4.096 MHz clock as clock source to achieve 2 mA consumption in power down
mode
operation
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»16 x 16 multiplication and 32 bit accumulation executed in one instruction cycle
»Single cycle normalization instruction
»32 bit barrel shifter with left/right shift 15 bits capability
»32 level hardware stack
»8 Auxiliary registers used in register indirect addressing.
»Zero-overhead hardware looping , maximum 8 instruction words executed repeatedly 1024 times
maximum
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»Built-in one PCM CODEC
»CODECs support 16-bit format linear data
»Support switch paths for DAM (digital answering machine) related applications
»Support two comparators for power-low and battery -low detection
»Support external L..P.F. for D/A output path
»Support external volume control
»On-chip differential line driver
»On-chip ALC (automatic level control)
»On-chip digital volume control of CODEC
»On-chip programmable receive/transmit gain control of CODEC
»Easy interface to FAX or cordless Phone
»Fabricated in 0.5 um 5V CMOS process
»128 pins PQFP package
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1.2 DIFFERENCE between MX93011C and MX93111
MX93011C
MX93111
INTERNAL RAM
SIZE
2K Words
2.5K Words
Bank0 : 0x0000 ~ 0x03FF(1K)
Bank1 : 0x0400 ~ 0x07FF(1K)
0X0800
Bank0 : 0x0000 ~ 0x03FF(1K)
Bank1 : 0x0400 ~ 0x09FF(1.5K)
0X1000
EXTERNAL RAM
STARTING ADDRESS
INTERNAL ROM
SIZE
32k Words
0X8000
7-BIT
48k Words
EXTERNAL ROM
STARTING ADDRESS
REPEAT COUNT
REGISTER
0XC000
10-BIT
AR MODULO
7-BIT
10-BIT
REGISTER
INTERRUPT PENDING REG5 (R)
No
STATUS REGISTER
CONTINUOUS
Overflow problem
Fix continuous “ SQRA”
INSTRUCTION
“SQRA”
EXTENDED OUTPUT OPT21 – OPT19
PORT REGISTER
OPT22 – OPT19
CODEC COMMAND
REGISTER
No
REG5(R/W)
CODEC
REG16(R) : CDRR0
REG16(R/W): CDDR0, CDXR0
RECEIVE/TRANSMIT REG17(W) : CDXR0
REGISTERS
CODEC INTERFACE
Single external codec
interface
Single built-in internal codec
X’ TAL source
FLL Multiplication
Factor Register
(FLLMR)
32.256MHz & 32.768KHz
13-Bit (0 – 0x1FFF)
4.096MHz
5-Bit (12 – 24)
FLL Control Register 12-Bit
No
No
No
(FLLCONR)
FLL Status Register
(FLLSR)
13-Bit
5-Bit
CMCK Divide Ratio
Register
(CMCKDIVR)
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MX93111
2.1 PIN OUT for 128 PIN PQFP MX93111
ED15
ED14
1
102
101
100
AGND
2
AVDD
ED13
3
LOUTN
LOUTP
CMP1I
ED12
4
99
ED11
5
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
ED10
6
CMP1O
CMP2I
ED9
7
ED8
8
CMP2O
VCOMP
GND
ED7
9
ED6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
ED5
TEST1\
TEST0\
HOLD\
ED4
ED3
ED2
HDB0/BIO0
HDB1/BIO1
HDB2/BIO2
HDB3/BIO3
GND
ED1
ED0
GND
MX93111
OPT22
CAS\/OPT21
DRD\/OPT20
DWR\/OPT19
RAS\/IPT8
VDD
VDD
HDB4/BIO4
HDB5/BIO5
HDB6/BIO6
HDB7/BIO7
ACK\/XF\
HRD\/OPT17
HWR\/OPT16
HILO/OPT18
IPT7
GND
EDCE\
EPCE\
ERD\
EWR\
EAD15
EAD14
EAD13
EAD12
EAD11
EAD10
EAD9
IPT6
IPT5
IPT4
IPT3
IPT2
IPT1
IPT0
EAD8
OPT0
EAD7
OPT1
EAD6
OPT2
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2.2 PIN DESCRIPTIONS
1. POWER/CLOCK/CONTROL PINS :
Name
VDD
Pin Type Pin Number
Description
Power
Power
23,47,84
24,51,85,93
17
5 Volt power source pins
Ground pins
GND
FLLEN\
IS
128
1 : Test X‘ tal mode.
0 : Single low X‘ tal mode. High clock will be generated from
FLL
XI
X‘ tal
X‘ tal
I/O(A)
IS
48
49
50
126
90
4.096 MHz crystal oscillator‘ s input
4.096 MHz crystal oscillator‘ s output
Output of internal PLL charge pump circuit.
Power on reset pin.Minium timing 50ms.
Level trigger.Hold down clock to DSP (X‘ tal oscillator or FLL is
still active) and related data ,address and control pins will go to
high-impedance state.
XO
CP
RST\
HOLD\
IS
EROM
IS
IS
127
46
Map all program memory space to external
Falling Edge-triggered non-maskable external interrupt / Test
clock in
NMI\/TCLK
INT1\
IS
45
91
92
Falling Edge-triggered maskable external interrupt
Test pin for CODEC
TEST0\
TEST1\
ISH
ISH
Test pin for CODEC
Note 1: FLLEN\,HOLD\,EROM,GND,NMI\/TCLK,INT1\,TEST0\,TEST1\ pin output low when DSP is in
reset state or in power down mode.
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2. CODEC INTERFACE PINS :
Name
Pin Type Pin Number
Description
AVDD
Power
Power
Power
Power
Power
I(A)
101,124
123
119
102,125
121
94
5V power for analog circuit
5V power for speaker driver
5V power for speaker driver
Ground for analog circuit
Ground for speaker driver
SVDD1
SVDD2
AGND
SGND
VCOMP
CMP2O
CMP2I
CMP1O
CMP1I
LOUTP
Reference voltage for voltage comparator
O(A)
I(A)
95
Voltage comparator 2 output
96
Non-inverting input of voltage comparator 2
Voltage comparator 1 output
O(A)
I(A)
97
98
Non-inverting input of voltage comparator 1
Non-inverting output of LIN-DRV with PGA;
PGA from 0 to 22.5 dB; 1.5 dB/step.
O(A)
99
LOUTN
VBG
AG
O(A)
O(A)
O(A)
100
103
104
Inverting output of LIN-DRV with PGA;
PGA from 0 to 22.5 dB; 1.5 dB/step.
Band-gap reference; normal 1.25V and should not be used
to sink or source current
Internal analog signal ground; normal 2.25V and should not
be used to sink or source current.
VREF
MIC
O(A)
I(A)
105
106
107
Voltage reference; normal 2.25V and can sink 450uA
Microphone input with PRE-PGA; PGA from -15 to 21 dB
Telephone line signal input with PRE-PGA;
PGA from -15 to 21 dB
LIN
I(A)
AUX1
I/O(A)
O(A)
O(A)
O(A)
O(A)
I/O(A)
O(A)
O(A)
O(A)
I/O(A)
O(A)
108
109
110
111
112
113
114
115
116
117
118
Auxiliary signal input with PRE-PGA; PGA from -15 to 21 dB
programmable gain amplifier(PRE-PGA) compensate capacitor
Automatic level control (ALC) time constant
Automatic level control (ALC) DC blocking capacitor output
Automatic level control (ALC) DC blocking capacitor input
1.anti-aliasing filter; 2. As an I/O port for AIN (A/D input)
Programmable Gain Amplifier Offset Capacitor
Option of external passive L.P.F (Low Pass Filter);
Option of external passive L.P.F (Low Pass Filter);
I/O port for SWK and SWH
PGAC1
ALCRC
ALCC1
ALCC2
FILT
PGAC2
LPFC1
LPFC2
AUX2
VR
External speaker volume control; use a variable 10K variable
Resistor.
SPKP
SPKN
O(A)
O(A)
120
122
Non-Inverting output of SPK-DRV with DA-PGA, ATT1 And
ATT2;PGA from 0 to 9 dB; Attenuator 1 & 2 from 0 to -45 dB.
Inverting output of SPK-DRV with DA-PGA, ATT1 And ATT2;
PGA from 0 to 9 dB; Attenuator 1 & 2 from 0 to -45 dB.
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MX93111
3. MEMORY INTERFACE PINS :
Name
Pin Type Pin Number
Description
EAD[15:0]
OA/Z
29-44
External memory address bus. Note 2
ED[15:0]
IT/OA/Z
1-16
External memory data bus. Note 2
EDCE\
EPCE\
ERD\
EWR\
CAS\
OA/Z
OA/Z
OA/Z
OA/Z
OA
25
26
27
28
19
22
20
21
External data memory chip enable. Note 2
External program memory chip enable. Note 2
External memory read enable. Note 2
External data memory write enable. Note 2
DRAM column address select
RAS\
OA/Z
OA
DRAM row address select
DRD\
DWR\
DRAM read enable
OA
DRAM write enable
Note 2: Placed in high-impedance state when DSP is in HOLD mode.
4. PARALLEL INTERFACE ( HOST INTERFACE ) PINS : When HOSTM bit in CTLR =0
Name
HDB[7:0]
HILO
Pin Type Pin Number
Description
IS/OA/Z
IS/OA/Z
IS/OA/Z
IS/OA/Z
OA
80-83,86-89
Parallel data bus to external host controller
High or low byte select. 1: select high byte 0: select low byte
Host read enable
76
78
77
79
HRD\
HWR\
ACK\
Host write enable
Acknowledge to external host that there is response from DSP
to be read by external host.
5. GENERAL PURPOSE I/O PORT PINS
Name
Pin Type Pin Number
Description
IPT[3:0]
IPT[7:4]
IPT8
ISH
IS
68-71
72-75
22
Input ports with internal pull high resister ( R ~= 150 K ohm)
Input ports
Input port
IS
OPT[15:0]
OB
52-67
Output ports
BIO[7:0]
OPT[18:16]
OPT[21:19]
OPT22
IS/OA
OA
80-83,86-89
76-78
19-21
18
Programmable bi-directional I/O ports
Output ports
OA
Output ports
OB
Output ports
XF\
OA
79
External flag. Can be changed directly by SXF/RXF instruction.
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Ver 0.01, December 5, 2000
MX93111
2.3 PIN TYPE ABBREVIATION :
Pin Type Description
Pin Type Description
IS
CMOS level schmidt trigger input buffer
CMOS level schmidt trigger input buffer
with an internal pull high resistor built in
8 mA drive output buffer
OB
Z
16 mA drive output buffer
High impedance state
ISH
OA
I(A)
X‘ tal
O(A)
Crystal oscillator input/output pin
Analog output port
Analog input port
I/O(A)
Analog Bi-direction port
2.4 PINS SUMMARY by PIN TYPE :
Pin Type Signal Name
Pin Type Description
IS
INT1\ , NMI\ , IPT[8:4], HILO, HWR\
HRD\, HOLD\, RST\, EROM, FLLEN\
IPT[3:0], TEST0\, TEST1\
OB
OPT[15:0],OPT22
ISH
OA
IS/OA
BIO[7:0] , HDB[7:0] , OPT[18:16]
CAS\, DRD\, DWR\, RAS\, ACK\
EAD[15:0] , EPCE\ , EDCE\
ERD\ , EWR\ .
IS/OA/Z ED[15:0]
OA/Z
X‘ tal
XI,XO .
I(A)
VCOMP, CMP2I, CMP1I, MIC, LIN
O(A)
CMP2O, CMP1O, LOUTP, LOUTN
VBG, AG, VERF, PGAC1, ALCRC
ALCC1, ALCC2, PGAC2, LPFC1
LPFC2, VR, SPKN, SPKP
I/O(A)
AUX1, FILT, AUX2 , CP
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MX93111
2.5 MULTIPLEX PINS :
HOSTM = 0 ( uP external )
Pin Number Signal Name Description
HOSTM = 1 (uP inside)
Signal Name Description
80-83,86-89 HDB[7:0]
Host data bus
BIO[7:0]
OPT18
OPT17
OPT16
Host data bus
Output port
Output port
Output port
External flag
76
78
77
79
HILO
HRD\
HWR\
ACK\
High low byte select
Host read enable
Host write enable
Acknowledge to HOLD\ XF\
Note : HOSTM is bit 1 of CTLR , Its power-on reset default is 0 .
DFS = 0 ( DRAM interface )
DFS = 1 ( FLASH interface )
Signal Name Description
Pin Number Signal Name Description
19
20
21
22
CAS\
DRD\
DWR\
RAS\
Column address select OPT21
Output port
Output port
Output port
Output port
DRAM read enable
DRAM write enable
Row address select
OPT20
OPT19
IPT8
Note : DFS is bit 1 of EXCTLR , Its power-on reset default is 0 .
2.6 I/O PORT INTERNAL CIRCUIT :
2.6.1. Input port
Pull-high resistor
: IPT0~IPT3, TEST0\, TEST1\
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MX93111
No pull-high resistor
: INT1\, NMI\, IPT4~IPT7, HOLD\
2.6.2. Output port
OPT0~OPT15
2.6.3. Bi-direction port
BIO0~BIO7,
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3. ARCHITECTURE
3.1 DATA UNIT
3.1.1 ALU
3.1.2 ACCUMULATOR
3.1.3 MULTIPLIER
3.2 MEMORY MAP AND ADDRESSING UNIT
3.2.1 MEMORY MAP AND MEMORY INTERFACE
3.2.2 IMMEDIATE ADDRESSING MODE
3.2.3 PAGED MEMORY-DIRECT ADDRESSING
3.2.4 REGISTER INDIRECT ADDRESSING MODE
3.2.5 MODULO ADDRESSING
3.2.6 MISCELLANEOUS ADDRESSING MODE
3.3 PROGRAM FLOW CONTROL UNIT
3.3.1 CLOCK GENERATOR/FLL
3.3.2 RUNNING MODE/PIPE LINE / WAITSTATE
3.3.3 BRANCH/CALL/REPEAT/LOOP/STACK REGISTER
3.3.4 INTERRUPT
VECTOR
MASK
STATUS
INTERRUPTIBLE
NESTING
3.4 APPLICATION INTERFACE UNIT
3.4.1 CODEC INTERFACE
3.4.2 DRAM INTERFACE
3.4.3 I/O FUNCTION
3.4.4 HOST INTERFACE
3.4.5 TIMER
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3.1 DATA UNIT
3.1.1 ALU
ARITHMETIC INSTRUCTIONS:
ABS
ADH/ADHK/ADHL Add data (from memory) or constant to high accumulator
ADL/ADLK/ADLL Add data (from memory) or constant to low accumulator
SBH/SBHK/SBHL Subtract data (from memory) or constant from high accumulator
SBL/SBLK/SBLL Subtract data (from memory) or constant from low accumulator
Absolute value of high accumulator
u Execute ABS on 0x8000 will cause incorrect result, because absolute value of 0x8000 exceed the
maximum positive number (0x7FFF) which can be represented.
u Data format for ALU is assumed to be signed two‘ s complement. Short constant is treated as
unsigned constant.
LOGIC INSTRUCTIONS:
OR/ORK/ORL
OR data (from memory) or constant with high accumulator
AND/ANDK/ANDL AND data (from memory) or constant with high accumulator
XOR/XORK/XORL Exclusive-OR data (from memory) or constant with high accumulator
DATA MOVEMENT INSTRUCTIONS:
LAC/LACK/LACL
Load data (from memory) or constant to high accumulator
Store contents of high or low accumulator to data memory
Load product register to accumulator
SAH/SAL
PAC
APAC/SPAC
POPH/POPL
PSHH/PSHL
Add/Subtract product register to/from accumulator
Pop top of stack to high/low accumulator
Push high/low accumulator onto stack
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MX93111
3.1.2 ACCUMULATOR
SCALING INSTRUCTIONS :
SFL/SFR/SFRS
Shift contents of accumulator left/right/right with sign extended
OVERFLOW MODE SETTING :
SOVM/ROVM
Set/Reset overflow mode
u When OVM bit being set , overflow mode protection is enabled. IF the results of data operation
during add/subtract and shifting instructions execution exceed the maximum or minimum value that
can be represented by the accumulator ,we call this condition as overflow. If overflow mode is
enable in this case , data in accumulator will be saturated to the largest positive or the negative
smallest number that can be represented.( 0x7FFF FFFF or 0x8000 0000)
NORMALIZE INSTRUCTIONS :
NOM
Normalize contents of accumulator
u This NOM instruction performs hardware normalization operation on signed two‘ s complement
numbers stored in the accumulator. The left shifted counts during normalization are stored in shift
count register (SHFCR) . Note : SHFCR is 5 bit wide in this normalize case , the following scaling
operation by “ SFL 0” has up to 31 bit left shift capability
FLAG:
SIGN
OV
MSB of high accumulator.
Overflow flag for last ACCH operation. This flag will be cleared by any
instructions
which will generate result in accumulator.
Accumulator zero flag. This bit reflects current accumulator status.
ACZ
These flags are all stored in status register, and can be read out by SSS instruction.
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3.2 MEMORY MAP AND ADDRESSING MODES
3.2.1 MEMORY MAP
0\h
On Chip Data RAM
1 K Words
1 K Words
03FF\h
0400\h
Bank0
0\h
On Chip Data RAM
Bank1
0\h
On Chip
07FF\h
0800\h
External
Program ROM
or RAM
Program ROM
BFFF\h
C000\h
On Chip Extended
RAM Bank1
0.5 K Words
1.5 K Words
09FF\h
0A00\h
0FFF\h
1000\h
External
Program ROM
or RAM
No defined
FFFF\h
External Data
RAM or ROM
FFFF\h
60 K Words
EROM= ‘ 1’
FFFF\h
EROM= ‘ 0’
PROGRAM MEMORY MAP
DATA MEMORY MAP
u Program memory map is selected by EROM . When EROM=1 , all program memory space are
mapped to external. When EROM=0 , the first 48 K words program memory space are mapped to
internal contact-programming ROM and the second 16 K words are mapped to external.
u Program addresses 0x0000 ~ 0x000B are reserved for interrupt vector, main program can start from
0x000C.
u Totally 2.5K words internal RAM. Only first 2 K words can be accessed by short direct mode
addressing. Refer to next section to see the details about data access.
3.2.2 IMMEDIATE ADDRESSING MODE
u In immediate addressing ,the immediate operand is contained in the instruction words. This
immediate operand is either a un-signed 7 bit short constant or a long 16 bit constant which may be
un-signed or signed(ADLL and SBLL instructions).
Example : Short immediate
ADHK 23
Long immediate
ADHL 0x1234
Add 23 or 0x1234 to high accumulator
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3.2.3 PAGED MEMORY DIRECT ADDRESSING
2 K words
Addressing
Space
Page0 : 0 ~ 127
Page1 : 128 ~ 255
Page2 : 256 ~ 383
DP[3:0].dma[6:0]
Page15 : 1920~2047
PAGED MEMORY DIRECT ADDRESSING
u In paged memory-direct addressing mode , data operand to be processed with is pointed by 11 bit
address , which are composed of 4 bit data page pointer and 7 bit within-page address.
u 4 bit data page pointer DP[3:0] (part of status register) will select one of 16 pages of internal data
RAM ( only first two k words of internal RAM). 7 bit direct memory address is encoded in instruction
word and will choose one of 128 memory location within the selected page.
u LDP or LDPK instruction can be used to modify data page pointer, SDP and SSS instructions can
be used to save data page pointer in data memory.
Example : ADH 127 ( if DP[3:0]=2 )
Add data from memory ( page 2, address within page is 127) to high accumulator
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3.2.4 REGISTER INDIRECT
64 K words
Addressing
Space
NARP[2:0]
ARP[2:0]
Data RAM
Bank0
1 K
AR0[15:0]
AR1[15:0]
AR2[15:0]
AR3[15:0]
AR4[15:0]
AR5[15:0]
AR6[15:0]
AR7[15:0]
Data RAM
Bank1
1 K
AR[15:0]
Extended
RAM Bank1
0.5 K
1.5 K
Not Defined
External Data
Ram or ROM
+/- 0,1,2,AR0
60 K
REGISTER-INDIRECT ADDRESSING MODE
u There are 8 auxiliary registers which are used as data memory pointer in register-indirect mode
addressing. ARP[2:0] in status register will choose one of them as current ar , and this 16 bit-wide
current ar will point to one of 64 k words data memory space in related instruction operation.
u A dedicated arithmetic unit is used to post modify the content of current ar parallel with instruction
execution without introducing any extra instruction cycle. Up to seven kinds of post-modification can
be made depending on what kind of operand specified in instruction word.
u ARP[2:0] also can be modified at the same time with new ARP for next following instructions use.
Syntax : INST * [,narp]
; Details about operand “ * ” and “ [,narp] ” are described below
Operand
Operation
Operand
[,narp]
None
Operation
*
+0
No operation
None
-AR0
+AR0
+
(arp) -ar0 à (arp)
(arp)+ar0à (arp)
(arp) + 1 à (arp)
(arp) - 1 à (arp)
(arp) + 2 à (arp)
(arp) - 2 à (arp)
,narp
narp à arp
-
++
--
Note : “ [,narp]” is an optional operand.
(arp) is one of 8 auxiliary registers which is pointed by arp.
Before instruction : ARP[2:0] = 5 AR5[15:0]=0x1234
Example
: ADH +, 2 ; Add data from memory pointed by AR5[15:0] to high accumulator
and increase AR5[15:0] by one as specified in operand “ + ” , ARP[2:0] are also
updated with value “ 2” for following use.
After instruction : ARP[2:0] = 2 AR5[15:0]=0x1235 Note: AR2[15:0] now becomes current ar .
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u MAR instruction can execute auxiliary register operation stated above alone .
u LAR , LARK and LARL instructions will load the content of specified auxiliary register with the data
from memory( addressed by short direct mode or register indirect mode) or immediate constant.
u SAR instruction will store the content of auxiliary register specially specified to data
memory( pointed by short direct mode or register indirect mode).
Special syntax :
LAR *, arps [,arp]
IN * , port_address [,narp]
OUT * , port_address [,narp]
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3.2.5 REGISTER INDIRECT ADDRESSING WITH MODULO ADDRESS
ARITHMETIC
u Writing a non-zero value to MODULO register(I/O mapped 13) will enable modulo arithmetic
operation in register-indirect addressing mode. A circular buffer whose length is MOD[9:0]+1 will be
formed. This buffer starts from M-word boundaries(N*M , N=0,1,2 ...64K/K-1),where M is the
smallest power of two that is equal to or greater than the size of circular buffer, and ends at buffer
size location relative to start point.
u In register-indirect addressing mode operation, whenever the current auxiliary register points to the
boundary of this circular buffer(either start or end boundary),it will be wrapped to the other side of
the boundary for next address.
u This circular buffer must be formed in continuous memory space, that is only +/- by one post ar
operation is allowed.
Before instruction : ARP[2:0] = 5 AR5[15:0]=0x1239 MOD[9:0]=25=0x19 M=32=0x20
AR5 just lies on the ending boundary( 0x1220 ~ 0x1239 )
Example
: ADH +, ; Add data from memory pointed by AR5[15:0] to high accumulator
After instruction : AR5[15:0]=0x1220 (wrapped to starting boundary)
3.2.6 MISCELLANEOUS ADDRESSING MODE
u In MB ,MBA ,MBS multiplication instructions , the LSB of data address is decided by “ R” or “ I”
operands. “ R” points to the even address location, “ I” points to the odd address location.
u In MPA array multiplication instructions, address of bank0 comes from current ar , and address of
bank1(offset address) comes from program counter which was originally stored in high
accumulator before instruction execution.
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3.3 PROGRAM FLOW CONTROL UNIT
3.3.1 CLOCK GENERATOR / FLL
CLOCK GENERATOR :
RAS\
DRAM refresh
circuit
CAS\
PWDN
4.096 MHz low
X‘ TAL
OSCILLATOR
TIMER
INTERRUPT
REQUEST
to DSP
1
¡
Ò
0
¡
4Ò096
Ò256
¡
CFS
XI
XO
¡
Ò
(8KHz)
CMCK
PLL
(2.048MHz)
1
0
0
1
CLOCK
to DSP
NMI\(TCLK)
PWDN
FLLEN\
HOLD\
RST\
SWHOLD
NMI\
INT1\
CLEAR
INT1M
TMRINT\
TMRM
CLOCK GENERATOR FUNCTION BLOCK DIAGRAM
u In normal mode, clock of DSP is selected(by FLLEN\ pin =0) directly from low x’ tal scillator.
In test clock mode, clock of DSP is selected(by FLLEN\ pin = 1) from NMI\ pin which
external test clock input.
u In power down mode ,clock of DSP is selected (by PWDN bit =1)direct from low X‘ tal( divided by
256). FLL will be turn off to save the power.
u In hardware or software hold mode ( issued by HOLD\ pin or SHOLD bit in CTLR) , clock to DSP
will be held down till hardware hold being deasserted by HOLD\ or SHOLD bit cleared by interrupt
request. Hold mode does not save more power like power down mode does, because FLL or High
X‘ tal is not turn off, but it responds faster for DSP resumes normal running. Timer is also active in
hold mode.
u EAD[15:0],ED[15:0],EDCE\,EPCE\,ERD\ and EWR\ pins will be placed in high-impedance state
when DSP is in hold mode.
u Details about codec clocks and timer interrupt ,please refer to section 3.4.1 and 3.4.5 .
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FLL :
4.096 MHz
X‘ TAL
¸
2
IMCLK
¸
256
IFS
XI
XO
R1
2.048´FLLM
DSP_CLK
C1
C2
DSP_CLK = 2.048MHz*FLLM[4:0]
IMCLK = 2.048 MHz
IFS = 2.048MHz/256
PWDN
FLLEN\
ENABLE
FREQUENCY LOCKED LOOP FUNCTION BLOCK DIAGRAM
u FLL ENABLE : FLL block is enabled by pin FLLEN\ =0 and will be disabled when DSP is in power
down mode.
u PROGRAMMABLE DIVIDER : Clock from 4.096MHz X’ TAL will be divided by 2 before being fed
into programmable divider. Programming FLLM[4:0] register ( I/O mapped 21) will change the
frequency of clock to DSP based on the following equation :
DSP_CLOCK = 4.096 MHz / 2 * FLLM[4:0]
Default : DSP_CLOCK = 4.096 MHz / 2 * 20 = 40.96 MHz
u LOCK IN TIME : Whenever a new frequency specified in FLLM register or DSP just comes back
from power down mode or just starts from power on reset ,the closed loop of FLL takes about 10 mili
second to lock at the target frequency.
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3.3.2 RUNNING MODE/PIPE LINE/WAITSTATE
Change
FLLM[12:0]
DSP CLOCK
RST\ 0 ¡ ÷1
Normal
Runing
Power On
Reset
PREFETCH
DECODE
N
N+1
N
N+2
N+1
PWDNS ¡ ÷0
HOLD\ =0 or
SHOLD=1
N-1
Wait
62.5 mS
EXECUATION
N-2
N-1
N
HOLD\ =1 or
Interrupt Request
PWDN =0
Hold
Mode
Power
Down
Instruction
Cycle Time
DSP RUNNING MODE
PIPE LINE and INSTRUCTION CYCLE TIME
RUNNING MODE :
u When DSP starts running from power on reset state , or change FLLM[4:0] during normal running
mode , it takes about 10 ms for PLL output clock to reach the target frequency.
u When DSP wakes up from power down mode by clearing PWDN bit , there will be 62.5 ms lead time
for DSP to switch running clock from low speed to high speed. PWDNS bit in CTLR reflects this
running speed status.
u When DSP runs into hold mode either by hardware HOLD\ pin asserted low or by setting SHOLD bit
in CTLR high , clock to DSP will be hold down until HOLD\ pin asserted high again or SHOLD bit
being cleared by external interrupt or internal timer interrupt request.
PIPE LINE /WAITSTATE:
u A complete operation of instruction execution is composed of there part :
PREFETCH : Fetch instruction code from program ROM (either internal or external)
DECODE
: Decode instruction and fetch data operand or store data in some
location if needed
EXECUTION : Execute data operation in data unit.
u There are three instructions executed in parallel, each one stays in different pipeline stage.
Instruction cycle is only 1/3 the time that one instruction execution really need.
u Instruction cycle time equals to the interval of one and half DSP clock for zero wait state case. Unit
increase in waitstate number(for PROGWAIT and DATAWAIT), increase the instruction cycle time
by one DSP clock.
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3.3.3 BRANCH/CALL/REPEAT/LOOP/STACK REGISTER
BRANCH :
u BS/BZ instructions: Branch immediate if bit being tested equals one or zero
Example : BS cnst3 , pma16 ; “ cnst3” will be used to select one of upper byte of status
register and test if condition is true or not.“ pma16” is new
program address which DSP will jump to if condition is true.
u BACC instruction: Unconditional branch. After executing this instruction DSP will jump to
address location specified in high accumulator.
CALL :
u CALL instruction: Call subroutine directly . Example : CALL pma16
u CALA instruction: Call subroutine indirectly. Subroutine address is specified in high
accumulator.
u Nesting CALL is permissible and has no limit before stack overflow occurs.
REPEAT :
u RC : Repeat counter. Instructions TBR , MPA and SQRA and instructions within program loop will
be executed RC[9:0]+1 times. This repeat counter can be read by IN instruction and written by
instructions RPT(RC[9:0])/RPTK(RC[6:0]).
LOOP :
u LUP/LUPK instructions : Enable hardware looping operation, and the following words
(maximum 8 words) instruction will be executed RC[9:0]+1 times.
u Branch and call instructions are not allowed within program loop.
STACK REGISTER :
31
RELATED
30
INSTRUCTIONS
OR CONDITION :
STACK POINTER
REGISTER
3
SSR
PC (NEXT)
ACCH
INTERRUPT/RETI
CALL/CALA/RET/RETI
POPH/PSHH
WRITE TO
SP[4:0]
2
1
0
READ FROM
ACCL
POPL/PSHL
32 X16 STACK
REGISTER
Data Memory
POP/PSH
u Stack register size : 32x16
u 5 bit stack pointer always points to the location within stack register where next data will be put.
u Nesting call can be formed by the help of stack register to store the return address.
u No pointer overflow or underflow protection built in, when such cases occur, the pointer will be
wrapped to the other side of the stack
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3.3.4 INTERRUPT
Interrupt Source Vector Address Priority Maskable Pending Status
Descriptions
Power-on reset or reset
Non-maskable interrupt
Single step interrupt
External maskable interrupt
Codec interrupt( 8 KHz)
Timer interrupt
RST\
NMI\
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
1st
2nd
3th
4th
5th
6th
No
No
SS
Yes
Yes
Yes
Yes
INT1\
Yes
Yes
Yes
CODECINT
TMRINT
u Interrupt Mask : Each bit in I/O mapped register 4 (IMR) enables or disables the servicing of an
individual interrupt. Global interrupt mask bit INTM equals “ 1” will mask all interrupt requests except
reset and non-maskable interrupt request. INTM bit is set or reset by DINT or EINT instruction.
u NMI\ and INT1\ are edge triggered interrupt which request DSP during high to low transition.
u Interruptible : State that INTM or individual interrupt mask bits are in reset state (“ 0” ) and no higher
priority interrupt being serviced or exist in pending status.
u Program flow within repeat loop such like LUP, TBR ,MPA and SQRA instructions , and at time
during DRAM data movement are all not interruptible.
u When a maskable interrupt request occurs , if DSP is in interruptible state, this request is granted by
DSP and following service routine will be executed, otherwise this request will be hold in pending
status bit until the DSP enters interruptible state again
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u When DSP jumps into interrupt subroutine , INTM bit is automatically set high ( After push status
register onto stack ) to prevent from nesting interrupt occurs. Execute EINT will change this situation
and then make nesting interrupt permissible.
u Software hold state will be terminated and return to normal running if external interrupt or timer
interrupt occurs and is granted by DSP.
u Single step(I/O mapped 7) provides an “ always exist ” interrupt condition. DSP will be interrupted
after every instruction cycle.(DSP must be in interruptible state)
u No register will be automatically saved in stack register except status register during interrupt
service routine. Cares should be taken with the current values stored in X-register, product register
and accumulator , backup them at first in interrupt routine if needed.
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3.4 APPLICATION INTERFACE UNIT
3.4.1 CODEC INTERFACE
IFS
(8 KHz )
¡
2Ò56
IMCK
(2.048 MHz)
Clock from pLL
u IMCK is directly from PLL output. IFS equals to IMCK/256.
IFS (8KHz)
IMCK(2.048 MHz)
D15
D14
D13
D12
D0
D15
D14
D13
CDR0 ; CDX0
Codec Interrupt Request
u After CFS positive pulse DSP begins to exchange data with external codec through CDR0 and
CDX0. DSP transmits data at CMCK rising edge and receives data at CMCK falling edge.
u First data received will be put into the MSB of codec receive registers(I/O mapped 16,17).
u First data transmitted will come from the MSB of codec transmit registers(I/O mapped 16,17).
u After LSB (16th) data transmitted or received, DSP will generate an internal codec interrupt request.
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3.4.2 DRAM INTERFACE
DRAMCOL[14:0]
DRAMROW[14:0]
Start
Start
RAMA[9:0]
DRAMCNT[5:0]
¡ b
TOIRAM
Data RAM
Bank1
External
DRAM
u DRAM controller support data movement between DSP RAM bank1 and external DRAM
u Support FAST-PAGE and EDO-PAGE mode DRAMs
u Data movement starts from non-zero value written to DRAMCNT[5:0] (I/O mapped 9)
u DSP will be hold during this data movement
u RAMA[9:0] (I/O mapped 9) specifies the starting address where data movement begin
u DRAMCOL[14:0](I/O mapped 10) and DARMROW[14:0](I/O mapped 11) specify the column and
row part of DRAM starting address where this data movement begin
u TOIRAM(I/O mapped 11) defines the direction of data movement
0 : DSP ¡ ÷DRAM 1: DSP¡ öDRAM
u DRAMSIZE[1:0](I/O mapped 8) define the configuration of DRAM data width :
0 : x1 1: x4 2: x8 3: x16
u DRAMWAIT[2:0](I/O mapped 8) are the wait state number during DRAM data access
Find the larger one of DRAMWAIT[2:0] below
TRAC < 73 ns + (12.2 ns x DRAMWAIT[2:] ) or
TCAC < 11 ns + (12.2 ns x DRAMWAIT[2:0]
u Refresh mode : CAS before RAS refresh
Refresh cycle time : every 15.258 us ( 64 KHz)
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3.4.3 I/O FUNCTION
u IN/OUT instructions transfer data between internal data RAM and I/O mapped registers
u Up to 9 input port pins , 24 output port pins and 8 programmable bi-directional I/O pins can be used
in general I/O function
u HOSTM is software bits in CTLR(I/O mapped 7).DFS is software bits on EXCTLR.
u IPT[3:0] built with internal pull high register(R ~ = 150 K ohm)
u XF\ can be used as general output pin which can be set or reset directly by RXF and SXF instruction
Application
HOSTM DFS Input Ports
Output ports
OPT[15:0]
Bidirection I/O
None
External Host/DRAM
External Host/FLASH
No external Host/DRAM
No external Host/FLASH
0
0
1
1
0
1
0
1
IPT[7:0]
IPT[8:0]
IPT[7:0]
IPT[8:0]
OPT[21:19;15:0]
OPT[18:0]
None
BIO[7:0]
BIO[7:0]
OPT[21:0]
BIT
REG0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
OPT[15:0]
REG1(W)
REG1(R)
REG2
OPT[23:19]
IPT[8:0]
BIO[7:0]
BIO[15:8]
OPT[18:16]
REG7
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3.4.4 HOST INTERFACE
CMDRDY ¡ ÷1
HILO
External
Host
Controller
HDB[7:0]
High Byte Low Byte
Command Register
HRD\
HWR\
ACK\ ¡ ÷0
u HOSTM (I/O mapped 7) define the HOST mode and multiplex some DSP I/O pins
HOSTM : 0 : External host controller
1 : No external host controller
u External host can read or write byte-wide command from or to this COMMAND REGISTER through
HDB[7:0] and HILO select pins. HILO pin=1 will select upper byte of this register.
u When external host writes command to high byte of this register , CMDRDY bit in CTLR will be set
till this register being read by DSP.
u When DSP writes command to this register , ACK\ pin will go low till high byte of this register being
read by external host.
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3.4.5 TIMER
PWDN
4.096 MHz X‘ TAL
OSCILLATOR
TIMER
1
0
¡
Ò
INTERRUPT
REQUEST
to DSP
¡
Ò
XI
XO
R1
C1
C2
PWDN Timer Interrupt Period
0
1
1 mili second
1/32 second
u Timer accuracy is determined by crystal‘ s character ,R1,C1,C2 and stray capacitance on PCB.
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4.1 I/O Mapped Registers Summary
Register
Name
Bit
Width
16
I/O
Related Instructions
Descriptions
Address
0 (R/W)
1 (R/W)
1 (R)
OPTR
IN/OUT
IN/OUT
IN
Output ports register
EXTOPTR
IPTR
5
Extended output ports register
Input ports register
11
BIOR/CMDR
16
2 (R/W)
IN/OUT
Bi-directional I/O ports / HOST
command register
SHFCR
IMR
4
4
3 (R/W)
4 (R/W)
5 (R/W)
7 (R/W)
8 (R/W)
IN/OUT/SFL/SFR/SFRS Shift count register
IN/OUT
IN/OUT
IN/OUT
IN/OUT
Interrupt mask register
Codec command register
Control register
CDCMR
CTLR
2
15
11
WSTR
Memory wait state and DRAM
configuration register
DRAMACR
DRAMCOLR
DRAMROWR
RCR
16
15
16
7
9 (R/W)
IN/OUT
DRAM access control register
DRAM column address register
DRAM row address register
Repeat counter
10 (R/W) IN/OUT
11 (R/W) IN/OUT
12 (R)
13(R)
IN
MODR
7
IN/MOD/MODK
Modulo register for modulo
addressing
XR
16
5
14 (R)
15 (R)
IN
X register (one of source registers to
16x16 multiplier)
SPR
IN/PSH/PSHH/PSHL
Stack pointer register
POP/POPH/POPL
CDRR0
CDXR0
16
16
15
16
4
16 (R)
16 (W)
18 (W)
19 (W)
20 (W)
21(R/W)
24(R/W)
IN
Codec0 receive register
OUT
OUT
OUT
OUT
IN/OUT
IN/OUT
Codec0 transmit register
PRODLR
PRODHR
TESTR
Lower word of product register
Upper word of product register
Testing register for internal use
PLL multiplication register
Extended Control register
PLLMR
5
EXTCTLR
4
Notes: (R) : This register is read only
(W) : This register is write only
(R/W) : This register can be read or write
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32 I/O Mapped
Registers Addressing
Space
Page0 : 0 ~ 7
Page1 : 8 ~ 15
Page2 : 16 ~ 23
Page 3 : 24 ~ 31
IOP[1:0].port_address[2:0]
PAGED I/O MAPPED REGISTER ADDRESSING
u
u
u
Address of I/O mapped registers are composed of 2 bit I/O page pointer which are stored in status
register and 3 bit within page port_address.
LIP or LIPK instruction can be used to modify I/O page pointer, SIP and SSS instructions can be
used to save I/O page pointer in data memory.
3 bit port_address are directly specified in part of instruction .
4.2 Non I/O Mapped Registers Summary
Register
Name
Bit
Width
16
I/O
Related Instructions
Descriptions
Address
ACCH
SAH/ADH/SBH/POPH High word of accumulator
PSHH/AND/OR/XOR
ABS/LAC ...
ACCL
ACC
PC
16
32
16
SAL/ADL/SBL/POPL
PSHL ...
Low word of accumulator
32 bits accumulator
SBL/ADL/SFL/SFR
NOM/ Multiply ...
CALL/CALA/TRAP/BS Program counter. Acts as program
BZ/BACC/RET/RETI
Reset/Interrupt
SSS/BS/BZ
memory pointer
SSR
16
Status register
INTM : EINT/DINT
TB : BIT
OVM : ROVM/SOVM
ARP : MAR
IOP : LIP/SIP
DP : LDP/SDP
LAR/SAR/MAR
AR0 ~ AR7
16x8
Auxiliary registers. Used as data
memory pointer in register-indirect
mode addressing
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4.3 I/O Mapped Registers Description
4.3.1 OPTR (I/O mapped 0 : R/W) : Output Ports Register
Bit
Field
Default
Description
15 ~ 0 OPT[15:0]
0
Output ports register. Content of this register will be reflected to
corresponding output pins.
4.3.2 EXTOPTR (I/O mapped 1 : W) : Extended Output Ports Register
Bit
14~ 11
Field OPT[22:19]
Bit
Field
Default
Description
Output ports register. Content of this register will be reflected to
corresponding output pins.
14 ~ 11 OPT[22:19]
0
4.3.3 IPTR (I/O mapped 1 : R) : Input Ports Register
Bit
10
9
8
7~0
Field ACK\ / XF\ EROM IPT8 IPT[7:0]
Bit
Field
Default
Description
Host acknowledge / External flag. Status bit, mapped from pin number
14.
10
ACK\ / XF\
1
9
8
EROM
IPT8
X
X
Status bit, mapped from pin number 97
Input port, mapped from pin number 93 when DFS bit in EXTCTLR
equals one
7 ~ 0
IPT[7:0]
X
Input ports, mapped from 15 ~ 22
4.3.4 CMDR / BIOR (I/O mapped 2 : R/W) : Command or
Bi-directional I/O ports Register
Bit
15 ~ 0
Option
Field CMD[15:0]
Field BIO[15:0]
If HOSTM bit in CTLR =0
If HOSTM bit in CTLR =1
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4.3.4 CMDR / BIOR (I/O mapped 2 : R/W) : Command or Bi-directional I/O ports
Register ( Continued )
Bit
Field
Default
Description
15 ~ 0 CMD[15:0]
0
Parallel host command register. External Host can read or write byte-
wide command from or to this CMD register through HDB[7:0] and
Hilo select pins. Hilo pin =1 will select upper byte of this CMD register.
Related Flag : When external host writes command to high byte of this
register , CMDRDY bit in CTLR will be set till this
register being read by DSP.
When DSP writes command to this register , ACK\ pin
will go low till high byte of this register being read by
external host.
15 ~ 0 BIO[15:0]
0
BIO[7:0] are programmable bi-directional I/O ports. Ports direction of
BIO[7:0] are programmed by BIO[15:8] bits respectively.
BIO15 : 0 à BIO7 Input port
1 à BIO7 output port
..........
4.3.5 SHFCR (I/O mapped 3 : R/W ) : Shift Count Register
Bit
Field
Default
Description
4 ~ 0 SHFC[4:0]
0
Shift Count of barrel shifter . If the value of operand specified in
SFL/SFR/SFRS usage equal 0 , left shift or right shift count of barrel
shifter will be decided by this register.
In normalize operation by “ NOM” , left shift counts are also stored in
this register, but with one more extra bit for 31-bit shifting. In this case,
the 5-bit SHFC[4:0] can be read by “ IN” instruction for later operation.
But for “ OUT” instruction, only SHFC[3:0] can be written, SHFC[4] is
always forced to 0 for backward compatible issue.
4.3.6 IMR (I/O mapped 4 : R/W ) : Interrupt Mask Register
Bit
3
2
1
0
Field SSM TMRM CODECM INT1M
Bit
Field
Default
Description
Interrupt mask bit will disable or enable individual interrupt
1 : disable
0 : enable
3
2
1
0
SSM
TMRM
1
1
1
1
Single step interrupt mask bit
Timer interrupt mask bit
CODECM
INT1M
Codec interrupt mask bit
External interrupt 1 mask bit
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4.3.7 CDCMR (I/O mapped 5 : R or R/W ) : Codec command register
Bit
9
8
2
1
0
Field CDREADYX ISDATA ICPDX ISDENX ISDATAW
R
Bit
9
Field
Default R/W
Description
If CDREADYX = 0, CODEC is ready
DSP read register from CODEC
CDREADYX
ISDATAR
ICPDX
R
R
8
2
0
1
0
R/W Set CODEC powerdown. 0 = power down.
R/W DSP read/write register enable
R/W DSP write register to CODEC
1
ISDENX
0
ISDATAW
4.3.8 CTLR (I/O mapped 7 : R/W ) : Control Register
Bit
14 ~ 12
11
10
9
8
Field OPT[18:16] PWDN SWHOLD
Bit
7
6
5
4
3
2
1
0
Field
CMDRDY PWDNS SS
SNSEL HOSTM
Bit
Field
Default
Description
14 ~ 12 OPT[18:16]
0
Output ports to pin when HOSTM in CTLR = 1 .
Share pin location with HILO , HRD\ and HWR\ .
11
10
PWDN
0
Power down mode enable. When power down mode being enabled by
setting this bit DSP will switch running clock source to low x‘ tal, and
turn off high X’ tal or PLL to save power.
When DSP is waken up by clearing this bit, DSP will stay in slow speed
running for 62.5 ms till PLL output stabilize or high X‘ tal startup and
stabilize , then switch back to high speed running.
1 = Power down.
SWHOLD
0
Software hold enable. When this bit being set , DSP will stop program
execution, but high X‘ tal and PLL will not be turn off. Timer clock are
still active during this mode. Software hold does not save more power
like power down mode does, but responds faster for DSP resuming
normal running from this mode when SHOLD bit is cleared by interrupt
request. (Individual interrupt mask bit should be enabled first.)
1 = Hold.
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4.3.8 CTLR (I/O mapped 7 : R/W ) : Control Register ( Continued )
6
CMDRDY
0
Host command ready flag. This bit will be set if external host write
command to high byte of CMDR , and will be cleared when DSP reads
CMDR.
5
PWDNS
0
Power down status bit. This bit will be set if PWDN bit being set. But
will be cleared late by 62.5 ms after PWDN being cleared. This bit
indicates what kind of speed DSP running with currently.
Single step interrupt enable. When this bit being set , DSP will enter
single step interrupt vector 0x0004 at end of each instruction.
Sign extended mode select in ADL/ADLL SBL/SBLL instructions.
0 : Fill “ 0” in upper word of accumulator.
4
2
SS
0
0
SNSEL
1 : Sign extended in upper word of accumulator.
Host mode select : 0 : External host controller.
1
HOSTM
0
1 : No external host controller.
This bit also acts as pins multiplex select.
0 : HDB[7:0] HILO
HRD\ HWR\ ACK\ ( External host )
1 : BIO[7:0] OPT18 OPT17 OPT16 XF\ ( Internal host )
4.3.9 WSTR (I/O mapped 8 : R/W ) : Memory Wait State Number and
DRAM Configuration Register
Bit
10 ~ 9
8 ~ 6
5 ~ 3
2 ~ 0
Field DRAMSIZE[1:0] DATAWAIT[2:0] DRAMWAIT[2:0] PROGWAIT[2:0]
Bit
Field
Default
Description
10 ~ 9
DRAMSIZE[1:0]
1
DRAM configuration select. 0 : x1 1: x4 2: x8 3: x16
8 ~ 6
5 ~ 3
DATAWAIT[2:0]
DRAMWAIT[2:0]
7
7
External data memory wait state number.
TAA or TCS < 26.5ns + ( 31 ns x DATAWAIT[2:0] )
DRAM wait state number. Find the larger one below :
TRAC < 73 ns + ( 15.5 ns x DRAMWAIT[2:0] ) or
TCAC < 11 ns + ( 15.5 ns x DRAMWAIT[2:0] )
External program memory wait state number.
TAA or TCS < 26.5ns + ( 31 ns x PROGWAIT[2:0] )
All calculation is based on the assumption that DSP is running
with 32.256 MHz Clock.
2 ~ 0
PROGWAIT[2:0]
7
If FAST bit in EXTCTLR equals 0 , all wait state numbers
should be increased by one to meet the timing requirement stated
above .
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4.3.10 DRAMACR (I/O mapped 9 : R/W ) : DRAM Access Control Register
Bit
15 ~ 10
9 ~ 0
Field DRAMCNT[5:0]
RAMA[9:0]
Bit
Field
Default
Description
15 ~ 10 DRAMCNT[5:0]
0
Write a non zero value to this register will start data movement
between internal data RAM and external DRAM .At this moment ,
DSP will hold operation till this data movement complete and
these bits ( DRAMCNT[5:0] ) will be clear .
DRAMCNT[5:0] indicate how many DRAM address location will
involved in this movement.
9 ~ 0
RAMA[9:0]
0
RAM bank 1 OFFSET address. This address points to starting
location where data movement begin. Data in extended RAM
bank1( 0x0800 ~ 0x09FF) can‘ t be moved.
4.3.11 DRAMCOLR (I/O mapped 10 : R/W ) : DRAM Column Address Register
Bit
Field
Default
Description
14 ~ 0 DRAMCOL[14:0]
0
Column part of DRAM starting address where data movement
begin
4.3.12 DRAMROWR (I/O mapped 11 : R/W ) : DRAM Row Address Register
Bit
15
14 ~ 0
Field
TOIRAM
DRAMROW[14:0]
Bit
Field
TOIRAM
Default
Description
15
0
Data movement direction.
0 : Internal RAM of DSP à External DRAM
1 : External DRAM
à Internal RAM of DSP
14 ~ 0 DRAMROW[14:0]
0
Row part of DRAM starting address where data movement
begin
4.3.13 RCR (I/O mapped 12 : R) : Repeat Counter Register
Bit
Field
Default
Description
9 ~ 0
RC[9:0]
0
Instruction execution repeat counter.
Affected instructions: TBR MPA SQRA and instructions within
program loop . Read only register, but can be written by RPT and
RPTK instructions. Real repeat number is RC[9:0]+1 .
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4.3.14 MODR (I/O mapped 13 : R) : Modulo Register
Bit
Field
Default
Description
9 ~ 0
MOD[9:0]
0
Modulo Register. Non zero value of this register will enable
modulo arithmetic in register-indirect addressing mode. A circular
buffer , whose length is MOD[9:0]+1, will be formed. This circular
buffer starts on K-word boundaries , where K is the smallest
power of two that is equal to or greater than the size of the
circular buffer. In register-indirect addressing mode operation,
whenever the current auxiliary register points to the boundary
of this circular buffer , it will be wrapped to the other side of the
boundary for next address.
4.3.15 SPR (I/O mapped 15 : R) : Stack Register Pointer
Bit
Field
Default
Description
4 ~ 0
SP[4:0]
0
Stack register pointer. This pointer always points to the location
within stack register where next data will be put. No pointer
overflow or underflow protection built in, when such cases occur,
the pointer will be wrapped to the other side of the stack.
4.3.16 CDRR0 (I/O mapped 16 : R) : Codec Receive Register
Bit
Field
Default
Description
15 ~ 0
CDR0[15:0]
Undefined After Codec frame sync. goes high, DSP begins to receive data
from external Codec when Codec master clock goes low. The
first data received will be put into the MSB of this register.
When DSP has received sixteen bits data, DSP will stop
receiving operation and trigger internal Codec interrupt.
4.3.17 CDXR0 (I/O mapped 16 : W) : Codec Transmit Register
Bit
Field
Default
Description
15 ~ 0
CDX0[15:0]
Undefined After Codec frame sync. goes high, DSP begins to transmit
data
to external Codec when Codec master clock goes high. The
first
data transmitted will come from the MSB of this register.
When DSP has transmitted sixteen bits data, DSP will stop
transmitting operation and trigger internal Codec interrupt.
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4.3.18 TESTR (I/O mapped 20 : W) : Test Register
Bit
Field
Default
Description
5 ~ 2
TEST[5:2]
0
Test bits used in testing.
4.3.19 PLLMR (I/O mapped 21 : W) : P LL Multiplication Factor Register
Bit
Field
Default
Description
12 ~ 0
PLLM[4:0]
0x14
PLL multiplication factor register.
F_DSP = 4.096MHz / 2 * PLLM[4:0]
Default:
F_DSP = 4.096MHz / 2 * 20 = 40.96 MHz
Range :
24.5 MHz < F_DSP < 49 MHz
Lock in time ~= 10 ms
Jitters : meet the requirement for digital answering machine
application. For other applications ,care need to be taken.
4.3.20 EXTCTLR (I/O mapped 24 : R/W) : Extended Control Register
Bit
15 ~ 2
1
0
Field Reserved
DFS
FAST
Bit
Field
Default
Description
15 ~ 2
Reserved
0
Output ports register. Content of this register will be reflected to
corresponding output pins.
1
0
DFS
0
1
DRAM or FLASH interface pins select. This bit is used to multiplex
pins between DRAM and FLASH interface.
0 : CAS\
DRD\
DWR\ RAS\ for DRAM interface
1: OPT21 OPT20 OPT19 IPT8 for FLASH interface
Output pad slew rate control bit. Used to reduced EMI.
0: Slow slew rate 1: Fast slew rate
FAST
Affected Pins : ED[15:];EAD[15:0];EPCE\;EDCE\;EWR\;ERD\;
RAS\;CAS\;DRD\;DWR\;
Notes: Reset / set this bit affect wait state number requirement for
external memory access.
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4.4 NON I/O mapped registers Description
4.4.1 ACCH : Upper Word of Accumulator
Bit
Field
Default
Description
Description
Description
Description
31 ~ 16 ACC[31:16] Undefined Upper word of accumulator.
4.4.2 ACCL : Lower Word of Accumulator
Bit
Field
Default
15 ~ 0 ACC[15:0]
Undefined Lower word of accumulator.
4.4.3 ACC : Accumulator
Bit
Field
Default
31 ~ 0 ACC[31:0]
Undefined Accumulator.
4.4.4 PC : Program Counter
Bit
Field
Default
15 ~ 0 PC[15:0]
0x0000 Program counter. This counter is used as program memory pointer
to control the DSP program flow.
In MPA instruction , this counter is used as one of data memory
pointer.
4.4.5 SSR : Status Register
Bit
15
14
13
12
11
10
9
8 ~ 6
5 ~ 4
3 ~ 0
Field INTM ARZ SGN OV ACZ TB OVM ARP[2:0] IOP[1:0] DP[3:0]
Bit
Field
Default
Description
This register will be saved automatically in stack register when
interrupt service begins and will be restored back when interrupt
service has completed.
SSS instruction can store this register to data memory.
Some other instructions can modify or store part of this register.
Global interrupt mask bit. This bit can be set by DINT or reset by
EINT instruction. Every time when DSP runs into interrupt service
routine , this global mask bit will be set to disable any other interrupt.
Clear this bit or execute EINT instruction can enable interrupt
again and make nesting interrupt possible.
15
14
INTM
ARZ
1
1
This bit registers the last operated auxiliary register ‘ s value equal
zero.
13
12
SGN
OV
Undefined MSB of high accumulator.
0
Overflow flag for last ACCH operation. This flag will be cleared by
any instructions which will generate result in accumulator.
11
ACZ
1
Accumulator zero flag. This bit reflects current accumulator status.
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4.4.5 SSR : Status Register ( Continued )
10
TB
0
Tested bit. This bit is used to stored one bit from data memory by
BIT instruction, and will be tested by following BZ or BS instruction .
Overflow mode select. 0 : Disable overflow mode
1 : Enable overflow protection during
9
OVM
0
arithmetic and shift left operation.
This bit can be reset/set by ROVM / SOVM instruction.
Auxiliary register pointer. This pointer points to one of eight auxiliary
registers as current ar in register-indirect addressing mode.
I/O mapped register Page pointer. This DSP can access total 32
internal I/O ports address formed by 4 pages , each page contains
eight ports address . Port address is specified as immediate operand
in IN / OUT instruction.
8 ~ 6
5 ~ 4
ARP[2:0]
IOP[1:0]
0
0
These bits can be modified by LIP/LIPK or saved by SIP
instructions.
3 ~ 0
DP[3:0]
0
Internal data memory page pointer used in direct memory addressing
mode. The DSP contains total 16 pages of internal RAM whose
range is from 0x0000 to 0x07FF.Each page contain 128 words, the
words address within page can be specified as immediate operand in
related instructions.
These bits can be modified by LDP/LDPK or saved by SDP
instructions.
Internal RAM located within (0x0800 ~ 0x09FF) can be accessed
only by register-indirect mode.
4.4.6 STR : Stack Register
Bit
15 ~ 0
Field ST[31:0][15:0]
Bit
Field
STACK
Default
Description
32x16
Undefined This register is used to stored return address from program counter
in the case of interrupt service begin or CALL/CALA instruction
execution.Or acts as data buffer for use in data exchange with
ACCH, ACCL , SSR and data from memory
REGISTER
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4.4.7 ARS : Auxiliary Registers
Bit
15 ~ 0
15 ~ 0
15 ~ 0
15 ~ 0
15 ~ 0
15 ~ 0
15 ~ 0
15 ~ 0
Field AR7[15:0] AR6[15:0] AR5[15:0] AR4[15:0] AR3[15:0] AR2[15:0] AR1[15:0] AR0[15:0]
These Auxiliary registers are used as data memory pointer in register-indirect mode addressing .
ARP[2:0] in status register will choose one of them as current AR , and the current AR acts as data
memory pointer in related instruction operation.
Content of current AR can be modify as follow :
+0
+
ar + 0 à ar or
ar + 1 à ar or
ar + 2 à ar or
-
ar - 1 à ar
ar - 2 à ar
++
+AR0
--
ar + ar0 à ar or -AR0 ar - ar0 à ar
ARP[2:0] can also be updated with new auxiliary register pointer : narp à arp
All operations stated above work in parallel with instruction execution.
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5.1 INSTRUCTION SET SUMMARY :
DATA UNIT INSTRUCTIONS:1.Arithmetic 2.Logic/Shift 3.Data movement 4.Mode setting
Mnemonic
Description
ADH/ADHK/ADHL Add data (from memory) or constant to high accumulator
ADL/ADLK/ADLL
SBH/SBHK/SBHL
SBL/SBLK/SBLL
ABS
Add data (from memory) or constant to low accumulator
Subtract data (from memory) or constant from high accumulator
Subtract data (from memory) or constant from low accumulator
Absolute value of high accumulator
OR/ORK/ORL
OR data (from memory) or constant with high accumulator
AND/ANDK/ANDL AND data (from memory) or constant with high accumulator
XOR/XORK/XORL Exclusive-OR data (from memory) or constant with high accumulator
SFL/SFR/SFRS
NOM
Shift contents of accumulator left/right/right with sign extended
Normalize contents of accumulator
LAC/LACK/LACL
SAH/SAL
Load data (from memory) or constant to high accumulator
Store contents of high or low accumulator to data memory
Pop top of stack to high/low accumulator
POPH/POPL
PSHH/PSHL
SOVM/ROVM
Push high/low accumulator onto stack
Set/Reset overflow mode
AUXILIARY REGISTERS AND DATA/IO PAGE POINTER INSTRUCTIONS
Description
Mnemonic
LAR/LARK/LARL
SAR
Load data (from memory) or constant to auxiliary register
Store auxiliary register to data memory
MAR
Modify auxiliary register pointer and update auxiliary register pointer
Load data (from memory) or constant to modulo register
MOD/MODK
LIP/LIPK
SIP
Load data (from memory) or constant to modify I/O page pointer in status register
Store I/O page pointer in status register to data memory
LDP/LDPK
SDP
Load data (from memory) or constant to modify data page pointer in status register
Store data page pointer in status register to data memory
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5.1 INSTRUCTION SET SUMMARY : ( Continued )
PROGRAM FLOW CONTROL INSTRUCTIONS
Mnemonic
RPT/RPTK
LUP/LUPK
BS/BZ
Description
Load data (from memory) or constant to repeat counter
Enable loop operation /Enable loop operation with short constant
Branch immediate if bit being tested set or reset
Call subroutine indirectly specified by contents of high accumulator
Call subroutine
CALA
CALL
BACC
Branch to address specified by contents of high accumulator
Disable / Enable interrupt
DINT/EINT
RET/RETI
NOP
Return from subroutine / interrupt
No operation
DATA MOVEMENT AND MISCELLANEOUS INSTRUCTIONS
Description
Mnemonic
OUT/OUTK/OUTL Load data (from internal data memory) or constant to I/O mapped register
IN
Move data from I/O mapped register to internal data memory
Move data bit from memory to TB in status register
Store status register to data memory
BIT
SSS
POP/PSH
SXF/RXF
Pop top of stack to data memory/push data memory value onto stack
Set/reset external flag
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5.2 ACRONYMS AND NOTATIONS :
à
Data transfer
pc
Program counter
pma16
(arp)
ar
16 bit program memory address
auxiliary register pointed by arp. also called current auxiliary register
current Auxiliary register
ar0
the first Auxiliary register
(arps)
dma7
dma
Auxiliary register pointed by arps
7 bit direct memory address within data page
16 bit whole data memory address formed by 0.dp(3:0).dma7
or by 16 bits current ar
(dma)
data memory pointed by dma
(dma)(3:0)
lowest nibble of (dma)
#
bit location indicator
(dma)(#cnst4)
*
bit data of (dma) which is pointed by cnst4
register indirect mode addressing operator , can be one of :
+0 , + ,++ , - , --, +ar0 , -ar0
[,narp]
Next AR point,
narp is a 3 bit constant. “ [” “ ]” means option , not real expression.
cnst2,cnst3,cnst4, 2 bit , 3 bit , 4 bit , 7 bit , 16 bit constant
cnst7,cnst16
1(DI),2(DE)
one cycle for data memory internal , two cycles for data memory
external
acc
Accumulator
p
product register
sp
stack register pointer
stack register pointed by sp
status register
(sp)
ss
CTLR
lc(2:0)
mr(6:0)
rc
control register
loop counter
modulo register
repeat counter
norm(4:0)
x
normalize register
multiplication operator
data page pointer
dp(3:0)
iop(1:0)
port_address
io_address
(io_address)
I/O page pointer
3 bit address within I/O page
5 bit I/O address formed by iop(1:0) and port_address
I/O mapped register pointed by io_address
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NOTE 1 : Instruction Encoding For Register Indirect Addressing
15 14 13 12 11 10
OPCODE
9
8
7
1
6
5
4
3
2
1
0
E6 E5 E4 E3 E2 E1 E0
Operand
Encoding
Operation
*
+0
E6
0
E5
0
E4
0
No operation
-AR0
+AR0
+
0
0
1
(arp) -ar0 à (arp)
(arp)+ar0à (arp)
(arp) + 1 à (arp)
(arp) - 1 à (arp)
(arp) + 2 à (arp)
(arp) - 2 à (arp)
0
1
0
1
0
0
-
1
0
1
++
--
1
1
0
1
1
1
Operand Encoding Encoding
Operation
[,narp]
None
E3
0
E2 E1 E0
No operation
, narp
1
narp
narp à arp
NOTE II : Instruction Encoding For Register Indirect Addressing
For MB , MBA , MBS Instructions only
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OPCODE
E2 E1 E0
Operand
Encoding
Operation
No operation
*
+0
E2
0
E1
0
E0
0
-AR0
+AR0
+
0
0
1
(arp) -ar0 à (arp)
(arp)+ar0à (arp)
(arp) + 1 à (arp)
(arp) - 1 à (arp)
(arp) + 2 à (arp)
(arp) - 2 à (arp)
0
1
0
1
0
0
-
1
0
1
++
--
1
1
0
1
1
1
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5.3 INSTRUCTION SET DESCRIPTION
ABS
Absolute value of high accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
ABS
Operation:
pc + 1 à pc
|acc(31:16)| à acc(31:16)
Words:
Cycles:
Note:
1
1
|0x8000| will exceed the maximum positive number which can be represented .
and will cause incorrect result .
ADH
Add data from memory to high accumulator
15 14 13 12 11 10
ADH dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
ADH * [,narp]
pc + 1 à pc
acc(31:16) + (dma) à acc(31:16)
Words:
Cycles:
1
1(DI) , 2(DE)
ADHK
Add immediate 7-bit unsigned short constant to high accumulator
15 14 13 12 11 10
ADHK cnst7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 1 à pc
acc(31:16) + cnst7 à acc(31:16)
Words:
Cycles:
1
1
ADHL
Add immediate 16-bit long constant to high accumulator
15 14 13 12 11 10
ADHL cnst16
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 2 à pc
acc(31:16) + cnst16 à acc(31:16)
Words:
Cycles:
2
2
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ADL
Add data from memory to low accumulator
15 14 13 12 11 10
ADL dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
ADL * [,narp]
pc + 1 à pc
acc(31:0) + (dma) à acc(31:0)
1
Words:
Cycles:
Note:
1(DI) , 2(DE)
Data operand is expanded into 32 bit long width with MSBs optionally sign
extended or filled with “ 0” bits. This option is controlled by SNSEL bit in CTLR.
ADLK
Add immediate 7-bit unsigned short constant to low accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
ADLK cnst7
Operation:
pc + 1 à pc
acc(31:0) + cnst7 à acc(31:0)
Words:
Cycles:
1
1
ADLL
Add immediate 16-bit long constant to low accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
ADLL cnst16
Operation:
pc + 2 à pc
acc(31:0) + cnst16 à acc(31:0)
Words:
Cycles:
Note:
2
2
Data operand is expanded into 32 bit long width with MSBs optionally sign
extended or filled with “ 0” bits. This option is controlled by SNSEL bit in CTLR.
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AND
AND data from memory with high accumulator
15 14 13 12 11 10
AND dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
AND * [,narp]
pc + 1 à pc
acc(31:16) AND (dma) à acc(31:16)
Words:
Cycles:
1
1(DI) , 2(DE)
ANDK
AND immediate 7-bit short constant with high accumulator
15 14 13 12 11 10
ANDK cnst7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 1 à pc
acc(22:16) AND cnst7 à acc(22:16)
0 à acc(31:23)
Words:
Cycles:
1
1
ANDL
AND immediate 16-bit long constant to high accumulator
15 14 13 12 11 10
ADLL cnst16
9
8
7
6
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
Syntax:
Operation:
pc + 2 à pc
acc(31:16) AND cnst16 à acc(31:16)
Words:
Cycles:
2
2
APAC
Add product register to accumulator
15 14 13 12 11 10
9
8
7
6
5
Syntax:
APAC
Operation:
pc + 1 à pc
acc + p à acc
Words:
Cycles:
1
1
BACC
Branch to address specified by high accumulator
15 14 13 12 11 10
9
8
7
6
5
Syntax:
Operation:
Words:
BACC
acc(31:16) à pc
1
2
Cycles:
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Copy data bit from memory to TB bit in status register
BIT
15 14 13 12 11 10
BIT dma7 , cnst4
BIT * , cnst4 [,narp]
pc + 1 à pc
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
(dma)(#cnst4) à TB bit in status register
Words:
Cycles:
1
1(DI) , 2(DE)
BS
Branch immediate if bit being tested equal one
15 14 13 12 11 10
BS cnst3 , pma16
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
If ss(#(cnst3+8)) = 1 then pma16 à pc
else pc+2 à pc
Words:
Cycles:
Note:
2
3
BS instruction will test one bit of status register‘ s upper byte. Bit 15 is always
one, and bit 8 is not defined in this test condition..
15 14 13 12 11 10
9
8
1
arz sgn ov acz tb ovm
: Part of upper byte of status register
BZ
Branch immediate if bit being tested equal zero
15 14 13 12 11 10
BS bbb , pma16
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
If ss(#(cnst3+8)) = 0 then pma16 à pc
else pc+2 à pc
Words:
Cycles:
Note:
2
3
BS instruction will test one bit of status register‘ s upper byte. Bit 15 is always
one, and bit 8 is not defined in this test condition..
15 14 13 12 11 10
9
8
1
arz sgn ov acz tb ovm
: Part of upper byte of status register
CALA
Call subroutine indirectly
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
CALA
Operation:
pc + 1 à (sp)
sp + 1 à sp
acc(31:16) à pc
Words:
Cycles:
1
2
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CALL
Call subroutine directly
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
CALL pma16
pc + 1 à (sp)
sp + 1 à sp
pma16 à pc
2
Operation:
Words:
Cycles:
3
DINT
Disable interrupt
15 14 13 12 11 10
DINT
9
8
7
6
5
4
3
2
2
2
1
1
1
0
0
0
Syntax:
Operation:
pc + 1 à pc
1 à INTM bit in status register
Words:
Cycles:
1
1
EINT
Enable interrupt
15 14 13 12 11 10
9
8
7
6
5
4
3
Syntax:
DINT
Operation:
pc + 1 à pc
0 à INTM bit in status register
Words:
Cycles:
1
1
IN
Move data from I/O mapped register to internal data memory
15 14 13 12 11 10
IN dma7, port_address
IN * , port_address [,narp]
pc + 1 à pc
9
8
7
6
5
4
3
Syntax:
Operation:
iop(1:0).port_address à io_address
(io_address) à (dma)
Words:
Cycles:
1
1
LAC
Load data from memory to high accumulator
15 14 13 12 11 10
LAC dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
LAC * [,narp]
pc + 1 à pc
(dma) à acc(31:16)
0
1
à acc(15:0)
Words:
Cycles:
1(DI) , 2(DE)
50
Ver 0.01, December 5, 2000
MX93111
LACK
Load immediate 7-bit unsigned short constant to high accumulator
15 14 13 12 11 10
LACK cnst7
pc + 1 à pc
cnst7 à acc(22:16)
0 à acc(31:23)
0 à acc(15:0)
1
9
8
7
6
5
4
3
3
3
2
2
2
1
1
1
0
0
0
Syntax:
Operation:
Words:
Cycles:
1
LACL
Load immediate 16-bit long constant to high accumulator
15 14 13 12 11 10
LACL cnst16
9
8
7
6
5
4
Syntax:
Operation:
pc + 2 à pc
cnst16 à acc(31:16)
0
2
2
à acc(15:0)
Words:
Cycles:
LAR
Load data from memory to auxiliary register specified
15 14 13 12 11 10
LAR dma7 , arps
LAR * , arps [,narp]
pc + 1 à pc
9
8
7
6
5
4
Syntax:
Operation:
(dma) à (arps)
1
Words:
Cycles:
Note:
1(DI) , 2(DE)
Data from memory( by direct mode or register indirect mode) will be loaded into
auxiliary register specified in instruction encoding( arps : 3 bit constant). Post
increment or decrement on current auxiliary register will not be performed during
this instruction operation, but new arp can be changed.
51
Ver 0.01, December 5, 2000
MX93111
LARK
Load immediate 7-bit short constant to auxiliary register specified
15 14 13 12 11 10
LARK cnst7 , arps
pc + 1 à pc
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
cnst7 à (arps)(6:0) , 0 à (arps)(15:7)
Words:
Cycles:
1
1
LARL
Load immediate 16-bit long constant to auxiliary register specified
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
LARL cnst16 ,arps
Operation:
pc + 2 à pc
cnst16 à (arps)
Words:
Cycles:
2
2
LDP
Load data from memory to modify data page pointer in status register
15 14 13 12 11 10
LDP dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
LDP * [,narp]
pc + 1 à pc
(dma)(3:0) à dp(3:0)
1
Words:
Cycles:
1(DI) , 2(DE)
LDPK
Load 4-bit short constant to modify data page pointer in status register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
LDPK cnst4
Operation:
pc + 1 à pc
cnst4 à dp(3:0)
Words:
Cycles:
1
1
52
Ver 0.01, December 5, 2000
MX93111
LIP
Load data from memory to modify I/O page pointer in status register
15 14 13 12 11 10
LIP dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
LIP * [,narp]
pc + 1 à pc
(dma)(5:4) à iop(1:0)
1
Words:
Cycles:
1(DI) , 2(DE)
LIPK
Load 2-bit short constant to modify I/O page pointer in status register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
LIPK cnst2
Operation:
pc + 1 à pc
cnst2 à iop(1:0)
Words:
Cycles:
1
1
LUP
Enable loop operation
15 14 13 12 11 10
LUP dma7, loop_number
LUP * , loop_number [,narp]
pc + 1 à pc
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
(dma)(9:0) à rc(9:0)
loop_number à lc(2:0)
1
Words:
Cycles:
Note:
1(DI) , 2(DE)
This instruction will enable hardware loop operation , and the following
(loop_number+1) words instruction(program loop) will be executed repeatedly
( rc +1) times.
Branch and call instructions are not allowed within program loop.
53
Ver 0.01, December 5, 2000
MX93111
LUPK
Load 7-bit short constant to repeat counter and enable loop operation
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
LUP cnst7 , loop_number
Operation:
pc + 1 à pc
cnst7 à rc(6:0)
loop_number à lc(2:0)
Words:
Cycles:
Note:
1
1
This instruction will enable hardware loop function , and the following
( loop_number+1 ) words instruction (program loop)will be executed repeatedly
( rc +1) times. No branch and call instructions are allowed within program loop.
MAR
Modify current auxiliary register and update auxiliary register pointer
15 14 13 12 11 10
MAR * [,narp]
9
8
7
6
5
4
3
2
1
0
0
0
Syntax:
Operation:
pc + 1 à pc
Modify the content of current auxiliary register pointed by current auxiliary
register pointer, and update this pointer with new pointer.
Words:
Cycles:
1
1
MOD
Load data from memory to modulo register
15 14 13 12 11 10
MOD dma7
9
8
7
6
5
4
3
2
1
Syntax:
Operation:
MOD * [,narp]
pc + 1 à pc
(dma)(9:0) à mr(9:0)
1
Words:
Cycles:
1(DI) , 2(DE)
MODK
Load immediate 7-bit short constant to modulo register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
Syntax:
MODK cnst7
Operation:
pc + 1 à pc
cnst7 à mr(6:0)
Words:
Cycles:
1
1
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Ver 0.01, December 5, 2000
MX93111
NOP
No operation
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
Words:
NOP
pc + 1 à pc
1
1
Cycles:
NOM
Normalize the content of accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
NOM
Operation:
pc + 1 à pc
Normalize(acc) à acc
Left Shift Count à SHFC
Words:
Cycles:
Note:
1
1
This NOM instruction performs hardware normalization operation on signed
two‘ s complement numbers stored in the accumulator. The left shifted counts
during normalization are stored in shift count register( SHFC ) .
OR
OR data from memory with high accumulator
15 14 13 12 11 10
OR dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
OR * [,narp]
pc + 1 à pc
acc(31:16) OR (dma) à acc(31:16)
Words:
Cycles:
1
1(DI) , 2(DE)
ORK
OR immediate 7-bit short constant with high accumulator
15 14 13 12 11 10
ORK cnst7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 1 à pc
acc(22:16) OR cnst7 à acc(22:16)
acc(31:23) à acc(31:23)
Words:
Cycles:
1
1
55
Ver 0.01, December 5, 2000
MX93111
ORL
OR immediate 16-bit long constant with high accumulator
15 14 13 12 11 10
ORL cnst16
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 2 à pc
acc(31:16) OR cnst16 à acc(31:16)
Words:
Cycles:
2
2
OUT
Load data from internal data memory to I/O mapped register
15 14 13 12 11 10
OUT dma7, port_address
OUT * , port_address [,narp]
pc + 1 à pc
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
iop(1:0).port_address à io_address
(dma) à (io_address)
Words:
Cycles:
1
1
OUTK
Move 7-bit short constant to I/O mapped register
15 14 13 12 11 10
OUTK cnst7, port_address
pc + 1 à pc
9
8
7
6
5
4
4
4
3
3
3
2
2
2
1
1
1
0
0
0
Syntax:
Operation:
iop(1:0).port_address à io_address
cnst7 à (io_address)(6:0)
Words:
Cycles:
1
1
OUTL
Move 16-bit long constant to I/O mapped register
15 14 13 12 11 10
OUTL cnst16, port_address
pc + 2 à pc
9
8
7
6
5
Syntax:
Operation:
iop(1:0).port_address à io_address
cnst16 à (io_address)
Words:
Cycles:
2
2
POP
Pop top of stack to data memory
15 14 13 12 11 10
POP dma7
9
8
7
6
5
Syntax:
Operation:
POP * [,narp]
pc + 1 à pc
sp - 1 à sp
(sp) à (dma)
56
Ver 0.01, December 5, 2000
MX93111
Words:
Cycles:
1
1(DI) , 2(DE)
POPH
Pop top of stack to high accumulator
15 14 13 12 11 10
POPH
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 1 à pc
sp - 1 à sp
(sp) à acc(31:16)
Words:
Cycles:
1
1
POPL
Pop top of stack to low accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
POPL
Operation:
pc + 1 à pc
sp - 1 à sp
(sp) à acc(15:0)
Words:
Cycles:
1
1
PSH
Push data from memory onto stack
15 14 13 12 11 10
PSH dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
PSH * [,narp]
pc + 1 à pc
(dma) à (sp)
sp + 1 à sp
Words:
Cycles:
1
1(DI) , 2(DE)
PSHH
Push high accumulator onto stack
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
PSHH
Operation:
pc + 1 à pc
acc(31:16) à (sp)
sp + 1 à sp
Words:
Cycles:
1
1
57
Ver 0.01, December 5, 2000
MX93111
PSHL
Push low accumulator onto stack
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
PSHL
Operation:
pc + 1 à pc
acc(15:0) à (sp)
sp + 1 à sp
Words:
Cycles:
1
1
RET
Return from subroutine
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
RET
Operation:
sp - 1 à sp
(sp) à pc
Words:
Cycles:
1
2
RETI
Return from interrupt
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
RETI
Operation:
sp - 1 à sp
(sp) à pc
sp -1 à sp
(sp) à status register
Words:
Cycles:
1
2
ROVM
Reset overflow mode
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
ROVM
Operation:
pc + 1 à pc
0 à OVM bit in status register
Words:
Cycles:
1
1
RPT
Load data from memory to repeat counter
15 14 13 12 11 10
RPT dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
RPT * [,narp]
pc + 1 à pc
(dma)(9:0) à rc(9:0)
1
Words:
Cycles:
1(DI) , 2(DE)
58
Ver 0.01, December 5, 2000
MX93111
RPTK
Load immediate 7-bit short constant to repeat counter
15 14 13 12 11 10
9
8
7
6
5
4
4
4
4
3
3
3
3
2
2
2
2
2
1
1
1
1
1
0
0
0
0
0
Syntax:
RPTK cnst7
Operation:
pc + 1 à pc
cnst7 à rc
Words:
Cycles:
1
1
RXF
Reset external flag
15 14 13 12 11 10
9
8
7
6
5
Syntax:
RXF
Operation:
pc + 1 à pc
0 à XF but 1 à XF\ pin
Words:
Cycles:
Notes:
1
1
XF\ is an inverted output of XF .
SAH
Store content of high accumulator to data memory
15 14 13 12 11 10
SAH dma7
9
8
7
6
5
Syntax:
Operation:
SAH * [,narp]
pc + 1 à pc
acc(31:16) à (dma)
1
Words:
Cycles:
1(DI) , 2(DE)
SAL
Store content of low accumulator to data memory
15 14 13 12 11 10
SAL dma7
9
8
7
6
5
Syntax:
Operation:
SAL * [,narp]
pc + 1 à pc
acc(15:0) à (dma)
1
Words:
Cycles:
1(DI) , 2(DE)
SAR
Store content of auxiliary register specified to data memory
15 14 13 12 11 10
SAR dma7 , arps
SAR * , arps [,narp]
pc + 1 à pc
9
8
7
6
5
4
3
Syntax:
Operation:
Words:
(arps) à (dma)
1
59
Ver 0.01, December 5, 2000
MX93111
Cycles:
SBH
1(DI) , 2(DE)
Subtract data ( from memory ) from high accumulator
15 14 13 12 11 10
SBH dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
SBH * [,narp]
pc + 1 à pc
acc(31:16) - (dma) à acc(31:16)
Words:
Cycles:
1
1(DI) , 2(DE)
SBHK
Subtract immediate 7-bit unsigned short constant from high accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
SBHK cnst7
Operation:
pc + 1 à pc
acc(31:16) - cnst7 à acc(31:16)
Words:
Cycles:
1
1
SBHL
Subtract immediate 16-bit long constant from high accumulator
15 14 13 12 11 10
SBHL cnst16
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 2 à pc
acc(31:16) - cnst16 à acc(31:16)
Words:
Cycles:
2
2
SBL
Subtract data ( from memory ) from low accumulator
15 14 13 12 11 10
SBL dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
SBL * [,narp]
pc + 1 à pc
acc(31:0) - (dma) à acc(31:0)
1
Words:
Cycles:
Note:
1(DI) , 2(DE)
Data operand is expanded into 32 bit long width with MSBs optionally sign
extended or filled with “ 0” bits. This option is controlled by SNSEL bit in CTLR.
60
Ver 0.01, December 5, 2000
MX93111
SBLK
Subtract immediate 7-bit unsigned short constant from low accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
SBLK cnst7
Operation:
pc + 1 à pc
acc(31:0) - cnst7 à acc(31:0)
Words:
Cycles:
1
1
SBLL
Subtract immediate 16-bit long constant from low accumulator
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
SBLL cnst16
Operation:
pc + 2 à pc
acc(31:0) - cnst16 à acc(31:0)
Words:
Cycles:
Note:
2
2
Data operand is expanded into 32 bit long width with MSBs optionally sign
extended or filled with “ 0” bits. This option is controlled by SNSEL bit in CTLR.
SDP
Store data page pointer in status register to data memory
15 14 13 12 11 10
SDP dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
SDP * [,narp]
pc + 1 à pc
dp(3:0) à (dma)(3:0)
1
Words:
Cycles:
1(DI) , 2(DE)
SFL
Shift content of accumulator left ( LSBs filled with zero )
15 14 13 12 11 10
SFL cnst4
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 1 à pc
If ( cnst4!= 0)
then
acc(31:0) will be shifted left by cnst4 bits
else
acc(31:0) will be shifted left by shfc[3:0] bits
Words:
Cycles:
Notes:
1
1
shfc[3:0] is the content stored in SHFC register (I/O mapped 3 ).
61
Ver 0.01, December 5, 2000
MX93111
SFR
Shift content of accumulator right ( MSBs filled with zero )
15 14 13 12 11 10
SFR cnst4
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
pc + 1 à pc
If ( cnst4!= 0)
then
acc(31:0) will be shifted right by cnst4 bits
else
acc(31:0) will be shifted right by shfc[3:0] bits
Words:
Cycles:
Notes:
1
1
shfc[3:0] is the content stored in SHFC register (I/O mapped 3 ).
SFRS
Shift content of accumulator right ( MSBs filled with sign extended bit )
15 14 13 12 11 10
SFRS cnst4
pc + 1 à pc
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
If ( cnst4!= 0)
then
acc(31:0) will be shifted right by cnst4 bits
else
acc(31:0) will be shifted right by shfc[3:0] bits
Words:
Cycles:
Notes:
1
1
shfc[3:0] is the content stored in SHFC register (I/O mapped 3 ).
62
Ver 0.01, December 5, 2000
MX93111
SIP
Store I/O page pointer in status register to data memory
15 14 13 12 11 10
SIP dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
SIP * [,narp]
pc + 1 à pc
iop(1:0) à (dma)(1:0)
1
Words:
Cycles:
1(DI) , 2(DE)
SOVM
Set overflow mode ( Enable overflow mode protection)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
SOVM
Operation:
pc + 1 à pc
1 à OVM bit in status register
Words:
Cycles:
Note:
1
1
When OVM bit being set , overflow mode protection is enabled. IF result of data
operation during add/subtract and shifting instructions execution exceed the
maximum or minimum value that can be represented by the accumulator , data
in accumulator will be saturated to the largest positive or negative number that
can be represented.( 0x7FFFF FFFF or 0x8000 0000)
SSS
Store content of status register to data memory
15 14 13 12 11 10
SSS dma7
9
8
7
6
5
4
3
2
1
0
Syntax:
Operation:
SSS * [,narp]
pc + 1 à pc
ss(15:0) à (dma)
1
Words:
Cycles:
1(DI) , 2(DE)
SXF
Set external flag
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Syntax:
SXF
Operation:
pc + 1 à pc
1 à XF but 0 à XF\ pin
Words:
Cycles:
Notes:
1
1
XF\ is an inverted output of XF .
63
Ver 0.01, December 5, 2000
MX93111
XOR
XOR data from memory with high accumulator
15 14 13 12 11 10
XOR dma7
9
8
7
6
5
4
3
2
2
2
1
1
1
0
0
0
Syntax:
Operation:
XOR * [,narp]
pc + 1 à pc
acc(31:16) XOR (dma) à acc(31:16)
Words:
Cycles:
1
1(DI) , 2(DE)
XORK
XOR immediate 7-bit short constant with high accumulator
15 14 13 12 11 10
XORK cnst7
9
8
7
6
5
4
3
Syntax:
Operation:
pc + 1 à pc
acc(22:16) XOR cnst7 à acc(22:16)
acc(31:23) à acc(31:23)
Words:
Cycles:
1
1
XORL
XOR immediate 16-bit long constant with high accumulator
15 14 13 12 11 10
XORL cnst16
9
8
7
6
5
4
3
Syntax:
Operation:
pc + 2 à pc
acc(31:16) XORL cnst16 à acc(31:16)
Words:
Cycles:
2
2
64
Ver 0.01, December 5, 2000
MX93111
6 PCM CODEC
6.1 CODEC OVERVIEW
The PCM CODEC integrates key functions of the analog-front-end of DAM (with Digital Speakerphone)
related products into an integrated circuit. The PCM CODEC is especially powerful when applied to some
DAM models which are intended to meet different countries' specifications in the same system hardware.
User can achieve this goal by simply setting control firmware. This benefit will help DAM system makers
to save developing time and R&D resources.
The built-in CODEC has one A/D, D/A converters so as to meet the requirement of the digital answering
machine application. The on-chip digital filters, which are carried out with 16-bit and 2's complement
format, are used to get required frequency response of a PCM CODEC. PCM CODEC is 16-bit format
with 14-bit resolution.
Before the A/D digitizing the voice-band analog signal into digital format, the analog signal can be
ALC
PRE-
processed by a built-in Automatic Level Control (
) and PRE-Programmable Gain Amplifier (
PGA
). The
ALC
AD1-PGA
circuit controls the signal level about 1.2Vpp and
can provide 0 ~ 18dB gain
PRE-PGA
MIC
,
to get more larger signal. The
AUX1 LIN
circuit is used to control the gain of different sources like
or
input.
After the digital data is converted into analog signal by D/A converter, a fully differential line driver and
speaker driver are supported to drive the telephone line and 8W speaker directly without needing any
external amplifiers. Besides, the analog signal can be monitored by passing the on-chip volume control
or external volume control.
The MX93111 supports many switches as well. User can program the control registers of the PCM
CODEC to accomplish all specific operations of DAM (with digital speakerphone function) related
products.
65
Ver 0.01, December 5, 2000
MX93111
BLOCK DIAGRAM (PCM CODEC)
AVDD
C5
VDD
C4
23
47
84
C7
AUX-I/O
FAX TXA
C6
Corelessphone
101
102
125
124
114
113
24,51,85,93,17
DGND
R2
BUF
AG
FILT
PGAC2
105
VREF
AVDD AGND VDD
50
CP
C18
R1
C1
C2
PCM CODEC
SWI
DSP
MCLK
FS
X
Master
Cloc
AD1
PGA
SWC
SWA
a
signal
DSP
SWD
MIC
C8
A
b
MIC
AUX1
LIN
PRE
PGA
106
108
107
X
X
Frame
Sync
AIN
a
A
I
signal
b
c
A
DSP
Transm
DATA
C1
DR
ALC
SWN
N
C19
AG
d
DSP
Receive
DATA
DX
X
SWB
109
PGAC1
SWJ
C9
A
O
U
T
110
111
ALCRC
ALCC1
+
R3
C1
C1
ALCC2
LOUTP
AOUT
112
99
TELEPHONE
LIN
LIN
DRV
LOUTN
INTERFACE
100
123
SWL
SVDD1
SVDD2
SGND
AVD
C1
119
121
SCLK
uP
X
SWG
SWF
Send
SCLK
SPK
ATT1
ATT2
A
a
SPKP
SPKN
122
120
SPK
DRV
D/A
PGA
L.P.F.
SERIAL
CONTROL
UNIT
SDENB
SDATA
uP
X
X
Enable
SDATA
B
VR
VR
LPFC2
LPFC1
118
116
115
uP
TX / RX
Control
DATA
C1
C1
CMP1
CMP2
uP
check
CMP10
CMP20
SWK
SWH
97
95
SYSTEM
Power
103
104
VBG
AG
C1
C1
uP
check
AG
SYSTEM
Battery
AUX2
117
VCOMP
94
CMP1I
98
CMP2I
96
R4
R5
R6
R7
AUX-I/O
X : Internal Signal
AC/DC
ADAPTOR
BATTERY
POWER
V reference
for POW and BAT
2 Comparators
FAX RXA
Corelessphone
66
Ver 0.01, December 5, 2000
MX93111
BASIC COMPONENTS REQUIRED
REFERANCE PART
DESCRIPTION
*R1
R2
68KW the resistor for internal PLL charge pump circuits
2KW
current limit resistor; to limit MIC bias current, please follow MIC specification
ALC
R3
560KW
release time constant;
R4, R5
CMP1I VCOMP
) for reference to
to scale down DC power supply (
to check
CMP2I VCOMP
) for reference to to check battery
power low
R6, R7
to scale down battery power (
low
*C1
*C2
100pF the capacitor for internal PLL charge pump circuits
6pF the capacitor for internal PLL charge pump circuits
C8, C17
C11
0.1uF DC blocking capacitor (0.1~10uF)
0.22uF DC blocking capacitor (0.1~10uF); H.P.F.
¡
Ü £ k
1/2 * 4.4KW * C6 (0.22uF) = 164Hz
3dB point : fc
C6
C9
10uF
DC offset canceling compensative capacitor (4.7~10uF, the larger the better)
0.1uF DC offset canceling compensative capacitor (0.1~1uF, the larger the better)
0.1uF De-couple capacitor (0.1~10uF)
C3, C4, C5,
C12, C16
C15
FUNCTIONAL DESCRIPTION
0.1uF De-couple capacitor (0.01~10uF); see
ALC
C10
10uF
5000pF anti-aliasing capacitor
L.P.F.
attack time constant;
*C7
¡
Ü
£
k
C13, C14
*VR1
passive
; 3dB point : fc
1/2 * 3KW * C13 (where C13 = C14)
SWH SWF
or
10KW to attenuate the input signal from
, if use digital volume control,
then do
VR
SPKP
and
not need a resistor between
@ where : " * " mark shows the requirement of the component can not be changed.
67
Ver 0.01, December 5, 2000
MX93111
6.2 FUNCTIONAL DESCRIPTION
. PCM CODEC
A/D D/A
converters and all digital filters;
. The block includes
A/D D/A
&
1.
&
Converters
Channel :
A. Input Range : 0 ~ 3Vpp (3Vpp as A/D 0dB full swing (0dBFS));
A/D
B. Digital Filters : For the purpose of out-of-band noise filtering, IIR digital filters are implemented
on the same chip ( >26dB / 60Hz; <1dB / 300Hz ~ 3.4KHz; >14dB / 3.6KHz ~ 4.6KHz; >32dB /
4.6KHz );
D/A
Channel :
A. Output swing : 0 ~ 3Vpp (3Vpp as D/A 0dB full swing (0dBFS));
B. Digital Filters :
a. G.711 specification;
b. The digital input applied to D/A converter can not be a DC signal other than idle (bits all
zero), as limit cycles in the embodiment method at a level of -70dBm will present at the
analog output.
2.Data format : Linear format
@ Linear 16-bit format : 14-bit resolution with 2 LSB = 0
SIGN \ SCALE
POSITIVE
MIN
MAX
0000 0000 0000 0000
1111 1111 1111 1100
0111 1111 1111 1100
1000 0000 0000 0000
NEGATIVE
68
Ver 0.01, December 5, 2000
MX93111
Power Down Mode
.
The CODEC will recover from power-down mode when
keeps high;
ICPDX
. Support system power (Adapter and Battery) detection. The function will work well even under 3V power
Supply;
. Support power-down control when
keeps low;
ICPDX
. Support 4 power-down modes for special applications:
CDREADYX
ICPDX
VBG
VAG
COMPARE
PDLG
SLEEPA
MODE
SLEEP
REG 6 (7,6)
REG 6 (7,6)
REG 6 (7,6)
REG 6 (7,6)
(SLEEPA,SLEEP) = (SLEEPA,SLEEP) = (SLEEPA,SLEEP) = (SLEEPA,SLEEP) =
FUNCTION
VBG
( 0,0 )
on
( 0,1 )
off
( 1,0 )
off
( 1,1 )
on
reference
POW BAT
&
on
off
on
on
all analog blocks
A/D and D/A
off
off
off
on
off
off
off
off
Table 1
* Power down procedure
1. Keep (SLEEPA, SLEEP) = (0,0) in stand by mode.
2. Setup (SLEEPA, SLEEP) to system required mode.
3. Trigger CODEC power down. Clear
(bit 2) = 0.
CDCMR ICPDX
4. Trigger DSP power down. Set
bit (bit 11) = 1.
CTLR PWDN
* Wake up procedure
1. Trigger DSP wake up. Clear
bit (bit 11) = 0.
CTLR PWDN
2. Wait DSP stable. Wait
bit (bit 5) = 0.
CTLR PWDNS
3. Setup (SLEEPA, SLEEP) = (0,0).
4. Trigger CODEC wake up. Set
(bit 2) = 1.
CDCMR ICPDX
5. Wait CODEC ready. Wait
(bit 9) = 0.
CDCMR CDREADYX
69
Ver 0.01, December 5, 2000
MX93111
. 3-Channel Input (MIC,AUX1,LIN) with PRE-PGA (Pre-Programmable Gain Control)
. Input Range : 0 ~ AVDD-2Vpp;
PRE-PGA
.
gain step from 21dB to -15dB (21, 18, 15, 12, 9, 7.5, 6, 4.5, 3, 0, -3, -6, -9, -12, -15dB);
FILT
AUX2
output;
. Driving Capacity : more than 400uA at
and
. Input Impedance : more than 25KW;
FILT
. THD : less than 70dB at
output;
. There is just one path which can be selected at the same time;
PRE-PGA
. The gain setting of the path will be mapped to the
when user changes the path of Input.
ALC (Automatic Level Control)
.
. Input Range : 0 ~ 1.2Vpp (Loop Gain : 40dB);
FIG. 5 FIG. 7
;
. Output Characteristic : see
. Loop Gain : 42dB max (with external RC time constant);
FILT AUX2
output;
~
. Driving Capacity : more than 400uA at
and
output (Loop Gain : 40dB).
FILT
. THD : less than 40dB at
. AD1 PGA
. Input Range : 0 ~ AVDD-2Vpp;
AD1-PGA
.
can support gain step from 0dB to 18dB (0, 4, 8, 18dB);
. FILT as I/O Port
. Input Range : 0 ~ AVDD-2Vpp;
. Input Impedance : more than 1KW;
. Output Impedance : less than 1KW;
. Load Capacitance : 5000pF;
. AUX1 & AUX2 as I/O Port
. Input Range : 0 ~ AVDD-2Vpp;
. Input Impedance : more than 15KW;
. Output Impedance : less than 15KW;
. External passive L.P.F. (Low Pass Filter)
LPFC1
. External capacitors (
LPFC2
) can be changed to attenuate high frequency noise at
SPKP
and
SPKN
and
output;
LPFC1
LPFC2
) are NC (no connection), then passive
L.P.F.
L.P.F.
. When external capacitors (
by-passed;
and
and
will be
LOUTP
LOUTN
) can be chosen to pass or by-pass the
. Output of the Line Driver (
LPFC1/LPFC2
;
.
can be a D/A output pin and output impedance is around 3KW/6KW;
. D/A PGA
. Input Range : 0 ~ AVDD-2Vpp;
DA-PGA
.
can support gain step from 0dB to 6dB (2dB/step);
70
Ver 0.01, December 5, 2000
MX93111
. Line Driver (
)
LIN-DRV
. Not only support the programmable gain from 0 to 22.5dB, but also fully differentially drive 6Vpp over
600W;
SWE SWJ SWK
SWL
are opened, then the line driver will be muted to -70dB and
. If switches
power-down automatically;
1. output swing : Single Ended (only use
,
,
and
LOUTP LOUTN
or
) : 0 ~ 3Vpp (over 600W load, at LIN-
LOUTP LOUTN
DRV = 0dB); Fully differential (use
0dB);
+
) : 0 ~ 6Vpp (over 600W load, at LIN-DRV =
LIN-DRV
2.
gain step from 0dB to 22.5dB (1.5dB/step);
3. THD : less than 70dB at 6Vpp output over 600W load;
. Attenuator ( )
&
ATT1 ATT2
. Speaker output signal can be attenuated either by internal register or external resistor;
SWF SWH
are opened, then attenuator will be muted to -70dB automatically;
. If switches
and
(internal register) : 16 steps programmable, from -45dB to 0dB (-45, -39, -33, -27, -24, -21, -
18, -15, -12, -9, -7.5, -6, -4.5, -3, -1.5, 0dB);
ATT2
ATT1
1.
2.
(external variable resistor) : from -45 ~ 0dB (determined by external 10KW potentiometer);
3. THD : less than 70dB;
AUX2
4. input range for
: 0 ~ AVDD-2Vpp;
AUX2
5. input impedance for
: more than 15KW;
. Speaker Driver (SPK-DRV)
SWF
SWH
SPK-DRV
are opened, then will be power-down automatically;
. If switches
and
SPKP SPKN
);
1. Maximum output swing : 6Vpp with 8W load at fully differential output (
2. THD : less than 60dB (at 6Vpp/8W load);
+
. Voltage Reference (VREF & VAG)
VREF
. Two 2.25VW voltage references are on-chip generated, where
is for external circuit use and
VAG
is for internal circuit use;
VREF
.
can be used to bias the microphone, the level shift circuit or other applications;
driving capacity : more than 400uA;
VREF
1.
VREF
2. User can use the
to provide DC bias to external components;
. Bandgap Reference (VBG)
VBG
. A bandgap circuit generates a voltage source ( ) which is around 1.2VW.It is with low temperature
coefficient and good power supply rejection;
. If user changes VBG bypass capacitor (C15) then the MX93002 warm-up time will be changed; see
The Timing Diagram of CODEC Function;
71
Ver 0.01, December 5, 2000
MX93111
. Serial Control Interface
IFS
ISDATAW/ISDATAR
to read/write the internal control registers;
. Use
for synchronization with
. All registers will keep original setting when the CODECs returns from power-down or sleep mode;
ISDENX
1. When
serial control data
ISDENX
(serial data enable) signal active low, the CODECs starts to receive(transmit)
ISDATAW (ISDATAR)
;
ISDATAW / ISDATAR
from low to high when transmitting / receiving is complete;
format : 3 addresses from A2 to A0, 8 data from D7 to D0 (A2 is MSB and D0 is
2. Set
ISDATA(R/w)
3.
LSB);
. Two Comparatoes for AC power and battery power
.To detect AC power and battery power or other applications;
1.input range : 0~AVDD-2Vpp (with 7V surge protection);
2.input impedence : more than 10^12W;
3.input offset voltage : less than 10Mv;
4.output impedence : less than 10KW
5.slew rate : 3V/us max;
. Switches
. There are three registers (REG0, REG3 and REG6) which are used to control all of the switches so
that user can direct many different signal paths, for examples:
MIC
SPKP/N
LOUTP/N
:
1. Record signal from
A. Record signal from
a. System initialization [set
gain 0/6dB (REG5 bit(1)) and set
MIC
and play signal to
or play signal to
:
MIC
LIN
or Record signal from
MIC
LIN
ALC
gain (REG2 bit(3~0)), set
gain (REG1 bit(7~4), set
gain (REG6 bit(1,0))]
: set REG0 = 0X0048
PRE-PGA SWC ALC
A/D-PGA
b. Record signal from
MIC SWA
SWD
SWD
AD1-PGA PCM CODEC AIN1
AD1-PGA PCM CODEC AIN1
Þ
Þ
Þ
Þ
(
on) Þ
Þ
Þ
LIN
c. Record signal from
: set REG0 = 0X00C8
LIN SWA PRE-PGA
SWC ALC
Þ
Þ
Þ
(
on) Þ
LOUTP/N
:
Þ
SPKP/N
B. Play signal to
or play signal to
L.P.F.
D/A-PGA
gain (REG6
a. System initialization [fix the value of
, set (REG6 bit(5)), set
ATT1
LIN-DRV
gain (REG1 bit(3~0))]
bit(3,2), set
gain (REG3 bit(3~0)) and
SPKP/N
b. Play signal to
PCM CODEC AOUT1
SPKP/N
(use digital volume control) : set REG 0 = 0X0003
L.P.F. SWF DA-PGA SWG ATT1
SPK-DRV
Þ
Þ
Þ
Þ
Þ
(
) Þ
LOUTP/N
c. Play signal to
: set REG 0 = 0X0004
L.P.F. SWL LIN-DRV LOUTP/N
Þ
PCM CODEC AOUT1
PCM CODEC AOUT2
i.
Þ
Þ
Þ
Þ
SWE
LIN-DRV
LOUTP/N
Þ
ii.
Þ
SPKP/N
LOUTP/N
d. Play signal to
(use digital volume control) and
: set REG 0 = 0X0007
PCM CODEC AOUT1
SPKP/N
L.P.F.
SWF
DA-PGA
Þ Þ
SWG ATT1 SPK-DRV
i.
Þ
Þ
Þ
(
) Þ
Þ
PCM CODEC AOUT2
SWE
LIN-DRV
LOUTP/N
Þ
Þ
72
Ver 0.01, December 5, 2000
MX93111
PCM CODEC AOUT1
L.P.F.
SWF
SWL
DA-PGA
Þ
LIN-DRV
Þ
SWG ATT1
SPK-DRV
) Þ Þ
ii.
Þ
Þ
Þ
Þ
(
SPKP/N
LOUTP/N
Þ
2. Room Monitoring:
A. System initialization [set
MIC
ALC
gain 0/+6dB (REG5 bit(1)), set
gain (REG2 bit(3~0)), set
LIN-DRV
gain (REG1 bit(3~0)), set REG3 bit(6,5) and set REG6 bit(1,0)]
B. Switches path:
a. Remote Monitoring:
MIC
SWA
PRE-PGA
SWC ALC
SWJ
LIN-DRV
LOUTP/N
Þ
Þ
Þ
Þ
(
on) Þ
b. Local Detecting DTMF:
LIN SWI AD1-PGA PCM CODEC AIN1
Þ
Þ
Þ
Þ
. Power Consumption of CODEC (with 600 line load and 8 speaker load)
W
W
Max. Power
Consumption LIN-DRV
SPK-DRV
Analog
circuits
Unit
Dis/Enable Dis/Enable
Operation
Stand-by
Disable
Disable
Enable
Disable
Enable
Disable
Disable
Disable
Disable
Disable
Enable
Enable
Disable
Disable
20
20
mA
mA
Operating
31
217
217
120
20
Power-down
uA
uA
Power-down with SLEEP = 1
LIN-DRV
SPK-DRV
(with 8W load) full swing output
@ Test condition : 1. at
(with 600W load) /
LIN-DRV
SPK-DRV
2. see
and
Descriptions
73
Ver 0.01, December 5, 2000
MX93111
6.3 CONTROL REGISTERS DEFINITION
REGISTER 0
ADDRESS BIT
DATA
A2
A1
A0
0
0
0
DATA BIT
POWER-ON
DESCRIPTION
D7
D6
D5
0
D4
0
D3
0
D2
D1
0
D0
0
0
0
0
SWA
SWB
SWC
SWD
SWF
SWG
SWA
SWA
SWA
SWA
SWA
PRE-PGA
LIN
GAIN SETTING
(
) D(7,6) = (1,1) : path of
= (1,0) : path of
is "c Þ A",
is "b Þ A",
is "a Þ A",
setting follows
setting follows
setting follows
PRE-PGA
PRE-PGA
AUX1
GAIN SETTING
MIC
= (0,1) : path of
GAIN SETTING
AG
)
= (0,0) : path of
is "d Þ A", (GROUNDING to
SWB
is "OPEN"
SWB
SWC
SWD
SWF
SWG
SWB
is "CLOSE", D(5) = (0) : path of
(
(
(
) D(5) = (1) : path of
) D(4) = (1) : path of
) D(3) = (1) : path of
) D(1) = (1) : path of
) D(0) = (1) : path of
= (0) : path of
SWC
SWD
SWF
SWG
SWG
SWC
is "a Þ A"
is "b Þ A", D(4) = (0) : path of
is "CLOSE", D(3) = (0) : path of
is "CLOSE " , D(1) = (0) : path of
SWD
is "OPEN"
SWF
(
is " OPEN "
ATTENUATOR 1 (ATT1)
ATTENUATOR 2 (ATT2)
(
is "a Þ A",
is "a Þ B",
REGISTER 1
ADDRESS BIT
DATA
A2
A1
A0
0
0
1
DATA BIT
POWER-ON
DESCRIPTION
D7
D6
D5
D4
0
D3
D2
D1
D0
0
0
0
0
0
0
0
LIN
PRE-PGA
LIN-DRV
GAIN SETTING
GAIN SETTING (
)
LIN
NOTE 1
(
(
GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB; see
LIN-DRV
NOTE 2
GAIN SETTING ) D(3~0) = (F) ~ (0) : 22.5dB ~ 0dB 1.5dB/step; see
REGISTER 2
ADDRESS BIT
DATA
A2
A1
A0
0
1
0
DATA BIT
POWER-ON
DESCRIPTION
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
AUX1
PRE-PGA
MIC
PRE-PGA
GAIN SETTING ( )
GAIN SETTING (
)
AUX1
NOTE 1
GAIN SETTING ) D(7~4) = (F) ~ (0) : 21dB ~ -15dB; see
(
(
MIC
NOTE 1
GAIN SETTING ) D(3~0) = (F) ~ (0) : 21dB ~ -15dB; see
74
Ver 0.01, December 5, 2000
MX93111
REGISTER 3
ADDRESS BIT
DATA
A2
A1
A0
0
1
1
DATA BIT
POWER-ON
DESCRIPTION
D7
D6
0
D5
0
D4
0
D3
D2
D1
D0
0
SWH
1
1
1
1
SWI
SWJ
SWK
ATT1
GAIN SETTING
SWH
SWH
SWH
is "OPEN”
(
(
(
(
(
) D(7) = (1) : path of
is "CLOSE", D(7) = (0) : path of
SWI
SWI
is "CLOSE", D(6) = (0) : path of
SWI
) D(6) = (1) : path of
) D(5) = (1) : path of
is "OPEN"
SWJ
SWJ
SWJ
is "CLOSE", D(5) = (0) : path of
is "CLOSE", D(4) = (0) : path of
is "OPEN"
SWK
SWK
ATT1
SWK
) D(4) = (1) : path of
is "OPEN"
NOTE 3
GAIN SETTING ) D(3~0) = (F)~(0) : - 45dB ~ 0dB; see
REGISTER 5
ADDRESS BIT
DATA
A2
A1
A0
1
0
1
DATA BIT
POWER_ON
DESCRIPTION
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
0
D0
0
0
0
ALC1
SPKHI
ADA
AIADID
DAYT
ADYT
ALC0
TDSPCK
D ( 5 ~ 2 and 0 ) : reserved
SPKP/N
SPK-DRV
( SPKHI ) D(6) = (0) :
D(6) = (1) :
can drive 8W load when
turns on
SPKP/N
SPK-DRV
appears high impedance (10KW) and
will keep a quiescent
SPK-DRV
ALC
open loop
current when
gain is 38dB
turns on( ALC1 , ALC0 ) D(7,1) = (0,0) :
ALC
(ALC1,ALC0) = (0,1) :
= (1,0) : reserved
ALC
open loop gain is 42dB
PRE-PGA
ALCC1 SWC
= (1,1) : external
option (
Output :
,
path “ a” Input :
ALCC2
)
REGISTER 6
ADDRESS BIT
DATA
A2
A1
A0
1
1
0
DATA BIT
POWER_ON
DESCRIPTION
D7
0
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
SWL
SPK-DRV
AD1-PGA
SLEEPA
SLEEP
SPK-
MUTE
GAIN
GAIN
SETTING
SETTING
75
Ver 0.01, December 5, 2000
MX93111
( SLEEPA , SLEEP ) D(7,6) = (0,0) : when the CODEC gets into power down mode, all the blocks of the
VBG
CODEC will be disabled except the
POW BAT
reference and 2
comparators (
,
)
D(7,6) = (0,1) : when the CODEC gets into power down mode, all the blocks of the
CODEC will be disabled
D(7,6) = (1,0) : when the CODEC gets into power down mode, all the blocks of the
POW BAT
CODEC will be disabled except 2 comparators (
,
)
D(7,6) = (1,1) : when the CODEC gets into power down mode, all the analog blocks
of the CODEC will be still functional and can be programmed by
control registers
SWL
SWL
SWL
NOTE 7
(
) D(5) = (1) : path of
is "CLOSE", D(5) = (0) : path of
is "OPEN” ; see
SPK-DRV
SPK-DRV
( SPK-MUTE ) D(4) = 1 : force
mute to -70dB, D(4) = 0 : force
un-mute
NOTE 5
SPK-DRV
AD1-PGA
(
(
GAIN SETTING ) D(3,2) = (0,0) ~ (1,1) : 0dB ~ 8dB; 2dB/step; see
NOTE 2
GAIN SETTING ) D(1,0) = (0,0) ~ (1,1) : 0dB ~ 18dB; see
REGISTER 7
ADDRESS BIT
DATA
A2
A1
A0
1
1
1
DATA BIT
POWER_ON
DESCRIPTIN
D7
D6
D5
D4
0
D3
D2
D1
D0
0
0
0
0
0
0
0
SWN
READ
REGISTER ADDRESS
SWN
SWN
SWN NOTE 7
is "OPEN” ; see
(
) D(4) = (1) : path of
is "CLOSE", D(5) = (0) : path of
( READ ) D(3) = 1 : read data from Register 0 ~ 7, D(3) = 0 : write data to Register 0 ~ 7
( REGISTER ADDRESS ) D(2~0) : When READ = 1, then
a. READ will be cleared automatically;
ISDENX
b. if next DSP
signal active low, the content of REGISTER ADDRESS will be dumped
ISDATAR
out through CODEC
interface;
NOTE 1 PRE-PGA
:
gain step; from -15dB to 22dB
1111
21dB
1110
18dB
1101
15dB
1100
12dB
1011
9dB
1010
1001
6dB
1000
7.5dB
4.5dB
0111
0110
0101
0dB
0100
-3dB
0011
-6dB
0010
-9dB
0001
0000
3.0dB
1.5dB
-12dB
-15dB
76
Ver 0.01, December 5, 2000
MX93111
NOTE 2 AD1-PGA
:
gain step; from 0dB to 18dB
00
01
10
11
0dB
4dB
8dB
18dB
NOTE 3 AD2-PGA
:
gain step; from -6dB to 39dB; 3dB/step
1111
39dB
1110
36dB
1101
33dB
1100
30dB
1011
27dB
1010
24dB
1001
21dB
1000
18dB
0111
15dB
0110
12dB
0101
9dB
0100
6dB
0011
3dB
0010
0dB
0001
-3dB
0000
-6dB
NOTE 4 LIN-DRV
:
gain step; from 0dB to 22.5dB; 1.5dB/step
1111
1110
1101
1100
1011
1010
1001
1000
22.5dB 21dB 19.5dB 18dB 16.5dB 15dB
13.5dB 12dB
0111
0110
9dB
0101
0100
6dB
0011
0010
3dB
0001
0000
0dB
10.5dB
7.5dB
4.5dB
1.5dB
NOTE 5 SPK-DRV
:
gain step; from 0dB to 6dB; 2dB/step
00
01
10
11
0dB
2dB
4dB
6dB
NOTE 6 ATT1
:
(Attenuator 1) gain step; from 0dB to -45dB
1111 1110 1101 1100 1011
1010
1001
1000
-45 dB -39 dB -33 dB -27 dB -24 dB -21 dB -18 dB -15 dB
0111
0110
0101
0100
0011
0010
0001
0000
0 dB
-12 dB
-9 dB -7.5 dB -6 dB -4.5 dB -3 dB -1.5 dB
NOTE 7
SWE SWJ
SWL
: 1.
2.
,
and
can not be turned on at the same time;
SWJ
SWN
and
can not be turned on at the same time;
SWE SWJ SWL
SWK
3. If
,
or
is turned on, then
will be taken as an output port;
4. If SWK is taken as an input port, SWK, SWE, SWJ and SWL cannot be turned on at the
same time;
77
Ver 0.01, December 5, 2000
MX93111
7.1 DC CHARACTERISTICS:
SYMBOL
PARAMETER
Operation temperature
Storage temperature
Operation Frequency
Supply Voltage
CONDITION
MIN
0
TYP
MAX
70
UNIT
0C
-55
150
0C
40.96
MHz
Volt
Volt
Volt
VCC
GND
VIH
4.5
5
0
5.5
Ground
Input high voltage
Input low voltage
Pull high register
Output low current
Output low current
Active current
Schmidt trigger input(IS) 0.7*VCC
Schmidt trigger input(IS)
for IPT[3:0] pins
VIL
0.3*VCC Volt
RH
150 K
ohm
mA
mA
mA
mA
IOL(OA)
IOL(OB)
ICC1
ICC2
@VOL=0.4
@VOL=0.4
@40.96 MHz
@32768 Hz
8
16
Power down current
Absolute Maximum Rating
PARAMETER
MIN
TYP
MAX
UNIT
S
AVDD to AGND
VDD to DGND
-0.3
-0.3
6.0
6.0
V
V
Voltage at any Digital Input or Output
Current at any Digital Input or Output
Operating Ambient Temperature Range
Storage Temperature Range
DGND-0.3
VDD+0.3
8
V
mA
¢
J
J
J
0
70
¢
-65
150
¢
Lead Temperature ( Soldering, 10 seconds )
260
78
Ver 0.01, December 5, 2000
MX93111
Power Supply
PARAMETER
MIN
TYP
MAX
5.5
12
UNIT
S
Power Supply Voltage :
Digital and Analog
4.5
5.0
V
Power Supply Current :
Stand-by :
Digital
10
20
mA
mA
Analog
Operating :
Digital
60
70
mA
mA
Analog ( see Page 92 )
Power-Down :
Digital
2
mA
uA
uA
Analog ( at REG4 bit 6 SLEEP = 0 )
Analog ( at REG4 bit 6 SLEEP = 1 )
120
20
Electrical Characteristics
BOLD
(
characters are guaranteed for AVDD = VDD = 5V ±5%,
¢
J
.
¢ J
*
Temperature = 0 ~ 70
Typical specified at AVDD = VDD = 5V, temperature = 25 . “ ” mark :
guaranteed by design )
Analog Input Ports
PARAMETER
MIN
TYP
MAX
UNIT
S
MIC / LIN / AUX1 :
Input Voltage
3.0
15
Vpp
pF
* Input Capacitance
* Input Impedance
20
KW
79
Ver 0.01, December 5, 2000
MX93111
Analog Output Ports
PARAMETER
MIN
TYP
MAX
UNIT
S
Line Driver :
Gain Range
0
22.5
dB
dB
Step Variation
0.3
6.0
Fully Differential (LOUTP+LOUTN) Full Swing /
with 600W load
Vpp
Single Ended (LOUTP) Full Swing / with 600W
load
3.0
Vpp
* External Load Capacitance
* Output Loading
200
pF
600
W
Speaker Driver :
Fully Differential (SPKP+SPKN) Full Swing / with
8W load
6.0
3.0
Vpp
Single Ended (SPKP) Full Swing / with 8W load
* External Load Capacitance
* Output Loading
Vpp
pF
100
4
8
W
the Quiescent current (when REG5 bit(6) SPKHI =
1)
mA
Analog I/O Ports
PARAMETER
FILT :
MIN
TYP
MAX
UNITS
as Input Port :
* Input Capacitance
* Input Impedance
as Output Port :
5000
1
pF
KW
* External Load Capacitance
* Output Impedance
AUX2 :
5000
1
pF
KW
as Input Port :
* Input Capacitance
* Input Impedance
as Output Port :
15
15
pF
KW
* External Load Capacitance
* Output Impedance
15
15
pF
KW
80
Ver 0.01, December 5, 2000
MX93111
Gain Variation
PARAMETER
MIN
TYP
MAX
UNITS
PRE-PGA :
Gain Range
Step Size
-15
22.5
dB
dB
dB
±1.5, ±3
±0.3
Step Variation
AD-PGA :
DA-PGA :
Gain Range
Step Size
0
0
9
9
dB
dB
dB
+3
Step Variation
±0.3
Gain Range
Step Size
dB
dB
dB
+3
Step Variation
±0.3
Attenuator
PARAMETER
MIN
TYP
MAX
UNIT
S
Attenuator 1 ( Digital Volume ) :
Gain Range
-45
0
dB
dB
dB
dB
Step Size
-6, -3, -1.5
±0.3
Step Variation
* Mute Attenuation
-70
Attenuator 2 ( External Volume ) :
Gain Range
-45
0
dB
the Requirement of External Resistor ( from
SPKP to VR )
10
KW
* Mute Attenuation
-70
dB
Bandgap ( VBG pin )
PARAMETER
MIN
TYP
MAX
UNIT
S
Output Voltage
* Output Current
1.16
1.2
1.24
V
Hi-z
81
Ver 0.01, December 5, 2000
MX93111
Voltage Reference ( VREF pin )
PARAMETER
Output Voltage
* Output Current
MIN
TYP
2.25
450
MAX
UNITS
2.0
2.5
V
uA
Two Comparators ( POW, BAT )
PARAMETER
Input Voltage (VCOMP, VPOW, VBAT)
* Hysteresis
MIN
TYP
MAX
UNITS
V
AVDD
15
mV
* Output Impedance of POWB and BATB pins
10
KW
82
Ver 0.01, December 5, 2000
MX93111
7.2 AC TIMING and CHARACTERISTICS:
7.2.1 RESET TIMING
Tw_reset
Tic
RST\
PROGRAM
PC=0x0000
PC=0x0001
DSP
MASTER
Tm
SYMBOL
PARAMETER
CONDITION
MIN
TYP
24.4
36.6
MAX UNIT
Tm
Tic
Master clock cycle time
Instruction cycle time
Reset low pulse width
@ 40.96 MHz
ns
ns
ns
@ 40.96 MHz 0 wait state
Tw_reset
3*Tm
NOTE : PLL output clock will be reset to a lower frequency (around 24 ~ 25 MHz) during power on reset
or at the starting point when DSP just comes back from power down mode. It takes about 10 ms for FLL
to lock at the target frequency specified in PLLMR(I/O mapped 21) when RST\ pin going high or PWDN
bit being cleared.
7.2.2 EXTERNAL PROGRAM and DATA READ TIMING
Tw_epce\ , Tw_edce\
EPCE\,EDCE\
Tw_ead
EAD[15:0]
ERD\
Td_erd\
Th_read
Ts_read
ED[15:0]
Data in
SYMBOL
Tw_epce\
Tw_edce\
Tw_ead
PARAMETER
CONDITION
see Note1
see Note1
MIN
TYP
MAX UNIT
Program read cycle time
Data read cycle time
Read address cycle time
Tm*(1.5+Wp)
Tm*(1.5+Wd)
ns
ns
Same as Tw_epce\ and
Tw_edce\
ns
Td_erd\
Ts_read
Th_read
Read enable delay time
Data read setup time
Data read hold time
Tm*0.5
ns
ns
ns
see Note2
20 or 40
0
10
15
NOTE1: Wp is PROGWAIT[2:0] in WSTR , Wd is DATAWAIT[2:0] in WSTR
NOTE2: Ts_read : 20 ns when FAST (in EXTCTLR) =1 , 40 ns when FAST (in EXTCTLR) =0
83
Ver 0.01, December 5, 2000
MX93111
7.2.3 EXTERNAL DATA WRITE TIMING
Tw_edce\
Tw_ead
EDCE\
EAD[15:0]
Twr
Tdh
EWR\
Tas
Tdw
ED[15:0]
Data out
SYMBOL
Tas
PARAMETER
Address set-up time
Write recovery time
Data set-up time
Data hold time
CONDITION
MIN
TYP
Tm*0.5
MAX UNIT
ns
ns
ns
ns
Twr
0
10
0
Tdw
Tdh
7.2.4 HOST INTERFACE TIMING
HRD\
Tdh_hostr
HWR\
Taa_hostr
Tdh_hostw
HDB[7:0]
Tds_hostw
SYMBOL
Taa_hostr
Tdh_hostr
Tds_hostw
Tdh_hostw
PARAMETER
CONDITION
MIN
TYP
MAX UNIT
Host read access time
50
ns
ns
ns
ns
Host read data hold time
Data setup time at host write
Data hold time at host write
5
40
10
84
Ver 0.01, December 5, 2000
MX93111
7.2.5 DRAM CAS BEFORE RAS REFRESH TIMING
Trp
Tras
Trpc
Tcsr
Trp
RAS\
CAS\
Tchr
Tcp
SYMBOL
Trp
PARAMETER
CONDITION
MIN
61
TYP
MAX UNIT
RAS\ precharge time
RAS\ to CAS\ precharge time
CAS\ setup time
@40.96 MHz
ns
ns
ns
ns
ns
ns
us
Trpc
“
48.8
Tcsr
“
12.2
85.4
Tras
RAS\ pulse width
“
Tcp
CAS\ precharge time
CAS\ hold time
“
24.4
Tchr
“
48.8
T_refresh
Refresh cycle time
see NOTE
15.258
NOTE : DSP will generate CAS\ before RAS\ self refresh every 15.258 us( 32768Hzx2) .
85
Ver 0.01, December 5, 2000
MX93111
7.2.6 DRAM READ/WRITE TIMING
RAS\
Trp
Tcp
Trcd
CAS\
Tcas
Tasc
Tasr
Trah
Tcah
Column Address
Column Address
Column Address
EAD[15:0]
DRD\
Row Address
Trcs
Ts_dramr Th_dramr
Data in
ED[15:0]
READ
CYCLE
Data in
Data in
Twcs
DWR\
Ts_dramw
Th_dramw
ED[15:0]
WRITE
CYCLE
Data Out
Data Out
Data Out
SYMBOL
Trp
PARAMETER
CONDITION
MIN
TYP
MAX UNIT
RAS\ precharge time
CAS\ precharge time
61
ns
ns
Tcp
24.4
Tcas
CAS\ low pulse width
see Note1
Tm*(2+W)/2
48.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Trcd
RAS\ to CAS\ delay time
Row address set-up time
Row address hold time
Tasr
0
Trah
24.4
Tasc
Column address set-up time
Column address hold time
Read command set-up time
DRAM read data set-up time
DRAM read data hold time
Write command set-up time
DRAM write data set-up time
DRAM write data hold time
0
Tcah
24.4
Trcs
0
Ts_dramr
Th_dramr
Twcs
see Note2
20 or 40
0
0
Ts_dramw
Th_dramw
0
36.6
NOTE1: W is DRAMWAIT[2:0] in WSTR
NOTE2: Ts_dramr : 20 ns when FAST (in EXTCTLR) =1
40 ns when FAST (in EXTCTLR) = 0
86
Ver 0.01, December 5, 2000
MX93111
7.2.7 CODEC TIMING DESCRIPTION
TIMING
Tupen1
Tupen2
Tups1
DESCRIPTION
MIN TYP MAX UNIT
from Vsclkh1 to Venl
from Vsclkh1 to Venh
40
40
40
IFS
IFS
IFS
ns
ns
ns
setting time for DSP transmitting ISDATAW from Vupenl to DSP
ISDATAW(n) ready
( @ where Tupen1+Tups1 must < IFS )
Tups2
Tuph
setting time for DSP transmitting ISDATAW from Vsclkh1(n+1) to DSP 40
IFS
ns
SDATA(n+1) ready
holding time for DSP transmitting ISDATAW from Vsclkh1(n+1) to DSP 40
Tups ns
2
ISDATAW(n)
ending
Tcdrd
Tcds1
Tcds2
Tcdh
from Vsclkh1(n+1) to CODEC reading ISDATAW(n)
20
20
ns
ns
ns
ns
setting time for CODEC transmitting ISDATAR from Vcdi2o to
ISDATAR(n) ready
setting time for CODEC transmitting ISDATAR from Vsclkh1(n+2) to
ISDATAR(n+1) ready
20
holding time for CODEC transmitting ISDATAR from ISDATAR(n)
ready to Vsclkh1(n+2)
IFS
Tcdo2i
Tuprd
from Venh to CODEC changing its ISDATAR interface to input port
20
ns
ns
ns
from Vsclkh1(n+1) to DSP reading ISDATAR(n)
40
40
IFS
IFS
Tupi2o
from Vsclkh1 to DSP changing its ISDATAR interface to output port
87
Ver 0.01, December 5, 2000
MX93111
TIMING DIAGRAM
Control Registers R/W Timing Diagram
CODEC READ
Vsclkh1
n
n+1
n+2
IFS
1
1
1
1
6 7
9
5
8
Venl
2
3
0
1
Tupen2
Tupen1
Venh
ISDENX
Tuph
Tups1
Tuph
Tups2
DSP ISDATW
interface
D2
D1
D0
A2
A1
A0
D7
D6
D4
D3
D5
n
n+1
Tcdrd
CODEC read ISDATAW
CODEC ISDATAW
interface
CODEC WRITE
Vsclkh1
n
n+1
n+2
IFS
1
1
3
1
1
1
3 4
2
1
0
Tupen1
Tupen2
ISDENX
Tcds2
Tcds1
Tcdh
CODEC
ISDATAR
D2
D1
D0
A2
A1
A0
D7
D6
D5
D4
D3
interface
n
n+1
Tuprd
DSP read ISDATAR
DSP ISDATAR
88
Ver 0.01, December 5, 2000
MX93111
The Timing Diagram of CODEC Function
(SLEEPA,SLEEP) = (0,0) or (1,1)
tF
tH
t I
tA
tB
tG
tJ
tK
tC tD
tE
VDD
AVDD
~ 1.2V
VBG
ICPDX
VAG
CP
Register
R/W
A/D and D/A
Analog Paths
Analog Paths
(SLEEPA,SLEEP)
= (0,0)
(SLEEPA,SLEEP)
= (1,1)
POW, BAT
2 OPs
@ Analog Paths : Analog I/O, Switches, PGA and Attenuator
: Stable
@
(SLEEPA,SLEEP) = (0,1) or (1,0)
tF
tH
t I
tA
tB
tG
tJ
tK
tE
tD
tC
VDD
AVDD
~ 3.4V
~ 1.2V
VBG
ICPDX
VAG
CP
Register
R/W
A/D and D/A
Analog Paths
POW, BAT
2 OPs
(SLEEPA,SLEEP)
= (0,1)
POW, BAT
2 OPs
(SLEEPA,SLEEP)
= (1,0)
@ Analog Paths : Analog I/O, Switches, PGA and Attenuator
: Stable
@
89
Ver 0.01, December 5, 2000
MX93111
The Timing Description of CODEC Function
TIMING
DESCRIPTION
MIN
TYP
MAX
UNIT
¡
started
keeps
Ü
3.0VDC
VDD AVDD
/
tA
tC
ICPDX
tH ICPDX
tC
Þ
tH
tJ
Þ
ICPDX
ICPDX
Power-down started (
keeps low )
Power-down ended (
keeps high)
tH
tA
t J ICPDX
keeps low
tB
VBG
VBG
( where
Þ
the charge time of
140
50
190
110
2
290
160
2.5
0.7
15
ms
us
bypass cap. = 0.1uF )
tD
tE
Þ
the lock-in time of PLL ( C1=100pF,
C2=6pF, R1=68KW )
tF
tJ
tH
tG
tK
tI
VAG
VAG
Þ
Þ
Þ
the charge time of
( where
1.5
0.3
6
ms
ms
ms
bypass cap. = 0.1uF )
the discharge time of
bypass cap. = 0.1uF )
VAG
VAG
( where
0.5
10
th
ti
VBG
Þ
the delay time of
disable ( where
VBG
bypass cap. = 0.1uF )
VBG
@ when change
i. from 0.1uF to 1uF : (
ii. from 0.1uF to 0.01uF : (
bypass capacitor (C15) :
¡
Ü
10 * (
tA
tB
)’
tA
tB
tA
Þ
Þ
)
¡
Ü
1/10 * (
tA
tB
tB
Þ )
Þ
)’
90
Ver 0.01, December 5, 2000
MX93111
A/D Path Characteristics
( 0dBFS : reference to Fin = 1.02KHz and A/D Input is Full Swing )
PARAMETER
MIN
76
TYP
77
MAX
78
UNITS
dB
Dynamic Range ( at -51dBFS )
THD+N ( at Vin = -6dBFS )
-58
-62
76
-64
dB
Interchannel Isolation of LIN/MIC/AUX1 ( at Vin =
dBFS
dBFS
Vpp
0dBFS )
-0.3
0.3
Gain Variation ( at Vin = -6dBFS )
3.0
Max. Overload Level
Frequency Response ( Measure Respone from
60Hz to
-23
-7
-26
-8
dB
dB
dB
dB
dB
dB
dB
dB
4000Hz, see FIG. 3 ) :
60Hz
-3
-4
150Hz
-0.8
+0.8
200Hz
-1.6
-4.5
-10
-45
300 ~ 3200Hz
3400Hz
3600Hz
3800Hz
4000Hz and Up
D/A Path Characteristics
( 0dBFS : reference to Fout = 1.02KHz and D/A Output is Full Swing )
PARAMETER
MIN
TYP
77
MAX
UNITS
dB
Dynamic Range ( at -51dBFS )
76
78
THD+N ( at Vin = -6dBFS )
46
dB
Gain Variation ( at Vin = -6dBFS )
± 0.1
dBFS
Out of Band Energy ( with 1.02KHz Image ) :
3.8KHz ~ 20KHz
-50
3.0
dBFS
Vpp
Output Level ( at AUX2 )
Frequency Response ( Measure Respone from
60Hz to
3800Hz, see FIG. 4 ) :
60Hz ~ 300Hz
300Hz ~ 2800Hz
3000Hz
-0.1
dB
dB
dB
dB
dB
dB
dB
- 0.6
+ 0.1
-1.1
-2.1
-3.7
-6.3
-10
3200Hz
3400Hz
3600Hz
3800Hz
Noise
( Test Condition : 1. A/D 1 or 2 Input Signal is 1.02KHz/0dB (Full Swing)
2. D/A 1 or 2 Output Signal is 1.02KHz/0dB (Full Swing )
91
Ver 0.01, December 5, 2000
MX93111
PARAMETER
Idle-Channel Noise
MIN
TYP
MAX
UNITS
( Input Grounded and Measurement Bandwidth
from 0 to 4000Hz ) :
A/D Path
-76
-83
dB
dB
D/A Path
VDD Power Supply Rejection
(A/D & D/A Input Grounded and VDD =
5.0VDC+100mVrms) :
A/D Channel : (Test Condition 1)
Fin = 0 ~ 4KHz
-54
-80
-82
dB
dB
dB
Fin = 4 ~ 25KHz
Fin = 25 ~ 50KHz
D/A Channel : (Test Condition 2)
Fin = 0 ~ 4KHz
-65
-80
-95
dB
dB
dB
Fin = 4 ~ 25KHz
Fin = 25 ~ 50KHz
AVDD Power Supply Rejection
(A/D & D/A Input Grounded and AVDD =
5.0VDC+100mVrms) :
A/D Channel : (Test Condition 1)
Fin = 0 ~ 4KHz
-72
-85
-87
dB
dB
dB
Fin = 4 ~ 25KHz
Fin = 25 ~ 50KHz
D/A Channel : (Test Condition 2)
Fin = 0 ~ 4KHz
-41
-53
-60
dB
dB
dB
Fin = 4 ~ 25KHz
Fin = 25 ~ 50KHz
Crosstalk :
A/D 1 to A/D 2 (Test Condition 1)
A/D 1 to D/A 1 (Test Condition 1)
A/D 1 to D/A 2 (Test Condition 1)
A/D 2 to A/D 1 (Test Condition 1)
A/D 2 to D/A 1 (Test Condition 1)
A/D 2 to D/A 2 (Test Condition 1)
D/A 1 to A/D 1 (Test Condition 2)
D/A 1 to A/D 2 (Test Condition 2)
D/A 1 to D/A 2 (Test Condition 2)
D/A 2 to A/D 1 (Test Condition 2)
D/A 2 to A/D 2 (Test Condition 2)
D/A 2 to D/A 1 (Test Condition 2)
-93
-92
-79
-98
-86
-86
-100
-94
-86
-99
-94
-86
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
92
Ver 0.01, December 5, 2000
MX93111
FIG. 1
MX93111 A/D1 Linear Format SNDR
60
55
50
45
40
35
30
25
20
15
10
SNDR dB
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Vin dB
FIG. 2
MX93111 D/A1 Linaer Format SNDR
80
70
60
50
40
30
20
10
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
93
Ver 0.01, December 5, 2000
MX93111
FIG. 3
MX93111 A/D1 Frequence Response
10
0
-10
-20
-30
-40
-50
-60
-70
dB
0
500
1000
1500
2000
freq.
2500
3000
3500
4000
FIG. 4
MX93111 D/A1 Frequence Response
2
0
-2
-4
dB
-6
-8
-10
-12
0
500
1000
1500
2000
2500
3000
3500
4000
freq. Hz
94
Ver 0.01, December 5, 2000
MX93111
FIG. 5
MX93111 ALC
3000
2500
2000
1500
1000
500
Vout
Vpp
0
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Vin (dB)
FIG. 6
16
14
12
10
8
GAIN
(dB)
6
4
2
0
-2
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
95
Ver 0.01, December 5, 2000
MX93111
FIG. 7
MX93111 ALC
60
55
50
45
40
35
30
25
20
15
10
SNDR
(dB)
-50
-45
-40
-35
-30
-25
-20
-15
-10
-5
0
Vin (dB)
96
Ver 0.01, December 5, 2000
MX93111
8.0 ORDERING INFORMATION
PART NO
MX93111
PACKAGE TYPE
PQFP
MX 93 111 F C
O
COMMERCIAL 0 ~ 70 C
PACKAGE TYPE F : PQFP
PRODUCT NUMBER
FAMILY PREFIX
MXIC COMPANY PREFIX
8.1 PACKAGE INFORMATION for 128 PIN PQFP
97
Ver 0.01, December 5, 2000
MX93111
MACRONIX INTERNATIONAL CO., LTD.
HEADQUARTERS:
No. 3, Creation Road III, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C.
TEL:+886-3-578-8888
FAX:+886-3-578-8887
TAIPEI OFFICE:
12F, No. 4, Min-Chuan E.Rd., Sec 3, Taipei, Taiwan, R.O.C.
TEL:+886-2-2509-3300
FAX:+886-2-2509-2200
EUROPE OFFICE:
Grote Winkellaan 95, Bus 1 1853 Strombeek, Belgium
TEL:+32-2-267-7050
FAX:+32-2-267-9700
SINGAPORE OFFICE:
5 Jalan Masjid Kembangan Court #01-12 Singapore 418924
TEL:+65-747-2309
FAX:+65-748-4090
MACRONIX AMERICA, INC.
1338 Ridder Park Drive, San Jose, CA95131 U.S.A.
TEL:+1-408-453-8088
FAX:+1-408-453-8488
JAPAN OFFICE:
NFK Kawasaki Building, 8F, 1-2 Higashida-cho, Kawasaki-ku
Kawasaki-shi, Kawasaki-ken 210, Japan
TEL:+81-44-246-9100
FAX:+81-44-246-9105
98
Ver 0.01, December 5, 2000
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