MX97103 [Macronix]
ISDN S/T-PCI TRANSCEIVER; ISDN S / T - PCI收发器
| 型号： | MX97103 |
| 厂家： | 
MACRONIX INTERNATIONAL |
| 描述： | ISDN S/T-PCI TRANSCEIVER |
| 文件： | 总13页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
MX97103
ISDN S/T-PCI TRANSCEIVER
FEATURE
• Single chip solution for ISDN PC card with PCI inter-
face
• Supports full duplex 2B+D ISDN S/T transceiver ac-
cording to ITU I.430
• Each B channel has 2x64 byte FIFO for each direction
• D channel has 2x32 byte FIFO for each direction
• EEPROM interface for loading vendor-specific data
• One programmable LED
• Integrate S-interface, D & B channel protocol control-
lers, and PCI controller
• Comply to ACPI Rev 1.0
• 0.5u CMOS
• 32-bit PCI bus interface
• 100-pin PQFP package
GENERAL DESCRIPTION
MX97103 is a single chip solution for ISDN-S connec-
tion on PCI bus. It integrates S-transceiver, D and B
channel protocol controllers, and PCI interface.
The layer 1 block comprises of PDLL, DAC, RT and MFC
functions. DPLL's function is to establish S/T frame syn-
chronization. DAC resolves the contention issue for
differnet TE accessing D channel at the same time. RT
deals with the receiving S/T data extraction and put out
the transmitted data at the corrent time slot. MFC is the
multiframing S and Q channel control block.
It can be divided into the following major functional blocks
:analog front end, layer 1 function, GCI interface. LAPD
controller, B channel HDLC controllers, EEPROM inter-
face and PCI interface. The important function of each
major block will be described below.
GCI is the digital bus for the IC. It can accomodate 8
GCI-compatible devices. This block converts the frame
between GCI and S/T interface.
According to ITU 1.430 spec. the S/T interface is a 4-
wire interface. Among them, 2 wires are used for trans-
mitting, and the other two are for receiving. The wiring
configurations include short passive bus, extended pas-
sive bus and point-to-point connection. For short pas-
sive bus, the operation distance is from 100m to 200m,
and the TEs(max 8)can be connected at random points
along the full length of the cable. For extended passive
bus, TEs connect to the cable at the far end from the NT.
The total length would be at least 500m and a differen-
tial distance between TE connection points is of 25 to
50m. For point-to-point connection, the cable length can
be 1km.
LAPD block relieves the microprocessor of the duty to
generate HDLC frame on the D channel. It can gener-
ate flag, CRC, address and control field automatically.
And it can generate S-frame for HDLC protocol. It con-
tains 2 FIFO of 2x32 byte each to facilitate the D packet
transmission and reception.
Two B channel HDLC controllers can handle tasks like
flag and CRC generation, zero insertion and deletion.
For each direction a 2x64 byte FIFO is provided to buffer
the data.
The analog front end deals with the signals transmitted
to and received from the wiring cable. It accepts the
digital data from layer 1 block and converts them into
appropriate signals to be sent out to the wire, and it also
receive the attenuated and distorted signal from the wire
and recover them to be processed by layer 1 block.
The EEPROM interface is used to load specific vendor
information after system hardware reset. Vendor ID and
device ID can be load to distinguish different products.
If EEPROM is not used, default values will be set.
The PCI interface enables the chip attached to PCI bus
directly without any glue logic. The bus speed can be
from 25MHz to 33MHz.
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MX97103
PIN CONFIGURATION
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
AD14
VSS
VDD
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AD26
AD17
VSS
AD28
AD29
VSS
AD30
AD31
VDD
CLK
VSS
RST#
INTA#
AVDD(C)
SX2
AD13
AD12
VDD
AD11
AD10
VSS
AD9
AD8
VSS
CBE0#
AD7
AD6
VSS
AD5
AD4
VDD
AD3
AD2
MX97103
SX1
AVDDX
AVDD(P)
AVSS(P+X)
BLOCK DIAGRAM
GCI interface
DU DD
S/T Interface
LAP-D&B-HDLC
B-channel
Transmitter
Multiframe
control
Activation/
Deactivation
GCI
Switching
FIFOS
Receiver
DPLL
PCI
Interface
EEPROM
Interface
7.68MHZ
OSC
DCL FSC1
PCI bus
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MX97103
PIN DESCRIPTION
PAD#
PIN NAME
AD[31:0]
TYPE
I/O
DESCRIPTION
42, 43, 45, 46, 48, 49,
51, 52, 56, 57, 59, 60,
62, 63, 65, 66, 80, 81,
83, 84, 86, 87, 89, 90,
93, 94, 96, 97, 99, 100,
2, 3
PCI address/data bus.
53, 68, 78, 92
CBE[3:0]#
FRAME#
I
I
PCI command/byte enable, command during address
phase, byte enable during data phase.
PCI FRAME# signal, asserted to indicate the start of a bus
transaction.
69
71
70
TRDY#
IRDY#
O
I
PCI Target ready, asserted by target agent.
PCI master ready, data transferred on the rising edge of
CLK when IRDY# and TRDY# both asserted.
PCI slave device select, specific for configuration cycle.
PCI Initialization device select, specific for configuration
cycle.
72
54
DEVSEL#
IDSEL
O
I
40
38
37
75
77
74
23
22
24
19
20
18
17
34
35
29
30
27
26
9
CLK
I
PCI clock, 33MHz
RST#
INTA#
PERR#
PAR
I
PCI bus reset
O/D
I/O
I/O
O
PCI bus interrupt request
PCI bus data error
PCI bus parity bit, even parity for AD and CBE
PCI stop signal
STOP#
BCL
O
GCI bit clock, 768KHz
SDS1
SDS2
FSC
O
GCI serial data strobe 1, programmable strobe signal
GCI serial data strobe 2, programmable strobe signal
GCI frame sync
O
O(I)
O(I)
I/O
I/O
O
DCL
GCI data clock, 1.536MHz
DU
GCI data upward to ST interface
GCI data downward from ST interface
S-bus transmitter output(positive)
S-bus transmitter output(negative)
S-bus receiver input
DD
SX1
SX2
O
SR2
I
SR1
I
S-bus receiver reference
XTAL1
XTAL2
LED2
LED1
I
Connection for 7.68MHz crystal/oscillator input
Crystal output
O
O
Auxillisry LED output 0
15
O
Auxilliary LED output 1
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MX97103
PAD#
PIN NAME
EECS
TYPE
DESCRIPTION
8
O
O
O
I
EEPROM chip select
EEPROM interface clock
Output data to EEPROM
Input data from EEPROM
test pins
7
EECK
6
EEDI
5
EEDO
TEST[4:1]
AVDD
10, 12, 13, 14
36, 33, 32
31, 28
Analog power
AVSS
Analog ground
4, 16, 41, 50, 61,
76, 85, 98
1, 11, 21, 25, 39,
44, 47, 55, 58, 64,
67, 73, 79, 82, 88,
91, 95
VDD
Digital power
VSS
Digital ground
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage(VDD)
4.75V to 5.25V
-0.5V to VDD+0.5V
-0.5V to VDD+0.5V
-55°C to 150°C
500mW
DC Input Voltage(Vin)
DC Output Voltage(Vout)
Storage Temperature Range(Tstg)
Power Dissipation(PD)
Lead Temp.(TL)(Soldering, 10sec)
ESD Rating(Rzap=1.5k, Czap=100pf)
Clamp Diode Current
260°C
2000V
±20mA
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MX97103
DC CHARACTERISTICS
PCI BUS D.C SPECS
PCI System signals
CLK, RST#
PCI Shared signals
AD[31:0](t/s), CBE[3:0]#(t/s), FRAME#(s/t/s), TRDY#(s/t/s), IDSEL(in), IRDY#(s/t/s), STOP#(s/t/s),
DEVSEL#(s/t/s), PAR(t/s), PERR#(s/t/s), INTA#(o/d), SERR#(s/t/s)
Temperature from 0 to 70°C;VDD=5V±5%, VSS=0V, AVSS=0V
SYMBOL
VIL
PARAMETER
L-input voltage
H-input voltage
L-output voltage
CONDITIONS
MIN.VALUE
2.0V
MAX.VALUE
0.8V
NOTES
1
VIH
5.4V
VOL
IOL1=3mA
IOL2=6mA
IOH=-2mA
VIN=0.5V
VIN=2.7V
at 1MHz
0.45V
VOH
IIL
H-output voltage
2.4V
L-input current
-70uA
70uA
10pF
17pF
50pF
IIH
H-input current
CI/O
CCLK
CL
Input/output capacitance
CLK input capacitance
Load capacitance
at 1MHz
NOTE:
1. IOL2 applies to signals with external pull-ups: FRAME#, TRDY#, IRDY#, STOP#, DEVSEL#
GCI BUS & EEPROM INTERFACE D.C. SPECS
GCI signals:
BCL, DCL, DD, DU, FSC.SDS1, SDS2
EEPROM signals:
EECS, EECK, EEDI, EEDO
SYMBOL
VIL
PARAMETER
L-input voltage
H-input voltage
L-output voltage
CONDITIONS
MIN.VALUE
2.0V
MAX.VALUE
0.8V
NOTES
1
VIH
5.4V
VOL
IOL1=2mA
IOL2=7mA
IOH=-400uA
0.45V
VOH
H-output voltage
2.4V
NOTE:
1. IOL2 is for DD only.
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MX97103
S-BUS D.C. SPECS
SX1, SX2, SR1, SR2
SYMBOL
VX
PARAMETER
CONDITIONS
RL=50 ohm
MIN.VALUE
2.03V
MAX.VALUE
2.31V
NOTES
Absolute value of output
pulse amplitude
(VSX2-VSX1)
SX1, SX2
RL=400 ohm
2.10V
2.39V
IX
Transmitter output
current
RL=5.6 ohm
7.5mA
13.4mA
RX
Transmitter output
impedance
(1) Inactive or during (1)10K ohm
binary 1, (2) during
binary 0 RL=50 ohm
IO<5uA
(2) 0 ohm
VSR1
VTR
Receive output voltage
Receiver threshold
2.35V
2.6V
SR1, SR2
SR1, SR2
Dependent on peak
level
225mV
375mV
voltage (VSR2-VSR1)
NOTE:
1. Due to the transformer, the load resistance seen by the circuit is four times RL.
CRYSTAL SPEC
27pF
External
oscillator
signal
XTAL1
XTAL2
XTAL1
XTAL2
CL
CL
NC
27pF
Crystal mode
Driving from external source
PARAMETER
Frequency
SYMBOL
f
LIMIT VALUES
7.680
UNIT
MHz
ppm
pF
Frequency calibration tolerance
Load capacitance
max. 100
max. 35
CL
Oscillator mode
fundamental
XTAL1 CLOCK CHARACTERISTICS
PARAMETER
LIMIT VALUES
MIN.
1:2
MAX.
2:1
Duty cycle
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MX97103
AC CHARACTERISTICS
Temperature from 0 to 70°C, VDD=5V±5%
2.4
2.0
0.8
Inputs are driven to 2.4V for a logical "1" and to 0.4V for
a logical "0". Timing meansurements are made at 2.0V
for a logical "1" and 0.8v for a logical "0". The AC-testing
output is loaded with a 150pF capacitor.
2.0
0.8
DUT
TEST POINTS
0.45
C=150pF
Input/Output waveform for AC tests
TIMING WAVEFORM
SERIAL INTERFACETIMING
DCL
tBCD
BCL
tFSD
FSC
SDS1/2
tSSD
tIOD
DD/DU(O)
tIIS
tIIH
DD/DU(I)
GCI TIMING
PARAMETER
SYMBOL
tIOD
MIN.
MAX.
GCI output data delay
GCI input data setup
GCI input data hold
FSC strobe delay
SDS strobe delay
Bit clock delay
20ns
20ns
20ns
-20ns
100ns
tIIS
tIIH
tFSD
tSDD
tBCD
20ns
120ns
20ns
-20ns
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MX97103
PCI SHARED SIGNALS A.C.TIMING WAVEFORM
1.5V
CLK
t2
t1
OUTPUT
INPUT
1.5V
Valid
Valid
t4
t3
t5
t6
PARAMETER
SYMBOL
MIN.
MAX.
11ns
NOTES
CLK signal valid delay
t1
t2
t3
t4
t5
t6
CL=50pF
CLK to signal invalid delay
2ns
2ns
Hi-Z to active delay from CLK
Active to Hi-Z delay from CLK
Input signal valid setup time before CLK
Input signal hold time from CLK
28ns
7ns
0ns
PCI SIDEBAND SIGNALS A.C.TIMING WAVEFORM
1.5V
CLK
t2
t1
OUTPUT
INPUT
1.5V
Valid
Valid
t4
t3
t5
t6
PARAMETER
SYMBOL
MIN.
MAX.
12ns
NOTES
CLK to sideband signal valid delay
CLK to signal invalid delay
t1
t2
t3
t4
t5
t6
CL=50pF
2ns
2ns
Hi-Z to active delay from CLK
Active to Hi-Z delay from CLK
28ns
Sideband signal valid setup time before CLK
Input signal hold time from CLK
12ns
0ns
P/N:PM0564
REV. 1.0, FEB. 23, 1999
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MX97103
APPLICATION
ISDN ACCESS ARCHITECTURE
ISDN User Area
ISDN
central office
TE(1)
U
T
S
TE(8)
LT-S
LT-S
LT-T
NT1
LT
telephone
line
TE(1)
TE(1)
LT-S
PBX(NT2)
NT1
LT
TE(8)
Direct Subscriber Access
PCI bus
where - TE is an ISDN terminal
= MX97103
- LT-S is a subscriber line termination
- LT-T is a trunk line termination
- LT is a trunk line termination in the central office
GCI CONNECTION
GCI
EEPROM
Data
Encryption
Speech
Processing
DSP-COFI
MX97103
S interface
PCI BUS
P/N:PM0564
REV. 1.0, FEB. 23, 1999
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MX97103
VDD
C3
C4
OSC
18pf
7.68MHz
18pf
R7
3.3K
VDD
10uF
XTAL1
DO
DI
SK
CS
XTAL2
EEDO
EEDI
EECK
EECS
EEPROM
(6 bit)
VDD
DCL
FSC
DD
DCLK
FS
DR
CODEC
DU
DX
VSS
R10
3.3K
R9
3.3K
AVSS
VDD
D2
D1
D5
D3
+5V
R1
33
2:1
MX97103
SX1
D4
D6
D7
R3
33
Over-
voltage
Pro-
SX2
SR1
DC point
RJ45
R5
8.2K
tection
circuits
2:1
R4
1.8K
47pF
D9
D8
R6
1.8K
R8
8.2K
D11
D10
INTAN
RSTN
SR2
FRAMEN
+5V
DC point
47pF
D12
D13
D14
CLK STOPN PAR PERRN TARDYN IDSELN IRDYN IDSEL CBEN[3:0] AD[31:0]
PCI BUS
P/N:PM0564
REV. 1.0, FEB. 23, 1999
10
MX97103
TEST CIRCUIT
To test digital function separately, DTMC[TMODE] can be set to enable the stimulus inputs from test1~4 pins.
PIN
DTMC SP2 SP1 SP0 I/O SIGNAL DESCRIPTION
TEST1
TEST2
TEST3
TEST4
TEST1
TEST2
TEST3
TEST4
TEST1
TEST2
TEST3
TEST4
TEST1
TEST2
TEST3
TEST4
TEST1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
I
XRAMI1 test RAMI1 input signal
XRAMI2 test RAMI2 input signal
I
I
XZC
test ZC input signal
test I0N input signal
I
XI0N
O
O
O
O
O
O
O
O
O
O
O
O
O
ARAMI1 RAMI1 from analog module
ARAMI2 RAMI2 from analog module
AZC
ZC from analog module
SAMP
S[0]
SAMP from analog module
activation/deactivation state code
S[1]
S[2]
S[3]
MBAS1
MBAS2
CLS
TIC bus arbitration state code
D channel collision
I0N from analog module
layer sync.
AI0N
RFN
For normal operation, DTMC should be set to 0. Test1~4 pins can be programmed to output internal signals for
monitoring purpose.
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REV. 1.0, FEB. 23, 1999
11
MX97103
PACKAGE INFORMATION
100-PIN PLASTIC QUAD FLAT PACKAGE (PQFP)
A
B
ITEM
A
MILLIMETERS
24.80±.40
20.00±.13
14.00±.13
18.80±.40
12.35 [REF]
.83 [REF]
.58 [REF]
.30 [Typ.]
INCHES
.967±.016
.787±.005
.551±.005
.740±.016
.486 [REF]
.033 [REF]
.023 [REF]
.012 [Typ.]
.026 [Typ.]
.094 [Typ.]
.047 [Typ.]
.006 [Typ.]
.004 max.
.018±.006
.004 min.
.103 max.
B
80
81
51
50
C
D
E
F
E
C
D
G
H
I
.65 [Typ.]
J
2.40 [Typ.]
1.20 [Typ.]
.15 [Typ.]
31
30
100
1
P
F
K
O
L
M
N
O
P
.10 max.
G
H
I
2.75±.15
J
.10 min.
N
3.30 max.
L
M
NOTE: Each lead centerline is located within .25 mm[.01
inch] of its true position [TP] at maximum material con-
dition.
K
ORDERING INFORMATION
PART NO.
PACKAGE
MX97103FC
100-PIN PQFP
P/N:PM0564
REV. 1.0, FEB. 23, 1999
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MX97103
MACRONIX INTERNATIONAL CO., LTD.
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TEL:+886-3-578-6688
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TEL:+1-847-963-1900
FAX:+1-847-963-1909
http : //www.macronix.com
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
13
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