NM22F1KSMAXBH-3TNA [NANYA]
MCP Specification;
| 型号： | NM22F1KSMAXBH-3TNA |
| 厂家： | 
Nanya Technology Corporation. |
| 描述： | MCP Specification |
| 文件： | 总68页 (文件大小：7579K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
MCP Specification
2Gb SLC NAND Flash (X8) + 1Gb LPDDR (X32)
2Gb SLC NAND Flash (X16) + 1Gb LPDDR (X16)
2Gb SLC NAND Flash (X8) + 1Gb LPDDR (X16)
Preliminary Version 1.3
Nanya Technology Corporation
Version 1.3
1
Nanya Technology Corp.
NTC has the rights to change any specifications or product without notification.
06/2016
All Rights Reserved. ©
2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Ordering Information
MCP
NAND
DRAM
Density Program Erase
Density
(Org.)
Part Number
Type
Type
Speed CL
(Org.)
Time
Time
2Gb
(256Mb X 8)
1Gb
(32Mb X 32)
NM2281KSMAXBH-3T SLC
NM22F1NSMAXBH-3T SLC
NM2281NSMAXBH-3T SLC
300μs
3.5ms LPDDR
400
400
400
3
3
3
2Gb
(128Mb X16)
1Gb
(64Mb X 16)
300μs
300μs
3.5ms LPDDR
3.5ms LPDDR
2Gb
(256Mb X 8)
1Gb
(64Mb X 16)
Version 1.3
06/2016
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Nanya Technology Corp.
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
NANYA MCP Part Numbering Guide
NM
2
28
1K
S
M
AX
B
H
3
T
Grade
NA = Commercial Grade
NANYA
MCP
DRAM Speed
T = 400Mbps @ CL=3
Product Family
2 =SLC NAND + LPDDR1
NAND Speed
3 = 300μs
NAND Organization
(Density, Config)
2F= 2Gb x16
Package
H = 130ball BGA
28= 2Gb x8
Device Version
B = 2nd version
DRAM Organization
(Density, Config)
1K= 1Gb x32
Reserve Code
AX=Default
1N= 1Gb x16
NAND Voltage
S= 1.8V
DRAM Interface (VDD/VDDQ)
M = LVCMOS (1.8V, 1.8V)
Version 1.3
06/2016
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Nanya Technology Corp.
All Rights Reserved. ©
2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Features
MCP
Separate SLC NAND and LPDDR RAM interfaces
Lead-free (RoHS compliant) and Halogen-free Package : 130-ball VFBGA (9.00mm x 8.00mm, pitch 0.65mm)
Operating temperature range: –25°C to +85°C
2Gb X8/X16 SLC NAND
Voltage Supply: 1.70V ~ 1.95V
Organization
1Gb X16/X32 LPDDR
Speed, Addressing and Retention Specification
Organization
64Mb X 16
32Mb X 32
- X8 Memory Cell Array: 2176 x 128K x 8
- X8 Data Register: 2176 x 8
Speed Grade
Number of Banks
Bank Address
Row
400-3-3-3
4
400-3-3-3
4
- X8 Page Program: 2176 Bytes
- X8 Block Erase: (128K + 8K) Bytes
- X16 Memory Cell Array: 1088 x 128K x 16
- X16 Data Register: 1088 x 16
- X16 Page Program:1088 Words
- X16 Block Erase: (64K + 4K) Words
Modes
BA[1:0]
A[13:0]
A[9:0]
7.8µs
72ns
BA[1:0]
A[12:0]
A[9:0]
7.8µs
72ns
Column
tREFI
tRFC
JEDEC LPDDR Compliant
- Low Power Consumption
Read, Reset, Auto Page Program, Auto Block Erase,
Status Read, Page Copy, Multi Page Program,
Multi Block Erase, Multi Page Copy, Multi Page Read
Mode control
- Double-data rate on DQs, DQS and DM
- 2n Prefetch Architecture
LVCMOS interface and Power Supply
- VDD/VDDQ= 1.70 to 1.95V
- Serial input/output
- Command control
Signal Integrity
- Configurable DS for system compatibility
Data Integrity
Number of valid blocks
- Min 2008 blocks
- Max 2048 blocks
Access time
- DRAM built-in Temperature Sensor for Temperature
Compensated Self Refresh (TCSR)
- Auto Refresh, Self Refresh and PASR Modes
Power Saving Modes
- Cell array to register: 25μs max
- Serial Read Cycle: 25ns min (CL=30pF)
Program/Erase time
- Deep Power Down Mode (DPD)
- Partial Array Self Refresh (PASR)
- Clock Stop capability during idle period
Programmable Mode Register Function
- Output Drive Impedance (full, 3/4, 1/2, 1/4)
- Burst Lengths (2, 4, 8, 16)
- Auto Page Program: 300μs/page typical
- Auto Block Erase: 3.5ms/block typical
Operating current
- Read (25ns cycle): 30 mA max
- Program (avg.): 30 mA max
- Burst Type (Sequential, Interleaved)
- Partial Array Self Refresh (1, 1/2, 1/4)
- Erase (avg.): 30 mA max
- Standby: 50 μA max
8 bit ECC for each 512 Bytes is required.
Version 1.3
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Nanya Technology Corp.
All Rights Reserved. ©
06/2016
2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
130b Ball Assignment – Flash X8 + DRAM X32
Part Number: NM2281KSMAXBH-XXX
1
2
3
4
5
6
7
8
9
10
A
B
C
D
E
F
NC
NC
CLE
VCC
VDD
VSS
NC
A
B
C
D
E
F
VSS
VDD
A6
A4
A5
A7
ALE
A9
VSS
R/
DQ31 DQ30 VDDQ VSSQ
DQ25 DQ27 DQ29 DQ28 VSSQ VDDQ
DM3 DQ26 VDDQ VSSQ
DQ17 DQ19 DQ24 DQ23
DM1 DQ9
DQ20 DQ21 DQ13 DQ12 DQS2
A8
CKE
NC
DQ18 DQS3 DQ22
A12
NC
A11
DM2
CK
VSSQ VDDQ
VDDQ VSSQ
DQ15 DQ16 DQS1
G
H
J
VDD
VSS
A1
VSS
VDD
G
H
J
Power
Ground
DRAM
Flash
RFU
BA1
A2
BA0
A10
A3
DQ14 DQ11 DQ10 DQS0 DM0
VSSQ VDDQ
A0
DQ0
NC
DQ7
DQ1
I/O 3
VCC
DQ8
DQ2
I/O 5
I/O 6
DQ6
DQ3
NC
DQ4 VDDQ VSSQ
DQ5 VDDQ VSSQ
I/O 7 VSSQ VDDQ
K
L
K
L
VDD
I/O 0
VSS
I/O 1
NC
M
N
I/O 2
NC
NC
NC
VDDQ VSSQ
M
N
NC
NC
1
NC
2
NC
3
NC
4
NC
5
VSS
6
I/O 4
7
VDD
8
VSS
9
RFU1
10
NOTE 1 This pin is reserved for TEST purpose and it must be connected to Ground or be NC.
Version 1.3
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Nanya Technology Corp.
06/2016
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
130b Ball Assignment – Flash X16 + DRAM X16
Part Number: NM22F1NSMAXBH-XXX
1
2
3
4
5
6
7
8
9
10
NC
NC
CLE
VCC
VDD
VSS
NC
A
B
C
D
E
F
A
B
C
D
E
F
VSS
VDD
A6
A4
A5
A7
ALE
A9
VSS
DQ9
UDQS
NC
R/
DQ15 DQ14 VDDQ VSSQ
DQ11 DQ13 DQ12 VSSQ VDDQ
A8
CKE
NC
NC
NC
NC
NC
NC
A0
NC
DQ8
NC
UDM DQ10 VDDQ VSSQ
A12
NC
A11
NC
NC
NC
NC
CK
VSSQ VDDQ
VDDQ VSSQ
NC
NC
VDD
VSS
A1
NC
NC
NC
VSS
VDD
G
H
J
G
H
J
Power
Ground
DRAM
Flash
RFU
BA0
A10
A3
NC
NC
LDQS LDM VSSQ VDDQ
BA1
A2
DQ7
DQ1
I/O 3
NC
DQ6
DQ3
DQ4 VDDQ VSSQ
DQ5 VDDQ VSSQ
DQ0
NC
DQ2
K
L
K
L
VDD
I/O 0
VSS
I/O 1
A13
I/O 5 I/O 14 I/O 7 VSSQ VDDQ
I/O 6 I/O 13 I/O 15 VDDQ VSSQ
I/O 2 I/O 10 VCC
I/O 9 I/O 11 I/O 12
M
N
M
N
NC
NC
1
I/O 8
2
VSS
6
I/O 4
7
VDD
8
VSS
9
RFU1
10
3
4
5
NOTE 1 This pin is reserved for TEST purpose and it must be connected to Ground or be NC.
Version 1.3
6
Nanya Technology Corp.
06/2016
All Rights Reserved. ©
2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
130b Ball Assignment – Flash X8 + DRAM X16
Part Number: NM2281NSMAXBH-XXX
1
2
3
4
5
6
7
8
9
10
NC
NC
CLE
VCC
VDD
VSS
NC
A
B
C
D
E
F
A
B
C
D
E
F
VSS
VDD
A6
A4
A5
A7
ALE
A9
VSS
DQ9
UDQS
NC
R/
DQ15 DQ14 VDDQ VSSQ
DQ11 DQ13 DQ12 VSSQ VDDQ
A8
CKE
NC
NC
NC
NC
NC
NC
A0
NC
DQ8
NC
UDM DQ10 VDDQ VSSQ
A12
NC
A11
NC
NC
NC
NC
CK
VSSQ VDDQ
VDDQ VSSQ
NC
NC
VDD
VSS
A1
NC
NC
NC
VSS
VDD
G
H
J
G
H
J
Power
Ground
DRAM
Flash
RFU
BA0
A10
A3
NC
NC
LDQS LDM VSSQ VDDQ
BA1
A2
DQ7
DQ1
I/O 3
VCC
NC
DQ6
DQ3
NC
DQ4 VDDQ VSSQ
DQ5 VDDQ VSSQ
I/O 7 VSSQ VDDQ
DQ0
NC
NC
DQ2
I/O 5
I/O 6
K
L
K
L
VDD
I/O 0
VSS
I/O 1
A13
I/O 2
NC
NC
VDDQ VSSQ
M
N
M
N
NC
NC
1
NC
2
NC
3
NC
4
NC
5
VSS
6
I/O 4
7
VDD
8
VSS
9
RFU1
10
NOTE 1 This pin is reserved for TEST purpose and it must be connected to Ground or be NC.
Version 1.3
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Nanya Technology Corp.
06/2016
All Rights Reserved. ©
2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
130b Package Outline Drawing (9.00mm x 8.00mm, pitch 0.65mm)
Unit: mm
* BSC (Basic Spacing between Center)
Might be changed before it’s finalized
Version 1.3
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Nanya Technology Corp.
06/2016
All Rights Reserved. ©
2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Ball Description – 2Gb X8/X16 SLC NAND
Symbol
Type
Function
Data Bus: The I/O0 to 7 pins are used as a port for transferring address, command and input/output data to
and from the device.
X8: I/O[7:0]
Input/output
X16: I/O[15:0]
The I/O8 to 15 pins are used as a port for transferring input/output data to and from the device. I/O8 to 15 pins
must be low level (V ) when address and command are input.
IL
Command Latch Enable: The CLE input signal is used to control loading of the operation mode command
into the internal command register. The command is latched into the command register from the I/O port on
the rising edge of the signal while CLE high.
CLE
ALE
Input
Input
Input
Address Latch Enable: The ALE signal is used to control loading address information into the internal
address register. Address information is latched into the address register from the I/O ports on the rising edge
of while ALE high.
Chip Enable: The device goes into a low-power Standby mode when goes High during the device is in
Ready state. The signal is ignored when device is in Busy state ( RY / = L), such as during a Program
or Erase or Read operation, and will not enter Standby mode even if the input goes High.
Read Enable: The signal controls serial data output. Data is available tREA after the falling edge of .
Input
Input
The internal column address counter is also incremented (Address = Address + 1) on this falling edge.
Write Enable: The signal is used to control the acquisition of data from the I/O port.
Write Protect: The signal is used to protect the device from accidental programming or erasing. The
internal voltage regulator is reset when is Low. This signal is usually used for protecting the data during
the power-on/off sequence when input signals are invalid.
Input
Ready / Busy Output: The RY / output signal is used to indicate the operation condition of the device.
The RY / signal is in Busy state ( RY / = L) during the Program, Erase and Read operations and will
return to Ready state ( RY / = H) after completion of the operation. The output buffer for this signal is an
open drain and has to be pulled-up to Vccq with an appropriate resister.
R/
Output
If RY / signal is not pulled-up to Vccq ( “Open” state), device operation cannot guarantee.
VCC
VSS
NC
Supply
Supply
─
Power Supply
Ground
No Connect: These pins should be left unconnected.
Version 1.3
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Ball Description – 1Gb X16/X32 LPDDR
Symbol 1
Type
Function
Clock: CK and are differential clock inputs. All address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of . Input and output data is referenced to the
crossing of CK and (both directions of crossing). Internal clock signals are derived from CK, .
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input
buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWERDOWN (row ACTIVE in any bank). CKE is
synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Input
buffers, excluding CK, and CKE, are disabled during power-down and self refresh mode which are
contrived for low standby power consumption.
CK,
Input
CKE
Input
Chip Select: enables (registered LOW) and disables (registered HIGH) the command decoder. All
commands are masked when is registered HIGH. provides for external bank selection on
systems with multiple banks. is considered part of the command code.
Input
Input
, ,
Command Inputs: , and (along with ) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled
HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS.
Although DM pins are input-only, the DM loading matches the DQ and DQS loading.
For x32 devices, DM0 corresponds to the data on DQ0-DQ7, DM1 corresponds to the data on
DQ8-DQ15, DM2 corresponds to the data on DQ16-DQ23, and DM3 corresponds to the data on
DQ24-DQ31.
X16:
LDM, UDM
X32:
Input
DM[3:0]
X16:DQ[15:0]
X32:DQ[31:0]
Input/output Data Bus: Bi-directional Input / Output data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data. Centered with
write data to capture write data.
X16:
LDQS, UDQS
X32:
Input/output For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the data on
DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data on
DQ24-DQ31.
DQS[3:0]
Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or
BA[1:0]
Input
PRECHARGE command is being applied. BA0 and BA1 also determine which mode register is loaded
during a LOAD MODE REGISTER command.
Address Inputs: provide the row address for ACTIVE commands, and the column address and auto
precharge bit(A10) for READ or WRITE commands, to select one location out of the memory array in the
respective bank. During a PRECHARGE command, A10 determines whether the PRECHARGE applies
to one bank (A10 LOW, bank selected by Bank Address Inputs) or all banks (A10 HIGH). The address
inputs also provide the opcode during a MODE REGISTER SET command.
Power Supply
X16:
A[13:0]
X32:
Input
A[12:0]
VDD
VSS
Supply
Supply
Supply
Supply
-
Ground
VDDQ
VSSQ
NC
DQ Power Supply: Isolated on the die for improved noise immunity.
DQ Ground: Provide isolated ground to DQs for improved noise immunity.
No Connect: These pins should be left unconnected.
NOTE 1 The signal may show up in a different symbol but it indicates to the same thing. e.g., /CK = CK# = = CKb, /DQS = DQS# =
= DQSb
Version 1.3
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06/2016
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Functional Block Diagram
VSS
VDD VDDQ VSSQ
CKE
CK
1Gb Mobile DDR
DM[3:0]
A[12:0]
BA[1:0]
DQ[31:0]
DQS[3:0]
[3:0]
NAND
CLE
ALE
2Gb NAND Flash
X8: I/O[7:0]
X16: I/O[15:0]
R/
VCC
Version 1.3
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Nanya Technology Corp.
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
2Gb(X8/X16) SLC NAND Flash
Version 1.3
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Nanya Technology Corp.
06/2016
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Descriptions
The device is a single 1.8V 2Gbit (2,281,701,376 bits) NAND Electrically Erasable and Programmable
2
Read-Only Memory (NAND E PROM) organized as X8: (2048 + 128) bytes x 64 pages x 2048blocks or X16:
(1024+64) words x 64 pages x 2048blocks .
The device has two 2176-bytes or 1088-words static registers which allow program and read data to be
transferred between the register and memory cell array in 2176-bytes or 1088-words increments. The Erase
operation is implemented in a single block unit (X8=128 Kbytes + 8K bytes: 2176 bytes x 64 pages) or (X16 = 64
Kwords + 4 Kwords: 1088 words x 64 pages).
The device is a serial-type memory device which utilizes the I/O pins for both address and data input/output as
well as for command inputs. The Erase and program operations are automatically executed making the device
most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
Version 1.3
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Function Block Diagram (X8)
VCC
VSS
Status register
Address register
Command register
Column buffer
Column decoder
Data register
I/O 0
I/O
to
Control circuit
I/O 7
Command register
CLE
ALE
Memory cell array
Logic control
Control circuit
RY
RY/
HV generator
Array Organization (X8)
The Program operation works on page units while the Erase operation works on block units
I/O 0
A page consists of 2176 bytes in which 2176 bytes are used for
main memory storage and 128 bytes are for redundancy or for
other uses.
I/O 7
1 Page = 2176 Bytes
1 Block = 2176 Bytes x 64 Pages = (128K + 8K) Bytes
Capacity = 2176 Bytes × 64 Pages × 2048 Blocks
1 Block = 64 Pages
(128K + 8K) Bytes
Array Address (X8)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
Address
1st cycle
2nd cycle
3rd cycle
4th cycle
5th cycle
CA0
CA8
PA0
PA8
PA16
CA1
CA9
PA1
PA9
L
CA2
CA10
PA2
PA10
L
CA3
CA11
PA3
PA11
L
CA4
L
CA5
L
CA6
L
CA7
L
Column Address
Column Address
Page Address
Page Address
Page Address
PA4
PA12
L
PA5
PA13
L
PA6
PA14
L
PA7
PA15
L
PA6 to PA16: Block address
PA0 to PA5: NAND address in block
Version 1.3
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Function Block Diagram (X16)
VCC
VSS
Status register
Address register
Command register
Column buffer
Column decoder
Data register
I/O 0
I/O
to
Control circuit
I/O 15
Command register
CLE
ALE
Memory cell array
Logic control
Control circuit
RY
RY/
HV generator
Array Organization (X16)
The Program operation works on page units while the Erase operation works on block units
I/O 0
A page consists of 1088 words in which 1024 words are used
I/O 15
for main memory storage and 64 words are for redundancy or
for other uses.
1 Page = 1088 Words
1 Block = 1088 Words x 64 Pages = (64K + 4K) Words
Capacity = 1088 Words x 64 Pages x 2048 Blocks
1 Block = 64 Pages
(64K + 4K) Words
Array Address (X16)
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 8 ~ I/O 15
Address
1st cycle
2nd cycle
3rd cycle
4th cycle
5th cycle
CA0
CA8
PA0
PA8
PA16
CA1
CA9
PA1
PA9
L
CA2
CA10
PA2
PA10
L
CA3
L
CA4
L
CA5
L
CA6
L
CA7
L
L
L
L
L
L
Column Address
Column Address
Page Address
Page Address
Page Address
PA3
PA11
L
PA4
PA12
L
PA5
PA13
L
PA6
PA14
L
PA7
PA15
L
PA6 to PA15: Block address
PA0 to PA5: NAND address in block
Note I/O 8 ~ 15 must be held low when address is input.
Version 1.3
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2Gb SLC NAND + 1Gb LPDDR
Preliminary
Features, specification, functions and
operations are not finalized
NM2281K(N)SMAXBH
NM22F1NSMAXBH
Absolute Maximum Ratings
Symbol
VCC
Rating
Value
Unit
Power Supply Voltage
Input Voltage
-0.6 to + 2.5
-0.6 to + 2.5
-0.6 to Vcc + 0.3 (≤2.5V)
0.3
VIN
V
VI/O
Input / Output Voltage
Power Dissipation
PD
W
oC
oC
TSOLDER
TSTG
Soldering Temperature (10 s)
Storage Temperature
260
-55 to +125
Capacitance1
(TA=25℃, f=1.0MHz)
Symbol
CIN
Parameter
Input
Test Condition
Min
－
Max
10
Unit
pF
VIN=0V
COUT
Output
VOUT=0V
－
10
pF
NOTE 1
This parameter is periodically sampled and is not tested for every device.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Valid Blocks
Symbol
NVB
Parameter
Min
Typ.
－
Max
Unit
Number of Valid Blocks
2,008
2,048
Blocks
NOTE 1
The device occasionally contains unusable blocks.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The specification for the minimum number of valid blocks is applicable over lifetime.
The number of valid blocks is on the basis of single plane operations, and this may be decreased with two
plane operations.
Recommended DC Operating Conditions
Symbol
VCC
Parameter
Power Supply Voltage
Min
1.70
Typ.
－
Max
1.95
Unit
V
VIH
High Level Input Voltage
Low Level Input Voltage
VCC x 0.8
-0.31
－
VCC + 0.3
VCC x 0.2
V
VIL
－
V
Note 1
-2V (pulse width lower than 20 ns)
DC and Operation Characteristics
(Ta= -25 to 85℃, VCC=1.70 to 1.95V)
Symbol
IIL
Parameter
Input Leakage Current
Output Leakage Current
Serial Read Current
Test Conditions
Min
－
Typ.
－
－
－
－
－
－
－
－
4
Max
±10
±10
30
Unit
μA
VIN=0 to VCC
μA
ILO
VOUT=0 to VCC
－
mA
mA
ICCO1
ICCO2
ICCO3
ICCS
=VIL,IOUT= 0 mA, tcycle=25ns
－
Programming Current
Erasing Current
－
－
－
30
－
30
mA
μA
V
Standby Current
= VCC - 0.2 V, = 0 V/VCC
IOH = -0.1mA
－
50
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
VCC - 0.2
－
IOL = 0.1mA
－
－
0.2
－
V
IOL (RY/) Output Current of (RY/) pin
VOL=0.2V
mA
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
AC Timing Characteristics for Command / Address / Data Input
(Ta= -25 to 85℃, VCC=1.70 to 1.95V)
Symbol
Parameter
Min
Max
Unit
tCLS
tCLH
tCS
CLE Setup Time
CLE Hold Time
Setup Time
Hold Time
12
5
–
–
–
–
–
–
–
–
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
5
tCH
tWP
tALS
tALH
tDS
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
High Hold Time
12
12
5
12
5
tDH
tWC
tWH
25
10
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
AC Characteristics for Operation
Symbol
Parameter
Min
Max
Unit
tWW
tRR
High to Low
100
20
20
12
25
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
μs
μs
ns
Ready to Falling Edge
tRW
tRP
Ready to Falling Edge
Read Pulse Width
–
–
tRC
Read Cycle Time
–
tREA
tCEA
tCLR
Access Time
20
25
–
Access Time
–
CLE Low to Low
10
10
25
5
tAR
ALE Low to Low
–
tRHOH
tRLOH
tRHZ
tCHZ
tCSD
tREH
tIR
High to Output Hold Time
Low to Output Hold Time
High to Output High Impedance
High to Output High Impedance
High to ALE or CLE Don’t care
High Hold Time
–
–
–
60
20
–
–
0
10
0
–
Output-High-impedance-to- Falling Edge
High to Low
–
tRHW
tWHC
tWHR
tR
30
30
60
–
–
High to Low
–
High to Low
–
Memory Cell Array to Starting Address
Data Cache Busy in Read Cache (following 31h and 3Fh)
Data Cache Busy in Page Copy (following 3Ah)
High to Busy
25
25
30
100
tDCBSYR1
tDCBSYR2
tWB
–
–
–
X8
5/5/10/500
X16
tRST
Device Reset Time (Ready/Read/Program/Erase)
–
μs
6/6/10/500
NOTE1 tCLS and tALS cannot be shorter than tWP.
NOTE2 tCS should be longer than tWP + 8ns.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
AC Test Conditions
Condition
VCC : 1.70 to 1.95V
VCC – 0.2 V, 0.2 V
3ns
Parameter
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output Load
Vcc / 2
Vcc / 2
1 TTL GATE and CL=30pF
NOTE 1
Busy to ready time depends on the pull-up resistor tied to the RY/ pin.
Programming / Erasing Characteristics
(Ta= -25 to 85℃, VCC=1.70 to 1.95V)
Symbol
tPROG
Parameter
Average Programming Time
Min
–
Typ.
300
–
Max
700
10
Unit
μs
tDCBSYW1 Data Cache Busy Time in Write Cache (following 11h)
tDCBSYW21 Data Cache Busy Time in Write Cache (following 15h)
–
μs
–
–
700
4
μs
N
Number of Partial Program Cycles in the Same Page
Block Erase Time
–
–
cycle
ms
tBERASE
NOTE 1
–
3.5
10
t
depends on the timing between internal programming time and data in time.
DCBSYW2
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by operations shown in command
table. Address input, command input and data input/output are controlled by the CLE, ALE, , , and
signals, as shown in Mode Selection Table.
Mode Selection
CLE
H
ALE
L
L
H
Mode
Command Input
Data Input
＊
H
L
L
L
H
L
H
L
H
＊
Address Input
L
L
L
H
＊
Serial Data Output
During Program (Busy)
During Erase (Busy)
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
＊
H
＊
＊
＊
H1
＊
＊
＊
＊
＊
H1
＊
＊
H
H
＊
During Read (Busy)
L
＊
＊
H
L
Program, Erase Inhibit
Stand-by
0V/VCC
H: VIH, L=VIL *: VIH or VIL.
Note 1: If is low during read busy. and must be held High to avoid unintended command/address input to
device or read to device. Reset or Status Read command can be input during Read Busy.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Command Table
Function
1stCycle
80H
00H
05H
31H
3FH
80H
85H
80H
80H
81H
81H
00H
8CH
8CH
60H
90H
70H
71H
FFH
2ndCycle
－
Acceptable Command during Busy
Serial Data Input
Read
30H
E0H
－
Column Address Change in Serial Data Output
Read with Data Cache
Read Start for Last Page in Read Cycle with Data Cache
Auto Page Program
－
10H
－
Column Address Change in Serial Data Input
Auto Program with Data Cache
15H
11H
15H
10H
3AH
15H
10H
D0H
－
Multi Page Program
Read for Page Copy (2) with Data Out
Auto Program with Data Cache during Page Copy (2)
Auto Program for last page during Page Copy (2)
Auto Block Erase
ID Read
－
Status Read
O
O
O
－
Status Read for Multi-Page Program or Multi Block Erase
Reset
－
Read mode operation states
CLE
ALE
L
H
L
I/O0 to I/o15
Data output
Power
Active
Active
Output Select
L
L
Output Deselect
L
L
L
H
H
High impedance
H: VIH, L=VIL
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
ID Read
The device contains ID codes which can be used to identify the device type, the manufacturer, and features of
the device. The ID codes can be read out under the following timing conditions:
ID Definition Table(X8)
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex Data
Description
1st Data
2nd Data
3rd Data
4th Data
5th Data
Maker Code
Device Code
1
1
1
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
98H
AAH
90H
15H
76H
Chip Number, Cell Type
Page Size, Block Size, I/O Width
Plane Number
ID Definition Table(X16)
I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Hex Data
Description
1st Data
2nd Data
3rd Data
4th Data
5th Data
Maker Code
Device Code
1
1
1
0
0
0
0
0
1
1
0
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
0
1
0
0
0
1
0
98H
BAH
90H
55H
76H
Chip Number, Cell Type
Page Size, Block Size, I/O Width
Plane Number
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
3rd ID Data
Item
Description
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1
2
4
8
0
0
1
1
0
1
0
1
Internal Chip Number
2 Level Cell
4 Level Cell
8 Level Cell
16 Level Cell
0
0
1
1
0
1
0
1
Cell Type
Reserved
1
0
0
1
4th ID Data
Item
Description
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1 KB
2 KB
4 KB
0
0
1
1
0
1
0
1
Page Size
(w/o redundant area)
8 KB
64 KB
128 KB
256 KB
512 KB
X8
0
0
1
1
0
1
0
1
Block Size
(w/o redundant area)
0
1
I/O Width
Reserved
X16
0
0
1
5th ID Data
Item
Description
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
1 Plane
2 Plane
4 Plane
8 Plane
0
0
1
1
0
1
0
1
Plane Number
Reserved
0
1
1
1
1
0
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Status Read
The device automatically implements the execution and verification of the Program and Erase operations. The
status Read function is used to monitor the Ready/Busy status of the device, determine the result (pass/fail) of a
Program or Erase operation, and determine whether the device is in Protect mode. The device status is output
via the I/O port using after a “70h” command input. The Status Read can also be used during a Read
operation to find out the Ready/Busy status.
Status Register Definition for 70H Command
I/O
Page Program
Block Erase
Read
Cache Read
Cache Program
Definition
Chip Status1
Pass : 0 / Fail : 1
Chip Status2
I/O 0
Pass / Fail
Pass / Fail
Invalid
Invalid
Pass / Fail
I/O 1
Invalid
Invalid
Invalid
Invalid
Pass / Fail
Pass : 0 / Fail : 1
I/O 2
I/O 3
I/O 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Not Used
Not Used
Not Used
Page Buffer
Busy : 0 / Ready : 1
Data Cache
I/O 5
I/O 6
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Ready / Busy
Busy : 0 / Ready : 1
Write Protect
I/O 7
Write Protect
Not Used
Write Protect
Not Used
Write Protect
Not Used
Write Protect
Not Used
Write Protect
Not Used
Protected :0
/ Not Protected : 1
I/O8 to 15
Not Used
NOTE
The Pass/Fail status on I/O0 and I/O1 is only valid during a Program/Erase operation when the device is in
the Ready state.
Chip Status 1:
During a Auto Page Program or Auto Block Erase operation this bit indicates the pass/fail result.
During a Auto Page Programming with Data Cache operation, this bit shows the pass/fail results of the current
page program operation, and therefore this bit is only valid when I/O5 shows the Ready state.
Chip Status 2:
This bit shows the pass/fail result of the previous page program operation during Auto Page Programming with
Data Cache. This status is valid when I/O6 shows the Ready State.
The status output on the I/O5 is the same as that of I/O6 if the command input just before the 70h is not 15h or
31h.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
The 71H Command Status Description
I/O
Status
Output
Pass : 0 / Fail : 1
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
Chip Status1 : Pass / Fail
Pass : 0 / Fail : 1
Pass : 0 / Fail : 1
Pass : 0 / Fail : 1
Pass : 0 / Fail : 1
District 0 Chip Status1 : Pass / Fail
District 1 Chip Status2 : Pass / Fail
District 0 Chip Status1 : Pass / Fail
District 1 Chip Status2 : Pass / Fail
I/O 5
I/O 6
I/O 7
Ready / Busy
Data Cache Ready / Busy
Write Protect
Busy : 0 / Ready : 1
Busy : 0 / Ready : 1
Protected : 0 / Not Protected : 1
I/O0 describes Pass/Fail condition of district 0 and 1 (OR data of I/O1 and I/O2). If one of the districts fails during multi
page program operation, it shows “Fail”.
I/O1 to I/O4 shows the Pass/Fail condition of each district. For details on “Chip Status 1” and “Chip Status2” refer to
section “Status Read”.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Addressing for Program Operation
Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page of the
block to MSB (most significant bit) pages of the block. Random page address programming is prohibited.
Page 63
Page 31
Page 63
Page 31
(64)
(64)
‧
‧
‧
‧
‧
‧
(1)
(32)
‧
‧
‧
‧
‧
‧
Page2
Page 1
Page 0
Page2
Page 1
Page 0
(3)
(32)
(2)
(3)
(2)
(1)
Data Register
Data Register
From the LSB page to MSB page
DATA IN: Data(1) Data (64)
Ex.) Random page program (Prohibition)
DATA IN: Data(1) Data (64)
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
RY / : termination for the Ready/Busy pin (RY / )
A pull-up resistor needs to be used for termination because the RY / BY buffer consists of an open drain
circuit.
tr
tf
R
This data may vary from device to device.
we recommend that you use this data as a reference when selecting a resistor value.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Bad Block Test Flow
Regarding invalid blocks, bad block mark is in whole pages.
Please read one column of any page in each block. It makes sure that every invalid block has Marjority “0” data at
this column. If the data of the column is Marjority “0”, define the block as a bad block.
Start
Block No = 1
Fail
Read Check
Pass
Bad Block1
Block No. = Block No. +1
No
Last Block
Yes
End
Note1: No erase operation is allowed to detected bad blocks.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Failure phenomena for Program and Erase Operations
The device may fail during a Program or Erase operation.
The following possible failure modes should be considered when implementing a highly reliable system.
Failure Mode
Erase Failure
Programming Failure
Bit Error
Detection and Countermeasure Sequence
Read Status after Erase → Block Replacement
Read Status after Program → Block Replacement
ECC Correction / Block Refresh
Block
Page
Read
NOTE
ECC: Error Correction Code. 8 bit correction per 512 Bytes is necessary.
Block Replacement
Program
When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an
external buffer. Then, prevent further system accesses to Block A ( by creating a bad block table or by using
anther appropriate scheme).
Erase
When an error occurs during an Erase operation, prevent future accesses to this bad block (again by creating a
table within the system or by using another appropriate scheme).
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Power-on/off sequence
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence.
During the initialization the device Ready/Busy signal indicates the Busy state as shown in the figure below. In this
time period, the acceptable commands are FFh or 70h.
The signal is useful for protecting against data corruption at power-on/off.
Do not turn off the power before write/erase operation is complete. Avoid using the device when the battery
is low. Power shortage and/or power failure before write/erase operation is complete will cause loss of data
and/or damage to data.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
TIMING DIAGRAMS
Latch Timing Diagram for Command/Address/Data
Command Input Cycle Timing Diagram
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Address Input Cycle Timing Diagram
Data Input Cycle Timing Diagram
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Serial Read Cycle Timing Diagram
Status Read Cycle Timing Diagram
*: 70h represents the hexadecimal number
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Read Cycle Timing Diagram
Read Cycle Timing Diagram: When Interrupted by
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Read Cycle with Data Cache Timing Diagram (1/2)
*: The column address will be reset to 0 by the 31h command input
Read Cycle with Data Cache Timing Diagram (2/2)
Make sure to terminate the operation with 3Fh command
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Column Address Change in Read Cycle Timing Diagram (1/2)
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Column Address Change in Read Cycle Timing Diagram (2/2)
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Data Output Timing Diagram
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Auto-Program Operation Timing Diagram
*: M: up to 2175 (byte input data for x8 device)
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Auto-Program Operation with Data Cache Timing Diagram (1/3)
CA0 to CA11 is 0 in this diagram.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Auto-Program Operation with Data Cache Timing Diagram (2/3)
Repeat a max of 62 times
(in order to program pages 1 to 62 of a block).
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Auto-Program Operation with Data Cache Timing Diagram (3/3)
(*1)
tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG during cache programming is given by the following equation.
tPROG = tPROG of the last page + tPROG of the previous page − A
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
NOTE: Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by
issuing Status Read command (70h) and make sure the previous page program operation is
completed. If the page program operation is completed issue FFh reset before next operation.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Multi-Page Program Operation with Data Cache Timing Diagram (1/4)
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Multi-Page Program Operation with Data Cache Timing Diagram (2/4)
Repeat a max of 63 times
(in order to program pages 0 to 62 of a block).
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Multi-Page Program Operation with Data Cache Timing Diagram (3/4)
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Multi-Page Program Operation with Data Cache Timing Diagram (4/4)
(*1)
tPROG: Since the last page programming by 10h command is initiated after the previous cache
program, the tPROG during cache programming is given by the following equation.
tPROG = tPROG of the last page + tPROG of the previous page − A
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the tPROG of previous page, tPROG of the last page is tPROG max.
NOTE : Make sure to terminate the operation with 81h-10h- command sequence.
If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy)
by issuing Status
Read command (70h) and make sure the previous page program operation is completed.
If the page program operation is completed issue FFh reset before next operation.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Auto Block Erase Timing Diagram
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Multi Block Erase Timing Diagram
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
ID Read Operation Timing Diagram
Table 5: ID Definition Table
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
1Gb(X16/X32) LPDDR
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Descriptions
The 1Gb Mobile LPDDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It
is internally configured as a quad-bank DRAM.
The 1Gb chip is organized as 16Mbit x 4 banks x 16 I/O or 8Mbit x 4 banks x 32 I/O device. Each of the x16’s 268,435,456-bit
banks is organized as 16,384 rows by 1,024 columns by 16 bits. Each of the x32’s 268,435,456-bit banks is organized as
8,192 rows by 1,024 columns by 32 bits. In the reduced page-size option, each of the x32’s 268,435,456-bit banks are
organized as 16,384 rows by 512 columns by 32 bits. To achieve high-speed operation, our LPDDR SDRAM uses the double
data rate architecture and adopt 2n-prefetch interface designed to transfer two data per clock cycle at the I/O pins.
The chip is designed to comply with all key Mobile Double-Data-Rate SDRAM key features. All of the control and address
inputs are synchronized with a pair of externally supplied differential clocks, and latched at the cross point of differential
clocks (CK rising and falling). The input data is registered at both edges of DQS, and the output data is referenced to both
edges of DQS, as well as to both edges of CK. DQS is a bidirectional data strobe signal, transmitted by the LPDDR SDRAM
during READs (edge-aligned with data), and by the memory controller during WRITEs (center-aligned with data).
LPDDR SDRAM, Read and Write access are burst oriented. The address bits registered coincident with the ACTIVE
command to select the row in the specific bank. And then the address bits registered with the READ or WRITE command to
select the starting column location in the bank for the burst access. The burst length can be programmed as 2, 4, 8 or 16. An
Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of burst access.
LPDDR SDRAM with Auto Refresh mode, and the Power-down mode for power saving. And the Deep Power Down Mode
can achieve the maximum power reduction by removing the memory array power within Low Power DDR SDRAM. With this
feature, the system can cut off almost all DRAM power without adding the cost of a power switch and giving up month-board
power-line layout flexibility. Self Refresh mode with Temperature Compensated Self Refresh (TCSR) and Partial Array Self
Refresh (PASR) options, which allow users to achieve additional power saving. The TCSR and PASR options can be
programmed via the extended mode register. The two features may be combined to achieve even greater power saving. The
DLL that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has been omitted to save
power.
All inputs are LVCMOS compatible. Devices will have a VDD and VDDQ supply of 1.8V (nominal).
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Absolute Maximum DC Ratings
Symbol
Parameter
Min
Max
2.4
Units
VDD / VDDQ
VDD / VDDQ supply voltage relative to Vss
-1.0
V
2.4 or (VDDQ + 0.3V),
Whichever is less
+150
Vin
Voltage on any pin relative to Vss
Storage Temperature (plastic)
-0.5
-55
V
Tstg
C
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
3. VDD and VDDQ must be within 300mV of each other at all times. VDDQ must not exceed VDD
.
Input / Output Capacitance
Symbol
Parameter
Min
Max
Unit
Notes
CCK
CDCK
CI
Input capacitance: CK,
1.5
-
3.0
0.25
3.0
pF
pF
pF
pF
pF
pF
Input capacitance delta: CK,
2
2
3
Input capacitance, all other input-only pins
Input capacitance delta, all other input-only pins
Input/output capacitance, DQ, DM, DQS
Input/output capacitance delta, DQ, DM, DQS
1.5
-
CDI
0.5
CIO
3.0
-
5.0
0.5
CDIO
Notes:
1. These values are guaranteed by design and are tested on a sample base only.
2. These capacitance values are for single monolithic devices only. Multiple die packages will have parallel capacitive loads.
3. Input capacitance is measured according to JEP147 procedure for measuring capacitance using a vector network analyzer.
VDD, VDDQ are applied and all other pins (except the pin under test) floating. DQs should be in high impedance state.
This may be achieved by pulling CKE to low level.
4. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS
pins. This is required to match signal propagation times of DQ, DQS and DM in the system.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
AC/DC Electrical Characteristics and Operating Conditions
Apply Note 1-3 to whole the table.
Symbol
VDD
Parameter
Min
1.70
1.70
Max
1.95
1.95
Unit
V
Notes
Supply voltage
-
-
VDDQ
I/O Supply voltage
V
Address and Command inputs
VIH
VIL
Input voltage high
Input voltage low
0.8 x VDDQ
-0.3
VDDQ + 0.3
0.2 x VDDQ
V
V
-
-
Clock inputs (CK, )
VIN
VID(DC)
VID(AC)
VIX
DC input voltage
-0.3
VDDQ + 0.3
VDDQ + 0.6
VDDQ + 0.6
0.6 x VDDQ
V
V
V
V
-
DC input differential voltage
AC Input Differential Voltage
AC Differential Crosspoint Voltage
0.4 x VDDQ
0.6 x VDDQ
0.4 x VDDQ
2
2
3
Data inputs
VIH(DC)
VIL(DC)
VIH(AC)
VIL(AC)
DC input high voltage
0.7 x VDDQ
-0.3
VDDQ + 0.3
0.3 x VDDQ
VDDQ + 0.3
0.2 x VDDQ
V
V
V
V
-
-
-
-
DC input low voltage
AC input high voltage
AC input low voltage
0.8 x VDDQ
-0.3
Data outputs
VOH
VOL
DC output high voltage: Logic 1 (IOH = -0.1mA)
DC output low voltage: Logic 0 (IOL = -0.1mA)
0.9 x VDDQ
-
-
V
V
-
-
0.1 x VDDQ
Leakage current
Input leakage current
Any input 0 ≦ VIN ≦ VDD
,
II
-1
-5
1
5
uA
uA
All other pins not under test = 0V
Output leakage current
IOZ
DQs are disabled; 0 ≦ VOUT ≦ VDDQ
Notes:
1.All voltages referenced to VSS and VSSQ must be same potential.
2.VID(DC) and VID(AC) are the magnitude of the difference between the input level on CK and the input level on .
3.The value of VIX is expected to be 0.5 * VDDQ and must track variations in the DC level of the same.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
IDD Specifications and Measurement Conditions (64Mx16)
Notes 1–5 apply to all the parameters/conditions in this table
Symbol
Parameter/Condition
LPDDR400
Unit Notes
Operating one bank active-precharge current:
100
IDD0
mA
6
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current:
400/600
IDD2P
IDD2PS
IDD2N
uA
uA
7,8
7
all banks idle, CKE is LOW; is HIGH, tCK = tCKmin;
(Typ./Max.)
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current with clock stopped:
all banks idle, CKE is LOW; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current:
400/600
(Typ./Max.)
18
14
5
mA
mA
mA
9
all banks idle, CKE is HIGH; is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current with clock stopped:
all banks idle, CKE is HIGH; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current:
IDD2NS
IDD3P
9
8
one bank active, CKE is LOW; is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current with clock stopped:
IDD3PS
5
mA
one bank active, CKE is LOW; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current:
20
16
IDD3N
IDD3NS
IDD4R
mA
mA
mA
mA
6
6
6
6
one bank active, CKE is HIGH; is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current with clock stopped:
one bank active, CKE is HIGH; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Operating burst read current:
135
135
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA
address inputs are SWITCHING; 50% data change each burst transfer
Operating burst write current:
IDD4W
one bank active; BL=4; tCK = tCKmin; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
Auto Refresh current:
100
15
IDD5
mA
mA
10
tRC = 140ns
tCK = tCKmin; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are
IDD5A
10,11
tRC = tREFI
STABLE
25oC
10
25
uA
uA
7,13
7
Deep power-down current:
IDD8
85oC
Address and control inputs are STABLE; data bus inputs are STABLE
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
IDD Specifications and Measurement Conditions (32Mx32)
Notes 1–5 apply to all the parameters/conditions in this table
Symbol
Parameter/Condition
LPDDR400
Unit Notes
Operating one bank active-precharge current:
100
IDD0
mA
6
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; is HIGH between valid commands;
address inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current:
400/600
IDD2P
IDD2PS
IDD2N
uA
uA
7,8
7
all banks idle, CKE is LOW; is HIGH, tCK = tCKmin;
(Typ./Max.)
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current with clock stopped:
all banks idle, CKE is LOW; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current:
400/600
(Typ./Max.)
18
14
5
mA
mA
mA
9
all banks idle, CKE is HIGH; is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
Precharge non power-down standby current with clock stopped:
all banks idle, CKE is HIGH; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current:
IDD2NS
IDD3P
9
8
one bank active, CKE is LOW; is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active power-down standby current with clock stopped:
IDD3PS
5
mA
one bank active, CKE is LOW; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current:
20
16
IDD3N
IDD3NS
IDD4R
mA
mA
mA
6
6
6
one bank active, CKE is HIGH; is HIGH, tCK = tCKmin;
address and control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current with clock stopped:
one bank active, CKE is HIGH; is HIGH, CK = LOW, CK = HIGH;
address and control inputs are SWITCHING; data bus inputs are STABLE
Operating burst read current:
150
150
one bank active; BL=4; CL=3; tCK = tCKmin; continuous read bursts; IOUT = 0 mA
address inputs are SWITCHING; 50% data change each burst transfer
Operating burst write current:
IDD4W
mA
mA
6
one bank active; BL=4; tCK = tCKmin; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
Auto Refresh current:
100
15
IDD5
10
tRC = 140ns
tCK = tCKmin; burst refresh; CKE is HIGH;
address and control inputs are SWITCHING; data bus inputs are
IDD5A
mA
uA
uA
10,11
7,13
7
tRC = tREFI
STABLE
25oC
10
25
Deep power-down current:
IDD8
Address and control inputs are STABLE; data bus inputs are STABLE
85oC
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
IDD6 Self-refresh and Partial Array Refresh) current
Notes 1–5, 7, and 12 apply to all the parameters/conditions in this table
Symbol
Parameter/Condition
Temperature
PASR
Typical
Max
Unit
Full Array
1/2 Array
1/4 Array
Full Array
1000
700
560
500
1200
─
uA
uA
uA
uA
85℃
Self refresh current:
─
CKE=LOW; tCK=tCK(min); Address
and control inputs are stable; Data
bus inputs are stable.
IDD6
─
45℃
1/2 Array
1/4 Array
400
350
─
─
uA
uA
IDD Notes:
1. All voltages referenced to VSS.
2. Tests for IDD may be conducted at nominal supply voltage levels, but the related specifications and device operation are guaranteed for
the full voltage and temperature range specified.
3. Timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VDDQ/2 (or,
to the crossing point for CK and ). The output timing reference voltage level is VDDQ/2.
4. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time with the outputs open.
5. IDD specifications are tested after the device is properly initialized, and are averaged at the defined cycle rate.
6. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective
parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.
7. Measurement is taken 500ms after entering into this operating mode to provide settling time for the tester.
8. VDD must not vary more than 4 % if CKE is not active while any bank is active.
9. IDD2N specifies DQ, DQS, and DM to be driven to a valid HIGH or LOW logic level.
10. CKE must be active (HIGH) during the entire time a REFRESH command is executed. From the time the AUTO REFRESH command is
registered, CKE must be active at each rising clock edge until tRFC later.
11. This limit is a nominal value and does not result in a fail. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW
(for example, during standby).
12. Values for IDD6 85°C are guaranteed for the entire temperature range.
13. IDD8 are typical values. IDD8 is measured at 25℃.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Electrical Characteristics and Recommended AC Operating Conditions
Note 1-9 apply to all of the parameters
LPDDR400
Symbol
Parameter
Unit Notes
Min
2.0
Max
5.0
6.5
-
CL=3
CL=2
CL=3
CL=2
tAC
tCK
Access window of DQs from CK,
ns
2.0
5.0
Clock cycle time
ns
12
12
-
tCH
tCL
CK high-level width
CK low-level width
0.45
0.45
0.55
0.55
tCK
tCK
tCH,
tCL
tHP
Half-clock period
-
ns
10,11
tCKE
CKE min. pulse width (high and low)
1*tCK
-
ns
ns
CL=3
CL=2
2.0
5.0
6.5
0.4
0.5
-
tDQSCK Access window of DQS from CK,
2.0
ns
tDQSQ DQS-DQ skew, DQS to last DQ valid, per group, per access
-
ns
20
11
11
tQHS
tQH
n/a
Data Hold Skew Factor
-
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per access
Data Valid output window (DVW)
tHP - tQHS
ns
tQH – tDQSQ
ns
CL=3
Data-out high-z window from CK,
CL=2
-
-
5.0
ns
tHZ
tLZ
19
6.5
ns
Data-out Low-z window from CK,
1.0
0.9
0.5
0.4
CL+1
2
-
ns
19
23
23
CL=3
1.1
tCK
tCK
tCK
tCK
tCK
ms
ns
tRPRE DQS read preamble
tRPST DQS read postamble
CL=2
1.1
0.6
tSRC
tSRR
tTQ
Read of SRR to next valid command
SRR-to-READ
-
-
-
-
-
-
-
-
Internal temperature sensor valid temperature output enable
DQ and DM input hold time relative to DQS (fast slew rate)
DQ and DM input hold time relative to DQS (slow slew rate)
DQ and DM input setup time relative to DQS (fast slew rate)
DQ and DM input setup time relative to DQS (slow slew rate)
DQ and DM input pulse width (for each input)
2
31
tDHf
0.48
0.58
0.48
0.58
1.8
13,14,15
13,14,16
13,14,15
13,14,16
17
tDHs
tDSf
ns
ns
tDSs
tDIPW
ns
ns
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
LPDDR400
Symbol
Parameter
Unit Notes
Min
0.75
0.4
0.4
0.2
0.2
0.25
0
Max
tDQSS WRITE command to first DQS latching transition
tDQSH DQS input high pulse width
1.25
tCK
tCK
tCK
tCK
tCK
tCK
ns
0.6
tDQSL DQS input low pulse width
0.6
tDSH
tDSS
DQS falling edge from CK rising – hold time
DQS falling edge from CK rising – setup time
-
-
tWPRE DQS write preamble
-
tWPRES DQS write preamble setup time
tWPST DQS write postamble
-
21
0.4
0.9
1.1
0.9
1.1
2.3
2
0.6
tCK
ns
22
tIHf
tIHs
Address and Control input hold time (fast slew rate)
-
15,18
16,18
15,18
16,18
17
Address and Control input hold time (slow slew rate)
Address and Control input setup time (fast slew rate)
Address and Control input setup time (slow slew rate)
Address and Control input pulse width
-
ns
tISf
-
ns
tISs
-
ns
tIPW
tMRD
tRAS
-
ns
Load MODE Register command cycle time
ACTIVE to PRECHARGE command
-
tCK
ns
40
70,000
ACTIVE to ACTIVE / ACTIVE to AUTO REFRESH command
period
tRC
55
-
ns
tRCD
tRP
ACTIVE to READ or WRITE delay
PRECHARGE command period
15
-
ns
ns
ns
-
24
24
15
-
tRRD
tDAL
tWR
ACTIVE bank-a to ACTIVE bank-b command
Auto precharge write recovery + precharge time
Write recovery time
10
-
-
-
-
26
15
ns
tCK
ns
ns
ms
us
ns
tWTR
tXP
Internal WRITE to READ command delay
Exit power-down mode to first valid command
Exit SELF REFRESH to first valid command
Refresh period
2
-
6
-
28
27
tXSR
tREF
tREFI
tRFC
Notes:
112.5
-
-
-
64
7.8
-
Average periodic refresh interval
Auto Refresh command period
29,30
72
1. All voltages referenced to Vss.
2. All parameters assume proper device initialization.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
3. Tests for AC timing, and electrical AC and DC characteristics may be conducted at nominal supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range specified.
4. The circuit shown below represents the timing reference load used in defining the relevant timing parameters of the device. It is
not intended to be either a precise representation of the typical system environment or a depiction of the actual load presented
by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to system
environment. Specifications are correlated to production test conditions (generally a coaxial transmission line terminated at the
tester electronics). For the half-strength driver with a nominal 10pF load, parameters tAC and tQH are expected to be in the same
range. However, these parameters are not subject to production test but are estimated by design/characterization. Use of IBIS or
other simulation tools for system design validation is suggested.
5. The CK, input reference voltage level (for timing referenced to CK, ) is the point at which CK and cross; the input
reference voltage level for signals other than CK, is VDDQ/2.
6. The timing reference voltage level is VDDQ/2.
7. AC and DC input and output voltage levels are defined in the section for Electrical Characteristics and AC/DC operating conditions.
8. A CK/ differential slew rate of 2.0 V/ns is assumed for all parameters.
9. CAS latency definition: with CL = 3 the first data element is valid at (2 * tCK + tAC) after the clock at which the READ command
was registered (see figure); with CL = 2 the first data element is valid at (tCK + tAC) after the clock at which the READ command
was registered; with CL = 4 the first data element is valid at (3 * tCK + tAC) after the clock at which the READ command was
registered.
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NM22F1NSMAXBH
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH)
11. tQH = tHP - tQHS, where tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCL, tCH).
tQHS accounts for 1) the pulse duration distortion of on-chip clock circuits; and 2) the worst case push-out of DQS on one
transition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew
and output pattern effects, and p-channel to n-channel variation of the output drivers.
12. The only time that the clock frequency is allowed to change is during clock stop, power-down or self-refresh modes.
13. The transition time for DQ, DM and DQS inputs is measured between VIL(DC) to VIH(AC) for rising input signals, and VIH(DC) to
VIL(AC) for falling input signals.
14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal
transitions through the DC region must be monotonic.
15. Input slew rate ≥ 1.0 V/ns.
16. Input slew rate ≥ 0.5 V/ns and < 1.0 V/ns.
17. These parameters guarantee device timing but they are not necessarily tested on each device.
18. The transition time for address and command inputs is measured between VIH and VIL.
19. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a
specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
20. tDQSQ consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any
given cycle.
21. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before the corresponding
CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes
were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
22. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) will degrade accordingly.
23. A low level on DQS may be maintained during High-Z states (DQS drivers disabled) by adding a weak pull-down element in the
system. It is recommended to turn off the weak pull-down element during read and write bursts (DQS drivers enabled).
24. Speed bin (CL - tRCD - tRP) = 3 - 3 - 3
25. Speed bin (CL - tRCD - tRP) = 3 - 4 - 4 (all speed bins except LPDDR200)
26. tDAL = (tWR/tCK) + (tRP/tCK): for each of the terms, if not already an integer, round to the next higher integer.
27. There must be at least two clock pulses during the tXSR period.
28. There must be at least one clock pulse during the tXP period.
29. tREFI values are dependent on density and bus width.
30. A maximum of 8 Refresh commands can be posted to any given LPDDR, meaning that the maximum absolute interval between
any Refresh command and the next Refresh command is 8*tREFI.
31. It’s not supported for package level.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
OUTPUT SLEW RATE CHARACTERISTICS
PARAMETER
MIN
0.7
0.5
0.3
0.7
MAX
2.5
UNIT
V/ns
V/ns
V/ns
-
NOTES
Pull-up and Pull-Down Slew Rate for Full Strength Driver
Pull-up and Pull-Down Slew Rate for Three-Quarters Strength Driver
Pull-up and Pull-Down Slew Rate for Half Strength Driver
1,2
1,2
1,2
3
1.75
1.0
Output Slew rate Matching ratio (Pull-up to Pull-down)
NOTES:
1.4
1. Measured with a test load of 20 pF connected to VSSQ.
2. Output slew rate for rising edge is measured between VILD(DC) to VIHD(AC) and for falling edge between VIHD(DC) to VILD(AC).
3. The ratio of pull-up slew rate to pull-down slew rate is specified for the same temperature and voltage, over the entire
temperature and voltage range. For a given output, it represents the maximum difference between pull-up and pull-down
drivers due to process variation.
AC Overshoot/Undershoot Specification
PARAMETER
Maximum peak amplitude allowed for overshoot
SPECIFICATION
0.5 V
Maximum peak amplitude allowed for undershoot
0.5 V
The area between overshoot signal and VDD must be less than or equal to
The area between undershoot signal and GND must be less than or equal to
3 V-ns
3 V-ns
NOTES:
1. This specification is intended for devices with no clamp protection and is guaranteed by design.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
OUTPUT DRIVE STRENGTH CHARACTERISTICS
THREE-QUARTERS DRIVE
STRENGTH
FULL DRIVE STRENGTH
HALF DRIVE STRENGTH
VOLTAGE
[V]
PULL-DOWN
CURRENT
[mA]
PULL-UP
CURRENT
[mA]
PULL-DOWN
CURRENT
[mA]
PULL-UP
CURRENT
[mA]
PULL-DOWN
CURRENT
[mA]
PULL-UP
CURRENT
[mA]
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.85
0.90
0.95
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
0
0
0
0
0
0
0
0
0
0
0
0
2.8
18.53
26.8
-2.8
-18.53
-26.8
1.27
2.55
3.82
5.09
6.36
7.64
8.91
10.16
10.8
10.8
10.8
10.8
10.8
10.8
10.8
10.8
10.8
10.8
10.8
—
8.42
-1.27
-2.55
-3.82
-5.09
-6.36
-7.64
-8.91
-10.16
-10.8
-10.8
-10.8
-10.8
-10.8
-10.8
-10.8
-10.8
-10.8
-10.8
-10.8
—
-8.42
1.96
12.97
18.76
22.96
25.94
28
-1.96
-3.92
-5.88
-7.84
-9.8
-12.97
-18.76
-22.96
-25.94
-28
5.6
-5.6
12.3
-12.3
3.92
8.4
32.8
-8.4
-32.8
14.95
16.84
18.2
-14.95
-16.84
-18.2
5.88
11.2
14
37.05
40
-11.2
-14
-37.05
-40
7.84
9.8
16.8
19.6
22.4
23.8
23.8
23.8
23.8
23.8
23.8
23.8
23.8
23.8
23.8
23.8
—
42.5
-16.8
-19.6
-22.4
-23.8
-23.8
-23.8
-23.8
-23.8
-23.8
-23.8
-23.8
-23.8
-23.8
-23.8
—
-42.5
19.3
-19.3
11.76
13.72
15.68
16.66
16.66
16.66
16.66
16.66
16.66
16.66
16.66
16.66
16.66
16.66
—
29.75
31.2
-11.76
-13.72
-15.68
-16.66
-16.66
-16.66
-16.66
-16.66
-16.66
-16.66
-16.66
-16.66
-16.66
-16.66
—
-29.75
-31.2
44.57
46.5
-44.57
-46.5
20.3
-20.3
21.2
-21.2
32.55
33.24
33.95
34.58
35.04
35.95
36.86
37.77
38.68
39.59
40.5
-32.55
-33.24
-33.95
-34.58
-35.04
-35.95
-36.86
-37.77
-38.68
-39.59
-40.5
47.48
48.5
-47.48
-48.5
21.6
-21.6
22
-22
49.4
-49.4
22.45
22.73
23.21
23.67
24.14
24.61
25.08
25.54
26.01
26.48
26.95
-22.45
-22.73
-23.21
-23.67
-24.14
-24.61
-25.08
-25.54
-26.01
-26.48
-26.95
50.05
51.35
52.65
53.95
55.25
56.55
57.85
59.15
60.45
61.75
-50.05
-51.35
-52.65
-53.95
-55.25
-56.55
-57.85
-59.15
-60.45
-61.75
41.41
42.32
43.23
-41.41
-42.32
-43.23
—
—
—
—
—
—
NOTES:
1. Based on nominal impedance of 25 Ohms (Full Drive), 55 Ohms (Half Drive) and 36 Ohms(Three-Quarters) at VDDQ/2
2. The full variation in driver current from minimum to maximum due to process, temperature and voltage will lie within the
outer bounding lines of the I-V curve.
3. The I-V current for the optional quarter drive strength is approximately 50% of the half drive strength.
4. The IV current for the Three-Quarters Strength Driver is approximately 70% of the full drive strength current.
5. Implementation and availability of Three-Quarters Strength Driver is optional for speed bins LPDDR333 and below.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Standard Mode Register definition
BA1 BA0 A13 A12 A11 A10 A9
A8
↓
A7
↓
A6
↓
A5
↓
A4
↓
A3
↓
A2
↓
A1
↓
A0
↓
↓
↓
↓
↓
↓
↓
↓
MR select
Operating Mode
CAS Latency
BL
BT
MR select
Burst Type
BA1 BA0
A3
Standard MR
Status Register
Extended MR
Reserved
Sequential
Interleaved
0
0
1
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
BL
Reserved
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
A2
0
0
0
0
1
1
1
1
A1
A0
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
2
4
8
16
3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
A13-A9
Operating Mode
Normal Operation
All other states reserved
A8
0
-
A7
0
-
0
-
NOTE 1 : A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Extended Mode Register
BA1 BA0 A13 A12 A11 A10 A9
A8
↓
A7
↓
A6
↓
A5
↓
A4
↓
A3
↓
A2
↓
A1
↓
A0
↓
↓
↓
↓
↓
↓
↓
↓
TCSR 1
MR select
Operating Mode
DS
PASR
MR select
Driver Strength
Full
BA1 BA0
A7
0
0
0
0
1
1
1
1
A6
0
0
1
1
0
0
1
1
A5
0
1
0
1
0
1
0
1
Standard MR
Status Register
Extended MR
Reserved
0
0
1
1
0
1
0
1
Half
Quarter
Three-Quarters
Three-Quarters
Reserved
Reserved
Reserved
PASR
A2
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
All banks
0
0
0
0
1
1
1
1
Half array(BA1=0)
1/4 array(BA1=BA0=0)
Reserved
Reserved
Reserved
Reserved
Reserved
A13-A9
Operating Mode
Normal Operation
All other states reserved
A8
0
-
0
-
NOTE 1: On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
NOTE 2: A logic 0 should be programmed to all unused / undefined address bits to ensure future compatibility.
NOTE 3: Implementation and availability of Three-Quarters Strength Driver is optional for speed bins LPDDR333 and below.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Status Read Register (SRR)
NOTES:
1. Reserved bits should be set to zero for future compatibility.
2. Refresh multiplier is based on the memory device’s on-board temperature sensor. Required average periodic refresh interval =
tREFI x multiplier.
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
Revision History
Rev
1.0
Page
Modified
Description
Released
-
-
Preliminary Release
07/2014
1.1
-
-
Add ballout and P/N: NM2281NSMAXBH-3T.
New
06/2015
04/2016
Power-on/off sequence
& Timing Diagrams
1.2
P30-49
P5-7
(1) Modify NOTE 1.
(2) Modify L4, N1 to NC (was: RFU)
Ball Assignment
1.3
06/2016
RY/ : termination for
the Ready/Busy pin
P28
New
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NM2281K(N)SMAXBH
NM22F1NSMAXBH
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