D485505G [NEC]
LINE BUFFER 5K-WORD BY 8-BIT; 行缓冲器5K - WORD ×8位
| 型号： | D485505G |
| 厂家： | 
NEC |
| 描述： | LINE BUFFER 5K-WORD BY 8-BIT |
| 文件： | 总20页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD485505
LINE BUFFER
5K-WORD BY 8-BIT
Description
The µPD485505 is a 5,048 words by 8 bits high speed FIFO (First In First Out) line buffer. Its CMOS static circuitry
provides high speed access and low power consumption.
The µPD485505 can be used for one line delay and time axis conversion in high speed facsimile machines and
digital copiers.
Moreover, the µPD485505 can execute read and write operations independently on an asynchronous basis. Thus
the µPD485505 is suitable as a buffer for data transfer between units with different transfer rates and as a buffer for
the synchronization of multiple input signals. There are three versions, E, K, P, and L. This data sheet can be applied
to the version P and L. These versions operate with different specifications. Each version is identified with its lot
number (refer to 7. Example of Stamping).
Features
•
•
•
5,048 words by 8 bits
Asynchronous read/write operations available
Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns)
15 to 5,048 bits (Cycle time: 35 ns)
•
•
•
•
•
Power supply voltage VCC = 5.0 V ± 0.5 V
Suitable for sampling one line of A3 size paper (16 dots/mm)
All input/output TTL compatible
3-state output
Full static operation; data hold time = infinity
Ordering Information
Part Number
µPD485505G-25
µPD485505G-35
R/W Cycle Time
Package
25 ns
35 ns
24-pin plastic SOP
(11.43 mm (450))
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. M10059EJ7V0DSJ1 (7th edition)
Date Published December 2000 N CP(K)
Printed in Japan
The mark shows major revised points.
1994,1996
©
µPD485505
Pin Configuration (Marking side)
24-pin plastic SOP (11.43 mm (450))
[µPD485505G]
D
D
D
D
OUT0
OUT1
OUT2
OUT3
RE
1
24
23
22
21
20
19
18
17
16
15
14
13
D
D
D
D
IN0
IN1
IN2
IN3
2
3
4
5
WE
RSTR
GND
RCK
6
RSTW
7
V
CC
8
WCK
DOUT4
DOUT5
DOUT6
DOUT7
9
DIN4
DIN5
DIN6
DIN7
10
11
12
DIN0 - DIN7
: Data Inputs
DOUT0 - DOUT7 : Data Outputs
WCK
RCK
WE
: Write Clock Input
: Read Clock Input
: Write Enable Input
: Read Enable Input
: Reset Write Input
: Reset Read Input
: +5.0 V Power Supply
: Ground
RE
RSTW
RSTR
VCC
GND
Remark Refer to 5. Package Drawing for the 1-pin index mark.
2
Data Sheet M10059EJ7V0DS00
µPD485505
Block Diagram
V
CC
GND
WCK
RSTW
RE
Write Address Pointer
DIN0
DIN1
DIN2
DIN3
DIN4
DIN5
DIN6
DIN7
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
Memory Cell Array
40,384 bits
(5,048 words by 8 bits)
WE
Read Address Pointer
RCK
RSTR
Data Sheet M10059EJ7V0DS00
3
µPD485505
1. Input/Output Pin Function
Pin
I/O
In
Function
Pin
Pin
Symbol
Number
Name
Write data input pins.
24 - 21
DIN0
|
Data
Input
The data inputs are strobed by the rising edge of WCK at the end of a cycle
and the setup and hold times (tDS, tDH) are defined at this point.
16 - 13
1 - 4
DIN7
Out
In
Read data output pins.
DOUT0
Data
Output
|
The access time is regulated from the rising edge of RCK at the beginning of a
cycle and defined by tAC.
9 - 12
19
DOUT7
RSTW
Reset
Write
Input
Reset input pin for the initialization of the write address pointer.
The state of RSTW is strobed by the rising edge of WCK at the beginning of a
cycle and the setup and hold times (tRS, tRH) are defined.
6
20
5
RSTR
WE
Reset
Read
Input
In
Reset input pin for the initialization of the read address pointer.
The state of RSTR is strobed by the rising edge of RCK at the beginning of a
cycle and the setup and hold times (tRS, tRH) are defined.
Write
Enable
Input
In
Write operation control signal input pin.
When WE is in the disable mode (“H” level), the internal write operation is
inhibited and the write address pointer stops at the current position.
RE
Read
Enable
Input
In
Read operation control signal input pin.
When RE is in the disable mode (“H” level), the internal read operation is
inhibited and the read address pointer stops at the current position. The output
changes to high impedance.
17
8
WCK
RCK
Write
Clock
Input
In
In
Write clock input pin.
When WE is enabled (“L” level), the write operation is executed in
synchronization with the write clock. The write address pointer is incremented
simultaneously.
Read
Clock
Input
Read clock input pin.
When RE is enabled (“L” level), the read operation is executed in synchroniza-
tion with the read clock. The read address pointer is incremented
simultaneously.
4
Data Sheet M10059EJ7V0DS00
µPD485505
2. Operation Mode
µPD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
2.1 Write Cycle
When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock
input.
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-
line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart.
When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which
the WCK rising edge is in the WE = “H” level (tWEW). The WCK does not increment the write address pointer
at this time.
Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin
incrementing again.
2.2 Read Cycle
When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input
and data is output after tAC. Refer to Read Cycle Timing Chart.
When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which
the RCK rising edge is in the RE = “H” level (tREW). The RCK does not increment the read address pointer at
this time.
2.3 Write Reset Cycle/Read Reset Cycle
After power up, the µPD485505 requires the initialization of internal circuits because the read and write
address pointers are not defined at that time.
It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and
RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write
Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.
Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.
Data Sheet M10059EJ7V0DS00
5
µPD485505
Operation-related Restriction
Following restriction exists to read data written in a write cycle.
Read the written data after an elapse of 1/2 write cycle + tWAR since the write cycle ends (see Figure 2.1).
If tWAR is not satisfied, the output data may undefined.
Figure 2.1 Delay Bits Restriction Timing Chart
0
1
2
3
WCK
RCK
1/2 write cycle
t
WAR
0
1
2
High
impedance
0
1
2
3
DIN
t
AC
High impedance
DOUT
0
1
2
3
Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR
signals.
6
Data Sheet M10059EJ7V0DS00
µPD485505
3. Electrical Specifications
All voltages are referenced to GND.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to GND
Supply voltage
Symbol
VT
Condition
Rating
Unit
Note
–0.5
to VCC + 0.5
V
V
VCC
IO
–0.5 to +7.0
20
Output current
mA
˚C
˚C
Operating ambient temperature
Storage temperature
TA
0 to 70
Tstg
–55 to +125
Note –3.0 V MIN. (Pulse width = 10 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
VIH
Condition
MIN.
4.5
TYP.
5.0
MAX.
5.5
Unit
V
High level input voltage
Low level input voltage
Operating ambient temperature
2.4
VCC + 0.5
+0.8
V
Note
VIL
–0.3
V
TA
0
70
˚C
Note –3.0 V MIN. (Pulse width = 10 ns)
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
Test Condition
MIN.
TYP.
MAX.
80
Unit
mA
Operating current
ICC
Input leakage current
Output leakage current
II
VI = 0 to VCC, Other Input 0 V
VO = 0 to VCC,
–10
–10
+10
+10
µA
µA
IO
DOUT: High impedance
High level output voltage
Low level output voltage
VOH
VOL
IOH = –1 mA
IOL = 2 mA
2.4
V
V
0.4
Capacitance (TA = 25 ˚C, f = 1 MHz)
Parameter
Input capacitance
Output capacitance
Symbol
CI
Test Condition
MIN.
TYP.
MAX.
10
Unit
pF
CO
10
pF
Data Sheet M10059EJ7V0DS00
7
µPD485505
AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3
µPD485505-25
µPD485505-35
Parameter
Symbol
Unit
Notes
MIN.
25
MAX.
MIN.
35
MAX.
Write clock cycle time
Write clock pulse width
Write clock precharge time
Read clock cycle time
Read clock pulse width
Read clock precharge time
Access time
tWCK
tWCW
tWCP
tRCK
tRCW
tRCP
tAC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
ms
ns
11
12
11
12
25
35
11
12
11
12
18
25
Write data-read delay time
Output hold time
tWAR
tOH
470
5
5
5
7
3
7
3
3
7
7
3
3
7
7
3
3
7
0
0
0
0
3
470
5
Output low-impedance time
Output high-impedance time
Input data setup time
Input data hold time
RSTW/RSTR Setup time
RSTW/RSTR Hold time
RSTW/RSTR Deselected time (1)
RSTW/RSTR Deselected time (2)
WE Setup time
tLZ
18
18
5
25
25
4
4
tHZ
5
tDS
10
3
tDH
tRS
10
3
5
5
tRH
tRN1
tRN2
tWES
tWEH
tWEN1
tWEN2
tRES
tREH
tREN1
tREN2
tWEW
tREW
tRSTW
tRSTR
tT
3
6
10
10
3
6
7
WE Hold time
7
WE Deselected time (1)
WE Deselected time (2)
RE Setup time
3
8
10
10
3
8
9
RE Hold time
9
RE Deselected time (1)
RE Deselected time (2)
WE Disable time
3
10
10
10
0
RE Disable time
0
Write reset time
0
Read reset time
0
Transition time
35
3
35
8
Data Sheet M10059EJ7V0DS00
µPD485505
Notes 1. AC measurements assume tT = 5 ns.
2. AC Characteristics test condition
Input Timing Specification
3.0 V
1.5 V
0 V
Test points
t
T
= 5 ns
t
T
= 5 ns
Output Timing Specification
2.0 V
0.8 V
High impedance
High impedance
Test points
Output Loads for Timing
VCC
VCC
1.8 kΩ
1.8 kΩ
DOUT
DOUT
1.1 kΩ
1.1 kΩ
30 pF
5 pF
(tAC, tOH)
(tLZ, tHZ)
3. Input timing reference levels = 1.5 V. Output timing reference levels; VOH = 2.0 V, VOL = 0.8 V.
4. tLZ and tHZ are measured at ±200 mV from the steady state voltage. Under any conditions, tLZ ≥ tHZ
5. If either tRS or tRH is less than the specified value, reset operations are not guaranteed.
.
6. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding or
following the period of reset operations.
7. If either tWES or tWEH is less than the specified value, write disable operations are not guaranteed.
8. If either tWEN1 or tWEN2 is less than the specified value, internal write disable operations may extend to cycles
preceding or following the period of write disable operations.
9. If either tRES or tREH is less than the specified value, read disable operations are not guaranteed.
10. If either tREN1 or tREN2 is less than the specified value, internal read disable operations may extend to cycles
preceding or following the period of read disable operations.
Data Sheet M10059EJ7V0DS00
9
µPD485505
Write Cycle Timing Chart
Cycle n
Cycle n+1
Cycle n+2
Disable Cycle
Cycle n+3
t
WCK
t
WCP
WCK (Input)
WE (Input)
tWCW
t
WEN1
t
WES
t
WEH
t
WEN2
t
WEW
t
DS
t
DH
t
DS
t
DH
D
IN (Input)
(n)
(n+1)
(n+2)
(n+3)
Remark RSTW = “H” level
Read Cycle Timing Chart
Cycle n
Cycle n+1
Cycle n+2
Disable Cycle
Cycle n+3
t
RCK
t
RCP
RCK (Input)
RE (Input)
t
RCW
t
REN1
t
RES
t
REH
t
REN2
t
OH
t
AC
t
REW
tAC
t
LZ
t
HZ
t
LZ
High impedance
High impedance
DOUT (Output)
(n)
(n+1)
(n+2)
(n+3)
Remark RSTR = “H” level
10
Data Sheet M10059EJ7V0DS00
µPD485505
Write Reset Cycle Timing Chart (WE = Active)
Cycle n
Reset Cycle
Cycle 0
Cycle 1
WCK (Input)
Note
t
RN1
t
RS
t
RSTW
t
RH
tRN2
RSTW (Input)
WE (Input)
“L” Level
(n–1)
tDS
t
DH
t
DS
t
DH
(n)
(0)
(1)
D
IN (Input)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
Write Reset Cycle Timing Chart (WE = Inactive)
Cycle n
Disable Cycle
Cycle 0
Reset Cycle
WCK (Input)
Note
t
RH
t
RS
t
RN1
t
RSTW
t
RN2
RSTW (Input)
WE (Input)
t
WEH
t
WEN2
t
WEN1
t
WES
t
WEW
t
DS
t
DS
t
DH
(n)
(n–1)
(0)
DIN (Input)
Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW).
WCK can be input any number of times in a reset cycle.
Data Sheet M10059EJ7V0DS00
11
µPD485505
Read Reset Cycle Timing Chart (RE = Active)
Cycle n
Reset Cycle
Cycle 0
Cycle 1
RCK (Input)
Note
RSTR
t
RN2
t
RH
t
t
RS
t
RN1
RSTR (Input)
RE (Input)
“L” Level
t
AC
t
AC
t
AC
t
AC
(n–1)
(1)
DOUT (Output)
(n)
(0)
(0)
t
OH
t
OH
t
OH
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
Read Reset Cycle Timing Chart (RE = Inactive)
Cycle n
Disable Cycle
Cycle 0
Reset Cycle
RCK (Input)
Note
tRN2
tRH
tRSTR
tRS
tRN1
RSTR (Input)
tRES
tREN1
tREH
tREN2
RE (Input)
tREW
tAC
tAC
tHZ
tLZ
High impedance
(n–1)
DOUT (Output)
(n)
(0)
tOH
tOH
Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR).
RCK can be input any number of times in a reset cycle.
12
Data Sheet M10059EJ7V0DS00
µPD485505
4. Application
4.1 1 H Delay Line
µPD485505 easily allows a 1 H (5,048 bits) delay line (see Figure 4.1).
Figure 4.1 1 H Delay Line Circuit
40 MHz Clock
Reset
WCK
RCK
Data Input
Data Output
8
DIN
DOUT
8
WE
RSTW
RE
RSTR
Figure 4.2 1 H Delay Line Timing Chart
1 H
2 H
(5,048 Cycles)
(5,048 Cycles)
t
t
WCK
RCK
Cycle 0
Cycle 1
Cycle 2
Cycle 5,047
Cycle 0’
Cycle 0
Cycle 1’
Cycle 2’
Cycle 2
Cycle 3’
Cycle 3
Write
Read
Cycle 1
t
t
WCW
RCW
t
t
WCP
RCP
WCK/RCK
(Input)
t
RS
t
RH
RSTW /
RSTR
t
DS
t
DS
(Input)
t
DH
t
DH
D
IN
(0)
(1)
(2)
(5,046)
(5,047)
(0’)
(1’)
(2’)
(3’)
(Input)
t
AC
t
OH
D
OUT
(0)
(1)
(2)
(3)
(Output)
Remark RE, WE = “L” level
Data Sheet M10059EJ7V0DS00
13
µPD485505
4.2 n Bit Delay
It is possible to make delay read from the write data with the µPD485505.
(1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3)
(2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length. (Figure 4.4)
(3) Shift the address by disabling RE for the period proportionate to the delay length. (Figure 4.5)
n bit: Delay bits from write cycle to read cycle correspond to a same address cell.
Restrictions
Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer
to 2. Operation Mode Operation-related Restriction.
Cycle time
25 ns
MIN.
MAX.
21 bits
15 bits
5,048 bits
5,048 bits
35 ns
Figure 4.3 n-Bit Delay Line Timing Chart (1)
1 H
2 H
(n Cycles)
(n Cycles)
t
t
WCK
RCK
Cycle 0
Cycle 1
Cycle 2
Cycle n–1
Cycle 0’
Cycle 0
Cycle 1’
Cycle 1
Cycle 2’
Cycle 2
Cycle 3’
Cycle 3
Write
Read
t
t
WCW
t
t
WCP
RCP
RCW
WCK/RCK
(Input)
t
RS
t
RS
t
RH
t
RH
RSTW /
RSTR
(Input)
t
DS
t
DS
t
WAR
t
DH
t
DH
D
IN
(0)
(1)
(2)
(n–2)
(n–1)
(0’)
(1’)
(2’)
(3’)
(Input)
t
AC
t
OH
D
OUT
(0)
(1)
(2)
(3)
(Output)
Remark RE, WE = “L” level
14
Data Sheet M10059EJ7V0DS00
µPD485505
Figure 4.4 n-Bit Delay Line Timing Chart (2)
t
t
WCK
RCK
Cycle 0
Cycle 1
Cycle 2
Cycle n
Cycle 0
Cycle n+1 Cycle n+2 Cycle n+3
Cycle n–1
Write
Read
Cycle 1
Cycle 2
Cycle 3
t
t
WCW
RCW
t
t
WCP
RCP
WCK/RCK
(Input)
t
RS
t
WAR
t
RH
t
RS
RSTW
(Input)
t
RH
RSTR
(Input)
tDS
t
DS
t
DH
t
DH
D
IN
(0)
(1)
n Cycles
(2)
(n–2)
(n–1)
(n)
(n+1)
(n+2)
(n+3)
(Input)
t
AC
t
OH
D
OUT
(0)
(1)
(2)
(3)
(Output)
Remark RE, WE = “L” level
Figure 4.5 n-Bit Delay Line Timing Chart (3)
t
t
WCK
RCK
Cycle 0
Cycle 1
Cycle 2
Cycle n
Cycle 0
Cycle n+1 Cycle n+2 Cycle n+3
Cycle 1 Cycle 2 Cycle 3
Cycle n–1
Write
Read
t
t
WCW
RCW
t
t
WCP
RCP
WCK/RCK
(Input)
t
RS
t
WAR
t
RH
RSTW/
RSTR
(Input)
t
REH
t
REN2
RE
(Input)
t
DS
t
DS
t
DH
t
DH
D
IN
(0)
(1)
n Cycles
(2)
(n–2)
(n–1)
(n)
(n+1)
(n+2)
(n+3)
(Input)
t
AC
t
OH
High impedance
D
OUT
(0)
(1)
(2)
(3)
(Output)
Remark WE = “L” level
Data Sheet M10059EJ7V0DS00
15
µPD485505
4.3 Double-speed Conversion
Figure 4.6 shows an example timing chart of double-speed and twice reading operation (fR = 2fW, 5,048 by
2 cycle) for a write operation (fW = 5,048 cycle).
Caution The read operation collide with the write operation on the same line, last n bits output data
(5,048–n to 5,048) in the first read operation will be undefined (see Figure 4.6 Double-speed
Conversion Timing Chart).
Undefined bits mentioned above depend on the cycle time.
Read cycle time
25 ns
Undefined bits
21 bits
35 ns
15 bits
Figure 4.6 Double-speed Conversion Timing Chart
1H
2H
(5,048 Cycle)
(5,048 Cycle)
0
1
2
5046 5047
0'
1'
2'
5046' 5047' 0"
WCK
(Input)
RSTW
(Input)
D
IN
0
1
2
5046 5047 0'
1'
2'
5046' 5047'
0"
(Input)
1H
1H
(5,048 Cycle)
Second read cycle
2H
(5,048 Cycle)
First read cycle
(5,048 Cycle)
First read cycle
RCK
(Input)
RSTR
(Input)
t
AC
D
OUT
5046 5047
5046 5047
5046' 5047'
0' 1'
0
1
2
0
1
2
0' 1' 2'
(Output)
n bits output data will be undefined.
n bits output data will be undefined.
Remark RE, WE = “L” level
16
Data Sheet M10059EJ7V0DS00
µPD485505
5. Package Drawing
24-PIN PLASTIC SOP (11.43 mm (450))
24
13
detail of lead end
P
1
12
A
F
H
I
G
J
S
B
L
C
N
S
M
D
M
K
E
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
E
F
G
H
I
15.5±0.2
1.27 MAX.
1.27 (T.P.)
0.42±0.08
0.1±0.1
2.1±0.2
2.0
12.2±0.3
8.4±0.2
1.9±0.2
J
+0.08
0.17
K
−0.07
L
M
N
P
0.9±0.2
0.12
0.10
5°±5°
P24GM-50-450A-4
Data Sheet M10059EJ7V0DS00
17
µPD485505
6. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the µPD485505.
Type of Surface Mount Device
µPD485505G: 24-pin plastic SOP (11.43 mm (450))
7. Example of Stamping
Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version
P, and letter L, version L.
JAPAN
D485505
Lot number
18
Data Sheet M10059EJ7V0DS00
µPD485505
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and trans-
ported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input
levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to VDD or GND with a resistor, if it is considered to have a
possibility of being an output pin. All handling related to the unused pins must be judged device
by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until
the reset signal is received. Reset operation must be executed immediately after power-on for
devices having reset function.
Data Sheet M10059EJ7V0DS00
19
µPD485505
[MEMO]
•
The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
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redundancy, fire-containment, and anti-failure features.
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Customers must check the quality grade of each semiconductor product before using it in a particular
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"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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