MC-24222311F9-E85X-CD5 [NEC]
IC,MIXED MEMORY,FLASH+SRAM,HYBRID,BGA,85PIN,PLASTIC;
| 型号： | MC-24222311F9-E85X-CD5 |
| 厂家： | 
NEC |
| 描述： | IC,MIXED MEMORY,FLASH+SRAM,HYBRID,BGA,85PIN,PLASTIC 静态存储器 内存集成电路 |
| 文件： | 总40页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
MC-24222311-X
MCP (MULTI-CHIP PACKAGE) FLASH MEMORY AND MOBILE SPECIFIED RAM
64M-BIT FLASH MEMORY AND 32M-BIT MOBILE SPECIFIED RAM
Description
The MC-24222311-X is a stacked type MCP (Multi-Chip Package) of 67,108,864 bits (4,194,304 words by 16 bits)
Flash Memory and 33,554,432 bits (2,097,152 words by 16 bits) Mobile Specified RAM.
The MC-24222311-X is packaged in 85-pin TAPE FBGA.
Features
General Features
• Fast access time : tACC = 85 ns (MAX.) (Flash Memory)
tAA = 85 ns (MAX.) (Mobile Specified RAM)
• Supply voltage : 1.65 to 1.95 V (Chip) / 2.7 to 3.3 V (I/O) (Flash Memory), 2.7 to 3.1 V (Mobile Specified RAM)
• Output Enable input for easy application
• Wide operating temperature : TA = −25 to +85 °C
Flash Memory Features
• Four bank organization enabling simultaneous execution of program / erase and read
• High-speed read with page mode
• Bank organization : 4 banks (8M bits + 24M bits + 24M bits + 8M bits)
• Memory organization : 4,194,304 words × 16 bits
• Sector organization :
142 sectors (4K words × 16 sectors, 32K words × 126 sectors)
Boot sector allocated to the highest address (sector) and lowest address (sector)
• 3-state output
• Automatic program
• Program suspend / resume
• Unlock bypass program
• Automatic erase
• Chip erase
• Sector erase (sectors can be combined freely)
• Erase suspend / resume
• Program / Erase completion detection
• Detection through data polling and toggle bits
• Detection through RY (/BY) pin
• Sector group protection
• Any sector group can be protected
• Any protected sector group can be temporary unprotected
• Any sector group can be unprotected
• Sectors can be used for boot application
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M15820EJ3V0DS00 (3rd edition)
The mark shows major revised points.
Date Published February 2003 NS CP (K)
Printed in Japan
2001
MC-24222311-X
• Hardware reset and standby using /RESET pin
• Automatic sleep mode
• Boot block sector protect by /WP (ACC) pin
• Extra One Time Protect Sector provided
• Program / erase time
• Program : 11.0 µs / word (TYP.)
• Sector erase :
Program / erase cycle : 100,000 cycles
0.15 s (TYP.) (4K words sector), 0.5 s (TYP.) (32K words sector)
Program / erase cycle : 300,000 cycles
0.5 s (TYP.) (4K words sector), 0.7 s (TYP.) (32K words sector)
• Program / erase cycle : 300,000 cycles (MIN.)
Mobile Specified RAM Features
• Corresponded page read operation
• Memory organization : 2,097,152 words by 16 bits
• Supply current :At operating : 35 mA (MAX.)
At Standby Mode 1 : 100 µA (MAX.)
At Standby Mode 2 : 10 µA (MAX.) (Memory cell data hold invalid)
• Chip Enable inputs : /CEm pin
• Byte data control : /LB, /UB pin
• Standby Mode input : MODE pin
• Standby Mode 1 : Normal standby (Memory cell data hold valid)
• Standby Mode 2 : Density of memory cell data hole is variable (16M bits, 8M bits, 4M bits and 0M bit)
Preliminary Data Sheet M15820EJ3V0DS
2
MC-24222311-X
Ordering Information
Part number
Flash Memory Mobile Specified
access time RAM access time
Operating supply voltage
V
Package
Mounted
Flash Memory
ns (MAX.)
85
ns (MAX.)
85
Chip
I/O
MC-24222311F9-E85X-CD5
1.65 to 1.95
(Flash Memory)
2.7 to 3.1
2.7 to 3.3
85-pin TAPE µPD29F064115-X
(Flash memory) FBGA
(11 x 8)
(Mobile Specified RAM)
COMMANDS, HARDWARE SEQUENCE FLAGS, HARD WARE DATA PROTECTION, READ MODE REGISTER
SETTINGS, TIMING CHARTS and FLOW CHARTS for Flash Memory, refer to PAGE MODE FLASH MEMORY,
BURST MODE FLASH MEMORY Information (M15451E).
TIMING CHARTS OF MOBILE SPECIFIED RAM FOR MCP, refer to SRAM AND MOBILE SPECIFIED RAM
TAIMING CHARTS FOR MCP Information (M15819E).
Preliminary Data Sheet M15820EJ3V0DS
3
MC-24222311-X
Pin Configuration
/xxx indicates active low signal.
85-pin TAPE FBGA (11 × 8)
Top View
Bottom View
10
9
8
7
6
5
4
3
2
1
M
L K J H G F E D C B A
A
B
B
C
D
E
C
F G H J K L M
Top View
A
D
E
F
G
H
J
K
L
M
10
9
8
7
6
5
4
3
2
1
NC
NC
NC
NC
NC
NC
NC
A16
NC
NC
NC
NC
NC
A15
A12
A21
A13
A9
NC
I/O15
I/O13
I/O4
I/O3
I/O9
/OE
Vss
I/O7
NC
NC
A11
A8
A14
A10
I/O14
I/O5
A19
I/O6
I/O12
NC
NC
NC
NC
/WE
MODE
A20
V
CCm
VCCQf
/WP(ACC) /RESET RY(/BY)
VCC
f
I/O11
I/O2
I/O8
/LB
A7
/UB
A6
A18
A5
A17
A4
I/O1
Vss
A0
I/O10
I/O0
NC
NC
NC
NC
NC
NC
A3
A2
A1
/CEf
/CEm
NC
NC
NC
NC
NC
NC
NC
Common Pins
A0 to A20 : Address Inputs
I/O0 to I/O15: Data Inputs / Outputs
Flash Memory Pins
A21
: Address Inputs
/CEf
: Chip Enable Input
/OE
: Output Enable Input
: Write Enable Input
: Ground
RY (/BY)
/RESET
: Ready (Busy) Output
: Hardware Reset Input
/WE
VSS
/WP (ACC) : Hardware Write Protect (Acceleration) Input
NC Note
: No Connection
VCCf
: Supply Voltage
VCCQf
: Input / Output Supply Voltage
Mobile Specified RAM Pins
/CEm : Chip Enable Input
MODE : Standby Mode Select Input
/LB, /UB : Byte Data Select Input
VCCm
: Supply Voltage
Note Some signals can be applied because this pin is not internally connected.
Remark Refer to 10. Package Drawing for the index mark.
Preliminary Data Sheet M15820EJ3V0DS
4
MC-24222311-X
Block Diagram
V
CCf
V
SS
V
CCQf
A0 to A21
A0 to A21
/RESET
/CEf
RY (/BY)
64 M-bit Flash Memory
(4,194,304 words by 16 bits)
/WP(ACC)
V
CCm
V
SS
I/O0 to I/O15
A0 to A20
32 M-bit Mobile Specified RAM
(2,097,152 words by 16 bits)
/WE
/OE
/CEm
MODE
/LB
/UB
Preliminary Data Sheet M15820EJ3V0DS
5
MC-24222311-X
CONTENTS
1. Bus Operations........................................................................................................................................................7
2. Sector Organization / Sector Address Table (Flash Memory) .............................................................................8
3. Sector Group Address Table (Flash Memory) ....................................................................................................12
4. Commands (Flash Memory) .................................................................................................................................14
5. Initialization (Mobile Specified RAM)...................................................................................................................16
6. Partial Refresh (Mobile Specified RAM) ..............................................................................................................17
6.1 Standby Mode ...............................................................................................................................................17
6.2 Density Switching.........................................................................................................................................17
6.3 Standby Mode Status Transition .................................................................................................................17
6.4 Addresses for Which Partial Refresh Is Supported...................................................................................18
7. Page Read Operation (Mobile Specified RAM) ...................................................................................................19
7.1 Features of Page Read Operation ...............................................................................................................19
7.2 Page Length ..................................................................................................................................................19
7.3 Page-Corresponding Addresses .................................................................................................................19
7.4 Page Start Address.......................................................................................................................................19
7.5 Page Direction...............................................................................................................................................19
7.6 Interrupt during Page Read Operation........................................................................................................19
7.7 Eight-Word Start Page Read Operation Prohibition ..................................................................................19
7.8 Cautions for Eight-Word Page Read Operation .........................................................................................20
8. Mode Register Settings (Mobile Specified RAM)................................................................................................21
8.1 Mode Register Setting Method ....................................................................................................................21
8.2 Cautions for Setting Mode Register............................................................................................................22
9. Electrical Specifications.......................................................................................................................................23
10. Package Drawing ..................................................................................................................................................35
11. Recommended Soldering Conditions .................................................................................................................36
12. Related Documents...............................................................................................................................................36
13. Revision History....................................................................................................................................................37
Preliminary Data Sheet M15820EJ3V0DS
6
MC-24222311-X
1. Bus Operations
Table 1-1. Bus Operations
Operation
Flash Memory
Mobile Specified RAM
/UB
Common
/RESET
H
/CEf /WP(ACC) /CEm MODE /LB
/OE /WE I/O0 to I/O7 I/O8 to I/O15
Full Standby
Standby Mode 1
Standby Mode 2 Note 1
H
L
×
×
H
H
L
H
L
×
×
×
×
High-Z
High-Z
Output Disable
Flash Memory
Word Read Note 2
Word Write
H
H
×
×
H
H
High-Z
High-Z
H
H
L
L
×
×
×
×
Note 3
Note 3
Note 3
L
H
×
H
L
×
Data Out
Data In
Data Out
Data In
Temporary Sector Group Unprotect
VID
High-Z or
High-Z or
Data In/Out Data In/Out
Automatic Sleep Mode
H
L
×
Note 3
L
H
Data Out
High-Z or
Data Out
High-Z or
Boot Block Sector Protect
×
×
L
×
×
×
×
×
×
×
Data In/Out Data In/Out
High-Z or High-Z or
Data In/Out Data In/Out
Accelerated Mode
H
L
×
×
VACC
Note 3
×
×
×
×
Hardware Reset
Mobile Specified RAM
Word Read
×
×
×
×
High-Z
High-Z
Note 4
Note 4
L
H
H
L
L
H
L
L
H
L
Data Out
Data Out
High-Z
Lower byte read
Upper byte read
Word Write
H
L
High-Z
Data In
Data Out
Data In
High-Z
L
L
×
Lower byte read
Upper byte read
H
L
H
High-Z
Data In
Caution Other operations except for indicated in this table are inhibited.
Notes 1. During normal operation, make /CEm = VIH, MODE = VIL, the device enters the Standby Mode 2. However,
make /CEm = VIH or VIL, and MODE = VIL at power application, the device enters the Standby Mode2.
2. When /OE = VIL, VIL can be applied to /WE. When /OE = VIH, a write operation is started. When /WE = VIL
and /OE = VIL, a write operation is started.
3. Mobile Specified RAM should be Standby.
4. Flash Memory should be Standby or Hardware reset.
Remarks 1. H : VIH, L : VIL, × : VIH or VIL, VID : 9.0 to 11.0 V, VACC : 8.5 to 9.5 V
2. Sector group protection and read the product ID are using a command.
3. MODE pin must be fixed to H during active operation.
4. If an address is held longer than the minimum read cycle time (tRC) in the flash memory read mode,
the automatic sleep mode is set.
Preliminary Data Sheet M15820EJ3V0DS
7
MC-24222311-X
2. Sector Organization / Sector Address Table (Flash Memory)
(1/4)
Bank
Sector
Organization
K words
4
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank D
3FFFFFH
3FF000H
SA141
SA140
SA139
SA138
SA137
SA136
SA135
SA134
SA133
SA132
SA131
SA130
SA129
SA128
SA127
SA126
SA125
SA124
SA123
SA122
SA121
SA120
SA119
SA118
SA117
SA116
SA115
SA114
SA113
SA112
SA111
SA110
SA109
SA108
SA107
SA106
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
1
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
3FEFFFH
3FE000H
4
3FDFFFH
3FD000H
4
3FCFFFH
3FC000H
4
3FBFFFH
3FB000H
4
3FAFFFH
3FA000H
4
3F9FFFH
3F9000H
4
3F8FFFH
3F8000H
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
3F7FFFH
3F0000H
3EFFFFH
3E8000H
3E7FFFH
3E0000H
3DFFFFH
3D8000H
3D7FFFH
3D0000H
3CFFFFH
3C8000H
3C7FFFH
3C0000H
3B7FFFH
3B8000H
3B7FFFH
3B0000H
3AFFFFH
3A8000H
3A7FFFH
3A0000H
39FFFFH
398000H
397FFFH
390000H
38FFFFH
388000H
387FFFH
380000H
Bank C
37FFFFH
378000H
377FFFH
370000H
36FFFFH
368000H
367FFFH
360000H
35FFFFH
358000H
357FFFH
350000H
34FFFFH
348000H
347FFFH
340000H
33FFFFH
338000H
337FFFH
330000H
32FFFFH
328000H
327FFFH
320000H
31FFFFH
318000H
Preliminary Data Sheet M15820EJ3V0DS
8
MC-24222311-X
(2/4)
Bank
Sector
Organization
K words
32
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank C
317FFFH
310000H
SA105
SA104
SA103
SA102
SA101
SA100
SA99
SA98
SA97
SA96
SA95
SA94
SA93
SA92
SA91
SA90
SA89
SA88
SA87
SA86
SA85
SA84
SA83
SA82
SA81
SA80
SA79
SA78
SA77
SA76
SA75
SA74
SA73
SA72
SA71
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
30FFFFH
308000H
307FFFH
300000H
2FFFFFH
2F8000H
2F7FFFH
2F0000H
2EFFFFH
2E8000H
2E7FFFH
2E0000H
2DFFFFH
2D8000H
2D7FFFH
2D0000H
2CFFFFH
2C8000H
2C7FFFH
2C0000H
2BFFFFH
2B8000H
2B7FFFH
2B0000H
2AFFFFH
2A8000H
2A7FFFH
2A0000H
29FFFFH
298000H
297FFFH
290000H
28FFFFH
288000H
287FFFH
280000H
27FFFFH
278000H
277FFFH
270000H
26FFFFH
268000H
267FFFH
260000H
25FFFFH
258000H
257FFFH
250000H
24FFFFH
248000H
247FFFH
240000H
23FFFFH
238000H
237FFFH
230000H
22FFFFH
228000H
227FFFH
220000H
21FFFFH
218000H
217FFFH
210000H
20FFFFH
208000H
207FFFH
200000H
Preliminary Data Sheet M15820EJ3V0DS
9
MC-24222311-X
(3/4)
Bank
Sector
Organization
K words
32
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank B
1FFFFFH
1F8000H
SA70
SA69
SA68
SA67
SA66
SA65
SA64
SA63
SA62
SA61
SA60
SA59
SA58
SA57
SA56
SA55
SA54
SA53
SA52
SA51
SA50
SA49
SA48
SA47
SA46
SA45
SA44
SA43
SA42
SA41
SA40
SA39
SA38
SA37
SA36
SA35
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
1F7FFFH
1F0000H
1EFFFFH
1E8000H
1E7FFFH
1E0000H
1DFFFFH
1D8000H
1D7FFFH
1D0000H
1CFFFFH
1C8000H
1C7FFFH
1C0000H
1BFFFFH
1B8000H
1B7FFFH
1B0000H
1AFFFFH
1A8000H
1A7FFFH
1A0000H
19FFFFH
198000H
197FFFH
190000H
18FFFFH
188000H
187FFFH
180000H
17FFFFH
178000H
177FFFH
170000H
16FFFFH
168000H
167FFFH
160000H
15FFFFH
158000H
157FFFH
150000H
14FFFFH
148000H
147FFFH
140000H
13FFFFH
138000H
137FFFH
130000H
12FFFFH
128000H
127FFFH
120000H
11FFFFH
118000H
117FFFH
110000H
10FFFFH
108000H
107FFFH
100000H
0FFFFFH
0F8000H
0F7FFFH
0F0000H
0EFFFFH
0E8000H
0E7FFFH
0E0000H
Preliminary Data Sheet M15820EJ3V0DS
10
MC-24222311-X
(4/4)
Bank
Sector
Organization
K words
32
Address
Sectors
Address
Sector Address Table
Bank Address Table
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank B
0DFFFFH
0D8000H
SA34
SA33
SA32
SA31
SA30
SA29
SA28
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
SA19
SA18
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
SA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
1
1
0
0
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
1
0
0
1
1
0
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
1
0
1
0
1
0
1
0
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
4
0D7FFFH
0D0000H
0CFFFFH
0C8000H
0C7FFFH
0C0000H
0BFFFFH
0B8000H
0B7FFFH
0B0000H
0AFFFFH
0A8000H
0A7FFFH
0A0000H
09FFFFH
098000H
097FFFH
090000H
08FFFFH
088000H
087FFFH
080000H
Bank A
07FFFFH
078000H
077FFFH
070000H
06FFFFH
068000H
067FFFH
060000H
05FFFFH
058000H
057FFFH
050000H
04FFFFH
048000H
047FFFH
040000H
03FFFFH
038000H
037FFFH
030000H
02FFFFH
028000H
027FFFH
020000H
01FFFFH
018000H
017FFFH
010000H
00FFFFH
008000H
SA8
007FFFH
SA7
007000H
4
006FFFH
006000H
SA6
4
005FFFH
SA5
005000H
4
004FFFH
004000H
SA4
4
003FFFH
SA3
003000H
4
002FFFH
002000H
SA2
4
001FFFH
SA1
001000H
4
000FFFH
000000H
SA0
Preliminary Data Sheet M15820EJ3V0DS
11
MC-24222311-X
3. Sector Group Address Table (Flash Memory)
(1/2)
Sector group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Size
Sector
SGA0
SGA1
SGA2
SGA3
SGA4
SGA5
SGA6
SGA7
SGA8
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
0
0
0
0
0
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
0
0
1
1
1
1
×
0
0
1
1
0
0
1
1
×
0
1
0
1
0
1
0
1
×
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
4K words (1 Sector)
96K words (3 Sectors)
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8 to SA10
SGA9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
128K words (4 Sectors) SA11 to SA14
128K words (4 Sectors) SA15 to SA18
128K words (4 Sectors) SA19 to SA22
128K words (4 Sectors) SA23 to SA26
128K words (4 Sectors) SA27 to SA30
128K words (4 Sectors) SA31 to SA34
128K words (4 Sectors) SA35 to SA38
128K words (4 Sectors) SA39 to SA42
128K words (4 Sectors) SA43 to SA46
128K words (4 Sectors) SA47 to SA50
128K words (4 Sectors) SA51 to SA54
128K words (4 Sectors) SA55 to SA58
128K words (4 Sectors) SA59 to SA62
128K words (4 Sectors) SA63 to SA66
128K words (4 Sectors) SA67 to SA70
SGA10
SGA11
SGA12
SGA13
SGA14
SGA15
SGA16
SGA17
SGA18
SGA19
SGA20
SGA21
SGA22
SGA23
Remark × : VIH or VIL
Preliminary Data Sheet M15820EJ3V0DS
12
MC-24222311-X
(2/2)
Sector group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Size
Sector
SGA24
SGA25
SGA26
SGA27
SGA28
SGA29
SGA30
SGA31
SGA32
SGA33
SGA34
SGA35
SGA36
SGA37
SGA38
SGA39
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
0
1
1
1
1
1
1
1
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
0
1
0
1
1
1
1
1
1
1
1
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
128 Kwords (4 Sectors) SA71 to SA74
128 Kwords (4 Sectors) SA75 to SA78
128 Kwords (4 Sectors) SA79 to SA82
128 Kwords (4 Sectors) SA83 to SA86
128 Kwords (4 Sectors) SA87 to SA90
128 Kwords (4 Sectors) SA91 to SA94
128 Kwords (4 Sectors) SA95 to SA98
128 Kwords (4 Sectors) SA99 to SA102
128 Kwords (4 Sectors) SA103 to SA106
128 Kwords (4 Sectors) SA107 to SA110
128 Kwords (4 Sectors) SA111 to SA114
128 Kwords (4 Sectors) SA115 to SA118
128 Kwords (4 Sectors) SA119 to SA122
128 Kwords (4 Sectors) SA123 to SA126
128 Kwords (4 Sectors) SA127 to SA130
96 Kwords (3 Sectors) SA131 to SA133
SGA40
SGA41
SGA42
SGA43
SGA44
SGA45
SGA46
SGA47
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4 Kwords (1 Sector)
4 Kwords (1 Sector)
4 Kwords (1 Sector)
4 Kwords (1 Sector)
4 Kwords (1 Sector)
4 Kwords (1 Sector)
4 Kwords (1 Sector)
4 Kwords (1 Sector)
SA134
SA135
SA136
SA137
SA138
SA139
SA140
SA141
Remark × : VIH or VIL
Product ID Code (Flash Memory)
Product ID code
Code output
I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
HEX
0010H
Manufacturer code
Device code
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
1
0
0
0
0
0
0
1
221CH
0001H Note
Sector group protection
Note If 0001H is output, the sector group is protected. If 0000H is output, the sector group is unprotected.
Preliminary Data Sheet M15820EJ3V0DS
13
MC-24222311-X
4. Commands (Flash Memory)
This sector explains the commands of the Flash Memory.
Table 4-1. Command Sequence
Command sequence
Bus
1st bus Cycle
2nd bus Cycle
3rd bus Cycle
4th bus Cycle
5th bus Cycle
6th bus Cycle
Cycle Address Data Address Data Address Data Address Data Address Data Address Data
Read / Reset Note1
Read / Reset Note1
1
3
4
1
1
6
6
1
1
3
2
2
2
2
3
×××H
555H
555H
BA
F0H
AAH
AAH
B0H
30H
AAH
AAH
B0H
30H
AAH
A0H
80H
80H
90H
AAH
RA
2AAH
2AAH
–
RD
55H
55H
–
–
555H
555H
–
–
F0H
A0H
–
–
RA
PA
–
–
RD
PD
–
–
–
–
–
–
–
–
–
Program
–
–
–
–
Program Suspend Note 2
Program Resume Note 3
Chip Erase
–
–
–
–
BA
–
–
–
–
–
–
–
–
–
–
555H
555H
BA
2AAH
2AAH
–
55H
55H
–
555H
555H
–
80H
80H
–
555H
555H
–
AAH
AAH
–
2AAH
55H
55H
–
555H
10H
30H
–
Sector Erase
2AAH
SA
–
Sector Erase Suspend Note 4, 5
Sector Erase Resume Note 4, 6
Unlock Bypass Set
Unlock Bypass Program Note 7
Unlock Bypass Chip Erase Note 7
Unlock Bypass Sector Erase Note 7
Unlock Bypass Reset Note 7
Product ID / Sector Group Protection
Information / Read Mode Register
Information
–
–
–
–
–
–
–
–
BA
–
–
–
–
–
–
–
–
–
555H
×××H
×××H
×××H
×××H
555H
2AAH
PA
55H
PD
10H
30H
555H
–
20H
–
–
–
–
–
–
–
–
–
–
–
×××H
SA
×××H 00HNote11
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2AAH
55H
(BA)
555H
90H
IA
ID
–
–
–
Sector Group Protection Note 8
Sector Group Unprotect Note 9
Extra One Time Protect Sector Entry
Extra One Time Protect
Sector Reset Note 10
4
4
3
4
×××H
×××H
555H
555H
60H
60H
AAH
AAH
SPA
SUA
60H
60H
55H
55H
SPA
SUA
555H
555H
40H
40H
88H
90H
SPA
SUA
–
SD
SD
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
2AAH
2AAH
xxxH
00H
Extra One Time Protect Sector
Program Note 10
4
6
4
3
555H
555H
×××H
555H
AAH
AAH
2AAH
2AAH
55H
55H
555H
555H
A0H
80H
PA
PD
AAH
SD
–
–
2AAH
–
–
–
–
Extra One Time Protect
Sector Erase Note 10
555H
55H EOTPSA 30H
Extra One Time Protect Sector
Protection Note 10
60H EOTPSA 60H EOTPSA 40H EOTPSA
–
–
–
–
–
–
Read Mode Register Set
AAH
2AAH
55H
REGD
C0H
–
–
Notes 1. Both these read / reset commands reset the device to the read mode.
2. Programming is suspended if B0H is input to the bank address being programmed to in a program
operation.
3. Programming is resumed if 30H is input to the bank address being suspended to in a program-suspend
operation.
4. If automatic erase resume and suspend are repeated at intervals of less than 100 µs, since it will become
suspend operation, without starting automatic erase, the erase operation may not be correctly completed.
5. Erasure is suspended if B0H is input to the bank address being erased in a sector erase operation.
6. Erasure is resumed if 30H is input to the bank address being suspended in a sector-erase-suspend
operation.
7. Valid only in the unlock bypass mode.
8. Valid only when /RESET = VID (except in the Extra One Time Protect Sector mode).
9. The command sequence that protects a sector group is excluded.
10. Valid only in the Extra One Time Protect Sector mode.
11. This command can be used even if this data is F0H.
Preliminary Data Sheet M15820EJ3V0DS
14
MC-24222311-X
Remarks 1. The system should generate the following address pattern:
555H or 2AAH (A10 to A0)
2. RA
RD
: Read address
: Read data
IA
: Address input as follows
Information
A21 to A12
Bank address
Bank address
A11 to A4
A3 to A0
Manufacturer code
Device code
Don’t care
Don’t care
0000
0001
0010
0100
Sector group protection information Sector group address Don’t care
Read mode register information Bank address Don’t care
ID
: Code output. For the manufacture code, device code and sector group protection
information, refer to the Product ID code (Flash Memory). For read mode register
information, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information (M15451E).
PA
PD
SA
: Program address
: Program data
: Erase sector address. The sector to be erased is selected by the combination of A21 to
A12. Refer to the Sector Organization / Sector Address Table (Flash Memory).
: Bank address. Refer to the Sector Organization / Sector Address Table (Flash
Memory).
BA
SPA
: Sector group address to be protected or protection-verified. Set the sector group address
(SGA) and (A6, A3, A2, A1, A0) = (VIL, VIL, VIL, VIH, VIL).
Sector group protection can be set for each sector group address. For details, refer to
PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information
(M15451E).
Refer to the Sector Group Address Table (Flash Memory) for the sector group address.
: Sector group address to be unprotected or unprotection-verified. Set the sector group
address (SGA) and (A6, A3, A2, A1, A0) = (VIH, VIL, VIL, VIH, VIL).
SUA
Sector group unprotect is performed for all sector group using a single command, however,
unprotect verification must be performed for each sector group address. For details, refer
to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information
(M15451E).
Refer to the Sector Group Address Table (Flash Memory) for the sector group address.
EOTPSA : Extra One Time Protect Sector area addresses. These addresses are 000000H to
007FFFH.
SD
: Data for verifying whether sector groups read from the address specified by SPA, SUA,
EOTPSA are protected or unprotected.
REGD : Read mode register information. Description for setting, refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
3. The sector group address is don't care except when a program / erase address or read address are
selected.
4. For the operation of bus, refer to PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY
Information (M15451E).
5. × of address bit indicates VIH or VIL.
Preliminary Data Sheet M15820EJ3V0DS
15
MC-24222311-X
5. Initialization (Mobile Specified RAM)
This device is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, before turning on the power, a 200 µs or longer wait time must precede any signal
toggling.
(2) After the wait time, read operation must be performed at least 3 times. After that, it can be normal operation.
Figure 5-1. Initialization Timing Chart
V
CCm (MIN.)
VCCm
Address (Input)
V
IH (MIN.)
IH (MIN.)
MODE (Input)
/CEm (Input)
t
RC
t
CP
V
Wait Time
Power On
Read Operation 3 times
Normal
Operation
200 s
µ
Cautions 1. Following power application, make MODE and /CEm high level during the wait time interval.
2. Following power application, make MODE high level during the wait time and three read
operations.
3. The read operation must satisfy the specs (Read Cycle (Mobile Specified RAM)).
4. The address is don’t care (VIH or VIL) during read operation.
5. Read operation must be executed with toggled the /CEm pin.
6. To prevent bus contention, it is recommended to set /OE to high level.
7. Do not input data to the I/O pins if /OE is low level during a read operation.
Preliminary Data Sheet M15820EJ3V0DS
16
MC-24222311-X
6. Partial Refresh (Mobile Specified RAM)
6.1 Standby Mode
In addition to the regular standby mode (Standby Mode 1) with a 32M bits density, Standby Mode 2, which performs
partial refresh, is also provided.
6.2 Density Switching
In Standby Mode 2, the capacities that can be selected for performing refresh are 16M bits, 8M bits, 4M bits, and 0M
bit.
The density for performing refresh can be set with the mode register. (For how to perform mode register settings,
refer to section 8. Mode Register Settings (Mobile Specified RAM)).
6.3 Standby Mode Status Transition
In Standby Mode 1, both /CEm and MODE are high level, and in Standby Mode 2, /CEm is high level and MODE is
low level. In Standby Mode 2, if 0M bit is set as the density, it is necessary to perform initialization the same way as
after applying power, in order to return to normal operation from Standby Mode 2. When the density has been set to
16M bits, 8M bits, or 4M bits in Standby Mode 2, it is not necessary to perform initialization to return to normal
operation from Standby Mode 2.
Preliminary Data Sheet M15820EJ3V0DS
17
MC-24222311-X
Figure 6-1. Standby Mode State Machine
Power On
/CEm = VIH
,
MODE = VIH
µ
Wait time 200
s
Dummy Read 3 times
Initial State
/CEm = VIL
MODE = VIH
Active
/CEm = VIH
,
/CEm = VIH
MODE = VIH
,
/CEm = VIH
,
MODE = VIL
MODE = VIL
/CEm = VIL
,
/CEm = VIL
,
MODE = VIH
MODE = VIH
Standby Mode 2
(16M bits / 8M bits
/ 4M bits)
/CEm = VIH, MODE = VIL
/CEm = VIH, MODE = VIL
Standby Mode 1
Standby Mode 2
(Data Invalid)
6.4 Addresses for Which Partial Refresh Is Supported
Data hold density
16M bits
Correspondence address
000000H to 0FFFFFH
000000H to 07FFFFH
000000H to 03FFFFH
8M bits
4M bits
Preliminary Data Sheet M15820EJ3V0DS
18
MC-24222311-X
7. Page Read Operation (Mobile Specified RAM)
7.1 Features of Page Read Operation
Features
4 Word Mode
8 Word Mode
Page length
4 words
A1, A0
8 words
A2, A1, A0
Page read-corresponding addresses
Page read start address
Don’t care
Don’t care
Enabled Note
(A2, A1, A0) = (VIL, VIL, VIL)
Sequential increment
Prohibited
Page direction
Interrupt during page read operation
Note An interrupt is output when /CEm = H or in case A2 or a higher address changes.
7.2 Page Length
Four words and eight words are supported as the page lengths. The page length is set with the mode register. Once
the page length is set in the mode register, this setting is retained until it is set again.
(For how to perform mode register settings, refer to section 8. Mode Register Settings (Mobile Specified RAM)).
7.3 Page-Corresponding Addresses
The four-word page read-enabled addresses are A1 and A0. Fix addresses other than A1 and A0 during four-word
page read. The eight-word page read-enabled addresses are A2, A1, and A0. Fix addresses other than A2, A1, and
A0 during eight-word page read operation.
7.4 Page Start Address
Since random page read is supported for four-word pages, any address can be used as the page start address.
Random page read is not supported for eight-word pages. Since the page read start addresses are only (A2, A1, A0) =
(VIL, VIL, VIL), it is not possible to start page read from any address other than (A2, A1, A0) = (VIL, VIL, VIL).
7.5 Page Direction
Since random page read is possible for four-word pages, there is not restriction on the page direction. Random page
read is not supported for eight-word pages. The page direction in this case is sequential increment.
7.6 Interrupt during Page Read Operation
When generating an interrupt during four-word page read, either make /CEm high level or change A2 and higher
addresses. Generating an interrupt during eight-word read is prohibited.
7.7 Eight-Word Start Page Read Operation Prohibition
When an eight-word page read has been started, starting a page read with write-modify-read is prohibited. To start
page read, do so from normal read.
Also, when an eight-word page read has been started, the /OE pin cannot be toggled.
Preliminary Data Sheet M15820EJ3V0DS
19
MC-24222311-X
7.8 Cautions for Eight-Word Page Read Operation
To perform normal read (A20 to A3: fixed) from normal read of (A2, A1, A0) = (VIL, VIL, VIL) to (A2, A1, A0) = (VIL, VIL,
VIH) with the eight-word page set with the mode register, be sure to toggle /OE for normal read (A2, A1, A0) = (VIL, VIL,
VIL). At this time, observe the /OE to address setup time (tOAS) and /OE pulse width (tOP) standard value.
When /OE is fixed to low level with normal read (A20 to A3: fixed) from normal read of (A2, A1, A0) = (VIL, VIL, VIL) to
(A2, A1, A0) = (VIL, VIL, VIH), eight-word page read starts.
Also, when performing a read operation to (A2, A1, A0) = (VIL, VIL, VIH) (A20 to A3 are fixed) from when (A2, A1, A0)
= (VIL, VIL, VIL) are in a write-abort state (/WE = L, however, write data cannot be written to the memory cell because
/LB, /UB = H), an eight-word page read operation is started.
Preliminary Data Sheet M15820EJ3V0DS
20
MC-24222311-X
8. Mode Register Settings (Mobile Specified RAM)
The page length and partial refresh density can be set using the mode register. Since the initial value of the mode
register at power application is undefined, be sure to set the mode register after initialization at power application.
When not using page read, set the mode register to random-accessible four-word page read mode. When not using
partial refresh, set the mode register to any value. Partial refresh mode will not be entered unless /CEm = H, MODE =
L, regardless of the register setting.
Once the page length and partial refresh density have been set in the mode register, these settings are retained until
they are set again, while applying the power supply. However, the mode register setting will become undefined if the
power is turned off, so set the mode register again after power application.
8.1 Mode Register Setting Method
The mode register setting mode can be entered by successively writing two specific data after two continuous reads
of the highest address (1FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles
and two write cycles).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
Table 8-1. shows the commands and command sequences.
Table 8-1. Command sequence
Command sequence
1st bus cycle
(Read cycle)
2nd bus cycle
(Read cycle)
3rd bus cycle
(Write cycle)
4th bus cycle
(Write cycle)
Partial refresh density Page length Address
Data
Address
Data
Address
Data
00H
00H
00H
00H
00H
00H
00H
00H
Address
Data
00H
04H
01H
05H
02H
06H
03H
07H
16M bits
8M bits
4M bits
0M bit
4 words
8 words
4 words
8 words
4 words
8 words
4 words
8 words
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
1FFFFFH
4th bus cycle (Write cycle)
I/O
15
0
14
0
13
0
12
0
11
10
0
9
0
8
0
7
0
6
0
5
0
4
3
0
2
1
0
Mode Register setting
0
0
PL
PD
Page length
0
1
4 words
8 words
I/O1 I/O0
Density
16M bits
8M bits
4M bits
0M bit
Partial
refresh density
0
0
1
1
0
1
0
1
Preliminary Data Sheet M15820EJ3V0DS
21
MC-24222311-X
8.2 Cautions for Setting Mode Register
Since, for the mode register setting, the internal counter status is judged by toggling /CEm and /OE, toggle /CEm at
every cycle during entry (read cycle twice, write cycle twice), and toggle /OE like /CEm at the first and second read
cycles.
If incorrect addresses or data are written, or if addresses or data are written in the incorrect order, the setting of the
mode register are not performed correctly.
When the highest address (1FFFFFH) is read consecutively three or more times, the mode register setting entries
are cancelled.
Once the page length and partial refresh density have been set in the mode register, these settings are retained until
they are set again.
Preliminary Data Sheet M15820EJ3V0DS
22
MC-24222311-X
9. Electrical Specifications
Before turning on power, input VSS 0.2 V to the /RESET pin until VCCf ≥ VCCf (MIN.) and keep that state for 200 µs.
Absolute Maximum Ratings
Parameter
Supply voltage
Symbol
VCCf
Condition
with respect to Vss
Rating
Unit
V
–0.5 to +2.4
–0.5 Note 1 to +4.0
–0.5 to +4.0
VCCm
Input / Output
VCCQf with respect to Vss
V
V
supply voltage
Input / Output voltage
VT
with respect /WP (ACC), /RESET
to Vss Except /WP (ACC), /RESET
–0.5 Note 2 to +13.0
–0.5Note 1 to VCCQf + 0.4 (4.0 V MAX.),
–0.5Note 1 to VCCm + 0.4 (4.0 V MAX.)
–25 to +85
Ambient operation
temperature
TA
°C
°C
Storage temperature
Tstg
–55 to +125
–25 to +85
Tbias
at bias
Notes 1. –2.0 V (MIN.) (pulse width ≤ 30 ns)
2. –2.0 V (MIN.) (pulse width ≤ 20 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCCf
Condition
MIN.
1.65
TYP.
MAX.
1.95
Unit
V
VCCm
VCCQf
VIH
2.7
3.1
Input / Output supply voltage
High level input voltage
2.7
3.3
V
V
Flash Memory
2.4
VCCQf+0.3 Note1
VCCm+0.3
11.0
Mobile Specified RAM
High voltage is applied (/RESET)
Flash Memory
0.8 VCCm
VID
VIL
9.0
Low level input voltage
–0.5 Note2
–0.3 Note3
8.5
+0.5
V
Mobile Specified RAM
High voltage is applied
0.2 VCCm
9.5
Accelerated programming voltage
Ambient operating temperature
VACC
TA
V
–25
+85
°C
Notes 1. VCCQf + 0.6 V (MAX.) (pulse width ≤ 20 ns)
2. –0.6 V (MIN.) (pulse width ≤ 20 ns)
3. –0.5 V (MIN.) (pulse width = 30 ns)
Preliminary Data Sheet M15820EJ3V0DS
23
MC-24222311-X
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Flash Memory
Parameter
High level output voltage
Low level output voltage
Input leakage current
Symbol
VOH
VOL
ILI1
Test condition
MIN.
TYP.
MAX.
Unit
V
IOH = −0.5 mA
0.8 VCCQf
IOL = 1.0 mA
0.2 VCCQf
V
VIN = VSS to VCCQf, VCCQf = VCCQf (MAX.)
/RESET = 11.0 V
1.0
35
µA
High voltage is applied
ILI2
I/O leakage current
Power Read
ILO
VI/O = VSS to VCCQf, VCCQf = VCCQf (MAX.)
/CEf = VIL, /OE = VIH, Cycle = 5 MHz,
IOUT = 0 mA
1.0
15
µA
ICC1
8
mA
supply
current Program, Erase
ICC2
ICC3
/CEf = VIL, /OE = VIH,
25
25
mA
Automatic programming / erase
VCCf = VCCf (MAX.), /CEf = /RESET =
/WP (ACC) = VCCQf 0.3 V, /OE = VIL
VCCf = VCCf (MAX.), /RESET = VSS 0.2 V
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
Standby
15
µA
Standby / Reset
ICC4
ICC5
ICC6
15
15
25
25
40
µA
µA
Automatic sleep mode
Read during
programming
mA
Read during erasing
Programming
ICC7
ICC8
VIH = VCCQf 0.2 V, VIL = VSS 0.2 V
/CEf = VIL, /OEf = VIH,
Automatic programming during suspend
/WP (ACC) pin
40
25
mA
mA
during suspend
Accelerated
IACC
5
10
25
mA
programming
VCCf
12
Low VCCf lock-out voltage Note
VLKO
1.0
V
Note When VCCf is equal to or lower than VLKO, the device ignores all write cycles. Refer to PAGE MODE FLASH
MEMORY, BURST MODE FLASH MEMORY Information (M15451E).
Remark VIN : Input voltage, VI/O : Input/ Output voltage
Preliminary Data Sheet M15820EJ3V0DS
24
MC-24222311-X
Mobile Specified RAM
Parameter
Symbol
Test condition
Density of
data hold
MIN.
TYP.
MAX.
Unit
High level output voltage
Low level output voltage
Input leakage current
I/O leakage current
VOH
VOL
ILI
IOH = –0.5 mA
IOL = 1.0 mA
0.8 VCCm
V
V
0.2 VCCm
+1.0
VIN = 0 V to VCCm
–1.0
–1.0
µA
µA
ILO
VI/O = 0 V to VCCm, /CEm = VIH or
/WE = VIL or /OE = VIH
+1.0
Operating supply current
Standby supply current
ICCA
/CEm = VIL, Minimum cycle time,
II/O = 0 mA
35
mA
ISB1
/CEm ≥ VCCm − 0.2 V, MODE ≥ VCCm − 0.2 V
/CEm ≥ VCCm − 0.2 V, MODE ≤ 0.2 V
32M bits
16M bits
8M bits
4M bits
0M bit
100
70
µA
ISB2
60
50
10
Remark VIN : Input voltage, VI/O : Input/ Output voltage
Preliminary Data Sheet M15820EJ3V0DS
25
MC-24222311-X
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[Flash Memory]
Input Waveform (Rise and Fall Time ≤ 5 ns)
V
CCQf
0 V
V
CCQf / 2
Test points
VCCQf / 2
Output Waveform
VCCQf / 2
Test points
VCCQf / 2
Output Load
1TTL + 30 pF
Preliminary Data Sheet M15820EJ3V0DS
26
MC-24222311-X
[Mobile Specified RAM]
Input Waveform (Rise and Fall Time ≤ 5 ns)
Vccm
0.8 Vccm
Vccm / 2
Test points
Vccm / 2
0.2 Vccm
VSS
5 ns
Output Waveform
Vccm / 2
Test points
Vccm / 2
Output Load
AC characteristics directed with the note should be measured with the output load shown in figure.
CL: 30 pF
5 pF (tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW)
ZO = 50 Ω
I/O (Output)
CL
50 Ω
V
CCm / 2
Remark CL includes capacitance of the probe and jig, and stray capacitance.
Preliminary Data Sheet M15820EJ3V0DS
27
MC-24222311-X
/CEf, /CEm Timing
Parameter
Symbol
Test Condition
MIN.
0
TYP.
MAX.
Unit
ns
Note
/CEf, /CEm recover time
tCCR
Read Cycle (Flash Memory)
Parameter
Read cycle time
Symbol
tRC
MIN.
85
MAX.
85
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
Note
1
Address access time
Page read cycle
tACC
tPRC
tPACC
tCEf
30
Page address access time
/CEf access time
30
85
25
25
1
2
/OE access time
tOE
Output disable time
Output hold time
tDF
tOH
0
/RESET pulse width
/RESET hold time before read
tRP
500
50
tRH
/RESET low
to read mode
At automatic mode
Except automatic mode
tREADY
20
500
/OE low level time from /WE high level
tOEH
20
Notes 1. /CEf = /OE = VIL
2. /OE = VIL
Remark
t
DF is the time from inactivation of /CEf or /OE to high impedance state output.
Preliminary Data Sheet M15820EJ3V0DS
28
MC-24222311-X
Write Cycle (Program / Erase) (Flash Memory)
(1/2)
Parameter
Write cycle time
Symbol
tWC
tAS
MIN.
85
0
TYP.
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Note
Address setup time (/WE to address)
Address setup time (/CEf to address)
Address hold time (/WE to address)
Address hold time (/CEf to address)
Input data setup time
tAS
0
tAH
45
45
45
0
tAH
tDS
Input data hold time
tDH
/OE hold time
Read
tOEH
0
Toggle bit, Data polling
10
0
Read recovery time before write (/OE to /CEf)
Read recovery time before write (/OE to /WE)
/WE setup time (/CEf to /WE)
/CEf setup time (/WE to /CEf)
/WE hold time (/CEf to /WE)
/CEf hold time (/WE to /CEf)
Write pulse width
tGHEL
tGHWL
tWS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
s
0
0
tCS
0
tWH
0
tCH
0
tWP
35
35
30
30
/CEf pulse width
tCP
Write pulse width high
tWPH
tCPH
tWPG
tCPG
tSER
/CEf pulse width high
Word programming operation time
Chip programming operation time
11
47
200
840
1.0
Sector erase operation time
4K words sector
0.15
0.5
0.5
0.7
65.4
96.2
7
s
1,2
1,3
32K words sector
4K words sector
32K words sector
1.5
3.0
5.0
Chip erase operation time
tCER
205
678
150
s
1,2
1,3
Accelerated programming time
Program / erase cycle
VCCf setup time
tACCPG
µs
cycle
µs
300,000
200
0
tVCS
tRB
RY (/BY) recovery time
/RESET pulse width
ns
tRP
500
20
ns
/RESET high-voltage (VID) hold time from high of RY(/BY)
when sector group is temporarily unprotect
/RESET hold time
tRRB
µs
tRH
50
ns
Notes 1. The preprogramming time prior to the erase operation is not included.
2. Program / erase cycle : 100,000 cycles
3. Program / erase cycle : 300,000 cycles
Preliminary Data Sheet M15820EJ3V0DS
29
MC-24222311-X
Write Cycle (Program / Erase) (Flash Memory)
(2/2)
Parameter
Symbol
MIN.
TYP.
MAX.
85
Unit
ns
Note
From completion of automatic program / erase to data
output time
tEOE
RY (/BY) delay time from valid program or erase
operation
tBUSY
85
ns
Address setup time to /OE low in toggle bit
Address hold time to /CEf or /OE high in toggle bit
/CEf pulse width high for toggle bit
/OE pulse width high for toggle bit
Voltage transition time
tASO
tAHT
15
0
ns
ns
ns
ns
µs
ns
ns
µs
µs
tCEPH
tOEPH
tVLHT
tVIDR
tVACCR
tTOW
tSPD
20
20
4
1
Rise time to VID (/RESET)
500
500
50
Rise time to VACC (/WP(ACC))
Erase timeout time
2
2
Erase suspend transition time
20
Notes 1. Sector group protection only.
2. Table only.
Write operation (Program / Erase) Performance (Flash Memory)
Parameter
Sector erase time
Description
The preprogramming time 4K words sector
MIN.
TYP.
MAX.
Unit
s
Note
1
0.15
0.5
0.5
0.7
65.4
96.2
11
1.0
1.5
prior to the erase
32K words sector
4K words sector
32K words sector
operation is not included
3.0
2
5.0
Chip erase time
The programming time prior to
the erase operation is not included
Excludes system-level overhead
Excludes system-level overhead
205
678
200
840
150
s
1
2
Word programming time
Chip programming time
µs
s
47
Accelerated programming time Excludes system-level overhead
Program / erase cycle
7
µs
300,000
cycle
Notes 1. Program / erase cycle : 100,000 cycles
2. Program / erase cycle : 300,000 cycles
Preliminary Data Sheet M15820EJ3V0DS
30
MC-24222311-X
Read Cycle (Mobile Specified RAM)
Parameter
Read cycle time
Symbol
tRC
MIN.
85
MAX.
10,000
10,000
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
2
3
Identical address read cycle time
Address skew time
tRC1
tSKEW
tCP
85
/CEm pulse width
10
Address access time
tAA
85
85
35
35
4
5
/CEm access time
tACS
tOE
/OE to output valid
/LB, /UB to output valid
Output hold from address change
/CEm to output in Low-Z
/OE to output in Low-Z
/LB, /UB to output in Low-Z
/CEm to output in High-Z
/OE to output in High-Z
/LB, /UB to output in High-Z
tBA
tOH
10
10
5
tCLZ
tOLZ
tBLZ
tCHZ
tOHZ
tBHZ
5
25
25
25
Notes 1. One read cycle (tRC) must satisfy the minimum value (tRC(MIN.)) and maximum value (tRC(MAX.) = 10 µs). tRC
indicates the time from the /CEm low level input point or address change start point, whichever is later, to
the /CEm high level input point or the next address change start point, whichever is earlier. As a result, there
are the following four conditions for tRC.
1) Time from address change start point to /CEm high level input point
2) Time from address change start point to next address change start point
3) Time from /CEm low level input point to next address change start point
4) Time from /CEm low level input point to /CEm high level input point
(address access)
(address access)
(/CEm access)
(/CEm access)
2. The identical address read cycle time (tRC1) is the cycle time of one read operation when performing
continuous read operations toggling /OE , /LB, and /UB with the address fixed and /CEm low level. Perform
settings so that the sum (tRC) of the identical address read cycle times (tRC1) is 10 µs or less.
3. tSKEW indicates the following three types of time depending on the condition.
1) When switching /CEm from high level to low level, tSKEW is the time from the /CEm low level input point
until the next address is determined.
2) When switching /CEm from low level to high level, tSKEW is the time from the address change start point to
the /CEm high level input point.
3) When /CEm is fixed to low level, tSKEW is the time from the address change start point until the next
address is determined.
Since specs are defined for tSKEW only when /CEm is active, tSKEW is not subject to limitations when /CEm is
switched from high level to low level following address determination, or when the address is changed after
/CEm is switched from low level to high level.
4. Regarding tAA and tACS, only tAA is satisfied during address access (refer to 1) and 2) of Note 1), and only
tACS is satisfied during /CEm access (refer to 3) of Note 1).
5. Regarding tBA and tOE, only tBA is satisfied if /OE becomes active later than /UB and /LB, and only tOE is
satisfied if /UB and /LB become active before /OE.
Preliminary Data Sheet M15820EJ3V0DS
31
MC-24222311-X
Page Read Cycle (Mobile Specified RAM)
Parameter
Page read cycle time
Symbol
MIN.
40
MAX.
Unit
ns
Note
tPRC
tPAA
tNPRC
tOAS
tOP
Page access time
35
ns
Normal to page read cycle time
/OE to address setup time
/OE pulse width
10,000
ns
1
2
−5
ns
10
ns
Notes 1. Normal to page read cycle time (tNPRC) is the total cycle time for one four-word page read and one eight-word
page read. Perform settings to that (tNPRC) is 10 µs or less.
2. /OE to address setup time (tOAS) and /OE pulse width (tOP) are effective only when eight-word page read is
set. (Refer to section 7.8 Cautions for Eight-Word Page Read Operation.)
Write Cycle (Mobile Specified RAM)
Parameter
Write cycle time
Symbol
tWC
MIN.
85
MAX.
10,000
10,000
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
2
3
4
Identical address write cycle time
Address skew time
tWC1
tSKEW
tCW
85
/CEm to end of write
/LB, /UB to end of write
Address valid to end of write
Write pulse width
40
30
35
30
20
10
0
tBW
tAW
tWP
Write recovery time
tWR
5
/CEm pulse width
tCP
Address setup time
tAS
Byte write hold time
tBWH
tDW
20
20
0
Data valid to end of write
Data hold time
tDH
/OE to output in Low-Z
/WE to output in High-Z
/OE to output in High-Z
Output active from end of write
tOLZ
tWHZ
tOHZ
tOW
5
25
25
5
Notes 1. One write cycle (tWC) must satisfy the minimum value (tWC(MIN.)) and the maximum value (tWC(MAX.) = 10 µs).
tWC indicates the time from the /CEm low level input point or address change start point, whichever is after,
to the /CEm high level input point or the next address change start point, whichever is earlier. As a result,
there are the following four conditions for tWC.
1) Time from address change start point to /CEm high level input point
2) Time from address change start point to next address change start point
3) Time from /CEm low level input point to next address change start point
4) Time from /CEm low level input point to /CEm high level input point
Preliminary Data Sheet M15820EJ3V0DS
32
MC-24222311-X
2. The identical address read cycle time (tWC1) is the cycle time of one write cycle when performing write
operations with the address fixed and /CEm low level, changing /LB and /UB at the same time, and toggling
/WE, as well as when performing a continuous write toggling /LB and /UB. Make settings so that the sum
(tWC) of the identical address write cycle times (tWC1) is 10 µs or less.
3. tSKEW indicates the following three types of time depending on the condition.
1) When switching /CEm from high level to low level, tSKEW is the time from the /CEm low level input point
until the next address is determined.
2) When switching /CEm from low level to high level, tSKEW is the time from the address change start point to
the /CEm high level input point.
3) When /CEm is fixed to low level, tSKEW is the time from the address change start point until the next
address is determined.
Since specs are defined for tSKEW only when /CEm is active, tSKEW is not subject to limitations when /CEm is
switched from high level to low level following address determination, or when the address is changed after
/CEm is switched from low level to high level.
4. Definition of write start and write end
/CEm
H to L
/WE
L
/LB, /UB
L
Status
Write start pattern 1
Write start pattern 2
Write start pattern 3
Write end pattern 1
Write end pattern 2
If /WE, /LB, /UB are low level, time when /CEm
changes from high level to low level
L
L
L
L
H to L
L
If /CEm, /LB, /UB are low level, time when /WE
changes from high level to low level
L
L to H
L
H to L
L
If /CEm, /WE are low level, time when /LB or /UB
changes from high level to low level
If /CEm, /WE, /LB, /UB are low level, time when
/WE changes from low level to high level
When /CEm, /WE, /LB, /UB are low level, time
when /LB or /UB changes from low level to high
level
L to H
5. Definition of write end recovery time (tWR)
1) Time from write end to address change start point, or from write end to /CEm high level input point
2) When /CEm, /LB, /UB are low level and continuously written to the identical address, time from /WE high
level input point to /WE low level input point
3) When /CEm, /WE are low level and continuously written to the identical address, time from /LB or /UB
high level input point, whichever is later, to /LB or /UB low level input point, whichever is earlier.
4) When /CEm is low level and continuously written to the identical address, time from write end to point at
which /WE , /LB, or /UB starts to change from high level to low level, whichever is earliest.
Preliminary Data Sheet M15820EJ3V0DS
33
MC-24222311-X
Read Write Cycle (Mobile Specified RAM)
Parameter
Read write cycle time
Symbol
MIN.
MAX.
Unit
ns
Note
1, 2
tRWC
tBWS
tBRS
10,000
Byte write setup time
Byte read setup time
20
20
ns
ns
Notes 1. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a write is performed at the identical address using /UB following
a read using /LB with /CEm low level, or when a write is performed using /LB following a read using /UB.
2. Make settings so that the sum (tRWC) of the identical address read cycle time (tRC1) and the identical address
write cycle time (tWC1) is 10 µs or less when a read is performed at the identical address using /UB following
a write using /LB with /CEm low level, or when a read is performed using /LB following a write using /UB.
Standby Mode Entry / Exit (Mobile Specified RAM)
Parameter
/CEm High to MODE Low
MODE High to /CEm Low
Symbol
tCM
MIN.
0
MAX.
Unit
ns
Note
tMC
30
ns
Cautions 1. Make MODE and /CEm high level during the wait time interval.
2. Make MODE high level during the wait time and three read operations.
3. The read operation must satisfy the read cycle specs (Read Cycle (Mobile Specified RAM)).
4. The address is don’t care (VIH or VIL) during read operation.
5. Read operation must be executed with toggled the /CEm pin.
6. To prevent bus contention, it is recommended to set /OE to high level.
7. Do not input data to the I/O pins if /OE is low level during a read operation.
Preliminary Data Sheet M15820EJ3V0DS
34
MC-24222311-X
10. Package Drawing
85-PIN TAPE FBGA (11x8)
ZD
w
S
B
ZE
B
E
10
9
8
7
6
5
4
3
2
1
A
INDEX MARK
w
S
A
M L K J H G F E D C B A
A
A2
S
y1
S
S
y
e
A1
S
M
φ
φ
x
b
A B
ITEM MILLIMETERS
D
E
8.00 0.10
11.00 0.10
0.20
w
e
0.80
A
1.11 0.10
0.27 0.05
0.84
A1
A2
b
0.45 0.05
0.08
x
y
0.10
y1
ZD
ZE
0.20
0.40
1.10
P85F9-80-CD5
Preliminary Data Sheet M15820EJ3V0DS
35
MC-24222311-X
11. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the MC-24222311-X.
Type of Surface Mount Device
MC-24222311F9-CD5 : 85-pin TAPE FBGA (11 × 8)
12. Related Documents
Document Name
Document Number
PAGE MODE FLASH MEMORY, BURST MODE FLASH MEMORY Information
SRAM AND MOBILE SPECIFIED RAM TAIMING CHARTS FOR MCP Information
M15451E
M15819E
Preliminary Data Sheet M15820EJ3V0DS
36
MC-24222311-X
13. Revision History
Edition/
Date
Page
Type of
revision
Location
Description
(Previous edition → This edition)
This
Previous
edition
edition
3rd edition/
Feb. 2003
Throughout Throughout Modification Access time
Flash Memory : 90 ns → 85 ns
Mobile Specified RAM : 85, 95 ns → 85 ns
-E90X, -E85X → -E85X
Class
Supply voltage
Mobile Specified RAM : 2.6 to 3.1 V → 2.7 to 3.1 V
Preliminary Data Sheet M15820EJ3V0DS
37
MC-24222311-X
[MEMO]
Preliminary Data Sheet M15820EJ3V0DS
38
MC-24222311-X
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Preliminary Data Sheet M15820EJ3V0DS
39
MC-24222311-X
•
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change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
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•
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M8E 02. 11-1
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