MC-428LFG641FH-A60 概述
EDO DRAM Module, 8MX64, 60ns, MOS, DIM-168 DRAM
MC-428LFG641FH-A60 规格参数
生命周期: | Obsolete | 零件包装代码: | DIMM |
包装说明: | , | 针数: | 168 |
Reach Compliance Code: | unknown | ECCN代码: | EAR99 |
HTS代码: | 8542.32.00.28 | 风险等级: | 5.84 |
访问模式: | FAST PAGE WITH EDO | 最长访问时间: | 60 ns |
JESD-30 代码: | R-XDMA-N168 | 内存密度: | 536870912 bit |
内存集成电路类型: | EDO DRAM MODULE | 内存宽度: | 64 |
功能数量: | 1 | 端口数量: | 1 |
端子数量: | 168 | 字数: | 8388608 words |
字数代码: | 8000000 | 工作模式: | ASYNCHRONOUS |
最高工作温度: | 70 °C | 最低工作温度: | |
组织: | 8MX64 | 封装主体材料: | UNSPECIFIED |
封装形状: | RECTANGULAR | 封装形式: | MICROELECTRONIC ASSEMBLY |
认证状态: | Not Qualified | 最大供电电压 (Vsup): | 3.6 V |
最小供电电压 (Vsup): | 3 V | 标称供电电压 (Vsup): | 3.3 V |
表面贴装: | NO | 技术: | MOS |
温度等级: | COMMERCIAL | 端子形式: | NO LEAD |
端子位置: | DUAL | Base Number Matches: | 1 |
MC-428LFG641FH-A60 数据手册
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MOS INTEGRATED CIRCUIT
MC-428LFG641
3.3 V OPERATION 8M-WORD BY 64-BIT DYNAMIC RAM MODULE
UNBUFFERED TYPE, EDO
Description
The MC-428LFG641 is a 8,388,608 words by 64 bits dynamic RAM module on which 8 pieces of 64M DRAM :
PD4265805 are assembled.
µ
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• Unbuffered type
• EDO (Hyper page mode)
• 8,388,608 words by 64 bits organization
• Fast access and cycle time
Family
Access time
(MAX.)
50 ns
R/W cycle time EDO (Hyper page mode)
Power consumption (MAX.)
(MIN.)
84 ns
cycle time (MIN.)
20 ns
Active
3.89 W
3.31 W
Standby
14.4 mW
MC-428LFG641-A50
MC-428LFG641-A60
60 ns
104 ns
25 ns
(CMOS level input)
• Refresh cycle
Family
Refresh cycle
4,096 cycles / 64 ms
Refresh
MC-428LFG641-A50
MC-428LFG641-A60
/RAS only refresh, Normal read / write, /CAS before /RAS refresh,
Hidden refresh
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Single +3.3 V ± 0.3 V power supply
• Serial PD
The information in this document is subject to change without notice.
Document No. M11909EJ4V0DS00 (4th edition)
Date Published October 1997 NS
Printed in Japan
The mark shows major revised points.
1996
©
MC-428LFG641
Ordering Information
Part number
Access time
(MAX.)
Package
Mounted devices
MC-428LFG641FH-A50
MC-428LFG641FH-A60
MC-428LFG641FB-A50
MC-428LFG641FB-A60
50 ns
60 ns
50 ns
60 ns
168-pin Dual In-line Memory Module
(Socket Type)
8 pieces of µPD4265805G5
(400 mil TSOP(II))
Edge connector : Gold plated
[Single side]
8 pieces of µPD4265805LE
(400 mil SOJ)
[Single side]
2
MC-428LFG641
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
[ MC-428LFG641FH, 428LFG641FB ]
/XXX indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
GND
GND
DQ 0
DQ 1
DQ 2
DQ 3
Vcc
DQ 4
DQ 5
DQ 6
DQ 7
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
DQ 36
DQ 37
DQ 38
DQ 39
95
96
DQ 40
GND
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
Vcc
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ 8
GND
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
Vcc
DQ 14
DQ 15
NC
NC
GND
NC
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ 46
DQ 47
NC
NC
GND
NC
NC
NC
Vcc
Vcc
NC
/WE0
/CAS0
/CAS1
/RAS0
/OE0
GND
A0
/CAS4
/CAS5
NC
NC
GND
A1
A3
A2
A5
A4
A7
A6
A9
A8
A11
A10
NC
NC
Vcc
Vcc
NC
Vcc
NC
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NC
GND
NC
NC
GND
/OE2
/RAS2
/CAS2
/CAS3
/WE2
Vcc
/CAS6
/CAS7
NC
Vcc
NC
NC
NC
NC
NC
NC
NC
NC
GND
DQ 48
DQ 49
DQ 50
DQ 51
Vcc
GND
DQ 16
DQ 17
DQ 18
DQ 19
Vcc
A0 - A11
[ Row : A0 - A11, Column : A0 - A10 ]
DQ0 - DQ63 : Data Inputs / Outputs
: Address Inputs
DQ 52
NC
NC
NC
GND
DQ 53
DQ 54
DQ 55
GND
DQ 56
DQ 57
DQ 58
DQ 59
Vcc
DQ 20
NC
NC
NC
/RAS0, /RAS2 : Row Address Strobe
/CAS0 - /CAS7 : Column Address Strobe
GND
DQ 21
DQ 22
DQ 23
GND
DQ 24
DQ 25
DQ 26
DQ 27
Vcc
DQ 28
DQ 29
DQ 30
DQ 31
GND
NC
/WE0, /WE2
/OE0, /OE2
SDA
: Write Enable
: Output Enable
: Serial Data I/O for PD
: Clock Input for PD
: Address Input for EEPROM
: Power Supply
DQ 60
DQ 61
DQ 62
DQ 63
GND
NC
SCL
SA0 - SA2
VCC
NC
NC
NC
SA0
GND
: Ground
SA1
SDA
SA2
SCL
Vcc
Vcc
NC
: No Connection
3
MC-428LFG641
Block Diagram
/RAS0
/OE0
/RAS2
/OE2
/WE0
/CAS0
/WE2
/CAS4
/CAS /RAS /WE /OE
/CAS /RAS
/WE
/OE
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D0
D4
/CAS1
/CAS5
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ 8
DQ 9
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
D1
D5
/CAS2
/CAS6
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQ 23
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 48
DQ 49
DQ 50
DQ 51
DQ 52
DQ 53
DQ 54
DQ 55
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D2
D6
/CAS3
/CAS7
/CAS /RAS /WE /OE
/CAS /RAS /WE /OE
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D3
D7
SERIAL PD
A0 - A11
VCC
A0 - A11 : D0 - D7
D0 - D7
SCL
SDA
A0
A1
A2
GND
D0 - D7
SA0 SA1 SA2
Remark D0 - D7 : µPD4265805 (8M words by 8 bits organization)
4
MC-428LFG641
Electrical Specifications
• All voltages are referenced to GND.
CC
CC (MIN.)
• After power up (V ≥ V
), wait more than 100 µs (/RAS, /CAS inactive) and then, execute eight /CAS before
/RAS or /RAS only refresh cycles as dummy cycles to initialize internal circuit.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to GND
Supply voltage
Symbol
VT
Condition
Rating
−0.5 to +4.6
−0.5 to +4.6
50
Unit
V
VCC
IO
V
Output current
mA
W
Power dissipation
PD
8
Operating ambient temperature
Storage temperature
TA
0 to +70
−55 to +125
°C
°C
Tstg
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
−0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
VCC + 0.3
+0.8
V
Low level input voltage
VIL
V
Operating ambient temperature
TA
70
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
TYP.
MAX.
70
Unit
pF
Input capacitance
A0 - A11
CI2
/RAS0, /RAS2
/CAS0 - /CAS7
/WE0, /WE2
/OE0, /OE2
55
CI3
30
CI4
55
CI5
55
Data input/output capacitance
CI/O
DQ0 - DQ63
30
pF
5
MC-428LFG641
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
ICC1
Test condition
MIN.
MAX.
1,080
920
8
Unit
mA
Notes
1, 2, 3
Operating current
/RAS, /CAS cycling
tRAC = 50 ns
tRAC = 60 ns
tRC = tRC (MIN.), IO = 0 mA
/RAS, /CAS ≥ VIH (MIN.), IO = 0 mA
/RAS, /CAS ≥ VCC−0.2 V, IO = 0 mA
/RAS cycling, /CAS ≥ VIH (MIN.)
tRC = tRC (MIN.), IO = 0 mA
/RAS ≤ VIL (MAX.), /CAS cycling
tHPC = tHPC (MIN.), IO = 0 mA
/RAS cycling
Standby current
ICC2
ICC3
ICC4
ICC5
II (L)
mA
4
/RAS only refresh current
tRAC = 50 ns
tRAC = 60 ns
tRAC = 50 ns
tRAC = 60 ns
tRAC = 50 ns
tRAC = 60 ns
1,080
920
840
760
1,080
920
+5
mA 1, 2, 3 ,4
Operating current
mA
mA
µA
1, 2, 5
1, 2
(Hyper page mode (EDO))
/CAS before /RAS
refresh current
tRC = tRC (MIN.), IO = 0 mA
VI = 0 to 3.6 V
Input leakage current
−5
−5
All other pins not under test = 0 V
VO = 0 to 3.6 V
Output leakage current
IO (L)
+5
µA
Output is disabled (Hi−Z)
IO = −2.0 mA
High level output voltage
Low level output voltage
VOH
VOL
2.4
V
V
IO = +2.0 mA
0.4
Notes 1. ICC1, ICC3, ICC4 and ICC5 depend on cycle rates (tRC and tHPC).
2. Specified values are obtained with outputs unloaded.
3. ICC1 and ICC3 are measured assuming that address can be changed once or less during /RAS ≤ VIL (MAX.) and
IH (MIN.)
/CAS ≥ V
.
4. ICC3 is measured assuming that all column address inputs are held at either high or low.
5. ICC4 is measured assuming that all column address inputs are switched only once during each hyper page
(EDO) cycle.
6
MC-428LFG641
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
(1) Input timing specification
(2) Output timing specification
V
IH (MIN.) = 2.0 V
IL (MAX.) = 0.8 V
V
V
OH (MIN.) = 2.0 V
OL (MAX.) = 0.8 V
V
t
T
= 2 ns
tT = 2 ns
(3) Output load condition
V
CC
1,180
870
I/O
100 pF
CL
7
MC-428LFG641
Common to Read, Write, Read Modify Write Cycle
Parameter
Symbol
tRAC = 50 ns
tRAC = 60 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX.
Read / Write cycle time
/RAS precharge time
tRC
tRP
84
30
7
−
104
40
10
60
10
15
40
14
12
5
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
−
−
/CAS precharge time
tCPN
tRAS
tCAS
tRSH
tCSH
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tOES
tCLZ
tOLZ
tOED
tT
−
−
/RAS pulse width
50
8
10,000
10,000
/CAS pulse width
10,000
10,000
/RAS hold time
13
38
11
9
−
−
−
−
/CAS hold time
/RAS to /CAS delay time
/RAS to column address delay time
/CAS to /RAS precharge time
Row address setup time
Row address hold time
Column address setup time
Column address hold time
/OE lead time referenced to /RAS
/CAS to data setup time
/OE to data setup time
/OE to data delay time
Transition time (rise and fall)
Refresh time
37
25
−
45
30
−
1
1
2
5
0
−
0
−
7
−
10
0
−
0
−
−
7
−
10
0
−
0
−
−
0
−
0
−
0
−
0
−
10
1
−
13
1
−
50
64
50
64
tREF
−
−
Notes 1. For read cycles, access time is defined as follows:
Input conditions
Access time
Access time from /RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tRCD > tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD + tAA (MAX.)
tRCD + tCAC (MAX.)
tAA (MAX.)
tCAC (MAX.)
RAD (MAX.)
RCD (MAX.)
t
and t
are specified as reference points only; they are not restrictive operating parameters.
RAC AA
CAC
They are used to determine which access time (t , t or t ) is to be used for finding out when output
data will be available. Therefore, the input conditions t
RAD ≥ RAD (MAX.)
t
and tRCD ≥ tRCD (MAX.) will not cause any
operation problems.
2. tCRP (MIN.) requirement is applied to /RAS, /CAS cycles.
8
MC-428LFG641
Read Cycle
Parameter
Symbol
tRAC = 50 ns
tRAC = 60 ns
Unit
Notes
MIN.
MAX.
50
13
25
13
−
MIN.
MAX.
60
15
30
15
−
Access time from /RAS
Access time from /CAS
tRAC
tCAC
tAA
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
1
Access time from column address
Access time from /OE
−
−
tOEA
tRAL
tRCS
tRRH
tRCH
tOEZ
tCHO
−
−
Column address lead time referenced to /RAS
Read command setup time
25
0
30
0
−
−
Read command hold time referenced to /RAS
Read command hold time referenced to /CAS
Output buffer turn-off delay time from /OE
/CAS hold time to /OE
0
−
0
−
2
2
3
4
0
−
0
−
0
10
−
0
13
−
5
5
Notes 1. For read cycles, access time is defined as follows:
Input conditions
Access time
Access time from /RAS
tRAD ≤ tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tRAD > tRAD (MAX.) and tRCD ≤ tRCD (MAX.)
tRCD > tRCD (MAX.)
tRAC (MAX.)
tRAC (MAX.)
tRAD + tAA (MAX.)
tRCD + tCAC (MAX.)
tAA (MAX.)
tCAC (MAX.)
RAD (MAX.)
t
RCD (MAX.)
and t
are specified as reference points only; they are not restrictive operating parameters.
RAC AA
CAC
They are used to determine which access time (t , t or t ) is to be used for finding out when output
data will be available. Therefore, the input conditions t
RAD ≥ RAD (MAX.)
t
and tRCD ≥ tRCD (MAX.) will not cause
any operation problems.
2. Either tRCH (MIN.) or tRRH (MIN.) should be met in read cycles.
3. tOEZ (MAX.) defines the time when the output achieves the condition of Hi-Z and is not referenced to VOH or VOL.
4. /WE : inactive (in read cycle)
CHO
/CAS : inactive, /OE : active ...... t
is effective.
OCH
/RAS, /OE : active ...... t
is effective.
9
MC-428LFG641
Write Cycle
Parameter
Symbol
tRAC = 50 ns
tRAC = 60 ns
Unit
Notes
MIN.
MAX.
MIN.
MAX.
/WE hold time referenced to /CAS
/WE pulse width
tWCH
tWP
7
7
−
−
−
−
−
−
−
−
10
10
15
10
0
−
−
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
1
1
/WE lead time referenced to /RAS
/WE lead time referenced to /CAS
/WE setup time
tRWL
tCWL
tWCS
tOEH
tDS
13
7
0
2
/OE hold time
0
0
Data-in setup time
0
0
3
3
Data-in hold time
tDH
7
10
Notes 1. tWP (MIN.) is applied to late write cycles or read modify write cycles. In early write cycles, tWCH (MIN.) should be met.
2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
3. tDS (MIN.) and tDH (MIN.) are referenced to the /CAS falling edge in early write cycles. In late write cycles and
read modify write cycles, they are referenced to the /WE falling edge.
Read Modify Write Cycle
Parameter
Symbol
tRAC = 50 ns
tRAC = 60 ns
Unit
Note
MIN.
MAX.
MIN.
MAX.
Read modify write cycle time
tRWC
tRWD
tCWD
tAWD
107
64
−
−
−
−
133
77
−
−
−
−
ns
ns
ns
ns
/RAS to /WE delay time
1
1
1
/CAS to /WE delay time
27
32
Column address to /WE delay time
39
47
Note 1. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire cycle.
If t
RWD ≥ RWD (MIN.) CWD ≥ CWD (MIN.) AWD ≥ AWD (MIN.)
t
, t , t
t
t
and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify write
cycle and the data out will contain data read from the selected cell. If neither of the above conditions is
met, the state of the data out is indeterminate.
10
MC-428LFG641
Hyper Page Mode (EDO)
Parameter
Symbol
tRAC = 50 ns
tRAC = 60 ns
Unit
Notes
1
MIN.
MAX.
MIN.
MAX.
Read / Write cycle time
tHPC
tRASP
tHCAS
tCP
20
50
8
−
25
60
10
10
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
/RAS pulse width
125,000
125,000
/CAS pulse width
10,000
10,000
/CAS precharge time
7
−
30
−
−
35
−
Access time from /CAS precharge
/CAS precharge to /WE delay time
/RAS hold time from /CAS precharge
Read modify write cycle time
Data output hold time
tACP
−
tCPWD
tRHCP
tHPRWC
tDHC
41
30
52
5
52
35
66
5
2
3
−
−
−
−
−
−
/OE to /CAS hold time
tOCH
tOEP
5
−
5
−
/OE precharge time
5
−
5
−
Output buffer turn-off delay from /WE
/WE pulse width
tWEZ
tWPZ
tOFR
0
10
−
0
13
−
4,5
5
7
10
0
Output buffer turn-off delay from /RAS
Output buffer turn-off delay from /CAS
0
10
10
13
13
4,5
4,5
tOFC
0
0
Notes 1. tHPC (MIN.) is applied to /CAS access.
2. If tWCS ≥ tWCS (MIN.), the cycle is an early write cycle and the data out will remain Hi-Z through the entire
cycle. If t
RWD ≥ RWD (MIN.) CWD ≥ CWD (MIN.) AWD ≥ AWD (MIN.)
t
, t , t
t
t
and tCPWD ≥ tCPWD (MIN.), the cycle is a read modify
write cycle and the data out will contain data read from the selected cell. If neither of the above conditions
is met, the state of the data out is indeterminate.
3. /WE : inactive (in read cycle)
CHO
/CAS : inactive, /OE : active ...... t
is effective.
OCH
/CAS, /OE : active ...... t
is effective.
4. tOFC (MAX.), tOFR (MAX.) and tWEZ (MAX.) define the time when the output achieves the conditions of Hi-Z and is
OH
OL
not referenced to V or V
.
5. To make DQs to Hi-Z in read cycle, it is necessary to control /RAS, /CAS, /WE, /OE as follows. The effective
specification depends on state of each signal.
(1) Both /RAS and /CAS are inactive (at the end of the read cycle)
/WE : inactive, /OE : active
OFC
t
t
is effective when /RAS is inactivated before /CAS is inactivated.
is effective when /CAS is inactivated before /RAS is inactivated.
OFR
OFC
OFR
The slower of t
and t
becomes effective.
(2) Both /RAS and /CAS are active or either /RAS or /CAS is active (in read cycle)
OEZ
/WE, /OE : inactive ...... t
is effective.
Both /RAS and /CAS are inactive or /RAS is active and /CAS is inactive (at the end of read cycle)
RRH
RCH
WEZ
WPZ
/WE, /OE : active and either t
or t
becomes effective.
The faster of (1) and (2) becomes effective.
must be met ...... t
and t
are effective.
OEZ
WEZ
The faster of t
and t
11
MC-428LFG641
Refresh Cycle
Parameter
Symbol
tRAC = 50 ns
tRAC = 60 ns
Unit
Note
MIN.
MAX.
MIN.
MAX.
/CAS setup time
tCSR
tCHR
tRPC
tWSR
tWHR
5
−
−
−
−
−
5
−
−
−
−
−
ns
ns
ns
ns
ns
/CAS hold time (/CAS before /RAS refresh)
/RAS precharge /CAS hold time
/WE setup time
10
5
10
5
10
15
10
15
/WE hold time
12
MC-428LFG641
Serial PD
Byte No.
Function Described
Number of serial PD bytes
Serial memory
Hex
5DH
08H
02H
0CH
0BH
01H
40H
00H
01H
32H
3CH
0DH
0FH
00H
00H
08H
00H
00H
01H
08H
14H
10H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
93 bytes
256 bytes
EDO
0
1
2
3
4
5
6
7
8
9
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
0
0
0
1
0
0
0
Fundamental memory type
Number of rows
12 rows
11 columns
1 bank
64 bits
0
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
50 ns
/RAS access time
-A50
-A60
-A50
-A60
60 ns
10
/CAS access time
13 ns
15 ns
11
12
Error detection/correction
Refresh period
None
Normal
×8
13
DRAM width
14
Error checking DRAM width
None
15 - 61
62
SPD revision
1
63
Checksum for bytes 0 - 62
-A50
-A60
64
Manufacture’s JEDEC ID code per
JEP-106E
65-71
72
73
74
75
76
77
78
79
80
81
82
83
00H
0
0
0
0
0
0
0
0
Manufacturing location
Part name
34H
32H
38H
4CH
46H
47H
36H
34H
31H
46H
42H
48H
2DH
41H
35H
36H
30H
20H
20H
20H
31H
20H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
1
0
0
1
0
1
1
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
0
0
1
0
Part name
Part name
Part name
Part name
Part name
Part name
Part name
Part name
Part name
Part name
MC-428LFG641FB
MC-428LFG641FH
84
85
86
Part name
Part name
Part name
-A50
-A60
87
88
89
90
91
92
Part name
Part name
Part name
Part name
PCB revision code
Blank
Remark 1 : High level (Serial data), 0 : Low level (Serial data)
13
MC-428LFG641
Read Cycle
t
RC
t
RP
t
RAS
V
V
IH
IL
/RAS
t
CSH
t
CRP
t
CPN
tRCD
t
t
RSH
CAS
V
V
IH
IL
/CAS
t
RAD
t
RAL
t
ASR
t
RAH
t
ASC
t
CAH
V
V
IH
IL
Address
Row
Col.
tRCH
t
RCS
t
WPZ
tRRH
V
V
IH
IL
/WE
/OE
t
OCH
t
t
OES
OEA
tCHO
t
WEZ
V
IH
V
IL
t
t
RAC
AA
t
t
OFC
OEZ
t
CAC
t
OLZ
t
OFR
t
CLZ
Hi - Z
Hi - Z
V
V
OH
OL
DQ
Data out
14
MC-428LFG641
Early Write Cycle
t
RC
t
RAS
t
RP
V
V
IH
IL
/RAS
/CAS
t
CSH
t
t
RSH
CAS
t
CRP
t
CPN
tRCD
V
V
IH
IL
t
RAD
t
ASC
t
CAH
t
ASR
t
RAH
V
V
IH
IL
Address
Row
Col.
t
WCS
t
WCH
V
V
IH
IL
/WE
DQ
tDS
t
DH
V
V
IH
IL
Data in
Remark /OE : Don’t care
15
MC-428LFG641
Late Write Cycle
tRC
tRAS
tRP
VIH
/RAS
VIL
tCSH
tCRP
tRCD
tRSH
tCPN
tCAS
VIH
/CAS
VIL
tRAD
tRAH
tASC
t
CAH
tASR
VIH
VIL
Address
Row
Col.
tCWL
tRWL
tRCS
tWP
VIH
VIL
/WE
tOEH
VIH
/OE
VIL
tOED
tDS
tDH
Hi - Z
VIH
VIL
DQ
Data in
16
MC-428LFG641
Read Modify Write Cycle
t
RWC
t
RAS
t
RP
V
V
IH
IL
/RAS
/CAS
t
CSH
t
CRP
t
RCD
t
CPN
t
t
RSH
CAS
V
V
IH
IL
t
RAD
t
ASR
t
RAH
t
ASC
CAH
t
V
V
IH
IL
Address
Row
Col.
t
t
t
RWD
AWD
CWD
t
t
CWL
RWL
t
RCS
t
WP
V
IH
/WE
/OE
V
IL
t
OEA
t
OEH
V
V
IH
IL
t
t
t
RAC
AA
CAC
t
OED
t
DS
tDH
V
V
IH
IL
DQ
DQ
Data in
t
OLZ
OEZ
t
t
CLZ
Hi - Z
Hi - Z
V
V
OH
OL
Data out
17
MC-428LFG641
Hyper Page Mode (EDO) Read Cycle
t
RASP
t
RP
t
RHCP
V
V
IH
IL
/RAS
/CAS
t
RSH
t
CSH
t
HPC
t
CRP
t
HCAS
t
CPN
t
RCD
t
HCAS
t
CP
t
HCAS
t
CP
V
V
IH
IL
t
RAL
t
RAD
t
t
OFR
OFC
t
ASR
t
RAH
t
ASC
t
ASC
t
CAH
t
ASC
t
CAH
t
CAH
V
V
IH
IL
Address
/WE
Row
Col.
Col.
Col.
t
t
RCH
RRH
t
RCS
t
WPZ
V
V
IH
IL
t
WEZ
t
CHO
t
t
t
ACP
AA
t
t
t
ACP
t
OCH
t
t
OEA
AA
V
V
IH
IL
OLZ
CAC
CAC
/OE
t
RAC
t
AA
t
DHC
t
DHC
t
OEZ
t
CAC
CLZ
t
V
V
OH
OL
Hi - Z
DQ
Data out
Data out
Data out
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive /CAS cycles within the same /RAS cycle.
18
MC-428LFG641
Hyper Page Mode (EDO) Read Cycle (/WE Control)
t
RASP
t
RP
t
RHCP
V
V
IH
IL
/RAS
/CAS
t
RSH
t
CSH
t
t
CRP
ASR
HCAS
t
t
HCAS
t
CPN
t
RCD
t
HCAS
V
V
IH
IL
t
RAD
t
RAL
t
ASC
t
RAH
tASC
tCAH
CAH
t
CAH
t
t
ASC
V
V
IH
IL
Address
/WE
Row
Col.
Col.
Col.
t
RCH
t
WPZ
t
WPZ
t
WPZ
WEZ
t
RCS
t
RCH
t
RCS
t
RRH
t
RCH
tRCS
V
V
IH
IL
t
t
t
OCH
OEA
t
CHO
t
OLZ
V
IH
/OE
V
IL
t
t
t
OFR
t
t
RAC
AA
t
AA
OFC
OEZ
t
AA
t
CAC
CAC
t
WEZ
t
WEZ
t
t
CAC
CLZ
t
CLZ
t
CLZ
t
V
V
OH
OL
Hi - Z
Hi - Z
Hi - Z
DQ
Data out
Data out
Data out
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive /CAS cycles within the same /RAS cycle.
19
MC-428LFG641
Hyper Page Mode (EDO) Read Cycle (/OE Control)
t
RASP
t
RP
t
RHCP
V
V
IH
IL
/RAS
t
t
RSH
t
CSH
t
HPC
t
CRP
t
RCD
t
HCAS
t
CP
t
HCAS
t
CP
HCAS
t
CPN
V
V
IH
IL
/CAS
t
RAD
t
OFC
t
RAL
t
OFR
t
ASC
t
RAH
t
ASR
t
ASC
t
CAH
t
ASC
t
CAH
t
CAH
V
V
IH
IL
Address
Row
Col.A
Col.B
Col.C
t
RAC
t
t
RCH
t
t
AA
t
t
AA
t
RCS
CAC
CAC
RRH
t
t
t
OES
CAC
V
V
IH
IL
/WE
t
AA
t
CHO
t
CHO
t
OCH
t
ACP
t
OCH
t
ACP
CHO
t
OEA
t
OEP
tOEP
tOCH
t
OEP
V
V
IH
IL
/OE
DQ
t
t
OEA
OLZ
t
t
OEA
OLZ
t
OLZ
t
CLZ
t
OEZ
t
CLZ
t
OEZ
t
OEZ
t
OEZ
V
V
OH
OL
Hi - Z
Hi - Z
Data out A
Data out B
Data out B
Data out C
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive /CAS cycles within the same /RAS cycle.
20
MC-428LFG641
Hyper Page Mode (EDO) Early Write Cycle
t
RASP
t
RP
t
RHCP
V
V
IH
IL
/RAS
/CAS
t
CSH
t
HPC
t
RSH
t
CRP
tRCD
t
HCAS
tCP
t
HCAS
tCP
t
HCAS
t
CPN
V
V
IH
IL
t
RAL
t
RAD
t
ASR
t
RAH
t
ASC
t
ASC
t
ASC
t
CAH
t
CAH
t
CAH
V
V
IH
IL
Address
Row
Col.
Col.
Col.
t
WCS
t
WCS
t
WCS
t
WCH
t
WCH
t
WCH
V
V
IH
IL
/WE
t
DS
t
DS
t
DS
t
DH
t
DH
t
DH
V
V
IH
IL
DQ
Data in
Data in
Data in
Remarks 1. /OE : Don’t care
2. In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive /CAS cycles within the same /RAS cycle.
21
MC-428LFG641
Hyper Page Mode (EDO) Late Write Cycle
t
RASP
tRP
t
RHCP
V
V
IH
IL
/RAS
/CAS
t
HPC
t
RSH
t
CSH
CRP
t
CPN
t
t
RCD
t
HCAS
t
CP
t
HCAS
t
CP
t
HCAS
V
V
IH
IL
tRAL
RAD
t
t
ASR
t
RAH
tASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
V
V
IH
IL
Address
Row
Col.
Col.
Col.
tCWL
t
t
t
t
CWL
CWL
RWL
tRCS
tWP
t
WP
t
RCS
WP
tRCS
V
V
IH
IL
/WE
/OE
t
OEH
t
OEH
t
OEH
V
V
IH
IL
t
OED
t
DS
t
DH
t
OED
DS
t
DH
t
OED
t
DS
t
DH
t
Hi-Z
Hi-Z
Hi-Z
V
V
IH
IL
Data in
Data in
Data in
DQ
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive /CAS cycles within the same /RAS cycle.
22
MC-428LFG641
Hyper Page Mode (EDO) Read Modify Write Cycle
t
RASP
t
RP
V
V
IH
IL
/RAS
t
HPRWC
t
t
CRP
t
RCD
t
HCAS
t
t
CP
t
HCAS
t
CP
t
HCAS
t
CPN
V
V
IH
IL
/CAS
Address
/WE
t
RAD
t
RAL
ASR
t
CAH
ASC
t
CAH
t
ASC
t
CAH
t
RAH
t
ASC
V
V
IH
IL
Row
Col.
Col.
Col.
t
ACP
t
ACP
t
t
t
RWD
tCWL
t
t
t
CPWD
t
t
t
CPWD
t
CWL
WP
AWD
CWD
AWD
CWD
AWD
CWD
t
RWL
t
WP
CWL
t
RCS
t
tRCS
t
t
RCS
t
WP
V
V
IH
IL
t
RAC
AA
t
t
AA
t
AA
t
CAC
OEA
t
OEH
t
CAC
t
OEH
t
OEH
t
CAC
OEA
t
t
OEA
t
V
V
IH
IL
/OE
t
CLZ
t
OED
t
CLZ
t
OED
t
CLZ
t
OED
t
OEZ
t
OLZ
t
OEZ
t
OLZ
t
OLZ
t
OEZ
Hi-Z
Hi-Z
Hi-Z
Hi-Z
V
V
OH
OL
DQ
DQ
out
out
out
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
V
V
IH
in
in
in
IL
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive /CAS cycles within the same /RAS cycle.
23
MC-428LFG641
Hyper Page Mode (EDO) Read and Write Cycle
t
RASP
tRP
tRHCP
V
V
IH
IL
/RAS
/CAS
t
RSH
tCSH
HPC
t
t
CRP
tCPN
t
HCAS
t
RCD
t
HCAS
tCP
t
CP
t
HCAS
V
V
IH
IL
t
t
RAL
CAH
t
RAD
t
ASR
t
RAH
t
ASC
t
ASC
t
CAH
t
ASC
t
CAH
V
V
IH
IL
Row
Col.
Col.
Col.
Address
/WE
t
RCS
t
RCH
t
WCS
t
WCH
V
V
IH
IL
tCHO
t
t
t
ACP
t
t
t
OCH
OEA
OLZ
AA
V
V
IH
IL
CAC
/OE
t
OEZ
t
t
t
t
RAC
AA
t
DHC
t
WEZ
CAC
CLZ
V
V
OH
OL
Hi - Z
Hi - Z
DQ
DQ
Data out
Data out
t
DS
t
DH
V
V
IH
IL
Data in
Remark In the hyper page mode (EDO), read, write and read modify write cycles are available for each of the
consecutive /CAS cycles within the same /RAS cycle.
24
MC-428LFG641
/CAS Before /RAS Refresh Cycle
tRC
tRC
tRAS
tRP
tRAS
tRP
VIH
/RAS
VIL
tCRP
tCSR
tCHR
tRPC
tCSR
tCHR
tRPC
tCPN
VIH
/CAS
VIL
WSR
WSR
t
t WHR
t
tWHR
VIH
/WE
VIL
Remark Address, /OE : Don't care DQ : Hi-Z
/RAS Only Refresh Cycle
t
RC
tRC
t
RAS
t
RAS
t
RP
t
RP
V
V
IH
IL
/RAS
/CAS
t
CRP
t
CRP
t
RPC
t
CPN
V
V
IH
IL
ASR
t
t
RAH
tASR
t
RAH
V
V
IH
IL
Row
Row
Address
Remark /WE, /OE : Don't care DQ : Hi-Z
25
MC-428LFG641
Hidden Refresh Cycle (Read)
tRC
tRC
tRP
tRAS
t
RP
t
RAS
V
V
IH
IL
/RAS
/CAS
t
t
CRP
tRCD
tCHR
t
CPN
RSH
t
V
V
IH
IL
t
RAD
tRAL
ASR
ASC
tRAH
t
t
CAH
V
V
IH
IL
Row
Col.
Address
t
RCH
t
RCS
t
WPZ
tWHR
V
V
IH
IL
/WE
/OE
t
t
OES
tWEZ
t
CHO
OEA
V
V
IH
IL
t
RAC
tOFR
tAA
t
t
tOFC
tOEZ
CAC
OLZ
CLZ
t
Hi - Z
V
V
OH
OL
Hi - Z
DQ
Data out
26
MC-428LFG641
Hidden Refresh Cycle (Write)
t
RC
t
RC
tRAS
tRP
tRP
t
RAS
V
V
IH
IL
/RAS
/CAS
t
CRP
t
RCD
t
RSH
t
CHR
t
CPN
V
V
IH
IL
t
RAD
t
ASR
t
RAH
t
ASC
t
CAH
V
V
IH
IL
Address
Row
Col.
t
WSR
t
WHR
t
WCS
t
WCH
V
V
IH
IL
/WE
t
DS
t
DH
V
V
IH
IL
DQ
Data in
Remark /OE : Don’t care
27
MC-428LFG641
Package Drawings
[ MC-428LFG641FH ]
★
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
N
Y
Z
Q
S
(OPTIONAL HOLES)
B
A
T
H
J
K
C
I
G
D
E
B
A
UB3PS
ITEM MILLIMETERS
INCHES
5.250±0.006
0.450
detail of
part
part
detail of
A
B
C
D
E
G
H
I
133.35±0.13
11.43
W
36.83
1.450
6.35
0.250
54.61
2.150
6.35
0.250
1.27 (T.P.)
8.89
0.050 (T.P.)
0.350
G
P
J
24.495
42.18
0.964
D
K
L
1.661
17.78
0.700
M
N
P
Q
31.75
1.250
3.0 MAX.
1.0
0.118 MAX.
0.039
R2.0
R0.079
+0.005
0.157
R
4.0±0.1
–0.004
S
T
3.0
0.118
1.27±0.1
4.0 MIN.
0.25 MAX.
0.05±0.004
0.157 MIN.
0.010 MAX.
U
V
+0.003
0.039
W
1.0±0.05
–0.002
X
Y
Z
2.54 MIN.
3.0 MIN.
3.0 MIN.
0.100±0.004
0.118 MIN.
0.118 MIN.
28
MC-428LFG641
[ MC-428LFG641FB ]
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
Y
Z
N
Q
S
(OPTIONAL HOLES)
B
A
H
T
J
K
C
I
G
D
E
B
A
UB3JS
ITEM MILLIMETERS
INCHES
5.250±0.006
0.450
detail of
part
detail of
part
A
B
C
D
E
G
H
I
133.35±0.13
11.43
W
36.83
1.450
6.35
0.250
54.61
2.150
6.35
0.250
1.27 (T.P.)
8.89
0.050 (T.P.)
0.350
G
P
J
24.495
42.18
0.964
D
K
L
1.661
17.78
0.700
M
N
P
Q
31.75
1.250
5.08 MAX.
1.0
0.200 MAX.
0.039
R2.0
R0.079
+0.005
0.157
R
4.0±0.1
–0.004
S
T
3.0
0.118
1.27±0.1
4.0 MIN.
0.25 MAX.
0.05±0.004
0.157 MIN.
0.010 MAX.
U
V
+0.003
0.039
W
1.0±0.05
–0.002
X
Y
Z
2.54 MIN.
3.0 MIN.
3.0 MIN.
0.100±0.004
0.118 MIN.
0.118 MIN.
29
MC-428LFG641
[MEMO]
30
MC-428LFG641
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the
device. Immediately after the power source is turned ON, the devices with
reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not
initialized until the reset signal is received. Reset operation must be
executed imme-diately after power-on for devices having reset function.
31
MC-428LFG641
[MEMO]
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
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