MC-4516CD641PS [NEC]
16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM; 16M - WORD 64位的同步动态RAM模块SO DIMM
| 型号： | MC-4516CD641PS |
| 厂家： | 
NEC |
| 描述： | 16M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE SO DIMM |
| 文件： | 总16页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4516CD641ES, 4516CD641PS
16M-WORD BY 64-BIT
SYNCHRONOUS DYNAMIC RAM MODULE (SO DIMM)
Description
The MC-4516CD641ES and MC-4516CD641PS are 16,777,216 words by 64 bits synchronous dynamic RAM
module (Small Outline DIMM) on which 8 pieces of 128M SDRAM: µPD45128163 are assembled.
These modules provide high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 16,777,216 words by 64 bits organization
• Clock frequency and access time from CLK
Part number
/CAS latency
CL = 3
Clock frequency (MAX.)
125 MHz
Access time from CLK (MAX.)
MC-4516CD641ES-A80
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
CL = 2
100 MHz
MC-4516CD641ES-A10
MC-4516CD641PS-A80
MC-4516CD641PS-A10
CL = 3
100 MHz
CL = 2
77 MHz
★
CL = 3
125 MHz
CL = 2
100 MHz
CL = 3
100 MHz
CL = 2
77 MHz
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0, BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3V ±0.3V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14014EJ5V0DS00 (5th edition)
Date Published February 2000 NS CP(K)
Printed in Japan
The mark • shows major revised points.
1999
©
MC-4516CD641ES, 4516CD641PS
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-4516CD641ES-A80
MC-4516CD641ES-A10
MC-4516CD641PS-A80
MC-4516CD641PS-A10
125 MHz
100 MHz
125 MHz
100 MHz
144-pin Small Outline DIMM
(Socket Type)
8 pieces of µPD45128163G5 (Rev. E)
(10.16mm (400) TSOP(II))
Edge connector: Gold plated
31.75 mm height
★
★
8 pieces of µPD45128163G5 (Rev. P)
(10.16mm (400) TSOP(II))
2
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Pin Configuration
144-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
2
4
Vss
Vss
DQ 0
DQ 1
DQ 2
DQ 3
1
/xxx indicates active low signal.
DQ 32
DQ 33
DQ 34
DQ 35
Vcc
3
6
5
8
7
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
9
VCC
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
DQ 36
DQ 37
DQ 38
DQ 39
Vss
DQ 4
DQ 5
DQ 6
DQ 7
Vss
DQMB4
DQMB5
Vcc
DQMB0
DQMB1
V
CC
A3
A0
A1
A4
A5
A2
Vss
Vss
DQ 40
DQ 41
DQ 42
DQ 43
Vcc
DQ 8
DQ 9
DQ 10
DQ 11
VCC
DQ 44
DQ 45
DQ 46
DQ 47
Vss
NC
NC
DQ 12
DQ 13
DQ 14
DQ 15
Vss
NC
NC
62
64
CKE0
Vcc
CLK0
Vcc
61
63
66
/CAS
CKE1
NC
/RAS
/WE
/CS0
/CS1
NC
65
68
67
70
69
72
NC
71
74
CLK1
Vss
73
76
Vss
75
78
NC
NC
77
A0 - A11
: Address Inputs
80
NC
NC
79
82
Vcc
VCC
81
[Row: A0 - A11, Column: A0 - A8]
84
DQ 48
DQ 49
DQ 50
DQ 51
Vss
DQ 16
DQ 17
DQ 18
DQ 19
Vss
83
86
85
BA0 (A13), BA1 (A12) : SDRAM Bank Select
88
87
90
89
92
91
DQ0 - DQ63
CLK0, CLK1
CKE0, CKE1
/CS0, /CS1
/RAS
: Data Inputs/Outputs
: Clock Input
94
DQ 52
DQ 53
DQ 54
DQ 55
Vcc
DQ 20
DQ 21
DQ 22
DQ 23
Vcc
93
96
95
98
97
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
99
: Clock Enable Input
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
A7
A6
BA0 (A13)
Vss
A8
Vss
BA1 (A12)
A11
A9
A10
Vcc
Vcc
/CAS
DQMB6
DQMB7
Vss
DQMB2
DQMB3
Vss
/WE
DQ 56
DQ 57
DQ 58
DQ 59
Vcc
DQ 60
DQ 61
DQ 62
DQ 63
Vss
SCL
Vcc
DQ 24
DQ 25
DQ 26
DQ 27
DQMB0 - DQMB7 : DQ Mask Enable
SDA
SCL
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
VCC
DQ 28
DQ 29
DQ 30
DQ 31
Vss
CC
V
SS
V
SDA
VCC
NC
: No Connection
3
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Block Diagram
CKE1
CKE0
/CS1
/CS0
/CS
/CS
CKE
CKE
/CS
CKE
CKE
/CS
UDQM
DQ 7
LDQM
DQ 8
UDQM
DQ 7
LDQM
DQ 8
DQMB0
DQ 0
DQMB1
DQ 8
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 6
DQ 6
DQ 1
DQ 9
DQ 9
DQ 5
DQ 5
DQ 2
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
UDQM
DQ 0
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
UDQM
DQ 0
DQ 4
DQ 4
DQ 3
DQ 3
DQ 3
DQ 4
DQ 2
DQ 2
DQ 5
DQ 1
DQ 1
DQ 6
DQ 0
D0
D4
DQ 0
D2
D6
DQ 7
LDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
LDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQMB4
DQ 32
DQ 33
DQ 34
DQ 35
DQ 36
DQ 37
DQ 38
DQ 39
DQMB5
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
DQ 1
DQ 1
DQ 2
DQ 2
DQ 3
DQ 3
DQ 4
DQ 4
DQ 5
DQ 5
DQ 6
DQ 6
DQ 7
DQ 8
DQ 7
DQ 8
/CS CKE
/CS CKE
CKE
CKE
/CS
/CS
UDQM
DQ 7
LDQM
DQ 8
UDQM
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
LDQM
LDQM
DQ 8
DQMB2
DQ 16
DQ 17
DQ 18
DQ 19
DQ 20
DQ 21
DQ 22
DQMB3
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DQ 6
DQ 9
DQ 9
DQ 5
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
UDQM
DQ 0
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
UDQM
DQ 0
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
D1
D5
D3
D7
DQ 23
DQMB6
DQ 48
LDQM
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQMB7
DQ 56
DQ 57
DQ 58
DQ 59
DQ 60
DQ 61
DQ 62
DQ 63
DQ 15
DQ 14
DQ 13
DQ 12
DQ 11
DQ 10
DQ 9
DQ 49
DQ 1
DQ 1
DQ 50
DQ 2
DQ 2
DQ 51
DQ 3
DQ 3
DQ 52
DQ 4
DQ 4
DQ 53
DQ 5
DQ 5
DQ 54
DQ 6
DQ 6
DQ 8
DQ 7
DQ 7
DQ 55
DQ 8
SERIAL PD
V
CC
D0 - D7
D0 - D7
C
VSS
SCL
SDA
A0 A1 A2
CLK0
CLK1
/RAS
/CAS
/WE
CLK : D0 - D3
CLK : D4 - D7
/RAS : D0 - D7
/CAS : D0 - D7
/WE : D0 - D7
A0 - A11
BA0
A0 - A11 : D0 - D7
A13 : D0 - D7
BA1
A12 : D0 - D7
Remarks 1. D0 - D7: µPD45128163 (2M words x 16 bits x 4 banks)
2. The value of all resistors is 10 Ω.
4
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 100 µs and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
8
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
Low level input voltage
VCC + 0.3
+ 0.8
70
V
VIL
V
Operating ambient temperature
TA
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
30
TYP.
MAX.
60
Unit
pF
Input capacitance
A0 - A11, BA0(A13), BA1(A12),
/RAS, /CAS, /WE
CI2
CI3
CI4
CI5
CI/O
CLK0, CLK1
CKE0, CKE1
/CS0, /CS1
23
18
18
7
37
30
30
14
18
DQMB0 - DQMB7
DQ0 - DQ63
Data input/output capacitance
9
pF
5
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
ICC1
Test condition
Burst length = 1, tRC ≥ tRC(MIN.)
MIN. MAX. Unit Notes
Operating current
/CAS latency = 2 -A80
560
560
560
560
8
mA
1
-A10
/CAS latency = 3 -A80
-A10
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL(MAX.), tCK = 15 ns
mA
mA
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
ICC2N
8
Precharge standby current in
non power down mode
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
160
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
ICC3N
64
40
Active standby current in
power down mode
mA
mA
32
Active standby current in
non power down mode
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
240
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞, Input signals are stable.
160
700
Operating current
(Burst mode)
ICC4
tCK ≥ tCK(MIN.), IO = 0 mA
/CAS latency = 2 -A80
mA
mA
2
3
-A10
/CAS latency = 3 -A80
-A10
560
820
680
★
★
CBR (Auto) refresh current
ICC5
tRC ≥ tRC(MIN.)
/CAS latency = 2 -A80
-A10
1,040
1,040
1,040
1,040
16
/CAS latency = 3 -A80
-A10
Self refresh current
ICC6
II(L)
CKE ≤ 0.2 V
mA
µA
µA
V
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 8
–3
+8
IO(L)
VOH
VOL
+3
2.4
IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
6
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
★ Test Conditions
Parameter
Value
2.4 / 0.4
1.4
Unit
V
AC high level input voltage / low level input voltage
Input timing measurement reference level
Transition time (Input rise and fall time)
V
1
ns
V
Output timing measurement reference level
1.4
t
CK
t
CH
t
CL
2.4 V
CLK
1.4 V
0.4 V
t
SETUP
t
HOLD
2.4 V
1.4 V
0.4 V
Input
t
AC
t
OH
Output
7
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Synchronous Characteristics
Parameter
Symbol
tCK3
-A80
-A10
Unit
Note
MIN.
8
MAX.
MIN.
10
MAX.
Clock cycle time
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
(125 MHz)
(100 MHz)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CK2
10
(100 MHz)
13
(77 MHz)
Access time from CLK
tAC3
6
6
6
7
1
1
t
AC2
CLK high level width
tCH
tCL
tOH
tLZ
3
3
3
0
3
3
2
1
2
1
2
1
2
2
3
3
3
0
3
3
2
1
2
1
2
1
2
2
CLK low level width
Data-out hold time
1
Data-out low-impedance time
Data-out high-impedance time
/CAS latency = 3
/CAS latency = 2
tHZ3
6
6
6
7
t
HZ2
Data-in setup time
Data-in hold time
tDS
tDH
Address setup time
Address hold time
CKE setup time
tAS
tAH
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
Command (/CS0, /CS1, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0, /CS1, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
1
1
ns
Note 1. Output load
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
8
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Asynchronous Characteristics
Parameter
Symbol
Unit
Note
-A80
-A10
MIN.
MAX.
MIN.
MAX.
ACT to REF/ACT command period (Operation)
REF to REF/ACT command period (Refresh)
ACT to PRE command period
tRC
tRC1
tRAS
tRP
70
70
ns
ns
70
78
48
120,000
50
120,000
ns
PRE to ACT command period
20
20
ns
Delay time ACT to READ/WRITE command
ACT(one) to ACT(another) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
tDAL3
20
20
ns
16
20
ns
8
1CLK+20
1CLK+20
2
10
ns
Data-in to ACT(REF) command
period (Auto precharge)
/CAS latency = 3
/CAS latency = 2
1CLK+20
ns
t
DAL2
1CLK+20
ns
Mode register set cycle time
Transition time
tRSC
tT
2
1
CLK
ns
0.5
30
64
30
64
Refresh time (4,096 refresh cycles)
tREF
ms
9
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
Serial PD
Byte No.
0
(1/2)
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
3
4
5
6
7
8
9
Total number of bytes of serial PD memory
08H
04H
0CH
09H
02H
40H
00H
01H
80H
A0H
60H
60H
00H
80H
10H
00H
01H
8FH
04H
06H
01H
01H
00H
0EH
A0H
D0H
60H
70H
00H
14H
14H
10H
14H
14H
14H
30H
32H
10H
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
256 bytes
SDRAM
12 rows
9 columns
2 banks
64 bits
0
Fundamental memory type
Number of rows
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 Cycle time
-A80
-A10
-A80
-A10
10 ns
6 ns
10
CL =3 Access time
6 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
None
Normal
×16
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
None
1 clock
1, 2, 4, 8, F
4 banks
2, 3
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
0
SDRAM module attributes
SDRAM device attributes : General
CL = 2 Cycle time
-A80
10 ns
13 ns
6 ns
-A10
-A80
-A10
24
CL = 2 Access time
7 ns
25-26
27
tRP(MIN.)
-A80
-A10
-A80
-A10
-A80
-A10
-A80
-A10
20 ns
20 ns
16 ns
20 ns
20 ns
20 ns
48 ns
50 ns
64M bytes
28
29
30
31
tRRD(MIN.)
tRCD(MIN.)
tRAS(MIN.)
Module bank density
10
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
(2/2)
Byte No.
32
Function Described
Command and address
Hex
20H
20H
10H
10H
20H
20H
10H
10H
00H
12H
12H
E8H
4EH
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
2 ns
-A80
-A10
-A80
-A10
-A80
-A10
-A80
-A10
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
signal setup time
2 ns
1 ns
1 ns
2 ns
2 ns
1 ns
1 ns
33
34
35
Command and address
signal hold time
Data signal input setup time
Data signal input hold time
SPD revision
36-61
62
-A80
-A10
-A80
-A10
1.2 A
1.2 A
63
Checksum
for bytes 0 - 62
64-71
72
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
Revision code
73-90
91-92
93-94
95-98
Manufacturing date
Assembly serial number
99-125 Mfg specific
126
Intel specification frequency
-A80
-A10
-A80
-A10
64H
64H
C7H
C5H
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
0
0
0
1
1
100 MHz
100 MHz
127
Intel specification /CAS
latency support
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348E).
11
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
★
Package Drawings
[MC-4516CD641ES]
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
N
Y
Z
M1 (AREA B)
R
Q
L
M
M2 (AREA A)
U1
U2
T
S
A
H
(OPTIONAL HOLES)
C
B
I
E
D
A1 (AREA A)
F
ITEM MILLIMETERS
A
A1
B
67.6
67.6±0.15
23.2
C
29.0
D
4.6
D1
D2
E
1.5±0.10
4.0
32.8
detail of A part
W
F
3.7
H
0.8 (T.P.)
3.3
D2
I
L
20.0
M
M1
M2
N
31.75±0.15
9.75
22.0
D1
3.8 MAX.
R2.0
X
Q
R
V
4.00±0.10
φ
S
1.8
T
1.0±0.1
U1
U2
V
3.2 MIN.
4.0 MIN.
0.25 MAX.
0.6±0.05
2.55 MIN.
2.0 MIN.
2.0 MIN.
M144S-80A14
W
X
Y
Z
12
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
[MC-4516CD641PS]
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
N
Y
Z
M1 (AREA B)
R
Q
L
M
M2 (AREA A)
I
U1
U2
T
S
A
H
(OPTIONAL HOLES)
C
B
E
D
A1 (AREA A)
F
ITEM MILLIMETERS
A
A1
B
67.6
67.6±0.15
23.2
C
29.0
D
4.6
D1
D2
E
1.5±0.10
4.0
32.8
detail of A part
W
F
3.7
H
0.8 (T.P.)
3.3
D2
I
L
20.0
M
M1
M2
N
31.75±0.15
9.75
22.0
D1
3.8 MAX.
R2.0
X
Q
R
V
4.00±0.10
φ
S
1.8
T
1.0±0.1
U1
U2
V
3.2 MIN.
4.0 MIN.
0.25 MAX.
0.6±0.05
2.55 MIN.
2.0 MIN.
2.0 MIN.
M144S-80A16
W
X
Y
Z
13
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
[MEMO]
14
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
15
Data Sheet M14014EJ5V0DS00
MC-4516CD641ES, 4516CD641PS
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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