MC-4532DC726LFA-A80 [NEC]
Synchronous DRAM Module, 32MX72, 6ns, MOS, DIMM-168;
| 型号： | MC-4532DC726LFA-A80 |
| 厂家： | 
NEC |
| 描述： | Synchronous DRAM Module, 32MX72, 6ns, MOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-4532DC726
32 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-4532DC726 is a 33,554,432 words by 72 bits synchronous dynamic RAM module on which 36 pieces of
64 M SDRAM: µPD4564441 are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 33,554,432 words by 72 bits organization (ECC type)
• Clock frequency and Access time from CLK
Part number
/CAS latency
Clock frequency
(MAX.)
Access time from CLK
(MAX.)
MC-4532DC726FA-A80
MC-4532DC726FA-A10
MC-4532DC726LFA-A80
MC-4532DC726LFA-A10
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
100 MHz
100 MHz
77 MHz
6 ns
6 ns
6 ns
7 ns
6 ns
6 ns
6 ns
7 ns
125 MHz
100 MHz
100 MHz
77 MHz
★
★
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• All DQs have 10 Ω ± 10 % of series resistor
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
• Stacked Module
★
• PC100 registered DIMM Rev. 1.0 compliant
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M13201EJ7V0DS00 (7th edition)
Date Published March 1999 NS CP(K)
Printed in Japan
The mark ★ shows major revised points.
1998
©
MC-4532DC726
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-4532DC726FA-A80
MC-4532DC726FA-A10
MC-4532DC726LFA-A80
MC-4532DC726LFA-A10
125 MHz
100 MHz
125 MHz
100 MHz
168-pin Dual In-line Memory Module
(Socket Type)
36 pieces of µPD4564441G5 (Rev. E)
(400 mil TSOP (II))
★
★
Edge connector: Gold plated
43.18 mm (1.70 inch) height
36 pieces of µPD4564441G5 (Rev. L)
(400 mil TSOP (II))
2
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
VSS
/xxx indicates active low signal.
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
V
SS
V
SS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
CB4
DQ14
DQ15
CB0
CB5
CB1
V
SS
V
SS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
SS
V
SS
A0
A2
A1
A3
A4
A0 - A11
: Address Inputs
A5
A6
A7
A8
A9
[Row : A0 - A11, Column : A0 - A9]
A10
BA0(A13)
A11
Vcc
BA1(A12)
Vcc
BA0 (A13), BA1 (A12) : SDRAM Bank Select
DQ0-DQ63, CB0-CB7 : Data Inputs/Outputs
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CLK0
V
SS
VSS
CLK0 - CLK3
CKE0
: Clock Input
CKE0
/CS3
DQMB6
DQMB7
NC
NC
/CS2
DQMB2
DQMB3
NC
: Clock Enable Input
: Write Protect Note
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
WP
Vcc
Vcc
NC
NC
NC
NC
/CS0 - /CS3
/RAS
CB6
CB2
CB7
CB3
V
SS
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
/CAS
/WE
DQ52
NC
DQ20
NC
DQMB0 - DQMB7
SA0 - SA2
SDA
: DQ Mask Enable
: Address Input for EEPROM
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
NC
NC
REGE
NC
V
SS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
V
SS
VSS
SCL
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
CC
V
SS
V
: Ground
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
VSS
CLK2
NC
WP
REGE
NC
: Register/Buffer Enable
: No Connection
V
SS
CLK3
NC
SA0
SA1
SA2
Vcc
Note WP is not used yet. It is connected to ground.
SDA
SCL
Vcc
3
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Block Diagram
(1/2)
/RCS1
/RCS0
RDQMB4
RDQMB0
I/O 0
I/O 1
I/O 2
I/O 3
DQ 0
DQ 1
DQ 2
DQ 3
I/O 3
I/O 2
I/O 1
I/O 0
DQ 32
DQ 33
DQ 34
DQ 35
I/O 3
I/O 2
I/O 1
I/O 0
DQM
DQM
/CS
/CS
/CS
/CS
DQM
/CS
/CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
/CS
/CS
D0
D18
D9
D27
DQ 36
DQ 37
DQ 38
DQ 39
DQ 4
DQ 5
DQ 6
DQ 7
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM
DQM
DQM
DQM
D1
D19
D10
D28
RDQMB5
RDQMB1
DQ 40
DQ 41
DQ 42
DQ 43
I/O 0
I/O 1
I/O 2
I/O 3
DQ 8
I/O 3
I/O 2
I/O 1
I/O 0
DQM
/CS
/CS
/CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 0
I/O 1
I/O 2
I/O 3
DQM
/CS
/CS
/CS
DQM
/CS
DQM
/CS
/CS
DQ 9
D2
D20
D11
D29
DQ 10
DQ 11
I/O 0
I/O 1
I/O 2
I/O 3
I/O 3
I/O 2
I/O 1
I/O 0
DQM
DQM
DQM
DQ 44
DQ 45
DQ 46
DQ 47
I/O 0
I/O 1
I/O 2
I/O 3
DQ 12
DQ 13
DQ 14
DQ 15
I/O 3
I/O 2
I/O 1
I/O 0
DQM
/CS
/CS
D12
D3
D21
D30
DQM
DQM
/CS
CB 4
CB 5
CB 6
CB 7
DQM
I/O 2
I/O 3
I/O 0
I/O 1
I/O 1
I/O 0
I/O 3
I/O 2
I/O 2
I/O 3
I/O 0
I/O 1
DQM
I/O 1
I/O 0
I/O 3
I/O 2
CB 0
CB 1
CB 2
CB 3
D13
D4
D22
D31
/RCS3
/RCS2
RDQMB2
RDQMB6
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQM
/CS
/CS
DQ 48
DQ 49
DQ 50
DQ 51
I/O 3
I/O 2
I/O 1
I/O 0
DQM
/CS
/CS
DQM
/CS
/CS
DQM
/CS
/CS
DQ 16
DQ 17
DQ 18
DQ 19
I/O 3
I/O 2
I/O 1
I/O 0
D5
D23
D32
D14
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ 20
DQ 21
DQ 22
DQ 23
DQM
DQ 52
DQ 53
DQ 54
DQ 55
DQM
DQM
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
D6
D24
D15
D33
RDQMB3
RDQMB7
I/O 0
I/O 1
I/O 2
I/O 3
DQM
/CS
/CS
I/O 3
I/O 2
I/O 1
I/O 0
I/O 3
I/O 2
I/O 1
I/O 0
DQ 24
DQ 25
DQ 26
DQ 27
DQM
DQ 56
DQ 57
DQ 58
DQ 59
/CS
/CS
I/O 0
I/O 1
I/O 2
I/O 3
DQM
/CS
/CS
DQM
/CS
/CS
D7
D25
D16
D34
DQ 60
DQ 61
DQ 62
DQ 63
I/O 3
I/O 2
I/O 1
I/O 0
DQM
I/O 3
I/O 2
I/O 1
I/O 0
DQM
I/O 0
I/O 1
I/O 2
I/O 3
DQM
DQ 28
DQ 29
DQ 30
DQ 31
DQM
I/O 0
I/O 1
I/O 2
I/O 3
D8
D26
D17
D35
SERIAL PD
CLK : D0, D1, D18
CLK : D2, D19, D20
CLK : D3, D4, D21
CLK : D5, D22, D23
CLK : D6, D7, D24
CLK : D8, D25, D26
SDA
20 Ω
SCL
CLK0
WP
A0
A1
A2
PLL1
47kΩ
SA0 SA1 SA2
CLK : Register 1, Register 2
CLK : D9, D10, D27
20 Ω
CLK : D11, D28, D29
CLK : D12, D13, D30
CLK : D14, D31, D32
CLK : D17, D34, D35
CLK : D15, D16, D33
CLK : Register 3, Register 4
Vcc
GND
D0 - D35, REGISTER, PLL
D0 - D35, REGISTER, PLL
C
PLL2
10 Ω
CLK1 - CLK3
30 pF
4
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Block Diagram
(2/2)
/RCS0 - /RCS1
RDQMB0 - RDQMB1
/RRAS
/CS0 - /CS1
DQMB0 - DQMB1
/RAS
/RAS: D0 - D8, D18 - D26
/CAS: D0 - D8, D18 - D26
/WE: D0 - D8, D18 - D26
A0 - A8: D0 - D8, D18 - D26
Register 1
/CAS
/RCAS
/WE
10 kΩ
/RWE
A0 - A8
RA0 - RA8
/LE
REGE
/RCS0 - /RCS1
RDQMB4 - RDQMB5
DQMB4 - DQMB5
/RRAS
/RCAS
/RAS: D9 - D17, D27 - D35
/CAS: D9 - D17, D27 - D35
/WE: D9 - D17, D27 - D35
Register 2
/RWE
RA0 - RA8
A0 - A8: D9 - D17, D27 - D35
/LE
/CS2 - /CS3
DQMB2 - DQMB3
CKE0
/RCS2 - /RCS3
RDQMB2 - RDQMB3
RCKE0
Register 3
/LE
CKE: D0 - D8, D18 - D26
RA9 - RA11, RBA0 - RBA1
A9 - A11, BA0 - BA1
A9 - A11, BA0 - BA1: D0 - D8, D18 - D26
/RCS2 - /RCS3
DQMB6 - DQMB7
RDQMB6 - RDQMB7
RCKE0
Register 4
/LE
CKE: D9 - D17, D27 - D35
RA9 - RA11, RBA0 - RBA1
A9 - A11, BA0 - BA1: D9 - D17, D27 - D35
Remarks 1. The series resistor values of DQs are 10 Ω.
2. WP is not used yet. It is connected to ground.
3. D0 - D35: µPD4564441 (4M words × 4 bits × 4 banks)
4. REGE ≤ VIL: Buffer Mode
IH
REGE ≥ V : Register Mode
5. Register: SN74ALVC16334DGG
PLL: CDC2509APW
6. D0 - D8, D18 - D26, Register 1, Register 3, and PLL 1 are assembled on main PCB.
D9 - D17, D27 - D35, Register 2, Register 4 and PLL 2 are assembled on sub PCB.
5
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 1 ms and then, execute power on sequence and CBR (Auto) refresh before proper
device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
−0.5 to +4.6
−0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
42
Operating ambient temperature
Storage temperature
TA
0 to +70
−55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
High level input voltage
Low level input voltage
Operating ambient temperature
VCC +0.3
+ 0.8
70
V
VIL
V
TA
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
8
TYP.
MAX.
17
Unit
pF
Input capacitance
A0 - A11, BA0(A13), BA1(A12),
/RAS, /CAS, /WE,
CI2
CI3
CI4
CI5
CI/O
CLK0 - CLK3
CKE0
15
14
8
35
31
17
12
21
/CS0 - /CS3,
DQMB0 - DQMB7
DQ0 - DQ63, CB0 - CB7
5
Data input/output capacitance
11
pF
6
Data Sheet M13201EJ7V0DS00
MC-4532DC726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
[MC-4532DC726FA]
Parameter
Symbol
Test condition
MIN. MAX. Unit Notes
Burst length = 1
tRC ≥ tRC(MIN.)
IO = 0 mA
Operating current
ICC1
/CAS latency = 2 -A80
-A10
2,350 mA
2,170
1
/CAS latency = 3 -A80
-A10
2,440
2,260
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns
536
28
mA
power down mode
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Precharge standby current in ICC2N
non power down mode
1,220 mA
Input signals are changed one time during 30 ns.
CKE ≥ VIH(MIN.), tCK = ∞
ICC2NS
216
Input signals are stable.
Active standby current in
power down mode
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
680
144
mA
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
1,400 mA
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞
360
Input signals are stable.
Operating current
(Burst mode)
ICC4
tCK ≥ tCK(MIN.)
/CAS latency = 2 -A80
-A10
2,620 mA
2,260
2
3
IO = 0 mA
/CAS latency = 3 -A80
-A10
2,890
2,620
CBR (Auto) refresh current
ICC5
tRC ≥ tRC(MIN.)
/CAS latency = 2 -A80
-A10
3,340 mA
3,340
/CAS latency = 3 -A80
-A10
3,430
3,430
Self refresh current
ICC6
II(L)
CKE ≤ 0.2 V
536
+ 20
+ 3
mA
µA
µA
V
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 20
– 3
IO(L)
VOH
VOL
2.4
IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
7
Data Sheet M13201EJ7V0DS00
MC-4532DC726
[MC-4532DC726LFA]
★
Parameter
Symbol
ICC1
Test condition
MIN. MAX. Unit Notes
Burst length = 1
tRC ≥ tRC(MIN.)
IO = 0 mA
Operating current
/CAS latency = 2 -A80
-A10
2,400 mA
2,220
1
/CAS latency = 3 -A80
-A10
2,490
2,310
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns
536
53
mA
power down mode
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Precharge standby current in ICC2N
non power down mode
1,220 mA
Input signals are changed one time during 30 ns.
CKE ≥ VIH(MIN.), tCK = ∞
ICC2NS
216
Input signals are stable.
Active standby current in
power down mode
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
680
144
mA
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
1,400 mA
ICC3NS CKE ≥ VIH(MIN.), tCK = ∞
540
Input signals are stable.
Operating current
(Burst mode)
ICC4
tCK ≥ tCK(MIN.)
/CAS latency = 2 -A80
-A10
2,670 mA
2,310
2
3
IO = 0 mA
/CAS latency = 3 -A80
-A10
2,940
2,640
CBR (Auto) refresh current
ICC5
tRC ≥ tRC(MIN.)
/CAS latency = 2 -A80
-A10
3,390 mA
3,390
/CAS latency = 3 -A80
-A10
3,480
3,480
Self refresh current
ICC6
II(L)
CKE ≤ 0.2 V
536
+ 20
+ 3
mA
µA
µA
V
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
DOUT is disabled, VO = 0 to 3.6 V
IO = – 4.0 mA
– 20
– 3
IO(L)
VOH
VOL
2.4
IO = + 4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK(MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK(MIN.).
8
Data Sheet M13201EJ7V0DS00
MC-4532DC726
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
T
• AC measurements assume t = 1ns.
IH
IL
• Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V and V .
T
IH(MIN.)
IL(MAX.)
and V
• If t is longer than 1ns, reference level for measuring timing of input signals is V
.
• An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
t
SETUP
t
HOLD
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
9
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Synchronous Characteristics (Registered Mode)
Parameter
Symbol
-A80
-A10
Unit
Note
MIN.
8
MAX.
MIN.
10
MAX.
Clock cycle time
/CAS latency = 3
/CAS latency = 2
tCK3
tCK2
tAC3
tAC2
(125 MHz)
(100 MHz)
ns
ns
ns
ns
%
10
(100 MHz)
13
(77 MHz)
Access time from CLK /CAS latency = 3
/CAS latency = 2
6
6
6
7
1
1
Input CLK duty cycle
40
3
60
40
3
60
Data-out hold time
/CAS latency = 3
/CAS latency = 2
tOH3
tOH2
tLZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
3
3
Data-out low-impedance time
0
0
Data-out high-
/CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
3
6
6
3
6
7
impedance time
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
3
3
2
2
tDH
1
1
tAS
1.5
0.9
1.5
0.9
1.5
1.5
1.5
0.9
1.5
0.9
1.5
1.5
tAH
tCKS
tCKH
tCKSP
tCMS
CKE setup time (Power down exit)
Command (/CS0 - /CS3, /RAS, /CAS,
/WE, DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS,
/WE, DQMB0 - DQMB7) hold time
tCMH
0.9
0.9
ns
Note 1. Output load
1.4 V
50Ω
Z = 50Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
10
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Asynchronous Characteristics (Registered Mode)
Parameter
Symbol
-A80
-A10
Unit
Note
MIN.
MAX.
MIN.
MAX.
REF to REF/ACT command period
ACT to PRE command period
tRC
tRAS
tRP
70
70
ns
ns
48
120,000
50
120,000
PRE to ACT command period
20
20
ns
Delay time ACT to READ/WRITE command
ACT(0) to ACT(1) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
tDAL3
tDAL2
tRSC
tT
20
20
ns
16
20
ns
−1CLK+8
−1CLK+10
ns
Data-in to ACT(REF) command period /CAS latency = 3
20
20
2
20
20
2
ns
(Auto precharge)
/CAS latency = 2
ns
Mode register set cycle time
Transition time
CLK
ns
0.5
30
64
1
30
64
Refresh time (4,096 refresh cycles)
tREF
ms
11
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Serial PD
(1/2)
Byte No.
0
Function Described
Hex
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into 80H
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
3
4
5
6
7
8
9
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
0AH
02H
48H
00H
01H
80H
A0H
60H
60H
02H
80H
04H
04H
01H
8FH
04H
06H
01H
01H
1FH
0EH
A0H
D0H
60H
70H
00H
14H
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
0
0
1
1
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
256 bytes
SDRAM
12 rows
10 columns
2 banks
72 bits
0
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 Cycle time
-A80
-A10
-A80
-A10
10 ns
6 ns
10
CL = 3 Access time
6 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
ECC
Normal
×4
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
×4
1 clock
1, 2, 4, 8, F
4 banks
2, 3
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
0
SDRAM module attributes
SDRAM device attributes : General
Registered
CL = 2 Cycle time
-A80
-A10
-A80
-A10
10 ns
13 ns
6 ns
24
CL = 2 Access time
7 ns
25-26
27
tRP(MIN.)
-A80
20 ns
-A10
-A80
-A10
-A80
-A10
-A80
-A10
14H
10H
14H
14H
14H
30H
32H
20H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
20 ns
28
29
30
31
tRRD(MIN.)
16 ns
20 ns
tRCD(MIN.)
20 ns
20 ns
tRAS(MIN.)
48 ns
50 ns
Module bank density
128M bytes
12
Data Sheet M13201EJ7V0DS00
MC-4532DC726
Serial PD
(2/2)
Byte No.
32
Function Described
Hex
15H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
1.5 ns
Command and address signal input
setup time
0
0
0
1
0
1
0
1
33
Command and address signal input
hold time
09H
0
0
0
0
1
0
0
1
0.9 ns
34
35
Data signal input setup time
Data signal input hold time
20H
10H
00H
12H
08H
6EH
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
0
2 ns
1 ns
36-61
62
SPD revision
1.2
63
Checksum for bytes 0 - 62 -A80
-A10
64-71
72
Manufacture’s JEDEC ID code
Manufacturing location
Manufacture’s P/N
Revision Code
73-90
91
93-94
95-98
99-125
126
Manufacturing date
Assembly serial number
Mfg specific
Intel specification frequency
64H
8FH
8DH
0
1
1
1
0
0
1
0
0
0
0
0
0
1
1
1
1
1
0
1
0
0
1
1
100 MHz
127
Intel specification /CAS
latency support
-A80
-A10
Timing Chart
★
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).
13
Data Sheet M13201EJ7V0DS00
MC-4532DC726
★
Package Drawings
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE) (1/3)
[ASSEMBLY DRAWING]
A
C
B
1
2
ITEM MILLIMETERS
A
B
C
43.18±0.13
8.10±0.25
4.00
M168S-50A92-1
14
Data Sheet M13201EJ7V0DS00
MC-4532DC726
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE) (2/3)
[PART DRAWING 1]
A
B
G
H
C
E
D
F
ITEM MILLIMETERS
A
B
C
D
E
F
133.35
126.95
22.18
17.00
39.18
1.27±0.1
4.0 MAX.
3.2
G
H
M168S-50A92-1
15
Data Sheet M13201EJ7V0DS00
MC-4532DC726
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE) (3/3)
[PART DRAWING 2]
A (AREA B)
Y
Z
N
M1 (AREA B)
R
Q
L
M
A
B
S
M2 (AREA A)
J
T
H
(OPTIONAL HOLES)
U
K
C
B
E
D
I
G
A1 (AREA A)
ITEM MILLIMETERS
A
A1
B
133.35
133.35±0.13
11.43
C
D
D1
D2
E
36.83
6.35
2.0
3.125
detail of A part
W
detail of B part
D2
54.61
G
H
I
6.35
1.27 (T.P.)
8.89
24.495
42.18
J
K
L
17.78
M
43.18±0.13
M1
M2
N
23.40
V
P
19.78
4.0 MAX.
1.0
X
D1
P
Q
R2.0
R
4.0±0.10
φ
S
T
3.0
1.27±0.1
4.0 MIN.
0.2±0.15
1.0±0.05
U
V
W
X
Y
Z
2.54±0.10
3.0 MIN.
3.0 MIN.
M168S-50A92-1
16
Data Sheet M13201EJ7V0DS00
MC-4532DC726
[MEMO]
17
Data Sheet M13201EJ7V0DS00
MC-4532DC726
[MEMO]
18
Data Sheet M13201EJ7V0DS00
MC-4532DC726
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
19
Data Sheet M13201EJ7V0DS00
MC-4532DC726
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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