MC-454AD645F-A10 [NEC]
Synchronous DRAM Module, 4MX64, 7ns, MOS, DIMM-168;
| 型号： | MC-454AD645F-A10 |
| 厂家： | 
NEC |
| 描述： | Synchronous DRAM Module, 4MX64, 7ns, MOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总20页 (文件大小：184K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-454AD645
4M-WORD BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULE
UNBUFFERED TYPE
Description
The MC-454AD645 is a 4,194,304 words by 64 bits synchronous dynamic RAM module on which 16 pieces of
16M SDRAM: µPD4516821A are assembled.
This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 4,194,304 words by 64 bits organization
• Clock frequency and clock access time
Family
/CAS latency
Clock frequency
(MAX.)
Clock access time
Power consumption (MAX.)
(MAX.)
6 ns
7 ns
7 ns
8 ns
8 ns
9 ns
7 ns
8 ns
Active
Standby
115.2 mW
MC-454AD645F-A80
MC-454AD645F-A10
MC-454AD645F-A12
MC-454AD645FA-A10B
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
83 MHz
5,414 mW
4,406 mW
4,550 mW
3,686 mW
3,974 mW
3,110 mW
3,686 mW
3,398 mW
(CMOS level input)
100 MHz
77 MHz
83 MHz
67 MHz
100 MHz
77 MHz
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Dual internal banks controlled by BA0 (Bank Select)
• Programmable burst-length: 1, 2, 4, 8 and full page
• Programmable wrap sequence (sequential / interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ± 10 % of series resistor
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible
• 2,048 refresh cycles / 32 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Unbuffered type
• Serial PD
The information in this document is subject to change without notice.
Document No. M12666EJ5V0DS00 (5th edition)
Date Published July 1998 NS CP (K)
Printed in Japan
The mark • shows major revised points.
1997
©
MC-454AD645
Ordering Information
Part number
Clock frequency
(MAX.)
Package
Mounted devices
MC-454AD645F-A80
MC-454AD645F-A10
MC-454AD645F-A12
MC-454AD645FA-A10B
125 MHz
100 MHz
83 MHz
168-pin Dual In-line Memory Module 16 pieces of µPD4516821AG5
(Socket Type)
(400 mil TSOP (II))
[Double side]
Edge connector : Gold plated
29.21 mm (1.15 inch) height
100 MHz
16 pieces of µPD4516821AG5 (Rev. P)
(400 mil TSOP (II))
[Double side]
2
MC-454AD645
Pin Configuration
168-pin Dual In-line MemoryModule Socket Type (Edge connector: Gold plated)
[MC-454AD645F, MC-454AD645FA]
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
V
SS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ0
DQ1
DQ2
DQ3
Vcc
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
V
SS
VSS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
NC
DQ14
DQ15
NC
NC
NC
V
SS
VSS
NC
NC
Vcc
/CAS
DQMB4
DQMB5
/CS1
/RAS
NC
NC
Vcc
/WE
DQMB0
DQMB1
/CS0
NC
V
SS
V
SS
A0
A2
A1
A3
A4
A5
A6
A7
A8
A9
A10
NC
Vcc
BA0(A11)
NC
Vcc
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CLK0
VSS
VSS
CKE0
/CS3
DQMB6
DQMB7
NC
NC
/CS2
DQMB2
DQMB3
NC
Vcc
Vcc
A0 - A10
: Address Inputs
NC
NC
NC
NC
[Row : A0 - A10, Column : A0 - A8]
NC
NC
NC
NC
V
SS
VSS
BA0 (A11)
DQ0 - DQ63
CLK0 - CLK3
CKE0, CKE1
/CS0 - /CS3
/RAS
: SDRAM Bank Select
: Data Inputs / Outputs
: Clock Input
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
DQ52
NC
DQ20
NC
: Clock Enable Input
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
NC
NC
NC
CKE1
V
SS
VSS
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
/CAS
V
SS
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
/WE
DQMB0 - DQMB7 : DQ Mask Enable
SA0 - SA2
SDA
: Address Input for EEPROM
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
: Ground
VSS
V
SS
SCL
CLK2
NC
CLK3
NC
CC
V
NC
SA0
SA1
SA2
Vcc
SDA
SCL
Vcc
SS
V
NC
: No Connection
3
MC-454AD645
Block Diagram
/WE
/CS0
/CS1
/CS2
/CS3
DQMB0
DQMB2
DQM
DQM /CS /WE
/CS
/CS
/CS
/CS
DQM /CS /WE
DQM
/CS
/WE
/WE
/WE
/WE
/WE
/WE
/WE
/WE
DQ 3
DQ 2
DQ 1
DQ 0
DQ 7
DQ 6
DQ 5
DQ 4
DQ 0
DQ 19
DQ 18
DQ 17
DQ 16
DQ 23
DQ 22
DQ 21
DQ 20
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D0
D2
D8
D10
DQMB3
DQMB1
DQM
DQM
/CS /WE
/CS /WE
DQM /CS
DQM
DQ 11
DQ 10
DQ 9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 27
DQ 26
DQ 25
DQ 24
DQ 31
DQ 30
DQ 29
DQ 28
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
I/O 5
I/O 6
I/O 7
DQ 8
D1
D3
D9
D11
DQ 15
DQ 14
DQ 13
DQ 12
DQMB6
DQMB4
DQM
/CS /WE
DQM
DQM
/CS /WE
DQM /CS
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 51
DQ 50
DQ 49
DQ 48
DQ 55
DQ 54
DQ 53
DQ 52
DQ 35
DQ 34
DQ 33
DQ 32
DQ 39
DQ 38
DQ 37
DQ 36
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D4
D6
D12
D14
DQMB5
DQMB7
/CS
DQM /CS /WE
DQM
/WE
DQM
/CS
DQM
DQ 43
DQ 42
DQ 41
DQ 40
DQ 47
DQ 46
DQ 45
DQ 44
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 59
DQ 58
DQ 57
DQ 56
DQ 63
DQ 62
DQ 61
DQ 60
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D5
D7
D13
D15
CLK : D2, D6
CLK : D3, D7
CLK : D0, D4
CLK : D1, D5
SERIAL PD
CLK2
CLK3
CLK0
SCL
SDA
A0
A1
A2
CLK : D10, D14
CLK : D11, D15
CLK : D8, D12
CLK : D9, D13
CLK1
SA0 SA1 SA2
A0 - A10
BA0
A0 - A10: D0 - D15
A11: D0 - D15
/RAS
/CAS
CKE0
/RAS: D0 - D15
/CAS: D0 - D15
CKE: D0 - D7
10 kΩ
CKE : D8-D15
CKE1
VCC
VSS
D0 - D15
D0 - D15
C
Remarks 1. The value of all resistors is 10 Ω except CKE1.
2. D0 - D15 : µPD4516821A (1M words × 8 bits × 2 banks)
4
MC-454AD645
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 100 µs and then, execute power on sequence and auto refresh before proper device
operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–1.0 to +4.6
–1.0 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
16
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Supply voltage
Symbol
VCC
Condition
MIN.
3.0
2.0
2.0
−0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
High level input voltage
VIH
MC-454AD645F
MC-454AD645FA
4.6
V
VCC+0.3
+0.8
70
Low level input voltage
VIL
TA
V
Operating ambient temperature
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter Symbol
Input capacitance
Test condition
MIN.
TYP.
MAX.
80
Unit
pF
CI1
CI2
CI3
CI4
CI5
A0 - A10, BA0 (A11), /RAS, /CAS, /WE
CLK0 - CLK3
36
CKE0, CKE1
50
/CS0 - /CS3
34
DQMB0 - DQMB7
15
★
C
I/O
DQ0 - DQ63
15
Data input / output capacitance
MC-454AD645F
MC-454AD645FA
pF
20
5
MC-454AD645
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
[MC-454AD645F]
Parameter
Symbol
ICC1
Test condition
Grade MIN. MAX. Unit Notes
Operating current
Burst length = 1
/CAS latency = 2 -A80
1,024 mA
944
1
tRC ≥ tRC (MIN.), IO = 0 mA
-A10
-A12
944
/CAS latency = 3 -A80
1,064
984
-A10
-A12
984
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL (MAX.), tCK = 15 ns
48
32
mA
mA
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞
ICC2N
Precharge standby current in
non power down mode
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
400
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ ,
96
Input signals are stable.
Active standby current in
power down mode
ICC3P
CKE ≤ VIL (MAX.), tCK = 15 ns
48
32
mA
mA
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
448
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞ ,
160
Input signals are stable.
Operating current
(Burst mode)
ICC4
tCK ≥ tCK (MIN.),
/CAS latency = 2 -A80
1,224 mA
1,024
2
IO = 0 mA
-A10
-A12
864
/CAS latency = 3 -A80
1,504
-A10
-A12
1,264
1,104
Refresh current
ICC5
ICC6
II (L)
tRC = 100 ns, tCK = MIN.
944
32
mA
mA
µA
3
Self refresh current
CKE ≤ 0.2 V
Input leakage current
Input leakage current (CKE1)
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
–80
+80
–500 +500
IO (L)
VOH
VOL
DOUT is disabled, VO = 0 to 3.6 V
IO = –2.0 mA
–10
2.4
+10
µA
V
IO = +2.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
MC-454AD645
[MC-454AD645FA]
Parameter
Symbol
ICC1
Test condition
Grade MIN. MAX. Unit Notes
Operating current
Burst length = 1
/CAS latency = 2 -A10B
/CAS latency = 3 -A10B
944
984
48
mA
mA
mA
1
tRC ≥ tRC (MIN.), IO = 0 mA
Precharge standby current in
power down mode
ICC2P
CKE ≤ VIL (MAX.), tCK = 15 ns
ICC2PS CKE ≤ VIL (MAX.), tCK = ∞
ICC2N
32
Precharge standby current in
non power down mode
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
400
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞ ,
96
Input signals are stable.
Active standby current in
power down mode
ICC3P
CKE ≤ VIL (MAX.), tCK = 15 ns
48
32
mA
mA
ICC3PS CKE ≤ VIL (MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
448
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞ ,
192
Input signals are stable.
Operating current
ICC4
tCK ≥ tCK (MIN.),
/CAS latency = 2 -A10B
/CAS latency = 3 -A10B
904
1,024
944
16
mA
2
3
(Burst mode)
IO = 0 mA
Refresh current
ICC5
ICC6
II (L)
tRC = 100 ns, tCK = MIN.
CKE ≤ 0.2 V
mA
mA
µA
Self refresh current
Input leakage current
Input leakage current (CKE1)
Output leakage current
High level output voltage
Low level output voltage
VI = 0 to 3.6 V, All other pins not under test = 0 V
–16
+16
–500 +500
IO (L)
VOH
VOL
DOUT is disabled, VO = 0 to 3.6 V
IO = –4.0 mA
–3
+3
µA
V
2.4
IO = +4.0 mA
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
7
MC-454AD645
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Characteristics Test Conditions
T
• AC measurements assume t = 1ns.
IH
IL
• Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V and V .
T
IH (MIN.)
IL (MAX.)
and V
• If t is longer than 1ns, reference level for measuring timing of input signals is V
.
• An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
t
SETUP
t
HOLD
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
8
MC-454AD645
Synchronous Characteristics
[MC-454AD645F]
Parameter
Symbol
-A80
MIN.
-A10
MIN.
-A12
MIN.
Unit
Note
MAX.
(125 MHz)
(83 MHz)
6
MAX.
(100 MHz)
(77 MHz)
7
MAX.
(83 MHz)
(67 MHz)
8
Clock cycle time
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
tCK3
tCK2
tAC3
tAC2
tCH
8
10
13
12
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
12
Access time from CLK
1
1
7
8
9
CLK high level width
CLK low level width
3
3
3.5
3.5
3
4
4
tCL
Data-out hold time
tOH
3
3
1
Data-out low-impedance time
tLZ
0
0
0
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
3
6
7
3
7
8
3
8
9
3
3
3
Data-in setup time
2.0
1.0
2.0
1.0
2.0
1.0
2.0
2.0
2.5
1.0
2.5
1.0
2.5
1.0
2.5
2.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
3.0
Data-in hold time
tDH
Address setup time
tAS
Address hold time
tAH
CKE setup time
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
1.0
1.0
1.5
ns
Note 1. Output load
1.4 V
50Ω
Z = 50Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
9
MC-454AD645
[MC-454AD645FA]
Parameter
Symbol
-A10B
Unit
Note
MIN.
10
MAX.
Clock cycle time
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
tCK3
tCK2
tAC3
tAC2
tCH
(100 MHz)
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
(77 MHz)
Access time from CLK
7
8
1
1
CLK high level width
CLK low level width
3.5
3.5
3
tCL
Data-out hold time
tOH
1
Data-out low-impedance time
tLZ
0
Data-out high-impedance time /CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
3
7
8
3
Data-in setup time
2.5
1.0
2.5
1.0
2.5
1.0
2.5
2.5
Data-in hold time
tDH
Address setup time
tAS
Address hold time
tAH
CKE setup time
tCKS
tCKH
tCKSP
tCMS
CKE hold time
CKE setup time (Power down exit)
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) setup time
Command (/CS0 - /CS3, /RAS, /CAS, /WE,
DQMB0 - DQMB7) hold time
tCMH
1.0
ns
Note 1. Output load
1.4 V
50Ω
Z = 50Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
10
MC-454AD645
Asynchronous Characteristics
[MC-454AD645F]
Parameter
Symbol
-A80
-A10
-A12
Unit
Note
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
REF to REF/ACT command period
ACT to PRE command period
tRC
tRAS
tRP
80
48
24
24
16
8
90
60
26
26
20
10
90
60
30
30
24
12
ns
ns
ns
ns
ns
ns
ns
120,000
120,000
120,000
PRE to ACT command period
tRCD
tRRD
tDPL
tDAL3
Delay time ACT to READ/WRITE command
ACT (0) to ACT (1) command period
Data-in to PRE command period
Data-in to ACT (REF) command /CAS latency = 3
period (Auto precharge)
1CLK
+24
1CLK
+26
1CLK
+30
/CAS latency = 2
tDAL2
1CLK
+24
1CLK
+26
1CLK
+30
ns
Mode register set cycle time
Transition time
tRSC
tT
2
2
1
2
1
CLK
ns
0.5
30
32
30
32
30
32
Refresh time
tREF
ms
11
MC-454AD645
[MC-454AD645FA]
Parameter
Symbol
-A10B
Unit
Note
MIN.
MAX.
REF to REF/ACT command period
ACT to PRE command period
PRE to ACT command period
tRC
tRAS
tRP
90
ns
ns
60
120,000
26
ns
tRCD
tRRD
tDPL
tDAL3
tDAL2
tRSC
tT
26
ns
Delay time ACT to READ/WRITE command
ACT (0) to ACT (1) command period
20
ns
10
ns
Data-in to PRE command period
Data-in to ACT (REF) command /CAS latency = 3
1CLK+26
ns
period (Auto precharge)
Mode register set cycle time
Transition time
/CAS latency = 2
1CLK+26
ns
2
1
CLK
ns
30
32
Refresh time
tREF
ms
12
MC-454AD645
Serial PD
[MC-454AD645F]
Byte No.
(1/2)
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
0
Defines the number of bytes written
into serial PD memory
80H
1
0
0
0
0
0
0
0
128 bytes
1
Total number of bytes of serial PD
memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
3
4
5
6
7
8
9
Fundamental memory type
04H
0BH
09H
02H
40H
00H
01H
80H
A0H
C0H
60H
70H
80H
00H
80H
08H
00H
01H
8FH
02H
06H
01H
01H
00H
0EH
C0H
D0H
F0H
70H
80H
90H
00H
0
0
0
0
0
0
0
1
1
1
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
SDRAM
11 rows
9 columns
2 banks
64 bits
0
Number of rows
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 cycle time MC-454AD645F-A80
MC-454AD645F-A10
10 ns
12 ns
6 ns
MC-454AD645F-A12
10
CL = 3 access time MC-454AD645F-A80
MC-454AD645F-A10
7 ns
MC-454AD645F-A12
8 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate / type
None
Normal
×8
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
/WE latency supported
SDRAM module attributes
SDRAM device attributes : General
CL = 2 cycle time MC-454AD645F-A80
MC-454AD645F-A10
None
1 clock
1, 2, 4, 8, F
2 banks
2, 3
0
0
12 ns
13 ns
15 ns
7 ns
MC-454AD645F-A12
24
CL = 2 access time MC-454AD645F-A80
MC-454AD645F-A10
8 ns
MC-454AD645F-A12
9 ns
25-26
13
MC-454AD645
(2/2)
Byte No.
27
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
24 ns
tRP (MIN.)
MC-454AD645F-A80
18H
1AH
1EH
10H
14H
18H
18H
1AH
1EH
30H
3CH
3CH
04H
00H
01H
98H
FCH
68H
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
0
1
1
1
0
0
1
1
1
1
0
1
1
0
0
0
1
1
1
0
0
1
0
1
0
0
0
1
0
1
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
MC-454AD645F-A10
MC-454AD645F-A12
MC-454AD645F-A80
MC-454AD645F-A10
MC-454AD645F-A12
MC-454AD645F-A80
MC-454AD645F-A10
MC-454AD645F-A12
MC-454AD645F-A80
MC-454AD645F-A10
MC-454AD645F-A12
26 ns
30 ns
16 ns
20 ns
24 ns
24 ns
26 ns
30 ns
48 ns
60 ns
60 ns
16M bytes
28
29
30
tRRD (MIN.)
tRCD (MIN.)
tRAS (MIN.)
31
32-61
62
Module bank density
SPD revision
1
63
Checksum for
bytes 0 - 62
MC-454AD645F-A80
MC-454AD645F-A10
MC-454AD645F-A12
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
66H
06H
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
66 MHz
2, 3
Intel specification /CAS latency support
14
MC-454AD645
[MC-454AD645FA]
(1/2)
Byte No.
0
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written
into serial PD memory
80H
1
0
0
0
0
0
0
0
128 bytes
1
Total number of bytes of serial PD
memory
08H
0
0
0
0
1
0
0
0
256 bytes
2
3
Fundamental memory type
04H
0BH
09H
02H
40H
00H
01H
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
SDRAM
11 rows
9 columns
2 banks
64 bits
0
Number of rows
Number of columns
Number of banks
Data width
4
5
6
7
Data width (continued)
Voltage interface
8
LVTTL
10 ns
7 ns
9
CL = 3 cycle time MC-454AD645FA-A10B A0H
CL = 3 access time MC-454AD645FA-A10B 70H
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25-26
DIMM configuration type
Refresh rate / type
00H
80H
08H
00H
01H
8FH
02H
06H
01H
01H
00H
0EH
None
Normal
×8
SDRAM width
Error checking SDRAM width
Minimum clock delay
None
1 clock
1, 2, 4, 8, F
2 banks
2, 3
Burst length supported
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
SDRAM module attributes
SDRAM device attributes : General
0
CL = 2 cycle time MC-454AD645FA-A10B D0H
CL = 2 access time MC-454AD645FA-A10B 80H
00H
13 ns
8 ns
15
MC-454AD645
(2/2)
Byte No.
27
Function Described
Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
26 ns
tRP (MIN.)
MC-454AD645FA-A10B 1AH
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
1
1
1
1
0
0
0
1
1
0
1
1
0
0
0
1
0
1
0
1
1
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
28
tRRD (MIN.)
tRCD (MIN.)
tRAS (MIN.)
MC-454AD645FA-A10B 14H
MC-454AD645FA-A10B 1AH
MC-454AD645FA-A10B 3CH
20 ns
29
26 ns
30
60 ns
31
Module bank density
04H
00H
01H
16M bytes
32-61
62
SPD revision
1
63
Checksum for
bytes 0 - 62
MC-454AD645FA-A10B FCH
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91-92 Revision code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
66H
06H
0
0
1
0
1
0
0
0
0
0
1
1
1
1
0
0
66 MHz
2, 3
Intel specification /CAS latency support
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).
16
MC-454AD645
Package Drawing
[MC-454AD645F, MC-454AD645FA]
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
Y
Z
M1 (AREA B)
N
R
Q
L
M
A
B
S
M2 (AREA A)
H
T
(OPTIONAL HOLES)
U
J
K
C
B
E
I
G
D
A1 (AREA A)
ITEM MILLIMETERS
A
A1
B
133.35
133.35±0.13
11.43
detail of A part
W
detail of B part
D2
C
36.83
6.35
D
D1
D2
E
2.0
3.125
54.61
G
H
6.35
V
X
P
1.27 (T.P.)
8.89
I
D1
24.495
42.18
J
K
L
17.78
M
M1
M2
N
29.21±0.13
9.43
19.78
4.0 MAX.
1.0
P
Q
R
R2.0
4.0±0.10
φ
S
3.0
T
1.27±0.1
4.0 MIN.
U
V
0.25 MAX.
1.0±0.05
W
X
2.54±0.10
3.0 MIN.
Y
Z
3.0 MIN.
M168S-50A65-1
17
MC-454AD645
[MEMO]
18
MC-454AD645
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the
device. Immediately after the power source is turned ON, the devices with
reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not
initialized until the reset signal is received. Reset operation must be
executed imme-diately after power-on for devices having reset function.
19
MC-454AD645
[MEMO]
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
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