MC-454DA726F-A10 [NEC]
Synchronous DRAM Module, 4MX72, 6ns, MOS, DIMM-168;
| 型号： | MC-454DA726F-A10 |
| 厂家： | 
NEC |
| 描述： | Synchronous DRAM Module, 4MX72, 6ns, MOS, DIMM-168 动态存储器 内存集成电路 |
| 文件： | 总16页 (文件大小：151K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
MC-454DA726
4 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE
REGISTERED TYPE
Description
The MC-454DA726 is an 4,194,304 words by 72 bits synchronous dynamic RAM module on which 5 pieces of 64M
SDRAM : µPD4564163 (Rev. E) are assembled. This module provides high density and large quantities of memory
in a small space without utilizing the surface-mounting technology on the printed circuit board.
Decoupling capacitors are mounted on power supply line for noise reduction.
Features
• 4,194,304 words by 72 bits organization (ECC type)
• Clock frequency and Clock access time
Family
/CAS latency
Clock frequency
(MAX.)
Clock access time
Power consumption (MAX.)
(MAX.)
6 ns
Active
Standby
45.0 mW
MC-454DA726-A80
MC-454DA726-A10
CL = 3
CL = 2
CL = 3
CL = 2
125 MHz
100 MHz
100 MHz
77 MHz
4,590 mW
4,050 mW
4,050 mW
3,420 mW
6 ns
(CMOS level input )
6 ns
7 ns
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0 and BA1 (Bank Select)
• Programmable burst-length (1, 2, 4, 8 and Full Page)
• Programmable wrap sequence (Sequential / Interleave)
• Programmable /CAS latency (2, 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• All DQs have 10 Ω ±10 % of series resistor
• Single 3.3 V ±0.3 V power supply
• LVTTL compatible
• 4,096 refresh cycles/64 ms
• Burst termination by Burst Stop command and Precharge command
• 168-pin dual in-line memory module (Pin pitch = 1.27 mm)
• Registered type
• Serial PD
The information in this document is subject to change without notice.
The mark • shows major revised points.
Document No. M13715EJ1V0DS00 (1st edition)
Date Published July 1998 NS CP(K)
Printed in Japan
1998
©
MC-454DA726
Ordering Information
Part number
Clock frequency
MHz (MAX.)
Package
Mounted devices
MC-454DA726F-A80
MC-454DA726F-A10
125 MHz
168-pin Dual In-line Memory Module 5 pieces of µPD4564163G5 (Rev. E)
(Socket Type)
(400 mil TSOP (II))
100 MHz
Edge connector : Gold plated
38.1 mm (1.5 inch) height
[Single side]
2
MC-454DA726
Pin Configuration
168-pin Dual In-line Memory Module Socket Type (Edge connector : Gold plated)
[MC-454DA726F]
/xxx indicates active low signal.
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
V
SS
V
SS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ0
DQ1
DQ2
DQ3
Vcc
DQ36
DQ37
DQ38
DQ39
DQ4
DQ5
DQ6
DQ7
95
96
DQ40
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
DQ8
VSS
V
SS
97
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
DQ46
DQ47
CB4
DQ14
DQ15
CB0
CB5
CB1
VSS
V
SS
NC
NC
Vcc
NC
NC
Vcc
/WE
/CAS
DQMB4
DQMB5
NC
DQMB0
DQMB1
/CS0
NC
/RAS
V
SS
V
SS
A0
A2
A1
A0 - A11
: Address Inputs
A3
A4
A5
A6
[Row : A0 - A11, Column : A0 - A7]
BA0(A13), BA1(A12) : SDRAM Bank Select
DQ0 - DQ63,
A7
A8
A9
A10
BA0(A13)
A11
Vcc
BA1(A12)
Vcc
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
CLK1
NC
Vcc
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
CB0 - CB7
CLK0 - CLK3
CKE0
: Data Inputs/Outputs
: Clock Input
CLK0
V
SS
VSS
CKE0
NC
NC
/CS2
DQMB2
DQMB3
NC
DQMB6
DQMB7
NC
: Clock Enable Input
: Write Protect Note
: Chip Select Input
: Row Address Strobe
: Column Address Strobe
: Write Enable
Vcc
Vcc
WP
NC
NC
NC
NC
/CS0, /CS2
/RAS
CB6
CB7
CB2
CB3
VSS
VSS
DQ48
DQ49
DQ50
DQ51
Vcc
DQ16
DQ17
DQ18
DQ19
Vcc
/CAS
/WE
DQ52
NC
DQ20
NC
DQMB0 - DQMB7 : DQ Mask Enable
NC
NC
REGE
NC
VSS
VSS
SA0 - SA2
SDA
: Address Input for EEPROM
DQ53
DQ54
DQ55
DQ21
DQ22
DQ23
: Serial Data I/O for PD
: Clock Input for PD
: Power Supply
VSS
VSS
DQ56
DQ57
DQ58
DQ59
Vcc
DQ24
DQ25
DQ26
DQ27
Vcc
SCL
V
CC
DQ60
DQ61
DQ62
DQ63
DQ28
DQ29
DQ30
DQ31
SS
V
: Ground
REGE
NC
: Register / Buffer Enable
: No Connection
V
SS
VSS
CLK2
NC
CLK3
NC
WP
SA0
SA1
SA2
Vcc
SDA
SCL
Vcc
Note WP is not used yet. It is connected to ground.
3
MC-454DA726
Block Diagram
/CS0
/CS2
LDQM
/CS
/CS
/CS
DQMB 6
LDQM
/CS
DQMB 4
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
D0
D3
D1
D2
UDQM
UDQM
DQMB 2
DQMB 0
DQ 8
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ 8
DQ 7
DQ 6
DQ 5
DQ 4
DQ 3
DQ 2
DQ 1
DQ 0
DQ 9
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
/CS
DQMB 3
LDQM
DQMB 1
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
DQ8
D4
DQMB 7
UDQM
DQMB 5
UDQM
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ 8
DQ 8
DQ 9
DQ 9
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
20 Ω
CLK1,
CLK2,
CLK3
LDQM
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
10 Ω
CLK0
CLK : D0, D1, D3
CLK : D2, D4
CB4
CB0
CB1
CB5
CB2
CB6
CB3
CB7
10 Ω
10pF
30pF
PLL
5 pF
CLK : Register 1, Register 2
UDQM
SERIAL PD
D0 - D4,
Register1, Register2, PLL
DQ 8
V
CC
SDA
WP
DQ 9
SCL
C
DQ 10
DQ 11
DQ 12
DQ 13
DQ 14
DQ 15
D0 - D4,
Register1, Register2, PLL
GND
A0
A1
A2
47 kΩ
SA0 SA1 SA2
RA8 - RA11,
RBA0, RBA1
A8 - A11,
BA0, BA1 : D0 - D4
A0 - A7
RA0 - RA7
/RRAS
A0 - A7 : D0 - D4
A8 - A11, BA0, BA1
CKE0
CKE : D0 - D4
/RAS : D0 - D4
/CAS : D0 - D4
/WE : D0 - D4
/RAS
/CAS
/WE
RCKE0
RDQMB2, RDQMB3,
RDQMB6, RDQMB7
DQMB2, DQMB3,
DQMB6, DQMB7
/RCAS
Register1
Register2
/RCS2
/RWE
/CS2
RDQMB0, RDQMB1,
RDQMB4, RDQMB5
/RCS0
DQMB0, DQMB1,
DQMB4, DQMB5
/CS0
/LE
REGE
/LE
VCC
10kΩ
Remarks 1. The series register values of DQs are 10 Ω.
2. WP is not used yet. It is connected to ground.
3. D0 - D8 : µPD4564163 (Rev. E)(1M words × 16 bits × 4 banks)
4. REGE ≤ VIL : Buffer mode
IH
REGE ≥ V : Register mode
5. Register : SN74ALVC162334DGG
PLL : CDC2509APW
4
MC-454DA726
Electrical Specifications
• All voltages are referenced to V (GND).
SS
• After power up, wait more than 1 ms and then, execute power on sequence and auto refresh before proper device
operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on power supply pin relative to GND
Voltage on input pin relative to GND
Short circuit output current
Symbol
VCC
VT
Condition
Rating
–0.5 to +4.6
–0.5 to +4.6
50
Unit
V
V
IO
mA
W
Power dissipation
PD
11
Operating ambient temperature
Storage temperature
TA
0 to +70
–55 to +125
°C
°C
Tstg
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
VCC
VIH
Condition
MIN.
3.0
2.0
–0.3
0
TYP.
3.3
MAX.
3.6
Unit
V
Supply voltage
High level input voltage
Low level input voltage
VCC + 0.3
+ 0.8
70
V
VIL
V
Operating ambient temperature
TA
°C
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
CI1
Test condition
MIN.
4
TYP.
MAX.
10
Unit
pF
Input capacitance
A0 - A11, BA0(A13), BA1(A12),
/RAS, /CAS, /WE
CI2
CI3
CI4
CI5
CI/O
CLK0 - CLK3
CKE0
15
4
35
10
10
10
13
/CS0, /CS2
4
DQMB0 -DQMB7
DQ0 - DQ63, CB0 - CB7
4
Data input/output capacitance
6
pF
5
MC-454DA726
DC Characteristics (Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol
ICC1
Test condition
Burst length = 1, tRC ≥ tRC(MIN.) ,
IO = 0 mA
MIN. MAX. Unit Notes
Operating current
/CAS latency = 2
/CAS latency = 3
-A80
-A10
-A80
-A10
750
700
875
750
25.5
mA
1
Precharge standby current in ICC2P CKE ≤ VIL(MAX.), tCK = 15 ns
mA
mA
power down mode
ICC2PS CKE ≤ VIL(MAX.), tCK = ∞
12.5
350
Precharge standby current in ICC2N CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
non power down mode
Input signals are changed one time during 30 ns.
ICC2NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
ICC3P CKE ≤ VIL(MAX.), tCK = 15 ns
30
275
20
Active standby current in
power down mode
mA
mA
ICC3PS CKE ≤ VIL(MAX.), tCK = ∞
Active standby current in
non power down mode
ICC3N CKE ≥ VIH(MIN.), tCK = 15 ns, /CS ≥ VIH(MIN.),
Input signals are changed one time during 30 ns.
ICC3NS CKE ≥ VIH (MIN.), tCK = ∞, Input signals are stable.
375
50
Operating current
(Burst mode)
ICC4
tCK ≥ tCK(MIN.) , IO = 0 mA
/CAS latency = 2
/CAS latency = 3
/CAS latency = 2
/CAS latency = 3
-A80
-A10
-A80
-A10
-A80
-A10
-A80
-A10
1,125 mA
950
2
3
1,275
1,125
Refresh current
ICC5
tRC ≥ tRC(MIN.)
950
950
975
975
255
+ 10
mA
Self refresh current
ICC6 CKE ≤ 0.2 V
mA
µA
µA
V
Input leakage current
Output leakage current
High level output voltage
Low level output voltage
II(L)
VI = 0 to 3.6 V, All other pins not under test = 0 V
– 10
IO(L) DOUT is disabled, VO = 0 to 3.6 V
VOH IO = – 4.0 mA
VOL IO = + 4. 0 mA
– 1.5 + 1.5
2.4
0.4
V
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC1
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
.
.
2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
CC4
CK (MIN.)
addition to this, I
is measured on condition that addresses are changed only one time during t
3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
6
MC-454DA726
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
AC Characteristics Test Conditions
T
• AC measurements assume t = 1ns.
IH
IL
• Reference level for measuring timing of input signals is 1.4V. Transition times are measured between V and V .
T
IH (MIN.)
IL (MAX.)
and V
• If t is longer than 1ns, reference level for measuring timing of input signals is V
.
• An access time is measured at 1.4 V.
t
CK
t
CH
t
CL
2.0 V
1.4 V
0.8 V
CLK
t
SETUP
t
HOLD
2.0 V
1.4 V
0.8 V
Input
t
AC
t
OH
Output
7
MC-454DA726
Synchronous Characteristics (Registered Mode)
Parameter
Symbol
-A80
-A10
Unit
Note
MIN.
8
MAX.
MIN.
10
MAX.
Clock cycle time
/CAS latency = 3
/CAS latency = 2
tCK3
tCK2
tAC3
tAC2
(125 MHz)
(100 MHz)
ns
ns
ns
ns
%
10
(100 MHz)
13
(77 MHz)
Access time from CLK /CAS latency = 3
/CAS latency = 2
6
6
6
7
1
1
Input CLK duty cycle
40
3
60
40
3
60
Data-out hold time
/CAS latency = 3
/CAS latency = 2
tOH3
tOH2
tLZ
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1
1
3
3
Data-out low-impedance time
0
0
Data-out high-
/CAS latency = 3
/CAS latency = 2
tHZ3
tHZ2
tDS
3
6
6
3
6
7
impedance time
Data-in setup time
Data-in hold time
Address setup time
Address hold time
CKE setup time
CKE hold time
3
3
2
2
tDH
1
1
tAS
1.5
0.9
1.5
0.9
1.5
1.5
1.5
0.9
1.5
0.9
1.5
1.5
tAH
tCKS
tCKH
tCKSP
tCMS
CKE setup time (Power down exit)
Command (/CS0, /CS2, /RAS, /CAS,
/WE, DQMB0 - DQMB7) setup time
Command (/CS0, /CS2, /RAS, /CAS,
/WE, DQMB0 - DQMB7) hold time
tCMH
0.9
0.9
ns
Note 1. Output load
1.4 V
50 Ω
Z = 50 Ω
Output
50 pF
Remark These specifications are applied to the monolithic device.
8
MC-454DA726
Asynchronous Characteristics (Registered Mode)
Parameter
Symbol
-A80
-A10
Unit
Note
MIN.
MAX.
MIN.
MAX.
REF to REF/ACT command period
ACT to PRE command period
tRC
tRAS
tRP
70
70
ns
ns
48
120,000
50
120,000
PRE to ACT command period
20
20
ns
Delay time ACT to READ/WRITE command
ACT(0) to ACT(1) command period
Data-in to PRE command period
tRCD
tRRD
tDPL
tDAL3
tDAL2
tRSC
tT
20
20
ns
16
20
ns
−1CLK+8
−1CLK+10
ns
Data-in to ACT(REF) command period /CAS latency = 3
20
20
2
20
20
2
ns
(Auto precharge)
Mode register set cycle time
Transition time
/CAS latency = 2
ns
CLK
ns
0.5
30
64
1
30
64
Refresh time
tREF
ms
9
MC-454DA726
Serial PD
Byte No.
0
(1/2)
Function Described
Hex
80H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
Defines the number of bytes written into
serial PD memory
1
0
0
0
0
0
0
0
128 bytes
1
2
3
4
5
6
7
8
9
Total number of bytes of serial PD memory
Fundamental memory type
Number of rows
08H
04H
0CH
08H
01H
48H
00H
01H
80H
A0H
60H
60H
02H
80H
10H
10H
01H
8FH
04H
06H
01H
01H
1FH
0EH
A0H
D0H
60H
70H
00H
14H
14H
10H
14H
14H
14H
30H
32H
08H
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
1
1
1
1
1
0
1
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
0
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
256 bytes
SDRAM
12 rows
8 columns
1 bank
72 bits
0
Number of columns
Number of banks
Data width
Data width (continued)
Voltage interface
LVTTL
8 ns
CL = 3 Cycle time
-A80
-A10
-A80
-A10
10 ns
6 ns
10
CL = 3 Access time
6 ns
11
12
13
14
15
16
17
18
19
20
21
22
23
DIMM configuration type
Refresh rate/type
ECC
Normal
×16
SDRAM width
Error checking SDRAM width
Minimum clock delay
Burst length supported
×16
1 clock
1, 2, 4, 8, F
4 banks
2, 3
Number of banks on each SDRAM
/CAS latency supported
/CS latency supported
0
/WE latency supported
0
SDRAM module attributes
SDRAM device attributes : General
Registered
CL = 2 Cycle time
-A80
10 ns
13 ns
6 ns
-A10
-A80
-A10
24
CL = 2 Access time
7 ns
25-26
27
tRP(MIN.)
-A80
-A10
-A80
-A10
-A80
-A10
-A80
-A10
20 ns
20 ns
16 ns
20 ns
20 ns
20 ns
48 ns
50 ns
32M bytes
28
29
30
31
tRRD(MIN.)
tRCD(MIN.)
tRAS(MIN.)
Module bank density
10
MC-454DA726
(2/2)
Byte No.
32
Function Described
Hex
15H
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Notes
1.5 ns
Command and address signal input
setup time
0
0
0
1
0
1
0
1
33
Command and address signal input hold
time
09H
0
0
0
0
1
0
0
1
0.9 ns
34
35
Data signal input setup time
Data signal input hold time
20H
10H
00H
12H
05H
6BH
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
1
2 ns
1 ns
36-61
62
SPD revision
1.2
63
Checksum for bytes 0 - 62
-A80
-A10
64-71 Manufacture’s JEDEC ID code
72 Manufacturing location
73-90 Manufacture’s P/N
91 Revision Code
93-94 Manufacturing date
95-98 Assembly serial number
99-125 Mfg specific
126
127
Intel specification frequency
Intel specification /CAS
latency support
64H
87H
85H
0
1
1
1
0
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
1
1
100 MHz
-A80
-A10
Timing Chart
Refer to the SYNCHRONOUS DRAM MODULE TIMING CHART Information (M13348X).
11
MC-454DA726
Package Drawing
168 PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B)
N
Y
Z
Q
S
(OPTIONAL HOLES)
B
A
T
H
J
K
C
I
G
D
E
B
A1 (AREA A)
ITEM MILLIMETERS
INCHES
5.250
detail of
part
part
detail of
A
A1
B
C
D
E
G
H
I
133.35
133.35±0.13
11.43
W
5.250±0.006
0.450
36.83
1.450
6.35
0.250
54.61
2.150
6.35
0.250
1.27 (T.P.)
8.89
0.050 (T.P.)
0.350
G
P
D
J
24.495
42.18
0.964
K
L
1.661
17.78
0.700
M
N
P
Q
38.1
1.50
3.00 MAX.
1.0
0.118 MAX.
0.039
R2.0
R0.079
+0.005
0.157
R
4.0±0.1
–0.004
S
T
U
V
3.0
0.118
1.27±0.1
4.0 MIN.
0.05±0.004
0.157 MIN.
0.2±0.15 MAX. 0.00787±0.0059
+0.003
W
1.0±0.05
0.039
–0.002
X
Y
Z
2.54 MIN.
3.0 MIN.
3.0 MIN.
0.100±0.004
0.118 MIN.
0.118 MIN.
12
MC-454DA726
[MEMO]
13
MC-454DA726
[MEMO]
14
MC-454DA726
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to VDD or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
15
MC-454DA726
[MEMO]
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as
the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these
components to prevent damaging them.
When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact
with other modules may cause excessive mechanical stress, which may damage the modules.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
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