MPD703225GC(A)-8EU [NEC]
RISC Microcontroller, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LQFP-100;
| 型号： | MPD703225GC(A)-8EU |
| 厂家： | 
NEC |
| 描述： | RISC Microcontroller, CMOS, PQFP100, 14 X 14 MM, 0.50 MM PITCH, LQFP-100 微控制器 |
| 文件： | 总39页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703223, µPD703224
µPD703225, µPD703226
V850ES/GB1TM VENUS
32-/16-bit Single-Chip Microcontroller with CAN Interface
DESCRIPTION
The V850ES/GB1 VENUS single chip microcontroller is a member of NEC's V850 32-bit RISC family,
which match the performance gains attainable with RISC-based controllers to the needs of embedded
control applications. The V850 CPU offers easy pipeline handling and programming, resulting in com-
pact code size comparable to 16-bit CISC CPUs.
The V850ES/GB1 offers an excellent combination of general purpose peripheral functions, like serial
communication interfaces (UART, clocked SI), timers and measurement inputs (A/D converter), with
dedicated CAN network support. The device offers power-saving modes to manage the power con-
sumption effectively under varying conditions. Thus equipped, the V850ES/GB1 VENUS is ideally
suited for automotive applications.
FEATURES
•
•
•
•
•
32-bit RISC CPU with Harvard Architecture
Internal ROM: 128 KB
Internal RAM: 6 KB
CAN Interface: 1 channel (DCAN)
Serial Interfaces: 4 channels
- 3-wire mode: 2 channels
•
Frequency range:
- Main: 8 MHz to 16 MHz
- Crystal Sub clock: 32.768 kHz (µPD703224)
- RC sub clock: 40 to 100 kHz (µPD703226)
Built-in low power saving mode:
- Halt, Watch, Stop
•
•
- UART mode: 2 channels (LIN compatible)
Temperature range:
- -40°C to +85°C
•
Timers: 7 channels
- 16-bit dual time-base timer: 1 channel
- 16-bit capture/compare timer: 1 channel
- 8-bit multi purpose timer: 3 channels
- Watch timer: 1 channel
-
-
µPD703223(A), µPD703224(A),
µPD703225(A), µPD703226(A)
- Package:
-
100 LQFP, 0.5 mm pin-pitch (14 × 14 mm)
- Watchdog timer: 1 channel
•
•
•
10-bit resolution A/D Converter: 12 channels
I/O lines: 84
Power supply voltage range: +4.0 V to +5.5 V
ORDERING INFORMATION
Device
Package
Mask ROM RAM Sub Clock
Part Number
µPD703223GC(A)-8EU
µPD703224GC(A)-8EU
µPD703225GC(A)-8EU
µPD703226GC(A)-8EU
96 KB
128 KB
96 KB
4 KB
6 KB
4 KB
6 KB
Crystal
RC
V850ES/GB1
LQFP100 14 × 14 mm
128 KB
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative
for availability and additional information.
NEC Corporation 2005
Document No. U15870EE1V1DS00
Data Published: April 2005
µPD703223, µPD703224, µPD703225, µPD703226
INTERNAL BLOCK DIAGRAM
power supply
NMI
Interrupt
Controller
CPU Core
INTP0 to INTP8
PC
TIG00 to TIG05
16-bit Timer
TMG0
Barrel
Shifter
Hardware
Multiplier
TOG01 to TOG04
Bus
control
unit
Mask/
ROM
System
Registers
TIC00, TIC01
TOC0
16-bit Timer
TMC0
A
L
U
General
Registers
TI50
RAM
8-bit Timer
TM50
TO50
TI51
Internal Peripheral Bus
Ports
8-bit Timer
TM51
TO51
10-bit ADC
12 channels
TI52
8-bit Timer
TM52
TO52
Note 2
CRXD0
CTXD0
DCAN0
RXD60
TXD60
UART60
Key
Return
KR0-KR7
RXD61
TXD61
UART61
CSI00
SI00
SO00
SCK00
XT1/CL1Note 1
XT2/CL2 Note 1
CLKOUT
X1
V
DD50 - VDD51
VSS51
Oscillator and
SI01
SO01
SCK01
VSS30 - VSS31
Clock Generator
CSI01
REGC0/REGC1
IC
X2
System Control
RESET
Watch
Timer
Watchdog
Timer
Notes: 1. µPD703223, µPD703224: XT1,XT2,
µPD703225, µPD703226: CL1,CL2
2. The CAN macro of this device fulfils the requirements according ISO 11898. Additionally the
CAN macro was tested according to the test procedures required by ISO 16845. The CAN
macro successfully passed all test patterns. Beyond these test patterns, other tests like
robustness tests and processor interface tests as recommended by C&S/FH Wolfenbuettel
have successfully been issued.
2
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
PIN IDENTIFICATION
ANI0 to ANI11 Analog Input
RESET
Reset Input
AVDD/AVREF
AVSS
Analog Power Supply
RXD60, RXD61
UART Receive Data
Analog Ground
SCK00, SCK01
SI00, SI01
Synchronous Interface Clock
Synchronous Interface Input
Synchronous Interface Output
Timer 5 Count Input
CLKOUT
CRXD0
CTXD0
Processor Clock Output
CAN Receive Data
CAN Transmit Data
SO00, SO01
TI50, TI51, TI52
TIC00, TIC01
TIG00 to TIG05
INTP0 to INTP8 External Interrupt Input
Timer C0 Capture Input
Timer G0 Capture Input
NMI
Non-Maskable Interrupt Input
P00 to P06
P10 to P15
P20 to P25
P30 to P34
P40 to P47
Port 0
Port 1
Port 2
Port 3
Port 4
TO50, TO51, TO52 Timer 5 Compare Output
TOC0 Timer C0 Compare Output
TOG01 to TOG04 Timer G0 Compare Output
TXD60, TXD61
X1, X2
UART Transmit Data
Main System Clock
XT1, XT2
(CL1,CL2)
P50 to P57
Port 5
Port 7
Crystal (RC) Sub Clock
P70 to P711
REGC0, REGC1
VSS30, VSS31
3.3 V Regulator Output
Ground
PCS0 to PCS1 Port CS
PCT0, PCT1,
Port CT
VSS51
Ground for I/O Buffers
PCT4, PCT6
VDD50
VDD51
IC
PDH0 to PDH5 Port DH
PCM0 to PCM3 Port CM
PDL0 to PDL15 Port DL
Digital Power Supply
Power Supply for I/O Buffers
Internally connected
KR0 to KR7
Key Return Inputs
DATA SHEET U15870EE1V1DS00
3
µPD703223, µPD703224, µPD703225, µPD703226
PIN CONFIGURATION
•
100-Pin Plastic LQFP (fine pitch) (14 mm × 14 mm) (Top View)
AVDD/AVREF
AVSS
75
74
73
72
71
70
1
2
3
4
PCT1
PCT0
P00/INTP0
PDH5
PDH4
P01/INTP1
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
VDD50
PDH3
PDH2
5
6
PDH1
7
69
68
PDH0
8
67
66
65
64
63
62
61
60
59
PCM3
REGC1
VSS31
9
REGC0
VSS30
10
11
12
13
PCM2
PCM1/CLKOUT
PCM0
VSS51
X1
X2
RESET
V850/GB1 "VENUS"
14
15
16
17
Note CL1/XT1
Note CL2/XT2
NMI
VDD51
PDL15
P06/INTP6
P10/SI00
P11/SO00
P12/SCK00
18
19
20
21
22
23
24
25
PDL14
IC
58
57
56
55
54
53
52
51
PDL13
PDL12
PDL11
PDL10
PDL9
PDL8
P13/RXD60/INTP7
P14/TXD60
P15
P40/KR0
Note: µPD703223, µPD703224: XT1,XT2,
µPD703225, µPD703226: CL1,CL2
4
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
Table of Contents
1.
2.
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 I/O Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Port Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.4 Non-Port Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.1 I/O capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Main oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.3 Sub oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2.4 Recommended oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.3.1 Supply current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.3.2 Data retention characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2.4 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.1 General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.2 AC test load condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.3 Basic operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.4.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.5 Peripheral Function Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5.1 Key return timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5.2 Interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.5.3 Timer G0 / Timer C0 /Timer 5n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5.4 CSI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.5.5 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.6 DCAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.5.7 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.5.8 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.
4.
Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Recommended Soldering Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DATA SHEET U15870EE1V1DS00
5
µPD703223, µPD703224, µPD703225, µPD703226
List of Figures
Figure 1-1:
Figure 2-1:
Figure 2-2:
Figure 2-3:
Figure 2-4:
Figure 2-5:
Figure 2-6:
Figure 2-7:
Figure 2-8:
Figure 2-9:
Figure 2-10:
Figure 2-11:
Figure 2-12:
Figure 2-13:
Figure 3-1:
Input / Output Circuits.................................................................................................. 13
Main Oscillator Recommendations.............................................................................. 21
Sub Oscillator Recommendations ............................................................................... 21
RC Oscillator Connection ............................................................................................ 22
Data Retention Timing................................................................................................. 26
AC Test Input Waveform, AC Test Load Condition..................................................... 27
AC Test Load Condition .............................................................................................. 27
RESET Timing............................................................................................................. 28
Key Return Timing....................................................................................................... 29
Interrupt Timing ........................................................................................................... 29
Timer G0 Characteristics............................................................................................. 30
Timer C0 Characteristics............................................................................................. 30
Timer 5n Characteristics.............................................................................................. 30
CSI Slave Mode Characteristics.................................................................................. 32
Package Drawing ........................................................................................................ 34
6
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
List of Tables
Table 1-1:
Table 1-2:
Table 1-3:
Table 2-1:
Table 2-2:
Table 2-3:
Table 2-4:
Table 2-5:
Table 2-6:
Table 2-7:
Table 2-8:
Table 2-9:
Pin Functions.................................................................................................................... 9
Mode of Port Pin After Reset.......................................................................................... 14
Non-Port Pin Recommended Connections..................................................................... 17
Absolute Maximum Ratings............................................................................................ 18
I/O Capacitance.............................................................................................................. 19
Main Oscillator Characteristics....................................................................................... 19
Crystal Sub Oscillator Characteristics ............................................................................ 20
RC Sub Oscillator Characteristics .................................................................................. 20
DC Characteristics.......................................................................................................... 23
Power supply current...................................................................................................... 24
Power Supply Current .................................................................................................... 25
Data Retention Characteristics....................................................................................... 26
Table 2-10: Reset Timing .................................................................................................................. 27
Table 2-11: Reset Timing .................................................................................................................. 28
Table 2-12: Key Return Timing.......................................................................................................... 29
Table 2-13: Interrupt Timing .............................................................................................................. 29
Table 2-14: Timer G0 / Timer C0 / Timer 5n Characteristics............................................................. 30
Table 2-15: CSI Master Mode Characteristics................................................................................... 31
Table 2-16: CSI Slave Mode Characteristics..................................................................................... 31
Table 2-17: UART Characteristics..................................................................................................... 32
Table 2-18: DCAN Characteristics..................................................................................................... 32
Table 2-19: A/D Converter Characteristics........................................................................................ 33
Table 2-20: Voltage regulator ............................................................................................................ 33
Table 4-1:
Soldering Conditions ...................................................................................................... 35
DATA SHEET U15870EE1V1DS00
7
µPD703223, µPD703224, µPD703225, µPD703226
8
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
1. Pin Functions
1.1 Pin Functions
Table 1-1: Pin Functions (1/4)
Pin
Function
Driver Software
Type Pull Up
I/O
No.
1
Name
Default
Analog Supply
Alternate
AVDD/AVREF
-
-
-
-
-
-
-
-
AVSS
2
3
4
5
6
7
8
9
Analog Ground
P00/INTP0
P01/INTP1
P02/INTP2
P03/INTP3
P04/INTP4
P05/INTP5
VDD50
External interrupt input INTP0
External interrupt input INTP1
External interrupt input INTP2
Port 0:
7-bit input/output port
I/O
5-W
X
External interrupt input INTP3
External interrupt input INTP4
External interrupt input INTP5
Digital Supply
-
-
-
-
-
-
-
10 REGC0
VSS30
Internal Voltage Regulator Output
Digital Ground
-
11
-
-
-
-
12 X1
Main Oscillator Input
Main Oscillator Output
Reset Input
-
I
16
16
2
-
13 X2
-
O
I
-
14 RESET
15 CL1/XT1
16 CL2/XT2
17 NMI
-
-
Sub Oscillator Input
Sub Oscillator Output
Non-Maskable Interrupt Input
Port 0: 7-bit input/output port
-
I
16
16
2
-
-
O
I
-
-
-
18 P06/INTP6
19 P10/SI00
20 P11/SO00
21 P12/SCK00
External interrupt input INTP6
I/O
5-W
5-W
5-A
5-W
X
X
X
X
3-wire Serial Link 0 Data Input I/O
3-wire Serial Link 0 Data Output I/O
3-wire Serial Link 0 Clock I/O
I/O
I/O
Port 1: 6-bit input/output port
P13/RXD60/
INTP7
UART0 Data Input
External interrupt input INTP7
22
5-W
X
23 P14/TXD60
24 P15
UART0 Data Output
-
I/O
I/O
5-A
5-A
X
X
DATA SHEET U15870EE1V1DS00
9
µPD703223, µPD703224, µPD703225, µPD703226
Table 1-1: Pin Functions (2/4)
Pin
Name
Function
Driver Software
Type Pull Up
I/O
No.
Default
Alternate
25 P40/KR0
Key Return Input 0
Key Return Input 1
TimerG0 Capture Trigger 0
TimerG0 Compare Output 0
P41/KR1/
26
TIG00
Key Return Input 2
TimerG0 Capture Trigger 1
TimerG0 Compare Output 1
P42/KR2/
27
TIG01/TOG01
Key Return Input 3
TimerG0 Capture Trigger 2
TimerG0 Compare Output 2
P43/KR3/
TIG02/TOG02
28
29
Port 4: 8-bit input/output port
I/O
5-W
X
Key Return Input 4
TimerG0 Capture Trigger 3
TimerG0 Compare Output 3
P44/KR4/
TIG03/TOG03
Key Return Input 5
TimerG0 Capture Trigger 4
TimerG0 Compare Output 4
P45/KR5/
TIG04/TOG04
30
31
P46/KR6/
TIG05
Key Return Input 6
TimerG0 Capture Trigger 5
32 P47/KR7
33 P50
Key Return Input 7
-
5-A
5-A
5-A
5-A
5-A
5-W
5-A
5-A
34 P51
-
35 P52
-
36 P53
-
Port 5: 8-bit input/output port
I/O
I/O
X
37 P54/CTXD0
38 P55/CRXD0
39 P56
DCAN0 Transmit Data
DCAN0 Receive Data
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
40 P57
41 PCS0
42 PCS1
43 PDL0
44 PDL1
45 PDL2
46 PDL3
47 PDL4
48 PDL5
49 PDL6
50 PDL7
51 PDL8
52 PDL9
53 PDL10
54 PDL11
55 PDL12
56 PDL13
57 IC
Port CS: 2-bit input/output port
5-K
-
Port DL: 16-bit input/output port
I/O
5-K
-
internally connected
DATA SHEET U15870EE1V1DS00
-
-
-
10
µPD703223, µPD703224, µPD703225, µPD703226
Table 1-1: Pin Functions (3/4)
Pin
Name
Function
Driver Software
Type Pull Up
I/O
I/O
No.
Default
Alternate
58 PDL14
59 PDL15
-
-
-
Port DL: 16-bit input/output port
5-K
-
VDD51
VSS51
60
61
Power Supply I/O Buffers
I/O Buffers Ground
-
-
-
-
-
-
-
-
62 PCM0
PCM1/
63
Port CM: 4-bit input/output port
CPU Clock Output
I/O
5-K
-
CLKOUT
64 PCM2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VSS31
65
Digital Ground
-
-
-
-
-
-
66 REGC1
67 PCM3
68 PDH0
69 PDH1
70 PDH2
71 PDH3
72 PDH4
73 PDH5
74 PCT0
75 PCT1
76 PCT4
77 PCT6
Internal Voltage Regulator Output
Port CM: 4-bit input/output port
I/O
5-K
-
Port DH: 6-bit input/output port
Port CT: 4-bit input/output port
I/O
I/O
5-K
-
P20/RXD61/
INTP8
UART1 Data Input
External interrupt input INTP8
78
5-W
79 P21/TXD61
80 P22/SI01
81 P23/SO01
82 P24/SCK01
83 P25
UART1 Data Output
5-A
5-W
5-A
5-W
5-A
3-wire Serial Link 1 Data Input
3-wire Serial Link 1 Data Output
3-wire Serial Link 1 Clock I/O
-
Port 2: 6-bit input/output port
X
P30/TI50/
TO50
8-bit Timer 50 External Clock
Input / PWM Output
84
P31/TI51/
TO51
8-bit Timer 51 External Clock
Input / PWM Output
85
P32/TI52/
TO52
8-bit Timer 52 External Clock
Input / PWM Output
86
Port 3: 5-bit input/output port
I/O
5-W
X
16 bits TimerC0
Capture Trigger 0 /
Compare Output 0
P33/TIC00/
TOC0
87
16 bits TimerC0
Capture Trigger 1
88 P34/TIC01
DATA SHEET U15870EE1V1DS00
11
µPD703223, µPD703224, µPD703225, µPD703226
Table 1-1: Pin Functions (4/4)
Pin
Name
Function
Driver Software
Type Pull Up
I/O
No.
Default
Alternate
ANI11
ANI12
ANI9
89 P711/ANI11
90 P710/ANI10
91 P79/ANI9
92 P78/ANI8
93 P77/ANI7
94 P76/ANI6
95 P75/ANI5
96 P74/ANI4
97 P73/ANI3
98 P72/ANI2
99 P71/ANI1
100 P70/ANI0
ANI8
ANI7
ANI7
Port 7: 12-bit input port
I
9-C
−
ANI6
ANI5
ANI3
ANI2
ANI1
ANI0
Caution: REGC0 and REGC1 have to be connected to each other and the capacitors on REGC0
and REGC1 have to be attached as tight as possible to the pins
12
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
1.2 I/O Circuits
Figure 1-1: Input / Output Circuits
Type 2
Type 5-A
VDD
Pullup
enable
P-ch
VDD
Data
P-ch
IN
IN/OUT
Output
disable
N-ch
Input
enable
VDD
Type 5-W
Type 5-K
Data
VDD
Pullup
enable
P-ch
P-ch
VDD
IN/OUT
Data
P-ch
N-ch
Output
disable
N-ch
IN/OUT
VSS
Output
disable
Input
enable
Input
enable
Type 9-C
Type 16
P-ch
feedback cut-off
Comparator
P-ch
+
IN
-
N-ch
AVSS
VREF
(threshold voltage)
Input
enable
Input
Output
DATA SHEET U15870EE1V1DS00
13
µPD703223, µPD703224, µPD703225, µPD703226
1.3 Port Pin
Table 1-2: Mode of Port Pin After Reset (1/3)
Pin Function after Reset
Port Name
PNMI
Pin Name
If not used
Single Chip Mode
Independently connect to
SS51 or VDD51 via resistor
NMI
NMI
V
P00/INTP0
P01/INTP1
Input: Independently connect to
VSS51 or VDD51 via resistor
P02/INTP2
Port Mode
(input mode)
P0
P03/INTP3
P04/INPT4
Output: leave open
P05/INPT5
P06/INPT6
P10/SI00
P11/SO00
Input: Independently connect to
P12/SCK00
VSS51 or VDD51 via resistor
Port Mode
P1
(input mode)
P13/INTP7/RXD60
P14/TXD60
Output: leave open
P15
P20/INTP8/RXD61
P21/TXD61
Input: Independently connect to
P22/SIO01
VSS51 or VDD51 via resistor
Port Mode
P2
P3
(input mode)
P23/SO01
Output: leave open
P24/SCK01
P25
P30/TI50/TO50
P31/TI51/TO51
P32/TI52/TO52
P33/TIC00/TOC0
P34/TIC01
Input: Independently connect to
VSS51 or VDD51 via resistor
Port Mode
(input mode)
Output: leave open
P40/KR0
P41/KR1/TIG00
P42/KR2/TIG01/TOG01
P43/KR3/TIG02/TOG02
P44/KR4/TIG03/TOG03
P45/KR5/TIG04/TOG04
P46/KR6/TIG05
P47/KR7
Input: Independently connect to
VSS51 or VDD51 via resistor
Port Mode
(input mode)
P4
Output: leave open
14
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
Table 1-2: Mode of Port Pin After Reset (2/3)
Pin Function after Reset
Port Name
Pin Name
If not used
Single Chip Mode
P50
P51
P52
Input: Independently connect to
VSS51 or VDD51 via resistor
P53
Port Mode
P5
(input mode)
P54/CTXD0
P55/CRCD0
P56
Output: leave open
P57
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
P78/ANI8
P79/ANI9
P710/ANI10
P711/ANI11
PCS0
Independently connect to
AVSS or AVDD via resistor
Port Mode
(input mode)
P7
Input: Independently connect to
Port Mode
(input mode)
VSS51 or VDD51 via resistor
PCS
PCT
PCS1
Output: leave open
PC0
Input: Independently connect to
VSS51 or VDD51 via resistor
PC1
Port Mode
(input mode)
PC4
Output: leave open
PC6
PDH0
PDH1
PDH2
PDH3
PDH4
PDH5
PCM0
PCM1
PCM2
PCM3
Input: Independently connect to
VSS51 or VDD51 via resistor
Port Mode
(input mode)
PDH
PCM
Output: leave open
Input: Independently connect to
VSS51 or VDD51 via resistor
Port Mode
(input mode)
Output: leave open
DATA SHEET U15870EE1V1DS00
15
µPD703223, µPD703224, µPD703225, µPD703226
Table 1-2: Mode of Port Pin After Reset (3/3)
Pin Function after Reset
Port Name
Pin Name
If not used
Single Chip Mode
PDL0
PDL1
PDL2
PDL3
PDL4
PDL5
PDL6
PDL7
PDL8
PDL9
PDL10
PDL11
PDL12
PDL13
PDL14
PDL15
Input: Independently connect to
VSS51 or VDD51 via resistor
Port Mode
(input mode)
PDL
Output: leave open
16
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
1.4 Non-Port Pin
Table 1-3: Non-Port Pin Recommended Connections
Pin Number Pin name
Connection for normal operation
Analog power supply
if not used
Connect to VDD51
Connect to VSS51
AVDD
AVSS
VDD50
1
2
9
Analog Ground
5.0 V Power supply
-
-
Connect an 1 µF capacitor between this
pin and Ground
10
REGC0
VSS30
11
12
13
14
15
16
57
60
Digital Ground
-
-
-
-
X1
X2
Refer to 2.2.4 for recommended circuit
Reset input
RESET
XT1
Connect to VSS30 or VSS31 via resistor
Refer to 2.2.4 for recommended circuit
XT2
Leave open
-
IC
Connect to Ground
I/O Buffers power supply
I/O Buffers Ground
Digital ground
VDD51
VSS51
VSS31
61
65
Connect an 1 µF capacitor between this
pin and Ground
66
REGC1
Caution: REGC0 and REGC1 have to be connected to each other and the capacitors on REGC0
and REGC1 have to be attached as tight as possible to the pins
DATA SHEET U15870EE1V1DS00
17
µPD703223, µPD703224, µPD703225, µPD703226
2. Electrical Specifications
2.1 Absolute Maximum Ratings
T = 25°C, V
= 0 V
SS51
A
Table 2-1: Absolute Maximum Ratings
Symbol Conditions
VDD50,
VDD51
Parameter
Ratings
Unit
VDD50 = VDD51
-0.5 ~ +6.0
-0.5 ~ +6.0
-0.5 ~ +0.5
-0.5 ~ +0.5
-0.5 ~ +6.0
AVDD
AVDD ≤ VDD5x + 0.5 V
VSS30 = VSS31
Supply voltage
Input voltage
VSS30,
VSS31
V
AVSS
VI
All port pinsNote 1
NMI, RESET
,
VI < VDD51 + 0.5 V
VIAN
IOL
VIAN < AVDD + 0.5 V
Analog Input Voltage
-0.5 ~ +6.0
4.0
1 pin
Low Level
Output current Note 1
All port pinsNote 1
All pins
1 pin
50
mA
-4.0
High Level
Output current Note 1
All port pinsNote 1
IOH
All pins
-50
VO1
TA
VO1 < VDD51 + 0.5 V
Output Voltage
-0.5 ~ +6.0
V
Operating temperature
Storage temperature
-40 ~ +85
°C
TSTGA
-65 ~ +150
Remarks: 1. x = 0, 1
2. The characteristics of the dual-functions pins are the same as those of the port pins
unless otherwise specified.
Note: All Ports pins are P0, P1, P2, P3, P4, P5, P7, PCS, PCT, PDH, PCM, PDL.
Cautions: 1. Avoid direct connections among the IC device output (or I/O) pins and between
V
or V and GND.
DD
CC
2. Product quality may suffer if the absolute maximum rating is exceeded even
momentarily for any parameter. That is, the absolute maximum ratings are rated
values at which the product is on the verge of suffering physical damage, and
therefore the product must be used under conditions that ensure that the abso-
lute maximum ratings are not exceeded. The ratings and conditions indicated for
DC characteristics and AC characteristics represent the quality assurance range
during normal operation.
18
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
2.2 General Characteristics
2.2.1 I/O capacitance
T = 25°C, V = V
= V
= V
= V
= AV = AV = 0 V
SS31 DD SS
A
DD50
DD51
SS51
SS30
Table 2-2: I/O Capacitance
Parameter
Input capacitance
Symbol
Test Conditions
MIN.
TYP.
MAX.
15
Unit
pF
CI
fC = 1 MHz
CIO
CO
Input/output capacitance
Output capacitance
15
pF
Unmeasured pins
returned to 0 V
15
pF
2.2.2 Main oscillator characteristics
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS51 SS
A
DD50
DD51
DD
SS30
SS31
Table 2-3: Main Oscillator Characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note 1
fXX
Main oscillator frequency
8
16
MHz
ms
17
After Reset Note 4
2 /f
XX
Oscillation stabilization
time Note 2, 3
TOST
After Stop mode Note 4
After Watch mode Note 6
Note 5
Note 5
2
ms
µs
100
Notes: 1. Indicates only the oscillation circuit characteristics. Refer to “AC Characteristic” for CPU
operation clock.
2. Time, which is required for internal stabilization. The OSTS register has to be set to a time,
which is longer than above defined values, before entering either WATCH or STOP mode.
3. After V
reaches oscillator voltage range MIN. 4.0 V
DD5X
4. Start-up time of external crystal or resonator is not included and must be checked with res-
onator supplier.
5. Typical value differs depending on settings of the Oscillation Stabilization Time Selection
register (OSTS)
6. To release watch mode, minimum 10-clock cycles time is required. If sub clock is used to
recover from watch mode, minimum time for watch mode release is determined by this
10-clock cycles.
DATA SHEET U15870EE1V1DS00
19
µPD703223, µPD703224, µPD703225, µPD703226
2.2.3 Sub oscillator characteristics
(1) Crystal sub oscillator
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS51 SS
A
DD50
DD51
DD
SS30
SS31
Table 2-4: Crystal Sub Oscillator Characteristics
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
kHz
s
fXT
Sub oscillator frequency
32.768
Oscillation stabilization time
10Note
TSOST
Note: Start-up time of external crystal must be checked with resonator supplier.
(2) RC sub oscillator
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V)
SS51 SS
A
DD50
DD51
DD
SS30
SS31
Table 2-5: RC Sub Oscillator Characteristics
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
fXT
Sub oscillator frequency
R = 500 kΩ, C = 33 pF
40
100
kHz
20
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
2.2.4 Recommended oscillator circuit
(1) Recommended Main system clock oscillator circuit
(a) Ceramic resonator or crystal resonator connection
Figure 2-1: Main Oscillator Recommendations
X1
X2
R1'
QU
C1'
C2'
Remark: Values of capacitors C1’, C2’ and R1’ depend on used resonator and must be specified in
cooperation with the manufacturer.
(2) Recommended subsystem clock oscillator circuit
(a) Ceramic resonator or crystal resonator connection: µPD703223 (A), µPD703224 (A)
Figure 2-2: Sub Oscillator Recommendations
XT1
XT2
R'1
C2'
QU
C1'
Remark: Values of capacitors C1’, C2’ and resistors R’1 depend on used resonator and must be
specified in cooperation with the manufacturer.
DATA SHEET U15870EE1V1DS00
21
µPD703223, µPD703224, µPD703225, µPD703226
(b) RC Oscillator connection: µPD703225 (A), µPD703226 (A)
Figure 2-3: RC Oscillator Connection
CL2
R
CL1
C
Cautions: 1. External clock to main clock or subsystem clock oscillator input is prohibited.
2. When using the main system clock or the sub system clock oscillator, wire as fol-
lows in the area enclosed by the broken lines in the above figures to avoid an
adverse effect from wiring capacitance.
•
•
•
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating
current flows.
•
Always make the ground point of the oscillator capacitor the same potential
as V
.
SS
•
•
Do not ground the capacitor to a ground pattern through which a high cur-
rent flows.
Do not fetch signals from the oscillator.
22
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
2.3 DC Characteristics
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS51 SS
A
DD50
DD51
DD
SS30
SS31
Table 2-6: DC Characteristics
Parameter
Symbol Test Conditions
MIN.
TYP.
MAX.
Unit
P11, P14-P15, P21, P23,
P25, P50-P54, P56-P57
VIH1
0.7 VDD51
VDD51
P00-P06, P10, P12-P13,
P20, P22, P24, P30-P34,
PDL0-PDL15, PCM0-PCM3,
PDH0-PDH5, PCT0, PCT1,
PCT4, PCT6, NMI
High level
Input Voltage
VIH2
0.8 VDD51
VDD51
P70-P711Note
RESET
VIH3
VIH4
0.7 AVDD
0.8 VDD51
AVDD
VDD51
P11, P14-P15, P21, P23,
P25, P50-P54, P56-P57
VIL1
VSS51
0.3 VDD51
P00-P06, P10, P12-P13,
P20, P22, P24, P30-P34,
PDL0-PDL15, PCM0-PCM3,
PDH0-PDH5, PCT0, PCT1,
PCT4, PCT6, NMI
V
Low level
Input voltage
VIL2
VSS51
0.2 VDD51
P70-P711Note
RESET
VIL3
VIL4
0.3 AVDD
0.2 VDD51
VDD51
VDD51
0.4
0
VSS51
IOH = -2.0 mA
IOH = -100 µA
IOL = 2.0 mA
IOL = 100 µA
VDD51 - 1.0 V
VDD51 - 0.5 V
VOH1
High Level Output Voltage
VOL1
Low Level Output Voltage
Input leakage
0.2
ILIH1
ILIL1
VI = VDD51
VI = 0 V
except for X1, X2, XT1, XT2
0.3
3
current, high
µA
Input leakage
current, low
except for X1, X2, XT1, XT2
P0, P1, P2, P3, P4, P5
-0.3
30
-3
Software
Pull-up
R1
10
100
kΩ
resistor
Note: Can only be used as digital input port when AV = V
DD
DD5x
DATA SHEET U15870EE1V1DS00
23
µPD703223, µPD703224, µPD703225, µPD703226
2.3.1 Supply current
(1) µPD703223 (A), µPD703224 (A)
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
f
= 16 MHz, f = 32.768 kHz
XT
XX
Table 2-7: Power supply current
Test Conditions MIN.
Operating Note 2
Parameter
Symbol
TYP.
30
MAX.
45
Unit
IDD1
HALT mode Note 3
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
20
30
mA
WATCH mode Note 4
STOP mode Note 5
1.5
50
2.3
Power Supply
Current Note 1
µPD703223(A)
µPD703224(A)
120
250
150
150
Sub Operating Note 6
Sub HALT mode Note 7
Sub WATCH mode Note 8
125
75
µA
75
Notes: 1. AV /AV
current, port current (including a current flowing through the on-chip pull-up
REF
DD
resistors) are not included.
2. CPU operating at maximum frequency (PCC = 0x00H), peripheral functions operating at
maximum frequency (excepted DCAN0).
3. CPU stopped, peripheral functions operating at maximum frequency (excepted DCAN0).
4. CPU stopped, all peripheral functions stopped (Watch timer and Watchdog timer operating
on subclock).
5. Subclock not connected.
6. CPU operating on subclock, main system clock oscillator stopped, all peripheral functions
stopped, (Watch timer and Watchdog timer operating on subclock).
7. CPU stopped, main system clock oscillator stopped, all peripheral functions stopped (Watch
timer and Watchdog timer operating on subclock).
8. CPU stopped, main system clock oscillator stopped, all peripheral functions stopped (Watch
timer and Watchdog timer operating on subclock).
24
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
(2) µPD703225 (A), µPD703226 (A)
T = -40°C to +85°C, V = V = AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
f
= 16 MHz, f = 32 kHz
XT
XX
Table 2-8: Power Supply Current
Test Conditions MIN.
Operating Note 2
Parameter
Symbol
TYP.
MAX.
45
Unit
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
30
20
HALT mode Note 3
30
mA
WATCH mode Note 4
STOP mode Note 5
1.5
50
2.3
Power Supply
Current Note 1
µPD703225(A)
µPD703226(A)
120
275
175
175
Sub Operating Note 6
Sub HALT mode Note 7
Sub WATCH mode Note 8
140
90
µA
90
Notes: 1. AV /AV
current, port current (including a current flowing through the on-chip pull-up
REF
DD
resistors) are not included.
2. CPU operating at maximum frequency (PCC = 0x00H), peripheral functions operating at
maximum frequency (excepted DCAN0).
3. CPU stopped, peripheral functions operating at maximum frequency (excepted DCAN0).
4. CPU stopped, all peripheral functions stopped (Watch timer and Watchdog timer operating
on subclock).
5. Subclock not connected.
6. CPU operating on subclock, main system clock oscillator stopped, all peripheral functions
stopped, (Watch timer and Watchdog timer operating on subclock).
7. CPU stopped, main system clock oscillator stopped, all peripheral functions stopped (Watch
timer and Watchdog timer operating on subclock).
8. CPU stopped, main system clock oscillator stopped, all peripheral functions stopped (Watch
timer and Watchdog timer operating on subclock).
DATA SHEET U15870EE1V1DS00
25
µPD703223, µPD703224, µPD703225, µPD703226
2.3.2 Data retention characteristics
T = -40 ~ +85°C:
A
Table 2-9: Data Retention Characteristics
Parameter
Symbol
Test Conditions
STOP mode Note
MIN.
TYP.
MAX.
Unit
VDDDR
Data retention voltage
3.0
5.5
V
(no functions operating)
tRVD
tFVD
tHVD
tDREL
Supply Voltage rise time
Supply Voltage fall time
200
200
0
µs
µs
ms
ns
Supply voltage hold time
STOP release signal input time
0
Data retention High-level input
voltage
VIHDR
VILDR
0.9VDDDR
0
VDDDR
All input ports
All input ports
V
V
Data retention High-level input
voltage
0.1VDDDR
Note: Subclock stopped
Figure 2-4: Data Retention Timing
Setting STOP mode
VDDDR
VDD
tFVD
tRVD
tDREL
tHVD
VIHDR
VIHDR
RESET (input)
STOP mode release interrupt (NMI, etc.)
(Released by falling edge)
STOP mode release interrupt (NMI, etc.)
(Released by rising edge)
VILDR
26
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
2.4 AC Characteristics
2.4.1 General
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Output pin load capacitance: C = 50 pF
L
Figure 2-5: AC Test Input Waveform, AC Test Load Condition
Test Points
VDD5x
0 V
0.8 VDD5x
0.2 VDD5x
2.4.2 AC test load condition
Figure 2-6: AC Test Load Condition
DUT
Load on test
= 50 pF
CL
2.4.3 Basic operation
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-10: Reset Timing
Symbol Test Conditions
fCPU
Parameter
MIN.
MAX.
Unit
CPU Operating clock
16
MHz
DATA SHEET U15870EE1V1DS00
27
µPD703223, µPD703224, µPD703225, µPD703226
2.4.4 Reset
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-11: Reset Timing
Symbol Test Conditions
tWRSL
Parameter
MIN.
MAX.
Unit
RESET low-level width
500
ns
Figure 2-7: RESET Timing
tWRSL
RESET
28
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
2.5 Peripheral Function Characteristics
2.5.1 Key return timing
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-12: Key Return Timing
Parameter
Symbol
Test Conditions
MIN.
500
MAX.
Unit
KRn input low level width Note
tWKRL
ns
Note: n = 0 to 7
Figure 2-8: Key Return Timing
tWKRL
KRn
2.5.2 Interrupt timing
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-13: Interrupt Timing
Parameter
NMI high-level width
NMI low-level width
Symbol
Test Conditions
Analog filter
MIN.
500
500
500
MAX.
Unit
ns
tWNIH
tWNIL
tWITH
tWITL
Analog filter
ns
INTPnNote high-level width
INTPnNote low-level width
Analog filter
ns
Analog filter
500
ns
Note: n = 0 to 8
Figure 2-9: Interrupt Timing
tWNIH
tWNIL
NMI
tWITH
tWITL
INTPn
Remark: n = 0 to 8
DATA SHEET U15870EE1V1DS00
29
µPD703223, µPD703224, µPD703225, µPD703226
2.5.3 Timer G0 / Timer C0 /Timer 5n
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-14: Timer G0 / Timer C0 / Timer 5n Characteristics
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
TT x 2 + 20Note 2
TIG0m high-level widthNote 1
TIG0m low-level widthNote 1
TIC0m high-level widthNote 3
tWTIGH
ns
TT x 2 + 20Note 2
TT x 2 + 20Note 2
tWTIGL
tWTICH
ns
ns
TT x 2 + 20Note 2
TIC0m low-level widthNote 3
TI5n input cycle timeNote 4
TI5n input high level withNote 4
TI5n low level widthNote 4
tWTICL
TWTI5CY
TWTI5CH
TWTI5CL
ns
ns
ns
ns
120
48
48
Notes: 1. m = 0 to 5
2. T : Depends on selected clock source for the peripheral clock supply and the setup of the
T
respective timer macro clock and timer channel setup
3. m = 0 to 1
4. n = 0 to 2
Figure 2-10: Timer G0 Characteristics
tWTIGH
tWTIGL
TIG0n
Figure 2-11: Timer C0 Characteristics
tWTICH
tWTICL
TIC01
Figure 2-12: Timer 5n Characteristics
tWTI5CY
tWTI5CH
tWTI5CL
TIC5n
30
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
2.5.4 CSI
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0
A
DD50
DD51
DD
SS51
SS30
SS31
SS
Table 2-15: CSI Master Mode Characteristics
Parameter Note
SCK0n cycle time
Symbol Test Conditions
MIN.
200
MAX.
Unit
ns
tCYSKM
tWSKHM
tWSKLM
tSSISKM
tHSKSIM
tDSKSOM
tHSKSOM
Output
Output
Output
0.5 tCYSK - 10
SCK0n high level width
ns
0.5 tCYSK - 10
SCK0n low level width
ns
SI0n set up time (to SCK0n ↑)
SI0n hold time (from SCK0n ↑)
SO0n output delay time (from SCK0n ↓)
SO0n output hold time (from SCK0n ↑)
30
30
ns
ns
30
ns
0.5 tCYSK - 5
ns
Remark: n = 0, 1
Table 2-16: CSI Slave Mode Characteristics
Symbol Test Conditions MIN.
Parameter Note
SCK0n cycle time
MAX.
Unit
ns
tCYSKS
tWSKHS
tWSKLS
tSSISKS
tHSKSIS
tDSKSOS
tHSKSOS
Input
Input
Input
200
0.5 tCYSK -10
0.5 tCYSK -10
SCK0n high level width
ns
SCK0n low level width
ns
SI0n set up time (to SCK0n ↑)
SI0n hold time (from SCK0n ↑)
SO0n output delay time (from SCK0n ↓)
SO0n output hold time (from SCK0n ↑)
50
50
ns
ns
50
ns
0.5 tCYSK - 5
ns
Remark: n = 0, 1
DATA SHEET U15870EE1V1DS00
31
µPD703223, µPD703224, µPD703225, µPD703226
Figure 2-13: CSI Slave Mode Characteristics
tCYSK
tWSKL
tWSKH
SCK0n
SI0n
tSSISK tHSKSI
Hi-Z
Input Data
tDSKSO
tHSKSO
Output Data
SO0n
2.5.5 UART
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-17: UART Characteristics
Parameter
Symbol Test Conditions
MIN.
MAX.
Unit
bps
TUART
fPeripheral ≥ 5 MHz
Transfer rate
312500
2.5.6 DCAN
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-18: DCAN Characteristics
Parameter
Symbol Test Conditions
MIN.
MAX.
Unit
Mbps
TDCAN
fXX = 16 MHz
Transfer rate
1
32
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
2.5.7 A/D converter
T = -40°C to +85°C, V
= V
= AV = 4.5 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-19: A/D Converter Characteristics
Parameter
Resolution
Symbol
Test Conditions
MIN.
TYP.
10
MAX.
Unit
-
-
Bit
LSB
µs
Overall ErrorNote 1
±3
Conversion timeNote 2
TCONV
TSAM
VIAN
5
12
Sampling timeNote 3
Analog input voltage
TCONV/6
µs
AVSS
AVDD
8.0
V
IAVDD
ILAVDD
A/D converter is operating
4.0
1.0
mA
µA
Analog supply current
A/D converter is stoppedNote 4
5.0
Notes: 1. The quantization error is not included
2. The conversion time T depends on the setting of the ADM register
CONV
3. The sampling time T
depends on the setting of the ADM register
SAM
4. The leakage current specification becomes valid if the A/D converter reference voltage is
switched off.
2.5.8 Voltage regulator
T = -40°C to +85°C, V
= V
= AV = 4.0 V ~ 5.5 V, V
= V
= V
= AV = 0 V
SS31 SS
A
DD50
DD51
DD
SS51
SS30
Table 2-20: Voltage regulator
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
Time starts when VDD50 reaches
minimum value of 4.0 V
(CREGC0 = CREGC1 = 1 µF) Note
Output voltage
stabilization time
tREG
2
ms
Note: C
& C
are respectively connected to REGC0 and REGC1 pins. They must have the
REGC1
REGC0
same value.
Remark: To improve EMI and noise filtering, it might be necessary to connect small size capaci-
tances in parallel with C & C
.
REGC1
REGC0
DATA SHEET U15870EE1V1DS00
33
µPD703223, µPD703224, µPD703225, µPD703226
3. Package Drawing
Figure 3-1: Package Drawing
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
ITEM MILLIMETERS
A
B
C
D
F
16.00±0.20
14.00±0.20
14.00±0.20
16.00±0.20
1.00
G
1.00
+0.05
0.22
H
−0.04
I
J
0.08
0.50 (T.P.)
1.00±0.20
0.50±0.20
K
L
+0.03
0.17
M
−0.07
N
P
Q
0.08
1.40±0.05
0.10±0.05
+7°
3°
R
−3°
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
34
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
4. Recommended Soldering Conditions
Solder this product under the following recommended conditions.
For details of the recommended soldering conditions, refer to information document Semiconductor
Device:
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended please consult NEC.
Table 4-1: Soldering Conditions
Symbol of Recommended Soldering
Soldering Method
Soldering Condition
Condition
Package peak temperature: 235°C,
Time: 30 seconds max. (210°C min.),
Number of times: 3 max.,
Infrared reflow
IR35-107-3
Number of days: 7 Note
Package peak temperature: 215°C,
Time: 30 seconds max. (210°C min.),
Number of times: 2 max.,
Number of days: 7 Note
VPS
VP15-207-2
-
Pin temperature: 300°C max.,
Time: 3 seconds max. (per side of device)
Partial heating
Note: The number of days refers to storage at 25°C, 65% RH MAX after the dry pack has been
opened.
After that, prebaking is necessary at 125 °C for 10 to 72 hours.
Caution: Do not use two or more soldering methods in combination (except partial heating
method).
DATA SHEET U15870EE1V1DS00
35
µPD703223, µPD703224, µPD703225, µPD703226
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
All other product, brand, or trade names used in this publication are the trademarks
or registered trademarks of their respective trademark owners.
Product specifications are subject to change without notice. To ensure that you have the latest
product data, please contact your local NEC Electronics sales office.
36
DATA SHEET U15870EE1V1DS00
µPD703223, µPD703224, µPD703225, µPD703226
•
The information in this document is current as of April, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
•
• While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
• NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
(1)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
(2)
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
M8E 02. 11-1
DATA SHEET U15870EE1V1DS00
37
µPD703223, µPD703224, µPD703225, µPD703226
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Orderinginformation
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
Filiale Italiana
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics America Inc.
SantaClara, California
Tel: 408-588-6000
800-366-9782
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Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Branch The Netherlands
Eindhoven, TheNetherlands
Tel: 040-244 58 45
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
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Duesseldorf, Germany
Tel: 0211-65 03 1101
Fax: 0211-65 03 1327
Fax: 040-244 45 80
Branch Sweden
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
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Singapore
Tel: 65-6253-8311
Fax: 65-6250-3583
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Madrid, Spain
Tel: 091- 504 27 87
Fax: 091- 504 28 60
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Milton Keynes, UK
Tel: 01908-691-133
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Taipei, Taiwan
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Succursale Française
Vélizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
38
DATA SHEET U15870EE1V1DS00
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