UPA2723UT1A-E2-AY [NEC]
Power Field-Effect Transistor, 33A I(D), 30V, 0.0035ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ROHS COMPLIANT, HVSON-8;
| 型号： | UPA2723UT1A-E2-AY |
| 厂家： | 
NEC |
| 描述： | Power Field-Effect Transistor, 33A I(D), 30V, 0.0035ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, ROHS COMPLIANT, HVSON-8 |
| 文件： | 总6页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
μPA2723UT1A
SWITCHING
N-CHANNEL POWER MOSFET
PACKAGE DRAWING (Unit: mm)
DESCRIPTION
The μ PA2723UT1A is N-channel MOSFET designed for low side device
of synchronous rectifier DC/DC converter.
1
8
2
3
4
7
6
5
FEATURES
• Low on-state resistance
6
0.2
0.10 S
RDS(on)1 = 2.5 mΩ MAX. (VGS = 10 V, ID = 17 A)
RDS(on)2 = 3.5 mΩ MAX. (VGS = 4.5 V, ID = 17 A)
• Thin type surface mount package with heat spreader (8-pin HVSON)
• RoHS Compliant
5.4 0.2
1
ABSOLUTE MAXIMUM RATINGS (TA = 25°C, All terminals are connected.)
0.2
Drain to Source Voltage (VGS = 0 V)
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC)
VDSS
VGSS
ID(DC)
ID(pulse)
PT1
30
20
V
V
1, 2, 3 : Source
4
: Gate
33
A
5, 6, 7, 8: Drain
Drain Current (pulse) Note1
200
A
Total Power Dissipation Note2
Total Power Dissipation (PW =10 sec) Note2
Channel Temperature
3.65 0.2
0.6 0.15
1.5
W
W
°C
°C
A
0.7 0.15
PT2
4.6
Tch
150
Storage Temperature
Tstg
−55 to +150
33
Single Avalanche Current Note3
Single Avalanche Energy Note3
IAS
EQUIVALENT CIRCUIT
EAS
109
mJ
Drain
THERMAL RESISTANCE
Channel to Ambient Thermal Resistance Note2
Body
Diode
Rth(ch-A)
Rth(ch-C)
83.3
1.5
°C/W
°C/W
Gate
Channel to Case (Drain) Thermal Resistance
Notes 1. PW ≤ 10 μs, Duty Cycle ≤ 1%
Source
2. Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm
3. Starting Tch = 25°C, VDD = 15 V, RG = 25 Ω, VGS = 20 → 0 V, L = 100 μH
Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade
the device operation. Steps must be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
2007
Document No. G17954EJ1V0DS00 (1st edition)
Date Published April 2007 NS CP(K)
Printed in Japan
μ PA2723UT1A
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Zero Gate Voltage Drain Current
Gate Leakage Current
IDSS
IGSS
VGS(off)
| yfs |
RDS(on)1
RDS(on)2
Ciss
VDS = 30 V, VGS = 0 V
10
μA
nA
V
VGS = 20 V, VDS = 0 V
VDS = 10 V, ID = 1 mA
VDS = 10 V, ID = 17 A
VGS = 10 V, ID = 17 A
VGS = 4.5 V, ID = 17 A
VDS = 10 V,
100
2.5
Gate to Source Cut-off Voltage
Forward Transfer Admittance Note
Drain to Source On-state Resistance Note
1.0
17
S
1.9
2.6
8100
1290
610
30
2.5
3.5
mΩ
mΩ
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-on Delay Time
Rise Time
Coss
Crss
td(on)
tr
VGS = 0 V,
f = 1 MHz
VDD = 15 V, ID = 17 A,
VGS = 10 V,
40
Turn-off Delay Time
Fall Time
td(off)
tf
RG = 10 Ω
160
55
Total Gate Charge
QG
VDD = 15 V,
64
Gate to Source Charge
Gate to Drain Charge
Body Diode Forward Voltage Note
Reverse Recovery Time
Reverse Recovery Charge
Gate Resistance
QGS
QGD
VF(S-D)
trr
VGS = 5 V,
19
ID = 33 A
24
IF = 33 A, VGS = 0 V
IF = 33 A, VGS = 0 V,
di/dt = 100 A/μs
f = 1 MHz
0.76
55
ns
nC
Ω
Qrr
66
RG
1.4
Note Pulsed
TEST CIRCUIT 1 AVALANCHE CAPABILITY
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
L
D.U.T.
V
V
GS
RG
= 25 Ω
50 Ω
R
L
90%
V
GS
Wave Form
V
GS
10%
90%
0
R
G
PG.
V
DD
PG.
GS = 20 → 0 V
V
DD
V
DS
90%
V
DS
V
0
GS
BVDSS
10% 10%
V
DS
Wave Form
0
I
AS
V
DS
I
D
τ
t
d(on)
t
r
t
d(off)
t
f
V
DD
t
on
t
off
τ = 1
μs
Duty Cycle ≤ 1%
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
= 2 mA
I
G
RL
50 Ω
PG.
V
DD
2
Data Sheet G17954EJ1V0DS
μ PA2723UT1A
TYPICAL CHARACTERISTICS (TA = 25°C)
DERATING FACTOR OF FORWARD BIAS
SAFE OPERATING AREA
FORWARD BIAS SAFE OPERATING AREA
1000
100
10
120
100
80
I
D(pulse)
D(DC)
I
60
40
1
Single Pulse
Mounted on a glass epoxy board of
25.4 mm x 25.4 mm x 0.8 mm
20
0.1
0
0
20 40 60 80 100 120 140 160
0.01
0.1
1
10
100
VDS - Drain to Source Voltage - V
TA - Ambient Temperature - °C
TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH
1000
100
10
Rth(ch-A) = 83.3°C/Wi
1
Rth(ch-C) = 1.5°C/Wi
0.1
0.01
Single pulse
th(ch-A): Mounted on a glass epoxy board of 25.4 mm x 25.4 mm x 0.8 mm
R
100 μ
1 m
10 m
100 m
1
10
100
1000
PW - Pulse Width - s
DRAIN CURRENT vs.
DRAIN TO SOURCE VOLTAGE
FORWARD TRANSFER CHARACTERISTICS
100
200
VGS = 10 V
80
60
40
20
0
T
ch = −55°C
150
100
50
25°C
75°C
125°C
4.5 V
V
DS = 10 V
Pulsed
Pulsed
0.8
0
0
0.2
0.4
0.6
1
0
1
2
3
4
5
VDS - Drain to Source Voltage - V
VGS - Gate to Source Voltage - V
3
Data Sheet G17954EJ1V0DS
μ PA2723UT1A
GATE TO SOURCE CUT-OFF VOLTAGE vs.
CHANNEL TEMPERATURE
FORWARD TRANSFER ADMITTANCE vs.
DRAIN CURRENT
2.5
100
10
1
T
ch = −55°C
25°C
75°C
2
1.5
1
125°C
0.5
0
V
DS = 10 V
V
DS = 10 V
= 1 mA
Pulsed
I
D
-75
-25
25
75
125
175
0.1
1
10
100
ID - Drain Current - A
Tch - Channel Temperature - °C
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
DRAIN CURRENT
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
GATE TO SOURCE VOLTAGE
8
15
I
D
= 17 A
Pulsed
6
4
2
0
10
5
V
1
GS = 4.5 V
10 V
Pulsed
1000
0
0.1
10
100
0
5
10
15
20
ID - Drain Current - A
VGS - Gate to Source Voltage - V
DRAIN TO SOURCE ON-STATE RESISTANCE vs.
CHANNEL TEMPERATURE
CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE
100000
8
I
D
= 17 A
Pulsed
6
4
2
0
10000
1000
100
C
iss
V
GS = 4.5 V
C
oss
rss
10 V
C
V
GS = 0 V
f = 1MHz
0.1
1
10
100
-75
-25
25
75
125
175
VDS - Drain to Source Voltage - V
Tch - Channel Temperature - °C
4
Data Sheet G17954EJ1V0DS
μ PA2723UT1A
DYNAMIC INPUT/OUTPUT CHARACTERISTICS
SOURCE TO DRAIN DIODE FORWARD VOLTAGE
6
4
2
0
1000
V
DD = 24 V
15 V
100
10
6 V
0 V
V
GS = 10 V
1
0.1
0.01
I
D
= 33 A
Pulsed
1.2
0
20
40
60
80
0
0.2
0.4
0.6
0.8
1
QG - Gate Charge - nC
VF(S-D) - Source to Drain Voltage - V
ORDERING INFORMATION
PART NUMBER
LEAD PLATING
Sn-Bi
PACKING
PACKAGE
μ PA2723UT1A-E1-AZ Note
μ PA2723UT1A-E2-AZ Note
μ PA2723UT1A-E1-AY Note
μ PA2723UT1A-E2-AY Note
8-pin HVSON
0.10 g TYP.
Tape 3000 p/reel
Pure Sn
Note Pb-free (This product does not contain Pb in the external electrode.)
5
Data Sheet G17954EJ1V0DS
μ PA2723UT1A
•
The information in this document is current as of April, 2007. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
•
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•
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M8E 02. 11-1
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