UPD161401 [NEC]
256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM; 256色1/ 80 DUTY LCD控制器/驱动器，片上RAM
| 型号： | UPD161401 |
| 厂家： | 
NEC |
| 描述： | 256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM |
| 文件： | 总124页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD161401
256-COLOR, 1/80-DUTY LCD CONTROLLER/DRIVER WITH ON-CHIP RAM
DESCRIPTION
The µPD161401 is an LCD controller/driver with RAM and is capable of driving a full-dot LCD. It can display 256
colors on an RGB-STN color LCD. This LCD controller/driver can drive a full-dot LCD of up to 101 × 80 pixel with a
single chip.
FEATURES
• LCD driver with on-chip display RAM
• Logic power supply operation from +1.8 V to +3.6 V
• Internal booster circuit: x 2 to x 7 selectable
• Dot display RAM: (101 x 80) x 8 bits
• 8 (R, G)/4 (B) grayscales selectable from 17 levels
• Full-dot output: 303 segment lines and 80 common lines
• Serial interface (SI, SCL) or 8-/16-bit parallel data input (i80 or M68 system interface)
• On-chip voltage divider resistor
• Selectable bias value: 1/9 to 1/5
• Selectable duty ratio: 1/80, 1/72 and 1/64 (main duty)
• On-chip oscillator
ORDERING INFORMATION
Part Number
Package
µPD161401W/P
Wafer/Chip (supports COF)
Remark Purchasing the above chip entail the exchange of documents such as a separate memorandum or product
quality, so please contact one of our sales representatives.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No.
Data Published June 2002 NS CP(K)
Printed in Japan
S15726EJ2V0DS00 (2nd Edition)
The mark ★ shows major revised points.
2001
©
µPD161401
CONTENT
1. BLOCK DIAGRAM ...................................................................................................................................5
2. PIN CONFIGURATION (Pad Layout) .....................................................................................................6
3. PIN FUNCTIONS......................................................................................................................................12
3.1 Power Supply Pins...........................................................................................................................................12
3.2 Logic Circuit Pins ............................................................................................................................................13
3.3 Driver Pins........................................................................................................................................................15
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS....................................16
5. FUNCTIONAL DESCRIPTION.................................................................................................................17
5.1 CPU Interface ....................................................................................................................................................17
5.1.1 Selecting interface type...........................................................................................................................17
5.1.2 Parallel interface.....................................................................................................................................17
5.1.3 Serial interface........................................................................................................................................19
5.1.4 Chip select..............................................................................................................................................19
5.1.5 Accessing display data RAM and internal registers................................................................................19
5.2 Display Data RAM ............................................................................................................................................21
5.2.1 Display data RAM...................................................................................................................................21
5.2.2 X address circuit .....................................................................................................................................21
5.2.3 Y address circuit .....................................................................................................................................23
5.2.4 Column address circuit ...........................................................................................................................24
5.2.5 Common scan circuit ..............................................................................................................................25
5.2.6 Display data latch circuit .........................................................................................................................28
5.2.7 Arbitrary address area access (window access mode (WAS)) ...............................................................28
5.3 Screen Processing...........................................................................................................................................30
5.3.1 Blink/reverse display circuit.....................................................................................................................30
5.3.2 Example of setting blink area..................................................................................................................33
5.4 Oscillator ..........................................................................................................................................................33
5.5 Display Timing Generator ...............................................................................................................................35
5.6 Power Supply Circuit.......................................................................................................................................37
5.6.1 Power supply circuit................................................................................................................................37
5.6.2 Booster circuit.........................................................................................................................................37
5.6.3 Voltage regulator circuit ..........................................................................................................................39
5.6.4 Level voltage control by operational amplifier.........................................................................................42
5.6.5 Application example of power supply circuit ...........................................................................................44
5.7 Driving LCD ......................................................................................................................................................48
5.7.1 Full-dot pulse modulation........................................................................................................................48
2
Data Sheet S15726EJ2V0DS
µPD161401
5.7.2 Grayscale palette....................................................................................................................................51
5.7.3 Setting of display size .............................................................................................................................52
5.7.4 Setting of LCD N-line inversion and M-line shift......................................................................................52
5.7.5 Reverse driving between frames ............................................................................................................54
5.8 Display Mode....................................................................................................................................................55
5.8.1 Selecting display mode...........................................................................................................................55
5.8.2 Screen scrolling .......................................................................................................................................58
5.8.3 Scroll setting examples............................................................................................................................59
5.9 Reset.................................................................................................................................................................61
6. COMMANDS............................................................................................................................................63
6.1 Control Register 1 (R0)....................................................................................................................................64
6.2 Control Register 2 (R1)....................................................................................................................................65
6.3 Reset Command Register (R3) .......................................................................................................................66
6.4 X Address Register (R4)..................................................................................................................................66
6.5 Y Address Register (R5)..................................................................................................................................66
6.6 MIN.·X Address Register (R7) .........................................................................................................................67
6.7 MAX.·X Address Register (R8)........................................................................................................................67
6.8 MIN.·Y Address Register (R9) .........................................................................................................................67
6.9 MAX.·Y Address Register (R10)......................................................................................................................68
6.10 Display Memory Access Register (R12).......................................................................................................68
6.11 Main Duty Setting Register (R14) .................................................................................................................69
6.12 Main Duty N-line Inversion Register (R15)...................................................................................................69
6.13 Main Duty M-line Shift Register (R16) ..........................................................................................................70
6.14 Sub-duty Setting Register (R17)...................................................................................................................71
6.15 Sub-duty N-line Inversion Register (R18) ....................................................................................................72
6.16 Sub-duty M-line Shift Register (R19)............................................................................................................73
6.17 COM Scanning Address Setting Register (R21)..........................................................................................74
6.18 Sub-duty Start Address Register (R22)........................................................................................................77
6.19 Scroll Fixed Area Position Register (R23) ...................................................................................................78
6.20 Scroll Fixed Area Width Register (R27) .......................................................................................................78
6.21 Scroll Step Number Register (R31) ..............................................................................................................79
6.22 Blink/Reverse Setting Register (R37)...........................................................................................................80
6.23 Complementary Color Blink X Address Register (R38)..............................................................................80
6.24 Complementary Color Blink Start Line Address Register (R39)................................................................81
6.25 Complementary Color Blink End Line Address Register (R40) .................................................................81
6.26 Complementary Color Blink Data Memory Register (R41) .........................................................................82
6.27 Specified Color Blink X Address Register (R42).........................................................................................82
6.28 Specified Color Blink Start Line Address Register (R43)...........................................................................83
6.29 Specified Color Blink End Line Address Register (R44) ............................................................................83
6.30 Specified Color Blink Data Memory Register (R45) ....................................................................................84
6.31 Specified Color Setting Register (R46) ........................................................................................................84
3
Data Sheet S15726EJ2V0DS
µPD161401
6.32 Reverse X Address Register (R47)...............................................................................................................84
6.33 Reverse Start Line Address Register (R48).................................................................................................85
6.34 Reverse End Line Address Register (R49) ..................................................................................................85
6.35 Reverse Data Memory Access Register (R50).............................................................................................86
6.36 Power System Control Register 1 (R52) ......................................................................................................87
6.37 Power System Control Register 2 (R53) ......................................................................................................88
6.38 Power System Control Register 3 (R54) ......................................................................................................89
6.39 Power System Control Register 4 (R55) ......................................................................................................90
6.40 Power System Control Register 5 (R56) ......................................................................................................91
6.41 Main Electronic Volume Register (R57) .......................................................................................................92
6.42 Sub-electronic Volume Register (R58).........................................................................................................92
6.43 RAM Test Mode Setting Register (R61)........................................................................................................93
6.44 Driving Mode Select Register (R64) .............................................................................................................93
6.45 Main R Grayscale Data Registers (R65 to R72) ...........................................................................................94
6.46 Main G Grayscale Data Registers (R73 to R80)...........................................................................................95
6.47 Main B Grayscale Data Registers (R81 to R84) ...........................................................................................96
6.48 Sub R Grayscale Data Registers (R85 to R92).............................................................................................97
6.49 Sub G Grayscale Data Registers (R93 to R100) ..........................................................................................98
6.50 Sub B Grayscale Data Registers (R101 to R104).........................................................................................99
7. µPD161401 REGISTER LIST ................................................................................................................100
8. POWER SEQUENCE.............................................................................................................................102
8.1 Power ON Sequence (with Internal Power Supply, Power ON → Display ON) ........................................103
8.2 Power OFF Sequence (with Internal Power Supply) ...................................................................................105
8.3 Power ON Sequence (with External Driving Power Supply, Power ON → Display ON)...........................106
8.4 Power OFF Sequence (with External Driving Power Supply).....................................................................107
8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF .................................................................108
8.6 Flow of VOUT and VLCD Voltages in Display Output and HALT/Standby Modes.........................................109
9. USING RAM TEST MODE.....................................................................................................................110
10. ELECTRICAL SPECIFICATIONS........................................................................................................111
11. CPU INTERFACE (Reference Example)............................................................................................120
4
Data Sheet S15726EJ2V0DS
µPD161401
1. BLOCK DIAGRAM
SEG
1
SEG303
O
1
O
80
Common driver
Segment driver
Common timing
generator
Segment gray-scale control
IFM0
IFM1
/CS1
CS2
/RD(E)
/WR(R,/W)
Display data latch
Graphic control
D15 to D8
D7(SI)
D6(SCL)
D5 to D0
RS
I/O
/DISP
buffer
Display data RAM
101 x 8 x 80 bits
Blink & Inverse data RAM
303 bits
TOUT15 to TOUT0
M,/S
FR
FRSYNC
Logic Control Circuit
DOF
TSTRTST
TSTVIHL
Data
control
Address
control
Data
register
TPWR0, TPWR1
Gray-scale
control
Register
Command
decorder
V
DD1
OSCIN1
OSCIN2
V
DD2
Oscillator
circuit
OSCOUT
OSCSYNC
Timing generator
VSS
+
-
C1 , C1
D/A
converter
Op amp.
LCD voltage generator
DC/DC
converter
+
-
C5 , C5
AMPOUTM
AMPOUTS
VOUT2
VR
VLCD
VLC1
VLC2
VLC3 VLC4
VOUT
VRS
IRS
Remark /xxx is an active-low signal.
5
Data Sheet S15726EJ2V0DS
µPD161401
2. PIN CONFIGURATION (Pad Layout)
• µPD161401W/P
Chip size: 2.57 x 16.05 mm2
Chip thickness: 485 µm (TYP.)
D
u
D
u
672
m
m
y
m
m
y
713
M1
O
80
O
41
671
Dummy
1
SEG303
SEG302
SEG301
Y
SEG194
SEG193
Dummy
SEG192
SEG191
X
I/O side
SEG
SEG
SEG
3
2
1
Dummy
317
360
D
O
1
D O40
M2
u
u
m
m
y
m
m
y
359
318
6
Data Sheet S15726EJ2V0DS
µPD161401
Details of pad and alignment mark
Pad type
A type
Pad size (Al): 39 x 71 µm2 TYP.
Bump size : 33 x 65 µm2 TYP.
Bump height: 17 µm TYP.
B type
Pad size (Al): 93 x 71 µm2 TYP.
Bump size: 87 x 65 µm2 TYP.
Bump height: 17 µm TYP.
Alignment mark (unit: µm)
X
Y
M1
M2
−1140.00
−1140.00
7560.00
−7560.00
Shape of mark (unit: µm)
Mark center
80φ (M1)
75φ (M2)
7
Data Sheet S15726EJ2V0DS
µPD161401
Table 2−1 Pad Layout (1/4)
µ
µ
µ
Pad Layout [ m]
Pad Layout [ m]
Pad Layout [ m]
Pad
No.
Pad Name
Pad
Pad
No.
Pad Name
Pad
Pad
No.
Pad Name
Pad
Type
X
Y
Type
X
Y
Type
X
Y
1 DUMMY
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
7230.00
7105.00
7060.00
7015.00
6970.00
6925.00
6880.00
6835.00
6790.00
6745.00
6700.00
6655.00
6610.00
6565.00
6520.00
6475.00
6430.00
6385.00
6340.00
6295.00
6250.00
6205.00
6160.00
6115.00
6070.00
6025.00
5980.00
5935.00
5890.00
5845.00
5800.00
5755.00
5710.00
5665.00
5620.00
5575.00
5530.00
5485.00
5440.00
5395.00
5350.00
5305.00
5260.00
5215.00
5170.00
5125.00
5080.00
5035.00
4990.00
4945.00
4900.00
4855.00
4810.00
4765.00
44720.00
4675.00
4630.00
4585.00
4540.00
4495.00
4450.00
4405.00
4360.00
4315.00
4270.00
4225.00
4180.00
4135.00
4090.00
4045.00
71 VSS
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
4000.00
3955.00
3910.00
3865.00
3820.00
3775.00
3730.00
3685.00
3640.00
3595.00
3550.00
3505.00
3460.00
3415.00
3370.00
3325.00
3280.00
3235.00
3190.00
3145.00
3100.00
3055.00
3010.00
2965.00
2920.00
2875.00
2830.00
2785.00
2740.00
2695.00
2650.00
2605.00
2560.00
2515.00
2470.00
2425.00
2380.00
2335.00
2290.00
2245.00
2200.00
2155.00
2110.00
2065.00
2020.00
1975.00
1930.00
1885.00
1840.00
1795.00
1750.00
1705.00
1660.00
1615.00
1570.00
1525.00
1480.00
1435.00
1390.00
1345.00
1300.00
1255.00
1210.00
1165.00
1120.00
1075.00
1030.00
985.00
141 D11
142 D11
143 D10
144 D10
145 D10
146 VSS
147 VSS
148 VSS
149 D9
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
850.00
805.00
2 VSS
3 VSS
72 VSS
73 VSS
760.00
4 VSS
74 M, /S
75 M, /S
76 M, /S
77 VDD1
78 VDD1
79 VDD1
80 IFM0
81 IFM0
82 IFM0
83 VSS
715.00
5 VOUT
6 VOUT
7 VOUT
8 VOUT2
9 VOUT2
10 VOUT2
11 VSS
12 VSS
13 VSS
670.00
625.00
580.00
535.00
490.00
150 D9
445.00
151 D9
400.00
152 D8
355.00
153 D8
310.00
−
14 C5
84 VSS
154 D8
265.00
−
15 C5
85 VSS
155 VSS
156 VSS
157 VSS
158 D7
220.00
−
16 C5
86 IFM1
87 IFM1
88 IFM1
89 VDD1
90 VDD1
91 VDD1
92 IRS
175.00
17 C5+
18 C5+
19 C5+
130.00
85.00
159 D7
40.00
−
20 C4
160 D7
-5.00
−
21 C4
161 D6
-50.00
−
22 C4
162 D6
-95.00
23 C4+
24 C4+
25 C4+
93 IRS
163 D6
-140.00
-185.00
-230.00
-275.00
-320.00
-365.00
-410.00
-455.00
-500.00
-545.00
-590.00
-635.00
-680.00
-725.00
-770.00
-815.00
-860.00
-905.00
-950.00
-995.00
-1040.00
-1085.00
-1130.00
-1175.00
-1220.00
-1265.00
-1310.00
-1355.00
-1400.00
-1445.00
-1490.00
-1535.00
-1580.00
-1625.00
-1670.00
-1715.00
-1760.00
-1805.00
-1850.00
-1895.00
-1940.00
-1985.00
-2030.00
-2075.00
-2120.00
-2165.00
-2210.00
-2255.00
94 IRS
164 D5
95 VSS
165 D5
−
26 C3
96 VSS
166 D5
−
27 C3
97 VSS
167 VSS
168 VSS
169 VSS
170 D4
−
28 C3
98 /CS1
29 C3+
30 C3+
31 C3+
99 /CS1
100 /CS1
101 CS2
102 CS2
103 CS2
104 VDD1
105 VDD1
106 VDD1
107 /DISP
108 /DISP
109 /DISP
110 RS
171 D4
−
32 C2
172 D4
−
33 C2
173 D3
−
34 C2
174 D3
35 C2+
36 C2+
37 C2+
175 D3
176 D2
177 D2
−
38 C1
178 D2
−
39 C1
179 VSS
180 VSS
181 VSS
182 D1
−
40 C1
41 C1+
111 RS
42 C1+
112 RS
43 C1+
113 VSS
114 VSS
115 VSS
116 /WR (R, /W)
117 /WR (R, /W)
118 /WR (R, /W)
119 /RD (E)
120 /RD (E)
121 /RD (E)
122 VDD1
123 VDD1
124 VDD1
125 D15
126 D15
127 D15
128 D14
129 D14
130 D14
131 D13
132 D13
133 D13
134 VSS
135 VSS
136 VSS
137 D12
138 D12
139 D12
140 D11
183 D1
44 VSS
184 D1
45 VSS
185 D0
46 VSS
186 D0
47 TPWR1
48 TPWR1
49 TPWR1
50 TPWR0
51 TPWR0
52 TPWR0
53 VRS
54 VRS
55 VRS
56 VSS
187 D0
188 VSS
189 VSS
190 VSS
191 FRSYNC
192 FRSYNC
193 FRSYNC
194 FR
195 FR
196 FR
57 VSS
197 DOF
198 DOF
199 DOF
200 OSCSYNC
201 OSCSYNC
202 OSCSYNC
203 VSS
204 VSS
205 VSS
206 OSCIN1
207 OSCIN1
208 OSCIN1
209 VSS
210 VSS
58 VSS
59 VSS
60 VSS
61 VSS
62 VDD2
63 VDD2
64 VDD2
65 VDD1
66 VDD1
67 VDD1
68 VSS
69 VSS
70 VSS
940.00
895.00
8
Data Sheet S15726EJ2V0DS
µPD161401
Table 2−1 Pad Layout (2/4)
µ
µ
µ
Pad Layout [ m]
Pad Layout [ m]
Pad Layout [ m]
Pad
No.
Pad Name
Pad
Pad
No.
Pad Name
Pad
Pad
Pad Name
Pad
Type
X
Y
Type
X
Y
No.
Type
X
Y
211 VSS
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-2300.00
-2345.00
-2390.00
-2435.00
-2480.00
-2525.00
-2570.00
-2615.00
-2660.00
-2705.00
-2750.00
-2795.00
-2840.00
-2885.00
-2930.00
-2975.00
-3020.00
-3065.00
-3110.00
-3155.00
-3200.00
-3245.00
-3290.00
-3335.00
-3380.00
-3425.00
-3470.00
-3515.00
-3560.00
-3605.00
-3650.00
-3695.00
-3740.00
-3785.00
-3830.00
-3875.00
-3920.00
-3965.00
-4010.00
-4055.00
-4100.00
-4145.00
-4190.00
-4235.00
-4280.00
-4325.00
-4370.00
-4415.00
-4460.00
-4505.00
-4550.00
-4595.00
-4640.00
-4685.00
-4730.00
-4775.00
-4820.00
-4865.00
-4910.00
-4955.00
-5000.00
-5045.00
-5090.00
-5135.00
-5180.00
-5225.00
-5270.00
-5315.00
-5360.00
-5405.00
281 VSS
282 VSS
283 VSS
284 VSS
285 VSS
286 VSS
287 VR
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1144.50
-1060.00
-935.00
-890.00
-845.00
-800.00
-755.00
-710.00
-665.00
-620.00
-575.00
-530.00
-485.00
-440.00
-395.00
-350.00
-305.00
-260.00
-215.00
-170.00
-125.00
-80.00
-5450.00
-5495.00
-5540.00
-5585.00
-5630.00
-5675.00
-5720.00
-5765.00
-5810.00
-5855.00
-5900.00
-5945.00
-5990.00
-6035.00
-6080.00
-6125.00
-6170.00
-6215.00
-6260.00
-6305.00
-6350.00
-6395.00
-6440.00
-6485.00
-6530.00
-6575.00
-6620.00
-6665.00
-6710.00
-6755.00
-6800.00
-6845.00
-6890.00
-6935.00
-6980.00
-7025.00
-7150.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
351 O8
352 O7
353 O6
354 O5
355 O4
356 O3
357 O2
358 O1
A
A
A
A
A
A
A
A
B
B
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
505.00
550.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7773.00
-7080.00
-6955.00
-6910.00
-6865.00
-6820.00
-6775.00
-6730.00
-6685.00
-6640.00
-6595.00
-6550.00
-6505.00
-6460.00
-6415.00
-6370.00
-6325.00
-6280.00
-6235.00
-6190.00
-6145.00
-6100.00
-6055.00
-6010.00
-5965.00
-5920.00
-5875.00
-5830.00
-5785.00
-5740.00
-5695.00
-5650.00
-5605.00
-5560.00
-5515.00
-5470.00
-5425.00
-5380.00
-5335.00
-5290.00
-5245.00
-5200.00
-5155.00
-5110.00
-5065.00
-5020.00
-4975.00
-4930.00
-4885.00
-4840.00
-4795.00
-4750.00
-4705.00
-4660.00
-4615.00
-4570.00
-4525.00
-4480.00
-4435.00
-4390.00
-4345.00
-4300.00
212 OSCIN2
213 OSCIN2
214 OSCIN2
215 VSS
595.00
640.00
685.00
216 VSS
730.00
217 VSS
775.00
218 OSCOUT
219 OSCOUT
220 OSCOUT
221 VSS
288 VR
820.00
289 VR
359 DUMMY
360 DUMMY
361 SEG1
362 SEG2
363 SEG3
364 SEG4
365 SEG5
366 SEG6
367 SEG7
368 SEG8
369 SEG9
370 SEG10
371 SEG11
372 SEG12
373 SEG13
374 SEG14
375 SEG15
376 SEG16
377 SEG17
378 SEG18
379 SEG19
380 SEG20
381 SEG21
382 SEG22
383 SEG23
384 SEG24
385 SEG25
386 SEG26
387 SEG27
388 SEG28
389 SEG29
390 SEG30
391 SEG31
392 SEG32
393 SEG33
394 SEG34
395 SEG35
396 SEG36
397 SEG37
398 SEG38
399 SEG39
400 SEG40
401 SEG41
402 SEG42
403 SEG43
404 SEG44
405 SEG45
406 SEG46
407 SEG47
408 SEG48
409 SEG49
410 SEG50
411 SEG51
412 SEG52
413 SEG53
414 SEG54
415 SEG55
416 SEG56
417 SEG57
418 SEG58
419 SEG59
420 SEG60
945.00
290 AMPOUTM
291 AMPOUTM
292 AMPOUTM
293 VSS
294 VSS
295 VSS
296 AMPOUTS
297 AMPOUTS
298 AMPOUTS
299 VSS
300 VSS
301 VSS
302 VLCD
303 VLCD
304 VLCD
305 VLC1
306 VLC1
307 VLC1
308 VLC2
309 VLC2
310 VLC2
311 VLC3
312 VLC3
313 VLC3
314 VLC4
315 VLC4
316 VLC4
317 DUMMY
318 DUMMY
319 O40
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
222 VSS
223 VSS
224 TSTRTST
225 TSTRTST
226 TSTRTST
227 TSTVIHL
228 TSTVIHL
229 TSTVIHL
230 TOUT15
231 TOUT15
232 TOUT15
233 TOUT14
234 TOUT14
235 TOUT14
236 TOUT13
237 TOUT13
238 TOUT13
239 TOUT12
240 TOUT12
241 TOUT12
242 TOUT11
243 TOUT11
244 TOUT11
245 TOUT10
246 TOUT10
247 TOUT10
248 TOUT9
249 TOUT9
250 TOUT9
251 TOUT8
252 TOUT8
253 TOUT8
254 TOUT7
255 TOUT7
256 TOUT7
257 TOUT6
258 TOUT6
259 TOUT6
260 TOUT5
261 TOUT5
262 TOUT5
263 TOUT4
264 TOUT4
265 TOUT4
266 TOUT3
267 TOUT3
268 TOUT3
269 TOUT2
270 TOUT2
271 TOUT2
272 TOUT1
273 TOUT1
274 TOUT1
275 TOUT0
276 TOUT0
277 TOUT0
278 VSS
320 O39
321 O38
322 O37
323 O36
324 O35
325 O34
326 O33
327 O32
328 O31
329 O30
330 O29
331 O28
332 O27
333 O26
334 O25
335 O24
336 O23
337 O22
338 O21
339 O20
-35.00
340 O19
10.00
341 O18
55.00
342 O17
100.00
343 O16
145.00
344 O15
190.00
345 O14
235.00
346 O13
280.00
347 O12
325.00
348 O11
370.00
279 VSS
280 VSS
349 O10
350 O9
415.00
460.00
9
Data Sheet S15726EJ2V0DS
µPD161401
Table 2−1 Pad Layout (3/4)
µ
µ
µ
Pad Layout [ m]
Pad Layout [ m]
Pad Layout [ m]
Pad
No.
Pad Name
Pad
Pad
No.
Pad Name
Pad
Pad
No.
Pad Name
Pad
Type
X
Y
Type
X
Y
Type
X
Y
421 SEG61
422 SEG62
423 SEG63
424 SEG64
425 SEG65
426 SEG66
427 SEG67
428 SEG68
429 SEG69
430 SEG70
431 SEG71
432 SEG72
433 SEG73
434 SEG74
435 SEG75
436 SEG76
437 SEG77
438 SEG78
439 SEG79
440 SEG80
441 SEG81
442 SEG82
443 SEG83
444 SEG84
445 SEG85
446 SEG86
447 SEG87
448 SEG88
449 SEG89
450 SEG90
451 SEG91
452 SEG92
453 SEG93
454 SEG94
455 SEG95
456 SEG96
457 SEG97
458 SEG98
459 SEG99
460 SEG100
461 SEG101
462 SEG102
463 SEG103
464 SEG104
465 SEG105
466 SEG106
467 SEG107
468 SEG108
469 SEG109
470 SEG110
471 SEG111
472 SEG112
473 SEG113
474 SEG114
475 SEG115
476 SEG116
477 SEG117
478 SEG118
479 SEG119
480 SEG120
481 SEG121
482 SEG122
483 SEG123
484 SEG124
485 SEG125
486 SEG126
487 SEG127
488 SEG128
489 SEG129
490 SEG130
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
-4255.00
-4210.00
-4165.00
-4120.00
-4075.00
-4030.00
-3985.00
-3940.00
-3895.00
-3850.00
-3805.00
-3760.00
-3715.00
-3670.00
-3625.00
-3580.00
-3535.00
-3490.00
-3445.00
-3400.00
-3355.00
-3310.00
-3265.00
-3220.00
-3175.00
-3130.00
-3085.00
-3040.00
-2995.00
-2950.00
-2905.00
-2860.00
-2815.00
-2770.00
-2725.00
-2680.00
-2635.00
-2590.00
-2545.00
-2500.00
-2455.00
-2410.00
-2365.00
-2320.00
-2275.00
-2230.00
-2185.00
-2140.00
-2095.00
-2050.00
-2005.00
-1960.00
-1915.00
-1870.00
-1825.00
-1780.00
-1735.00
-1690.00
-1645.00
-1600.00
-1555.00
-1510.00
-1465.00
-1420.00
-1375.00
-1330.00
1285.00
-1240.00
-1195.00
-1150.00
491 SEG131
492 SEG132
493 SEG133
494 SEG134
495 SEG135
496 SEG136
497 SEG137
498 SEG138
499 SEG139
500 SEG140
501 SEG141
502 SEG142
503 SEG143
504 SEG144
505 SEG145
506 SEG146
507 SEG147
508 SEG148
509 SEG149
510 SEG150
511 SEG151
512 SEG152
513 SEG153
514 SEG154
515 SEG155
516 SEG156
517 SEG157
518 SEG158
519 SEG159
520 SEG160
521 SEG161
522 SEG162
523 SEG163
524 SEG164
525 SEG165
526 SEG166
527 SEG167
528 SEG168
529 SEG169
530 SEG170
531 SEG171
532 SEG172
533 SEG173
534 SEG174
535 SEG175
536 SEG176
537 SEG177
538 SEG178
539 SEG179
540 SEG180
541 SEG181
542 SEG182
543 SEG183
544 SEG184
545 SEG185
546 SEG186
547 SEG187
548 SEG188
549 SEG189
550 SEG190
551 SEG191
552 SEG192
553 DUMMY
554 DUMMY
555 DUMMY
556 DUMMY
557 DUMMY
558 DUMMY
559 DUMMY
560 SEG193
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
-1105.00
-1060.00
-1015.00
-970.00
-925.00
-880.00
-835.00
-790.00
-745.00
-700.00
-655.00
-610.00
-565.00
-520.00
-475.00
-430.00
-385.00
-340.00
-295.00
-250.00
-205.00
-160.00
-115.00
-70.00
561 SEG194
562 SEG195
563 SEG196
564 SEG197
565 SEG198
566 SEG199
567 SEG200
568 SEG201
569 SEG202
570 SEG203
571 SEG204
572 SEG205
573 SEG206
574 SEG207
575 SEG208
576 SEG209
577 SEG210
578 SEG211
579 SEG212
580 SEG213
581 SEG214
582 SEG215
583 SEG216
584 SEG217
585 SEG218
586 SEG219
587 SEG220
588 SEG221
589 SEG222
590 SEG223
591 SEG224
592 SEG225
593 SEG226
594 SEG227
595 SEG228
596 SEG229
597 SEG230
598 SEG231
599 SEG232
600 SEG233
601 SEG234
602 SEG235
603 SEG236
604 SEG237
605 SEG238
606 SEG239
607 SEG240
608 SEG241
609 SEG242
610 SEG243
611 SEG244
612 SEG245
613 SEG246
614 SEG247
615 SEG248
616 SEG249
617 SEG250
618 SEG251
619 SEG252
620 SEG253
621 SEG254
622 SEG255
623 SEG256
624 SEG257
625 SEG258
626 SEG259
627 SEG260
628 SEG261
629 SEG262
630 SEG263
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
2045.00
2090.00
2135.00
2180.00
2225.00
2270.00
2315.00
2360.00
2405.00
2450.00
2495.00
2540.00
2585.00
2630.00
2675.00
2720.00
2765.00
2810.00
2855.00
2900.00
2945.00
2990.00
3035.00
3080.00
3125.00
3170.00
3215.00
3260.00
3305.00
3350.00
3395.00
3440.00
3485.00
3530.00
3575.00
3620.00
3665.00
3710.00
3755.00
3800.00
3845.00
3890.00
3935.00
3980.00
4025.00
4070.00
4115.00
4160.00
4205.00
4250.00
4295.00
4340.00
4385.00
4430.00
4475.00
4520.00
4565.00
4610.00
4655.00
4700.00
4745.00
4790.00
4835.00
4880.00
4925.00
4970.00
5015.00
5060.00
5105.00
5150.00
-25.00
20.00
65.00
110.00
155.00
200.00
245.00
290.00
335.00
380.00
425.00
470.00
515.00
560.00
605.00
650.00
695.00
740.00
785.00
830.00
875.00
920.00
965.00
1010.00
1055.00
1100.00
1145.00
1190.00
1235.00
1280.00
1325.00
1370.00
1415.00
1460.00
1505.00
1550.00
1595.00
1640.00
1685.00
1730.00
1775.00
1820.00
1865.00
1910.00
1955.00
2000.00
10
Data Sheet S15726EJ2V0DS
µPD161401
Table 2−1 Pad Layout (4/4)
µ
µ
Pad Layout [ m]
Pad Layout [ m]
Pad
No.
Pad Name
Pad
Pad
No.
Pad Name
Pad
Type
X
Y
Type
X
Y
631 SEG264
632 SEG265
633 SEG266
634 SEG267
635 SEG268
636 SEG269
637 SEG270
638 SEG271
639 SEG272
640 SEG273
641 SEG274
642 SEG275
643 SEG276
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
5195.00
5240.00
5285.00
5330.00
5375.00
5420.00
5465.00
5510.00
5555.00
5600.00
5645.00
5690.00
5735.00
701 O69
702 O70
703 O71
704 O72
705 O73
706 O74
707 O75
708 O76
709 O77
710 O78
711 O79
712 O80
713 DUMMY
A
A
A
A
A
A
A
A
A
A
A
A
B
-435.00
-480.00
-525.00
-570.00
-615.00
-660.00
-705.00
-750.00
-795.00
-840.00
-885.00
-930.00
-1055.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
644 SEG277
645 SEG278
646 SEG279
647 SEG280
648 SEG281
649 SEG282
650 SEG283
651 SEG284
652 SEG285
653 SEG286
654 SEG287
655 SEG288
656 SEG289
657 SEG290
658 SEG291
659 SEG292
660 SEG293
661 SEG294
662 SEG295
663 SEG296
664 SEG297
665 SEG298
666 SEG299
667 SEG300
668 SEG301
669 SEG302
670 SEG303
671 DUMMY
672 DUMMY
673 O41
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
1033.00
950.00
825.00
780.00
735.00
690.00
645.00
600.00
555.00
510.00
465.00
420.00
375.00
330.00
285.00
240.00
195.00
150.00
105.00
60.00
5780.00
5825.00
5870.00
5915.00
5960.00
6005.00
6050.00
6095.00
6140.00
6185.00
6230.00
6275.00
6320.00
6365.00
6410.00
6455.00
6500.00
6545.00
6590.00
6635.00
6680.00
6725.00
6770.00
6815.00
6860.00
6905.00
6950.00
7075.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
7773.00
674 O42
675 O43
676 O44
677 O45
678 O46
679 O47
680 O48
681 O49
682 O50
683 O51
684 O52
685 O53
686 O54
687 O55
688 O56
689 O57
690 O58
691 O59
15.00
692 O60
-30.00
693 O61
-75.00
694 O62
-120.00
-165.00
-210.00
-255.00
-300.00
-345.00
-390.00
695 O63
696 O64
697 O65
698 O66
699 O67
700 O68
11
Data Sheet S15726EJ2V0DS
µPD161401
3. PIN FUNCTIONS
3.1 Power Supply Pins
Symbol
VDD1
Pin Name
Pin No.
I/O
Description
Logic power supply
65 to 67, 77 to 79,
89 to 91,104 to 106,
122 to 124
−
Supplies power to the logic circuit.
VDD2
Booster circuit power
supply
62 to 64
−
−
Supplies power to the booster circuit.
VSS
Logic and driver
ground pin
2 to 4, 11 to 13, 44 to 46,
56 to 61, 68 to 73,
83 to 85, 95 to 97,
113 to 115, 134 to 136,
146 to 148, 155 to 157,
167 to 169, 179 to 181,
188 to 190, 203 to 205,
209 to 211, 215 to 217,
221 to 223, 278 to 286,
293 to 295, 299 to 301
5 to 7,
Ground pin for the logic and driver circuits.
VOUT,
VOUT2
Driver power supply
−
Supply power to the driver (output pins of the internal
booster circuit). Connect a 1 µF capacitor between GND
and these pins. When the internal booster circuit is not
used, the driver power can be directly input to the VOUT pin.
At this time, leave VOUT2 open.
8 to 10
VLCD,
Driver reference
power supply
302 to 304,
305 to 316
−
−
Supply the reference power for driving the LCD. Connect a
capacitor between GND and these pins when an internal
bias is selected.
VLC1 to VLC4
+
−
−
−
−
−
C1 , C1
Booster capacitor
connection pin
43 to 14
These pins are used to connect capacitors for the internal
booster circuit. Connect a 1 µF capacitor between the
corresponding (+) and (−) pins.
+
C2 , C2
+
C3 , C3
+
C4 , C4
+
C5 , C5
12
Data Sheet S15726EJ2V0DS
µPD161401
3.2 Logic Circuit Pins (1/3)
Symbol Pin Name
/CS1, Chip select
Pin No.
I/O
Description
98 to 100,
101 to 103
Input
These pins are chip select signal pins.
CS2
When /CS1 = L (CS2 = H), the chip is active, and data/command
can be input or output and I/O manipulated.
/RD (E)
Read (enable)
119 to 121
Input
When i80 system parallel data transfer is selected (/RD), read is
enabled by this signal. When this pin is L, data is output to the data
bus. When M68 system parallel data transfer is selected (E), this
pin inputs an enable signal that triggers data write or read.
But in the µPD161401, the data of the display access memory
register, the complementary color blink data memory register, the
specified color blink data memory register and the reverse data
memory access register (R12, R41, R45, R50) cannot be read.
When i80 system parallel data transfer is selected (/WR), write is
enabled by this signal. Data is written at the rising edge of this
signal. When M68 system parallel data transfer is selected (R, /W),
this pin determines the data transfer direction, as follows:
0: Write
/WR (R,/W)
Write (read/write)
116 to 118
Input
Input
1: Read
IFM0,
IFM1
Interface selection
86 to 88,
80 to 82
Selects an interface mode
IFM1
IFM0
Interface Mode
L
L
L
H
L
Serial
Setting prohibited
i80 series parallel
M68 series parallel
H
H
H
D0 to D15
(SI)
Data bus
187 to 182,
178 to 170,
166 to 158,
154 to 149,
145 to 137,
133 to 125
I/O
This is a bi-directional data bus connected to an 8- or 16-bit
standard CPU bus.
(serial input)
(serial clock)
(SCL)
When the serial interface mode is selected (IFM1, IFM0 = L, L), D7
functions as a serial data input pin (SI), and D6 serves as a serial
clock input pin (SCL). At this time, D0 to D5 and D8 to D15 go into a
high-impedance state.
When the 8-bit data bus is selected, only D0 to D7 are used, and D8
to D15 go into a high-impedance state. Data is input starting from its
higher byte, followed by the lower byte. If the chip is not selected,
all D0 to D15 go into a high-impedance state.
RS
Index register/data
command selection
Input
This pin is usually connected to the least significant bit of a
standard CPU address bus to identify whether data is an index
register or data/command.
110 to 112
RS = H: Indicates that D0 to D15 are data/command.
RS = L: Indicates that D0 to D15 are an index register.
13
Data Sheet S15726EJ2V0DS
µPD161401
(2/3)
Symbol
/DISP
Pin Name
Pin No.
I/O
Description
Reset
107 to 109
Input
Making /DISP low initializes the DISP flag in the control register 1
(R0) and turns OFF the display. When the serial interface is used,
the write counter is also initialized. Making /DISP high enables
writing. To light the display after it has been turned OFF by this pin,
make /DISP high and set the DISP flag to 1.
This pin inputs or outputs a liquid crystal AC signal.
M,/S = H : Output
FR
Frame signal
Frame sync signal
Display blink
194 to 196
191 to 193
197 to 199
74 to 76
I/O
I/O
M,/S = L : Input
When two or more µPD161401s are used in master/slave mode,
the respective FR pins must be connected to each other.
This pin inputs or outputs a liquid crystal AC sync signal.
M,/S = H : Output
FRSYNC
DOF
M,/S
M,/S = L : Input
When two or more µPD161401s are used in master/slave mode,
the respective FRSYNC pins must be connected to each other.
This pin controls blinking of the LCD.
I/O
M,/S = H : Output
M,/S = L : Input
When two or more µPD161401s are used in master/slave mode,
the respective DOF pins must be connected to each other.
This pin selects master or slave mode. In the master mode, it
outputs a timing signal necessary for driving the LCD. In the slave
mode, this timing signal is input from an external source to
synchronize the LCD. M,/S = H : Master mode
M,/S = L : Slave mode
Master/slave
Input
The status of each pin, including this pin, and the power circuit is
as follows depending on the status of the M,/S pin.
M,/S
H
Power Circuit
Enabled
FR
FRSYNC
Output
Input
DOF
Output
Input
Output
Input
L
Disabled
IRS
VLCD adjustment
Input
This pin selects the resistor used to adjust the VLCD voltage level.
IRS = H: The internal resistor is used.
92 to 94
IRS = L: The internal resistor is not used.
The VLCD voltage level is adjusted by an external voltage divider
resistor connected to the VR pin.
This pin is enabled only when the master operation mode is
selected. If the slave mode is selected, this pin is fixed to H or L.
14
Data Sheet S15726EJ2V0DS
µPD161401
(3/3)
Symbol
OSCIN1
Pin Name
Pin No.
I/O
Description
Oscillation signal pin
206 to 208
Input
These pins are connected with a resistor inserted between OSCIN1
and OSCOUT, and between OSCIN2 and OSCOUT. When an external
oscillator is used, input a clock signal to the OSCIN pin and leave
the OSCOUT pin open.
OSCIN2
212 to 214
218 to 220
200 to 202
Input
OSCOUT
OSCSYNC
Output
Display clock output
Test output
Output This pin outputs a clock for display. When using the µPD161401 in
the master or slave mode, refer to 5.4 Oscillator.
TOUT0 to
TOUT15
230 to 277
Output These pins are used when the µPD161401 is in the test mode.
Usually, leave these pins open.
TSTRTST,
TSTVIHL
TPWR0,
TPWR1
Test input pin
224 to 226,
227 to 229
50 to 52,
Input
These pins are used to set the µPD161401 in the test mode.
Usually, connect these pins to VSS.
Test input/output pin
I/O
These pins are used to input/output test signals when the
µPD161401 is in the test mode. Usually, leave these pins open.
47 to 49
3.3 Driver Pins
Symbol
Pin Name
Segment
Pin No.
I/O
Description
SEG1 to
SEG303
361 to 670
Output These pins output segment signals.
O1 to O80
Common
319 to 358,
673 to 712
53 to 55
Output These pins output common signals.
VRS
Operational amplifier
input
Input
These are the input pins of the operational amplifier that adjusts
the LCD driving voltage. VRS is used to input the reference voltage
of the amplifier for LCD voltage adjustment. VR is used to connect
a feedback resistor for the operational amplifier.
The feedback resistor is connected between this pin and GND,
AMPOUTM, or AMPOUTS. This pin is enabled only when the internal
divider resistor for VLCD voltage adjustment is not used (IRS = L).
When the internal divider resistor is used (IRS = H), this pin is not
used.
VR
287 to 289
AMPOUTM
AMPOUTS
DUMMY
Operational amplifier
output
290 to 292
296 to 298
Output These pins are the output pins of the operational amplifier that
adjusts the LCD driving voltage. The signals output by these pins
are connected to the LCD driving voltage adjuster resistor (refer to
5.6.3 Voltage regulator circuit) only when the internal resistor for
LCD voltage adjustment is not used (IRS = L). It is recommended
to connect a capacitor of 0.01 to 0.1 µF to these pins to stabilize
the output of the internal operational amplifier.
Dummy pin
1, 317, 318, 359,
360, 553 to 559,
671, 672, 713
−
These pins are not connected to the internal circuit.
15
Data Sheet S15726EJ2V0DS
µPD161401
4. PIN I/O CIRCUITS AND RECOMMENDED CONNECTION OF UNUSED PINS
The I/O circuit type of each pin and recommended connection of unused pins are shown in the table below.
Symbol
/CS1
Input Type
Schmitt-trigger A
Schmitt-trigger A
Schmitt-trigger A
I/O
Recommended of Unused Pins
Connect this pin to VSS.
Note
Input
Input
Input
−
−
−
CS2
Connect this pin to VDD1.
/RD(E)
Connect to VDD1 (i80 system interface), or to VDD1 or VSS (serial
interface).
/WR(R,/W)
IFM1, IFM0
D0 to D5
D6(SCL)
D7(SI)
Schmitt-trigger A
Schmitt-trigger A
Schmitt-trigger B
Schmitt-trigger B
Schmitt-trigger B
Schmitt-trigger B
Schmitt-trigger A
Schmitt-trigger C
Schmitt-trigger A
Schmitt-trigger A
Schmitt-trigger A
Schmitt-trigger A
Schmitt-trigger A
Schmitt-trigger A
Schmitt-trigger A
−
Input
Input
I/O
Connect to VDD1 or VSS (serial interface).
Mode setting pin
−
1
−
−
−
−
2
−
−
−
−
1
1
−
−
−
−
−
Leave open.
I/O
−
I/O
−
D8 to D15
RS
I/O
Leave open.
Input
Input
I/O
Register setting pin
Connect to VDD1.
/DISP
FR
Leave open (in master mode, M,/S = H).
Leave open (in master mode, M,/S = H).
Leave open (in master mode, M,/S = H).
Mode setting pin
FRSYNC
DOF
I/O
I/O
M,/S
Input
Input
Input
Input
Output
Output
Output
IRS
Mode setting pin
OSCIN1
OSCIN2
OSCOUT
OSCSYNC
TOUT0 to
TOUT15
Connect to VDD1 or VSS.
Connect to VDD1 or VSS.
Leave open (when an external clock is used).
Leave open.
−
−
Leave open.
TSTRTST
TSTVIHL
TPWR
Schmitt-trigger A
Schmitt-trigger A
−
Input
Input
I/O
Connect this pin to VSS (in normal operation mode).
Connect this pin to VSS (in normal operation mode).
Leave open.
−
−
−
Notes 1. Connect this pin to VDD1 or VSS depending on the mode selected.
2. Input VDD1 or VSS output from the CPU to this pin depending on the mode selected.
Remark Schmitt-trigger A : Schmitt inverter
Schmitt-trigger B : Schmitt NAND
Schmitt-trigger C : Schmitt inverter (with delay circuit)
16
Data Sheet S15726EJ2V0DS
µPD161401
5. FUNCTIONAL DESCRIPTION
5.1 CPU Interface
5.1.1 Selecting interface type
The µPD161401 transfers data through an 8-bit bi-directional data bus (D7 to D0), a 16-bit bi-directional data bus (D15
to D0), or a serial data input (SI) pin. Interface type can be selected by making the IFM1,IFM0 pin high or low, as shown
in the following table.
IFM1
IFM0
Interface type
Serial data input
Setting Prohibited
i80 system CPU
M68 system CPU
L
L
L
H
L
H
H
H
Parallel data input or serial data input can be chosen as by setting the polarity of IFM1 terminal, as shown in the
following table.
IFM1
/CS1, CS2
/CS1, CS2
/CS1, CS2
RS
RS
/RD
/RD
/WR
/WR
D15 to D8
D15 to D8
Hi-ZNote2
D7
D7
SI
D6
D6
D5 to D0
D5 to D0
Hi-ZNote2
H: Parallel input
L: Serial input
RS Note1
Note1
SCL
Notes 1. Fix these pins to the high or low level.
2. Hi-Z: High impedance
5.1.2 Parallel interface
When the parallel interface is selected (IFM = H), an 8-bit bi-directional data bus (D7 to D0) or 16-bit bi-directional data
bus (D15 to D0) can be selected by setting the BMOD flag of the control register 2 (R1) to 1 or 0. In addition, the
µPD161401 can be directly connected to an i80 or M68 system by making the IFM0 pin high or low as shown in the
following table.
IFM0
/CS1, CS2
/CS1, CS2
RS
RS
/RD
E
/WR
BMOD
D15 to D8
D15 to D8
Hi-ZNote
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
R,/W
0
1
0
1
H: M68 system CPU
RS
/RD
/WR
D15 to D8
Hi-ZNote
/CS1, CS2
L: i80 system CPU
Note Hi-Z : High impedance (may be open)
17
Data Sheet S15726EJ2V0DS
µPD161401
The data bus signals are identified by the combination of the RS, /RD(E), /WR (R,/W) signals as shown in the
following table.
Common
M68
i80
Common
Data Bus
D15 to D8
Function
Reads the register.
Writes the display data/register.
Prohibited
RS
1
R,/W
1
E
1
/RD
0
/WR
1
BMOD
D7 to D0
Note1
OUT
IN
0
1
0
1
0
1
0
1
Note1
Hi-Z
Note2
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
1
0
0
1
0
1
1
1
1
0
1
0
1
0
IN
OUT
OUT
IN
0
Writes the control index register.
IN
0/1
Other
Hi-Z
−
Remark IN : Input status (cannot be open), OUT : Output status, Hi-Z : High impedance (may be open)
Notes1. In the µPD161401, the data of the display access memory register, the complementary color blink data
memory register, the specified color blink data memory register and the reverse data memory access
register (R12, R41, R45, R50) are read-prohibited. However, if R12 is selected, the data bus signals D15 to
D0 enter an output state. If another register is specified, the D15 to D8 signals become Hi-Z and the D7 to D0
signals enter an output state.
2. Only the display access memory register (R12) enters the input state. If another register is specified, the D15
to D8 signals become Hi-Z.
18
Data Sheet S15726EJ2V0DS
µPD161401
5.1.3 Serial interface
When the serial interface has been selected (IFM1, IFM0 = L, L), as long as the chip is in an active state (/CS1= L,
CS2 = H ), serial data input (SI) and serial clock input (SCL) can be received. Serial data is read in the order of D7, then
D6 to D0 at the rising edge of the serial clock input from the serial input pin. This data is converted to parallel data in
synchronization with the 8th rising edge of the serial clock. Serial input data is judged as display data/command data if
RS = H and an index if RS = L. The RS input is read every 8th rising edge of the serial clock after the chip becomes
active and is used for data discrimination.
Figure 5−1. Serial Interface Signal Chart
CS2 = "H"
/CS1
D7
1
D6
2
D5
3
D4
4
D3
5
D2
6
D1
7
D0
8
D7
9
D6
10
D5
11
D4
12
D3
13
D2
14
D1
15
D0
16
D7
17
D6
18
SI
SCL
RS
Remarks 1. If the chip is not in an active state, the shift register and counter are reset to their initial statuses.
2. The serial clock counter is reset by initialization from the /DISP pin.
3. Data cannot be read when using serial interface mode.
4. Care must be taken when performing SCL wiring to avoid effects from terminal radiation or external noise
caused by the wiring length. It is recommended to confirm operation using the actual equipment to be
used.
5.1.4 Chip select
The µPD161401 has chip select pins (/CS1 and CS2). The CPU parallel interface or Serial interface can be used only
when /CS1 = L (CS2 = H).
If the chip select pins are not active, the D0 to D15 pins go into a high-impedance state, and the RS, /RD, and /WR pins
do not become active.
5.1.5 Accessing display data RAM and internal registers
When the CPU accesses the µPD161401, the CPU only has to satisfy the requirement of the cycle time (tCYC) and can
transfer data at high speeds. Usually, it is not necessary for the CPU to take wait time into consideration.
When the CPU writes data to the µPD161401, no dummy data is necessary. When reading data, dummy data is not
necessary either. In the µPD161401, the data of the display access memory register, the complementary color blink
data memory register, the specified color blink data memory register and the reverse data memory access register
(R12, R41, R45, R50) cannot be read. Figure 5−2 illustrates as follows.
19
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−2. Writing and Reading
Writing
/WR
DATA
N
N+1
N+2
N+3
Reading (other than display memory access register)
/WR
/RD
IRn
Data
IRn+1
Data
DATA
IRn
IRn + 1
IR Address
Set #n
IRn Register
Data Read
IR Address
Set #n+1
IRn+1 Register
Data Read
Caution Display access memory register, the complementary color blink data memory register, the
specified color blink data memory register and the reverse data memory access register (R12,
R41, R45, R50) cannot be read.
20
Data Sheet S15726EJ2V0DS
µPD161401
5.2 Display Data RAM
5.2.1 Display data RAM
This RAM stores dot data for display and consists of (101 × 80) × 8 bits. Any address of this RAM can be accessed by
specifying an X address and a Y address.
Display data D0 to D15 transmitted from the CPU corresponds to the pixels on the LCD (refer to Table 5−1). If the
µPD161401 is used in a multi-chip configuration, restrictions on display data transfer are relaxed and display setting
can be performed relatively freely.
The CPU writes data to the display RAM via I/O buffers. This write operation is performed independently of an
operation to read signals for driving the LCD. Therefore, even if the display data RAM is asynchronously accessed,
adverse effects such as flickering do not occur or the current LCD screen.
Table 5−1. Display Data RAM
MSB
D15
LSB MSB
LSB
D0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
Dot (R)
Dot (G)
Dot (B)
Dot (R)
Dot (G)
Dot (B)
Pixel 1
Pixel 2
LCD panel
Pixel 1
Pixel 2
Pixel 2
Pixel 3
Pixel 4
Pixel 4
Pixel 5
Pixel 5
Pixel 6
Pixel 6
Pixel 7
Pixel 7
Pixel 8
Pixel 1
Pixel 3
Pixel 8
00H
01H
02H
03H
04H
05H
06H
07H
5.2.2 X address circuit
An X address of the display data RAM is specified by using the X address register (R4) as shown in Figure 5−5.
If the X address increment mode (INC = 0: control register 2 (R1)) is used, the specified X address is incremented or
decremented by one each time display data is written. Whether the address is incremented or decremented is specified
by the XDIR flag of control register 2 (R1) as shown in Table 5−2.
In the increment mode, the X address is incremented up to 64H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 00H.
In the decrement mode, the X address is decremented to 00H. If more display data is written, the Y address is
incremented (YDIR = 0) or decremented (YDIR = 1), and the X address returns to 64H.
When the 16-bit data bus is selected (BMOD = 0), only an even address can be specified. Moreover, when the 16-bit
data bus is selected, dummy data is required as shown in Figure 5−3.
21
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−3. About Dummy Data Required when the 16-bit Data Bus is Selected
· When an ADC = 0
pixel1
101
D8
D7
D0
D15
Dummy data
SEG
1
SEG303
X address
00H 01H
pixel 1
64H
pixel 101
· When an ADC = 1
SEG303
pixel1
SEG
101
1
D8
D7
D0
D15
Dummy data
X address
00H 01H
pixel 1
64H
pixel 101
22
Data Sheet S15726EJ2V0DS
µPD161401
5.2.3 Y address circuit
A Y address of the display data RAM is specified by using the Y address register (R5) as shown in Figure 5−5. If the
Y address increment mode (INC = 1: control register 2 (R1)) is used, the specified Y address is incremented or
decremented by one each time display is written. Whether the address is incremented or decremented is specified by
the YDIR flag of control register 2 (R1) as shown in Table 5−2.
In the increment mode, the Y address is incremented up to 4FH. If more display data is written, the X address is
incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to 00H.
In the decrement mode, the Y address is decremented to 00H. If more display data is written, the X address is
incremented (XDIR = 0) or decremented (XDIR = 1), and the Y address returns to 4FH.
The relationship between the setting of INC, XDIR, and YDIR of control register 2 (R1) and the address is as follows:
Table 5−2. Relationship between INC, XDIR, and YDIR, and Address
INC
0
Setting
The address is successively incremented or decremented in the X direction when data is accessed.
The address is successively incremented or decremented in the Y direction when data is accessed Note
1
.
Note This setting cannot be used when the 16-bit parallel interface is used.
XDIR
Setting
0
1
Increments the X address (+1) when data is accessed.
Decrements the X address (−1) when data is accessed.
YDIR
Setting
0
1
Increments the Y address (+1) when data is accessed.
Decrements the Y address (−1) when data is accessed.
Table 5−3. Combination of INC, XDIR, and YDIR, and Address Direction
INC
XDIR
YDIR
Image of Address Scanning
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
A-1
A-2
A-3
A-4
B-1
B-2
B-3
B-4
0
1
Caution If the access direction is changed by using INC, XDIR, or YDIR, be sure to set the X address register
(R4) and Y address register (R5) before accessing the display RAM.
23
Data Sheet S15726EJ2V0DS
µPD161401
Y address register (R5)
D7
D6
D5
D4
D3
D2
D1
D0
YA6
YA5
YA4
YA3
YA2
YA1
YA0
YA6 to YA0
Sets a line address.
Figure 5−4. Combination of INC, XDIR, and YDIR, and Address Scanning Image
X address
00H
64H
00H
A-1
A-2
A-3
A-4
4FH
00H
X address
00H
64H
4FH
B-1
B-2
B-3
B-4
5.2.4 Column address circuit
When the contents of the display data RAM are displayed, column addresses are output to the SEG output pins as
shown in Figure 5−5.
The correspondence relationship between the column addresses of the display RAM and segment outputs can be
reversed by the ADC flag (segment driver direction select flag) of control register 1 (R0). This reduces the restrictions
on chip layout when the LCD module is assembled.
Table 5−4. Relationship between Column Address of Display RAM and Segment Output
SEG Output
SEG1
000H
12EH
SEG303
12EH
000H
ADC
(D1)
0
→
←
Column address
Column address
→
←
1
24
Data Sheet S15726EJ2V0DS
µPD161401
5.2.5 Common scan circuit
The common scan circuit sets the sequence for the scan line of the common signal in which the display RAM is to be
read. The RAM line reading direction is set as shown in Table 5−5 by the COMR flag of control register 1 (R0).
For example, if the duty ratio is 1/64, the number of scroll steps is 0, and COMR = 0, the RAM line reading direction
is from 00H to 3FH. If COMR = 1, it is from 3FH to 00H.
Table 5−5. Relationship between Common Scan Circuit and Scan Direction
COMR
(D0)
0
1
00H
4FH
→
→
4FH
00H
In addition, scanning of the common outputs can be assigned by using the COM scanning address setting register
(R21) as shown in Table 5−6, so that the scanning can be started from any O1 to O80 output pin. Therefore, the
common wiring of the LCD panel can be optimized when any duty ratio is selected.
When COMR = 0, the scan start (COM1) pin and scan end (COMa) pin are the On and O(n+a−1) pins, respectively. The
value of a is 64, 72, and 80 for 1/64 duty, 1/72 duty, and 1/80 duty, respectively. When COMR = 1, the scan start
(COM1) pin and scan end (COMa) pin are the O(82−a−n) and O(80−n+1) pins, respectively.
Examples of COM scan address settings for 1/64 duty, 1/72 duty, and 1/80 duty are shown in Tables 5−5, 5−7, and
5−8, respectively.
Table 5−6. COM Scanning Address Setting (1/64 duty)
COMR = 0
COMR = 1
the scan start
the scan end
(COMa)Note pin
O(n+a-1) Note
the scan start
the scan end
(COMa)Note pin
→
→
→
→
CSA4 CSA3 CSA2 CSA1 CSA0
n
(COM1) pin
On
(COM1) pin
O(82-a-n) Note
O(80-n+1)
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
O1
O2
O64
O65
O66
O67
O68
O69
O70
O71
O72
O73
O74
O75
O76
O77
O78
O79
O80
O17
O16
O15
O14
O13
O12
O11
O10
O9
O80
O79
O78
O77
O76
O75
O74
O73
O72
O71
O70
O69
O68
O67
O66
O65
O64
3
O3
4
O4
5
O5
6
O6
7
O7
8
O8
9
O9
10
11
12
13
14
15
16
17
O10
O11
O12
O13
O14
O15
O16
O17
O8
O7
O6
O5
O4
O3
O2
O1
Note When in 1/64 duty, a = 64.
25
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−7. COM Scanning Address Setting (1/72 duty)
COMR = 0
COMR = 1
Remark
the scan start
(COM1) pin
On
the scan end
(COMa)Note pin
the scan start
the scan end
(COMa)Note pin
→
→
→
→
CSA4 CSA3 CSA2 CSA1 CSA0
n
(COM1) pin
O(82-a-n) Note
O(n+a-1) Note
O(80-n+1)
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
2
O1
O2
O3
O4
O5
O6
O7
O8
O9
O72
O73
O74
O75
O76
O77
O78
O79
O80
O9
O8
O7
O6
O5
O4
O3
O2
O1
O80
O79
O78
O77
O76
O75
O74
O73
O72
3
4
5
6
7
8
9
10
Prohibit
since here
Note When in 1/72 duty, a = 72
Caution The COM scan address setting register (R21) should be set so that O1 ≤ scan start pin and scan end
pin ≤ O80. If any other settings are made the IC operation is not guaranteed.
Table 5−8. COM Scanning Address Setting (1/80 duty)
COMR = 0
COMR = 1
Remark
the scan start
the scan end the scan start
the scan end
(COMa)Note pin
→
→
CSA4 CSA3 CSA2 CSA1 CSA0
n
(COMa)Note pin
O(n+a-1) Note
O80
(COM1) pin
(COM1) pin
O(82-a-n) Note
O1
→
→
→
→
On
O1
O(80-n+1)
0
0
0
0
0
0
0
0
0
1
1
2
O80
Prohibit
since here
Note When in 1/80 duty, a = 80
Caution When this µPD161401 is used in 1/80 duty, the COM scan address setting register (R21) should be set
to CSA4, CSA3, CSA2, CSA1, CSA0 = 0, 0, 0, 0, 0. If any other settings are made the IC operation is not
guaranteed.
26
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−5. Configuration of X Address Register
1
1
0
0
1
D
D
D
D
6
5
4
3
0
0
0
0
0
0
0
0
0
0
Setting example 1/64 duty
COMR = 0
n
= 1(CSA4 to CSA0 = 0)
D2
Panel pin
COM output
0
0
64H
D
D
1
0
0
0
00H
0
1
01H
Line
Driver: On
address
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
1
2
3
4
5
6
7
8
9
10
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D
0
D7
D6
D5
D4
D3
D2
D1
D0
COM
COM
COM
COM
COM
COM
COM
COM
COM
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
1
2
3
4
5
6
7
8
9
Data
11
12
13
14
15
16
17
18
19
20
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
COM60
COM61
COM62
COM63
COM64
O
O
O
O
O
60
61
62
63
64
27
Data Sheet S15726EJ2V0DS
µPD161401
5.2.6 Display data latch circuit
The display data latch circuit temporarily stores (latches) the display data that is output from the display data RAM to
the LCD driver circuit.
The display scan command for forwarding or reversing data and the display ON/OFF command control the latched
data and do not affect the data of the display data RAM.
5.2.7 Arbitrary address area access (window access mode (WAS))
With the µPD161401, any area of the display RAM selected by the MIN. X/Y address registers (R7 and R9) and
MAX. X/Y address registers (R8 and R10) can be accessed.
First, select the area to be accessed by using the MIN. X/Y address registers and MAX. X/Y address registers. When
WAS of control register 1 is set to 1, the window access mode is then selected. The address scanning setting by INC,
XDIR, and YDIR of control register 2 (R1) is also valid in this mode, in the same manner as when data is normally
written to the display RAM. In addition, data can be written from any address by specifying the X address register (R4)
and Y address register (R5).
Note that the display RAM must be accessed after setting the X address register (R6) and Y address register (R7) if
the window access area has been set or changed by the MIN. X/Y address register (R7, R9) or MAX. X/Y address
register (R8, R10).
Figure 5−6. Example of Incrementing Address When INC = 0, XDIR = 0, and YDIR = 0
.
.
X address
MIN. X address
MAX.
00H
64H
Start point
00H
.
MIN. Y address
.
.
.
.
MAX. Y address
4FH
End point
Cautions 1. When using the window access mode, the relationship between the start point and end point
shown in the table below must be established.
Item
X address
Y address
Address Relation Ship
00H ≤ MIN. X address ≤ X address (R4) ≤ MAX. X address ≤ 64H
00H ≤ MIN. Y address ≤ Y address (R5) ≤ MAX. Y address ≤ 4FH
2. If invalid address data is set as the MIN./MAX. address, operation is not guaranteed.
3. Access the display RAM after setting the X address register (R6) and Y address register (R7) if the
window access area has been set or changed by the MIN. X/Y address register (R7, R9) or
MAX. X/Y address register (R8, R10).
28
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−7. Example of Sequence in Window Access Mode
Start
Control register 2
Sets window access mode.
(WAS = 1)
.
.
X address register (R7)
Y address register (R9)
MIN.
MIN.
Sets start point.
Sets end point.
.
X address register (R8)
Y address register (R10)
MAX.
.
MAX.
X address register (R4)
Y address register (R5)
Display memory access register (R12)
Data
No
Writing complete?
Yes
End
29
Data Sheet S15726EJ2V0DS
µPD161401
5.3 Screen Processing
5.3.1 Blink/reverse display circuit
The µPD161401 can blink or reverse a specific area of the full-dot display. Blinking is to turn ON/OFF display
repeatedly at about 1 Hz (complementary color or specified color can be selected) and reversing is to reverse the
grayscale data on the display.
The area to be blinked is specified by using the complementary color/specified color blink start/end line address
registers (R39, R40, R43, and R44), complementary color/specified color blink X address registers (R38, R42), and
complementary color/specified color blink data memory registers (R41, R45).
First, select a blink display start line address and end line address by using the start/end line address registers. Next,
select the column to be blinked by using the blink X address register and blink data memory register.
The specified color blink is blinked between the graphic data and the color data specified by the specified color setting
register (R46).
To select an area to be reversed, use the reverse start/end line address registers (R48, R49), reverse X address
register (R47), and reverse data memory access register (R50).
First, select line addresses at which reverse display is started and stopped, by using the reverse start/end line address
registers. Next, select a column to be reversed, by using the reverse X address register and reverse data memory
access register. The specified blink/reverse X address is incremented by one each time blink/reverse data has been
input.
The complementary color/specified color blink RAM and reverse RAM store the data to be blinked and reversed.
Each RAM is configured of 101 bits (12 × 8 + 5 bits).
To access a desired bit, specify an X address. Blink/reverse data D0 to D7 transmitted from the CPU corresponds to
SEGX on the LCD, as illustrated in Figure 5−8.
If the BLD bit and INV bit of the blink/reverse setting register (R37) are set to H after an area and data have been set,
blinking or reversing the data is started. Figure 5−9 shows the relationship between the start line address, end line
address, blinking/reversing data, and LCD.
If the same area is specified for complementary color blinking and specified color blinking, the specified color blinking
takes precedence.
Table 5−9. Reversing Operation and Display
Original Grayscale
After Reversing (supplement color)
R/G display data
0, 0, 0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
1, 1, 1
1, 1, 0
1, 0, 1
1, 0, 0
0, 1, 1
0, 1, 0
0, 0, 1
0, 0, 0
B display data
0, 0
0, 1
1, 0
1, 1
1, 1
1, 0
0, 1
0, 0
30
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−8. Correspondence between Blink/Reverse Data and Segment
When an ADC = 0
D3
D2
D1
D0
0
0
0
0
1
1
0
0
0
0
1
0
00H
01H
0CH
Data
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Column output
LCD
Output
Note The value written in D2 to D0 of X address 0CH is invalid.
When an ADC = 1
D
3
0
0
0
0
1
D2
1
0
0
D1
0
0
D0
0
1
00H
01H
0CH
Data
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Column output
LCD
Output
Note The value written in D7 to D5 of X address 00H is invalid.
Figure 5−9. Blink/Reverse Display Area Setting Image
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
0 0 1 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 0 0
Blink/reverse
data
Start line
End line
: Blink or reverse pixel
31
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−10. Example of Sequence of Setting Blink/Reverse Display
Start
Blink/reverse start line
address register
Blink/reverse end line
address register
Blink/reverse X address register
Blink/reverse data memory
Data
NO
Writing complete ?
YES
Blink/reverse setting register (R37)
(BLDn, INV = H)
End
The data configuration of the range specification registers (start/end line address registers R39, R40, R43, R44, R48,
and R49) of each line is in the format shown below. Each display area is set in this format. .
D7
D6
D5
D4
D3
D2
D1
D0
X_6
X_5
X_4
X_3
X_2
X_1
X_0
X_6 to X_0
Sets start/end line addresses.
Remark X_: CBS, CBE, SBS, SBE, IVS, IVE
32
Data Sheet S15726EJ2V0DS
µPD161401
5.3.2 Example of setting blink area
This section explains how to specify an area to be blinked, taking complementary color blinking as an example. The
same setting is also applied to specified color blinking and reverse display.
(1) Example of using 1 chip at duty ratio of 1/80
T.B.D.
Remark T.B.D. (To be determined.)
(2) Example of using 2 chip (Master and slave) at duty ratio of 1/80
T.B.D.
5.4 Oscillator
The µPD161401 has a CR oscillator (with external R) for main duty/sub-duty display. This oscillator generates the
display clock.
This oscillator is controlled by the DTY flag of control register 2 (R1), and the configuration of its display clock can be
set in accordance with the system used.
The function of each circuit of the oscillator is shown below. The main duty display/sub-duty display oscillator
becomes valid only when oscillation resistors (RM and RS) are connected to it. The clock for main duty display or sub-
duty display can be selected depending on the status of the DTY flag of control register 2 (R1).
Figure 5−11. Oscillator Block
Selected by DTY
OSCIN1
OSCIN2
Oscillator for
main duty/sub-duty
OSCOUT
To graphic driver circuit
OSCSYNC
The relationship between the frame frequency (fFRAME) in the normal display mode, oscillation frequency (fOSCINn), and
set duty frame is as follows.
fFRAME = fOSCINn ÷ 16 ÷ N
N = Duty ratio
33
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−10 shows the relationship between oscillation resistors RM and RS, and the display clock circuit.
Table 5−10. Relationship between Display Clock Circuit, Pins, and Resistor
RM Connection
Connected
RS Connection
Connected
Clock for Main Duty Display
Internal oscillation
Clock for Sub-duty Display
Internal oscillation
External clock
Example
A
B
Not connected
Not connected
External clock
Figure 5−12. Example of Using Clock
f
M
OSCIN1
OSCIN2
OSCOUT
OSCIN1
OSCIN2
OSCOUT
f
S
R
M
R
S
Open
(A)
(B)
OSCIN1 : For main duty
OSCIN2 : For sub-duty
Figure 5−13. Example of Master/Slave Connection
Master
Slave
(M,/S = H)
(M,/S = L)
OSCSYNC
OSCIN1
OSCIN2
Open
OSCOUT
(A)
34
Data Sheet S15726EJ2V0DS
µPD161401
5.5 Display Timing Generator
The display timing generator generates timing signals for the line address circuit and display data latch circuit, from
the display clock. The display data is latched to the display data latch circuit in synchronization with the display clock
and output to the segment driver output pins. The display data can be read completely independently of the access to
the display data RAM by the CPU. Therefore, even if the display data RAM is asynchronously accessed, no adverse
effect, such as flickering, occurs on the LCD.
The internal common timing, LCD AC signal (FR), and frame synchronization signal (FRSYNC) are generated by the
display clock. A driver waveform in the frame AC driving mode shown in Figure 5−14 is generated for the LCD driver
circuit.
When the µPD161401 is used in a multi-chip configuration, the display timing signals for the slave chip (FR and
FRSYNC) must be supplied from the master chip.
Table 5−11. Relationship between FR, FRSYNC, and Operation Mode
Operation Mode
Master (M,/S = H)
Slave (M,/S = L)
FR
FRSYNC
Output
Input
Output
Input
35
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−14. Driver Waveform in Frame AC Driver Mode
1 FRAME
1
2
3
4
5
6
7
8
78 79 80 1
2
3
4
5
6
7
8
78 79 80
OSCSYNC
FRSYNC
FR
RAM
DATA
VLCD
V
V
LC1
LC2
SEG
1
V
V
LC3
LC4
V
SS
V
LCD
V
V
LC1
LC2
COM
1
V
V
LC3
LC4
V
SS
V
LCD
V
V
LC1
LC2
COM
2
V
V
LC3
LC4
V
SS
V
LCD
V
V
LC1
LC2
COM80
V
V
LC3
LC4
V
SS
36
Data Sheet S15726EJ2V0DS
µPD161401
5.6 Power Supply Circuit
5.6.1 Power supply circuit
The power supply circuit generates the voltage necessary for driving the LCD. The power circuit consists of a booster
circuit, voltage regulator circuit, and voltage follower circuit.
Power system control register 1 (R52) turns ON/OFF the transformer, reference voltage generator, voltage regulator
circuit (V regulator circuit), and voltage follower circuit (V/F circuit). Part of the internal power supply function and an
external power supply can be used in combination. Table 5−12 shows the functions controlled by the 4-bit data of
power system control register 1 (R52). Table 5−13 shows examples of combinations of the power circuit functions.
Table 5−12. Function of Each Bit of Power System Control Register
Status
Item
1
0
OP3
OP2
OP1
OP0
: Booster circuit control bit
ON
ON
ON
ON
OFF
OFF
OFF
OFF
: Reference voltage generator control bit
: Voltage regulator circuit (V regulator circuit) control bit
: Voltage follower circuit (V/F circuit) control bit
Table 5−13. Examples of Combinations (Reference Values)
V/F
Booster Reference V Regulator
External
Booster
Status
OP3 OP2 OP1 OP0
Circuit
voltage
Circuit
Circuit
Power Input System Pins
<1> Only internal power supply is
used
1
1
1
1
Ο
Ο
Ο
Ο
VDD2
Used
<2> External VOUT power supply
0
1
1
0
1
0
1
1
×
Ο
×
Ο
×
Ο
Ο
VDD2, VOUT
VDD2,
Open
Used
<3> Only V/F circuit is used
Ο
AMPOUT
VDD2, VOUT,
VLCD,
Open
<4> Only external power supply is
used
0
0
0
0
×
×
×
×
VLC1 to VLC4
+
−
+
−
Remarks 1. The “booster system pins” are the C1 , C1 to C5 , C5 pins.
2. All the power circuits are turned OFF when the µPD161401 serves as a slave (M,/S pin = L).
5.6.2 Booster circuit
The power supply circuit has an internal booster circuit that increases the LCD driver voltage two- to seven-fold.
Because this booster circuit uses the internal oscillator signals, either the oscillator must be operating or an external
display clock must be input to operate this circuit.
+
−
+
−
The booster circuit usually uses the C1 , C1 to C5 , C5 pins and VDD2 pins. Keep the wiring impedance of these pins
as low as possible. The number of boosting steps for main duty display and sub-duty display is set as shown in Table
5−14 by the MBTn and SBTn flags of power system control register 4 (R55).
For the number of boosting steps and how to connect capacitors, refer to Figure 5−15.
37
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−15. Number of Boosting Steps and Capacitor Connection
To boost LCD drive voltage seven-fold
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x2
x7
x6
x5
x4
x3
x2
To boost LCD drive voltage six-fold
To boost LCD drive voltage five-fold
To boost LCD drive voltage four-fold
Open
Open
Open
Open
To boost LCD drive voltage three-fold
To boost LCD drive voltage two-fold
Open
Remark “xN” (N = 2 to 7) of the capacitors in the above figure indicates the maximum voltage applied to the
capacitors.
xN : VDD2 x N (V)
Table 5−14. Number of Boosting Steps of Main Duty/Sub-duty Display Booster Circuit (during Normal Display)
MBT2
MBT1
MBT0
Number of Boosting steps (unit: fold)
SBT2
SBT1
SBT0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Two
Three
Four
Five
Six
Seven
Prohibited
Prohibited
38
Data Sheet S15726EJ2V0DS
µPD161401
5.6.3 Voltage regulator circuit
The boosted voltage from VOUT is supplied to the voltage regulator circuit and output to the LCD drive voltage pin VLCD.
Because the µPD161401 has a 128-step electronic volume function and an internal VLCD adjuster resistor, a high-
accuracy voltage regulator circuit can be configured by adding only a few components.
VLCD regulator circuit
(a) When internal resistor for adjusting VLCD is used
By using the internal resistor for adjusting VLCD and the electronic control function, LCD drive voltage VLCD can be
controlled and the contrast of the LCD can be adjusted by using commands. In this case, no external resistor is
necessary. Where VLCD < VOUT, the value of VLCD can be calculated as follows:
Example Calculating value of VLCD (where VLCD < VOUT)
Rb
Ra
VLCD = (1 +
VLCD = (1 +
) VEV
Rb
Ra
α
256
) (1 −
) VREG
α
256
Remark VEV = (1 −
) VREG
Figure 5−16. Example of Circuit Using Internal Resistor for Adjustment VLCD
+
VLCD
V
EV (constant power supply + electronic volume)
−
Rb
Ra
VREG is the internal fixed power source of the IC and has three types of temperature characteristic curves. These
temperature characteristic curves can be adjusted as shown in Table 5−15 depending on the setting of power system
control register 1 (R52) (TCS2 to TCS0).
Table 5−15 shows VREG at TA = 25°C.
Table 5−15. Adjusting Temperature Characteristic Curve
Status
TCS2
TCS1
TCS0
Temperature Gradient (unit: %/°C)
VREG (TYP.) (unit: V)
Internal power supply
0
0
0
0
1
0
0
1
1
×
0
1
0
1
×
−0.12
−0.13
−0.15
−0.17
−
1.77
1.69
1.63
1.59
−
When external reference
power supply is used
39
Data Sheet S15726EJ2V0DS
µPD161401
α is the value of the electronic volume register. It can take any of 128 values in accordance with the data set to the 7-
bit electronic control register. The value of α set by the main electronic volume register (R57) (main duty display) and
sub-electronic volume register (R58) (sub-duty display) is shown in Table 5−16.
Table 5−16. Changes in Value of α Depending on Setting of Electronic Volume Register
MEV6
SEV6
MEV5
SEV5
MEV4
SEV4
MEV3
SEV3
MEV2
SEV2
MEV1
SEV1
MEV0
SEV0
α
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
256
126
125
124
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
2
1
0
Rb/Ra is a ratio of the internal resistors for adjusting VLCD. This resistance ratio can be adjusted in 128 steps, by using
power control register 2 (R53) (VRRn: main duty display mode, and SVRn: sub-duty display mode). The value of the
reference voltage (1 + Rb/Ra) is determined as shown in Table 5−17, depending on the setting of 4 bits of the VLCD
internal resistance ratio register.
Table 5−17. Determining Reference Voltage Value by Setting of Internal Resistance Ratio Register
Register
VRR3
SVR3
VRR2
SVR2
VRR1
SVR1
VRR0
SVR0
1 + Rb/Ra
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
40
Data Sheet S15726EJ2V0DS
µPD161401
(b) When external resistor is used (when internal resistor for adjusting VLCD is not used)
LCD drive voltage VLCD can be controlled not only by a setting of the internal resistor for adjusting VLCD (IRS = L)
but also by connecting resistors Rae, Rbe, and Rce between VSS and VR, between VR and AMPOUTM, and between
VR and AMPOUTS, respectively. In this case also, LCD drive voltage VLCD and the contrast of the LCD can be
adjusted by using the electronic control function and commands.
In addition, the µPD161401 can select two values of VLCD for normal display and partial display. These values are
set by using an external divider resistor and automatically selected by the DTY flag of control register 2 (R1).
Where VLCD < VOUT, the value of VLCD can be calculated by the expression in Example 1 (DTY = 0) and the
expression in Example 2 (DTY = 1).
Example 1. To calculate value of VLCD (DTY = 0, in main duty display mode)
Rbe
Rae
VLCD = (1 +
VLCD = (1 +
) VEV
Rbe
Rae
α
256
) (1 −
) VREG
α
256
Remark VEV = (1 −
) VREG
Example 2. To calculate value of VLCD (DTY = 1, in sub-duty display mode)
Rce
Rae
VLCD = (1 +
VLCD = (1 +
) VEV
α
256
Rce
Rae
) (1 −
) VREG
α
256
Remark VEV = (1 −
) VREG
Figure 5−17. Example of Circuit Using External Resistor
+
VLCD
−
Main/sub-duty VLCD
adjustment selector
B
A
AMPOUTM
AMPOUTS
VR
VRS
Rbe
Rce
Rae
Main duty display mode
(DTY = 0)
B
B
A
A
Sub-duty display mode
(DTY = 1)
41
Data Sheet S15726EJ2V0DS
µPD161401
5.6.4 Level voltage control by operational amplifier
Although the µPD161401 has a power-saving power supply circuit, the display quality may be degraded if it is used to
drive a high-load LCD panel. The driving capability of the segment output can be controlled as shown in Table 5−18 by
LCS1 and LCS0 of power system control register 5 (R56), and the driving capability of the common outputs can be
controlled as shown in Table 5−19 by LCC1 and LCC0 of the same register. By controlling the driving capability, the
display quality and power consumption may be improved. Determine the driving capability in accordance with the actual
display status. If the display quality is not sufficiently improved in any driving mode, it will be necessary to supply the
LCD drive voltage from an external power supply.
In addition, the operational amplifier driving modes shown in Table 5−20 can be selected by the setting of HPM1 and
HPM0, so that the wait time to stabilize the supply voltage immediately after the power has been turned ON or OFF can
be shortened.
PSM1 specifies whether a boosting voltage of VDD2 × 2 is applied to the VLC3 or VLC4 level voltage follower of (refer to
Table 5−21). If a voltage boosted two-fold is applied to the voltage follower circuit, the current consumption may be
reduced.
Thoroughly confirm and evaluate the VLC3 and VLC4 levels of the LCD panel with the actual system to determine
whether the two-fold LCD drive voltage is to be supplied.
PSM0 can be used to set the current value of all the voltage follower circuits as shown in Table 5−22.
Table 5−18. Setting Driving Capability of Segment Outputs (LCS1, LCS0 = 0, 0)
LCS1
LCS0
Segment Output Driving Capability (unit: fold)
0
0
1
1
0
1
0
1
One
Two
Four
Eight
Table 5−19. Setting Driving Capability of Common Outputs (LCS1, LCS0 = 0, 0)
LCC1
LCC0
Common Output Driving Capability (unit: fold)
0
0
1
1
0
1
0
1
Two
Four
Eight
Sixteen
Table 5−20. Setting Operation Mode of Operational Amplifier
HPM1
HPM0
Mode Setting
0
0
1
1
0
1
0
1
Normal mode
Power supply ON mode 1
Power supply OFF mode
Power supply ON mode 2
42
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−21. Setting of Two-Fold Drive Voltage
PSM1
Mode Setting
0
1
Not used
Used
Table 5−22. Voltage Follower Bias Current Setting
PSM0
Bias Current Setting (unit: fold)
0
1
One
Two
43
Data Sheet S15726EJ2V0DS
µPD161401
5.6.5 Application example of power supply circuit
Figure 5−18. IRS = H, [OP3, OP2, OP1, OP0] = [1, 1, 1, 1]
Six-fold drive voltage
VDD1
V
DD2
V
RS
V
R
V
OUT
Open
AMPOUTS
AMPOUTM
V
OUT2
+
1
C
C
V
LCD
-
1
V
V
LC1
LC2
C +
2
-
+
C
C
2
3
V
V
LC3
LC4
-
+
C
C
3
4
-
+
C
C
4
5
-
C
V
5
SS
Figure 5−19. IRS = L, [OP3, OP2, OP1, OP0] = [1, 1, 1, 1]
Six-fold drive voltage
Open
V
RS
V
V
DD1
DD2
V
OUT
AMPOUTS
Rc
V
R
Rb' Ra'
AMPOUTM
V
OUT2
C +
1
V
LCD
-
+
C
1
2
V
V
LC1
LC2
C
-
C
3
2
C +
-
V
V
LC3
LC4
C
C
3
4
+
-
+
C
4
5
C
-
C
V
5
SS
44
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−20. IRS = H, [OP3, OP2, OP1, OP0] = [0, 0, 0, 1]
VDD1
V
DD2
V
RS
V
R
Open
V
OUT
AMPOUTS
AMPOUTM
V
OUT2
Open
Open
C +
1
V
LCD
-
C
C
1
+
2
V
V
LC1
LC2
-
C
2
C +
3
V
V
LC3
LC4
-
+
C
C
3
4
-
+
C
4
C
5
-
C
5
V
SS
Figure 5−21. IRS = L, [OP3, OP2, OP1, OP0] = [0, 0, 0, 1]
V
RS
V
V
DD1
DD2
Open
V
R
V
OUT
V
OUT2
Open
Open
AMPOUTS
AMPOUTM
+
1
C
C
-
V
LCD
1
C +
2
V
V
LC1
LC2
-
C
2
C +
3
-
V
V
LC3
LC4
C
3
C +
4
-
C
C
4
+
5
-
C
5
V
SS
45
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−22. IRS = L, [OP3, OP2, OP1, OP0] = [0, 0, 0, 0]
V
RS
V
V
DD1
DD2
V
R
Open
AMPOUTS
AMPOUTM
V
OUT
V
OUT2
Open
C +
1
V
LCD
-
+
C
1
2
C
V
V
LC1
LC2
-
+
C
C
2
3
Open
V
V
LC3
LC4
-
C
3
C +
4
-
C
4
C +
5
-
C
5
V
SS
Figure 5−23. Master/Slave Connection Example 1
V
V
DD1
DD2
V
RS
V
V
DD1
DD2
V
RS
M,/S
V
R
V
R
M,/S
Open
C +
1
AMPOUTS
AMPOUTS
C +
1
-
1
C
C
AMPOUTM
AMPOUTM
C +
2
V
OUT
V
OUT
-
1
C +
C
+
-
2
2
C +
3
-
-
2
V
OUT2
C
3
Open
V
OUT2
LCD
C
C +
4
Slave
Master
C +
3
-
Open
C
4
C +
5
-
3
V
V
LCD
C
C +
4
-
C
5
V
LC1
V
LC1
-
4
C
V
V
V
LC2
LC3
C +
5
V
LC2
LC3
-
5
V
V
C
LC4
LC4
V
SS
V
SS
46
Data Sheet S15726EJ2V0DS
µPD161401
Figure 5−24. Master/Slave Connection Example 2
V
V
DD1
DD2
V
RS
V
V
DD1
DD2
V
RS
M,/S
V
R
V
R
M,/S
Open
Open
C +
1
AMPOUTS
AMPOUTM
AMPOUTS
AMPOUTM
-
1
C +
1
C
C +
2
-
1
C
V
OUT
V
V
OUT
C +
2
-
+
C
C
2
3
V
OUT2
OUT2
-
2
C
Open
C +
3
-
C
C
3
4
Master
Slave
+
Open
-
3
C
V
LCD
V
V
LCD
LC1
C +
4
-
+
C
C
4
V
LC1
5
-
C
C
4
+
-
5
C
5
V
LC2
LC3
V
LC2
-
V
V
C
5
V
LC3
LC4
V
LC4
V
SS
V
SS
47
Data Sheet S15726EJ2V0DS
µPD161401
5.7 Driving LCD
The µPD161401 has a full-dot driver. This full-dot driver can modulate grayscale, depending on the setting of the
pulse widths. In this driving mode, eight R/G output grayscales and four B output grayscales are selected from a 17-
stage grayscale palette, and the selected grayscales are registered to the output grayscale palette of the IC. For details,
refer to Table 5−23 Example of Pulse Width Modulation Output.
5.7.1 Full-dot pulse modulation
The pulse width modulation function of the µPD161401 divides the segment pulse width of the signal for normal LCD
display (16), and outputs the divided pulse width in accordance with the output timing of dots at the ratio of the
grayscale palette selected by a command.
Figure 5−25. Full-Dot Pulse Width Modulation
1 Frame
1
2
3
4
5
6
7
8
78 79 80 1
2
3
4
5
6
7
8
78 79 80
V
LCD
V
V
LC1
LC2
SEG
1
V
V
LC3
LC4
V
SS
V
LCD
V
V
LC1
LC2
COM
1
V
V
LC3
LC4
V
SS
Expanded view of part
1
2
3
16/16
8/16
1/16
V
LCD
VLC1
VLC2
Caution The width of the common output pulse is not modulated.
48
Data Sheet S15726EJ2V0DS
µPD161401
The pulse is output in the form of combined odd line/even line or even line/odd line output, as shown in Figure 5−26.
Table 5−23 shows the combination of the rising and falling edges of the pulse of each frame.
Figure 5−26. Example of Pulse Width Modulation Output of Odd/Even Line
1 Frame
1
2
3
4
5
6
7
8
9 10 11 12
78 79 80
1
2
3
4
5
6
7
8
VLCD
V
V
LC1
LC2
V
V
LC3
LC4
V
SS
1
2
3
16/16
8/16
16/16
16/16
6/16 8/16
49
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−23. Pulse Width Modulation Output
1 or 2 Frames
3 or 4 Frames
SEG Odd Number SEG Even Number
Grayscale Level
0
COM
SEG Odd Number
SEG Even Number
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
2n+1
2n+2
0
0
0
0
0
0
0
0
1
2
1 ↑
1 ↓
1 ↓
1 ↑
1 ↓
1 ↑
1 ↑
1 ↓
2 ↑
2 ↓
2 ↓
2 ↑
2 ↓
2 ↑
2 ↑
2 ↓
3
3 ↑
3 ↓
3 ↓
3 ↑
3 ↓
3 ↑
3 ↑
3 ↓
4
4 ↑
4 ↓
4 ↓
4 ↑
4 ↓
4 ↑
4 ↑
4 ↓
5
5 ↑
5 ↓
5 ↓
5 ↑
5 ↓
5 ↑
5 ↑
5 ↓
6
6 ↑
6 ↓
6 ↓
6 ↑
6 ↓
6 ↑
6 ↑
6 ↓
7
7 ↑
7 ↓
7 ↓
7 ↑
7 ↓
7 ↑
7 ↑
7 ↓
8
8 ↑
8 ↓
8 ↓
8 ↑
8 ↓
8 ↑
8 ↑
8 ↓
9
9 ↑
9 ↓
9 ↓
9 ↑
9 ↓
9 ↑
9 ↑
9 ↓
10
11
12
13
14
15
16
10 ↑
10 ↓
11 ↑
11 ↓
12 ↑
12 ↓
13 ↑
13 ↓
14 ↑
14 ↓
15 ↑
15 ↓
16 ↑
16 ↓
10 ↓
10 ↑
11 ↓
11 ↑
12 ↓
12 ↑
13 ↓
13 ↑
14 ↓
14 ↑
15 ↓
15 ↑
16 ↓
16 ↑
10 ↓
10 ↑
11 ↓
11 ↑
12 ↓
12 ↑
13 ↓
13 ↑
14 ↓
14 ↑
15 ↓
15 ↑
16 ↓
16 ↑
10 ↑
10 ↓
11 ↑
11 ↓
12 ↑
12 ↓
13 ↑
13 ↓
14 ↑
14 ↓
15 ↑
15 ↓
16 ↑
16 ↓
Remarks 1. n: Integer of 0 to 39
2. ↑A: Pulse rises in the middle of A line output.
3. ↓A: Pulse rises at the beginning of A line output.
4. A: PWM pulse width (A/16)
50
Data Sheet S15726EJ2V0DS
µPD161401
5.7.2 Grayscale palette
The µPD161401 has 17 levels of grayscale outputs. Eight R/G output grayscales and four B output grayscales can be
selected for each of main duty display and sub-duty display, by using the grayscale data registers (R65 to R104), and
can be output as the grayscale outputs of the IC to R/G/B.
Table 5−24. Correspondence of Grayscale Levels of Grayscale Data Registers
Set Value of Grayscale Data Register
Grayscale Level
Remark
D4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
D3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
D2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
D1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
D0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Level 0
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Level 8
Level 9
Level 10
Level 11
Level 12
Level 13
Level 14
Level 15
Level 16
OFF data
50%
100%
51
Data Sheet S15726EJ2V0DS
µPD161401
5.7.3 Setting of display size
The µPD161401 can set the main duty cycles in a range of 1/80, 1/72 and 1/64 duty, the sub-duty cycles in a range of
1/48, 1/40, 1/32, 1/24 and 1/16 duty. This can be done by setting MDT6 to MDT0 and SDT6 to SDT0 of the main duty
setting register (R14) and sub-duty setting register (R17) as Table 5−25 and 5−26:
Table 5−25. Setting of Main Duty (R14)
MDT6
MDT5
MDT4
MDT3
MDT2
MDT1
MDT0
Duty
1
1
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1/80
1/72
1/64
Table 5−26. Setting of Sub-duty (R17)
SDT6
SDT5
SDT4
SDT3
SDT2
SDT1
SDT0
Duty
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/48
1/40
1/32
1/24
1/16
5.7.4 Setting of LCD N-line inversion and M-line shift
During main duty display, the shift amount of the reverse position of AC driving and the reverse position of each
display frame can be set by the main duty N-line inversion register (R15) and main duty M-line shift register (R16). They
can also be set by the sub-duty N-line inversion register (R18) and sub-duty M-line shift register (R19) during sub-duty
display.
The N-line reverse cycle function can set a line to be reversed as shown in Table 5−27, depending on the setting of
MID5 to MID0 or SID5 to SID0 of the main or sub-duty N-line inversion register.
The M-line shift amount of the reverse position of each display frame can be set as shown in Table 5−28, by using
MSD5 to MSD0 or SSD5 to SSD0 of the main or sub-duty M-line shift register.
Table 5−27. Setting of N-line Inversion Register (R15)
MID5
SID5
MID4
SID4
MID3
SID3
MID2
SID2
MID1
SID1
MID0
SID0
Reversed
Cycle
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
38
39
40
52
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−28. Setting of M-line Shift Register
MSD5
SSD5
MSD4
SSD4
MSD3
SSD3
MSD2
SSD2
MSD1
SSD1
MSD0
SSD0
Reversed Position Shift Amount
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
1
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
38
39
40
Make sure that the display size, reverse cycle, and shift amount of reverse position have the relationship indicated by
the following expression:
Display size (duty) ≥ reverse cycle ≥ reverse shift amount
53
Data Sheet S15726EJ2V0DS
µPD161401
5.7.5 Reverse driving between frames
In the µPD161401, the LCD drive waveform can be reversed and output between frames by setting the FXOR flag of
Driving mode select register (R64), as shown in Figure 5−27. This function is executed in combination with the reverse
cycle and reverse shift functions.
Figure 5−27. Image of Reversal between Pulse Width Modulation Frames
Reversal between frames not implemented (FXOR = 0)
Reverse cycle (R15, R18)
Frame n
Frame n+1
Frame n+2
Frame n+3
Reverse position shift amount (R16, R19)
Implementation of reversal between frames (FXOR = 1)
Reverse cycle (R15, R18)
Frame n
Frame n+1
Frame n+2
Frame n+3
Reverse position shift amount (R16, R19)
54
Data Sheet S15726EJ2V0DS
µPD161401
5.8 Display Mode
5.8.1 Selecting display mode
The µPD161401 has two display modes: main duty display and sub-duty display. In each of these modes, any duty
ratio can be selected and parts other than the display area can be scanned with a non-selected waveform.
The display mode can be selected by using the DTY flag of control register 2 (R1), and parameters such as the duty
ratio, bias value, and number of boosting steps are automatically selected as shown in the table below.
Display Setting
Duty ratio
Main Duty Display (DTY = 0)
Main duty setting register (R14)
Sub-duty Display (DTY = 1)
Sub-duty setting register (R17)
N-line inversion
M-line shift
Main duty N-line inversion register (R15)
Main duty M-line shift register (R16)
Power system control register 2 (R53)
VRR3 to VRR0
Sub-duty N-line inversion register (R18)
Sub-duty M-line shift register (R19)
Power system control register 2 (R53)
SVR3 to SVR0
VLCD adjustment
Bias value
Power system control register 3 (R54)
BIS2 to BIS0
Power system control register 3 (R54)
SBIS2 to SBIS0
Number of boosting steps Power system control register 4 (R55)
MBT2 to MBT0
Power system control register 4 (R55)
SBT2 to SBT0
Electronic volume
Main electronic volume register (R57)
Sub-electronic volume register (R58)
Sub R grayscale data registers (R85 to R92)
Sub G grayscale data registers (R93 to R100)
Sub B grayscale data registers (R101 to R104)
Grayscale data setting
Main R grayscale data registers (R65 to R72)
Main G grayscale data registers (R73 to R80)
Main B grayscale data registers (R81 to R84)
When the mode is changed from the main duty display mode to the sub-duty display mode or vice versa, the display
screen may be temporarily disturbed, depending on the setting of each duty mode, if electric charge remains in the
smoothing capacitor connected between the LCD drive voltage pins (VLCD, VLC1 to VLC4) and VSS. It is recommended
that the following power sequence be observed to avoid any trouble that may occur when the display mode is changed.
55
Data Sheet S15726EJ2V0DS
µPD161401
(1) Main duty display mode to sub-duty display mode
★
Operation status
Main duty display mode
↓
Control register 1
R0
Display OFF. Internal operation starts.
DISP = 0, HALT = 0
↓
Change the operation mode of the operational
amplifier to “power OFF mode”.
Power system control register 5
R56
(HPM1 = 1, HPM0 = 0)
↓
Control register 2
R1
Sub-duty display mode setting Note1
DTY = 1
Wait time 1
Wait for at least 50 ms. Note2
↓
Change the operation mode of the operational
amplifier to “power ON mode”.
Power system control register 5
R56
(HPM1 = 0, HPM0 = 1)
Wait time 2
Wait for at least 150 ms. Note2
↓
The operation mode of the operational amplifier:
“normal mode”.
Power system control register 5
R56
(HPM1 = 0, HPM0 = 0)
↓
Control register 1
R0
Display ON. Internal operation starts.
(DISP = 1, HALT = 0)
↓
Setting completed
Notes 1. A scroll function cannot be used in sub-duty display mode. In the state where the scroll function is used by
main duty display mode when it changes to sub-duty, a scroll function is disregarded. Then, when it
changes to main duty display mode again, a scroll function returns to an effective state (state before
changing to sub-duty).
2. The wait times 1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine these values after thorough evaluation
with the actual system.
56
Data Sheet S15726EJ2V0DS
µPD161401
(2) Sub-duty display mode to main duty display mode
★
Sub-duty display mode Note1
Operation status
↓
Control register 1
R0
Display OFF. Internal operation starts.
DISP = 0, HALT = 0
↓
Change the operation mode of the operational
amplifier to “power ON mode”.
Power system control register 5
R56
(HPM1 = 0, HPM0 = 1)
↓
Control register 2
R1
Main duty display mode setting
DTY = 0
Wait time
Wait for at least 160 ms. Note2
↓
The operation mode of the operational amplifier:
“normal mode”.
Power system control register 5
R56
(HPM1 = 0, HPM0 = 0)
↓
Control register 1
R0
Display ON. Internal operation starts.
(DISP = 1, HALT = 0)
↓
Setting completed
Notes 1. A scroll function cannot be used in sub-duty display mode. In the state where the scroll function is used by
main duty display mode when it changes to sub-duty, a scroll function is disregarded. Then, when it
changes to main duty display mode again, a scroll function returns to an effective state (state before
changing to sub-duty).
2. The wait time varies depending on the characteristics of the LCD panel and the capacitance of the boosting
or smoothing capacitor. It is recommended to determine this value after thorough evaluation with the actual
system.
57
Data Sheet S15726EJ2V0DS
µPD161401
5.8.2 Screen scrolling
The µPD161401 has a screen scroll function. This function is enabled during main duty display. The width of the area
to be fixed is specified by the scroll fixed area width register (R27) and the number of scroll steps is set by the scroll
step number register (R31). By these settings, other parts of screen can be scrolled with part of the screen fixed. To
specify the position of the area to be fixed, set the FIXAHL flag of the scroll fixed area position register (R23) as shown
in Table 5−29. Specify the fixed area position on the upper part of the LCD panel in master mode and on the bottom
part of the panel in slave mode.
Table 5−29. Scroll Fixed Area Width Register (R27)
FIXAW1
FIXAW0
Fixed area width
0
0
1
1
0
1
0
1
0
16
24
32
Table 5−30. Scroll Step Count Register (R31)
MST6
MST5
MST4
MST3
MST2
MST1
MST0
Number of Scroll Steps
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
1
1
1
0
0
0
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
78
79
Other settings prohibited
Note that the relationship between the number of scroll steps and the width of the scroll fixed area needs to be set so
that the following condition is set.
Number of scroll steps ≤ 79 − Width of scroll fixed area
Caution If values other than the above is set, the operation is not guaranteed.
Table 5−31. Scroll Fixed Area Position Register (R23)
FIXAHL
LCD Display Position
0
1
Bottom
Upper
58
Data Sheet S15726EJ2V0DS
µPD161401
5.8.3 Scroll setting examples
(1) Setting example 1
★
Duty: 1/64 duty
RAM read direction: normal (R0:COMR = 0)
Scroll fixed area width: 16 lines (R27: FIXAW1,0 = 0,1)
(a) Scroll fixed position: upper (R23: FIXAHL = 1)
(b) Scroll fixed position: bottom (R23: FIXAHL = 0)
Y address
Y address
00H
COM1
00H
Fixed area
COM16
0FH
Display RAM
Display RAM
COM49
COM64
30H
3FH
Fixed area
3FH
4FH
4FH
The relationships between the numbers of scroll steps and RAM Y address scan order in cases of (a) and (b) are as
follows.
(a)
Number of scroll steps: 0 (R31: MSTn = 00H)
Number of scroll steps: 1 (R31: MSTn = 01H)
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 00H → 0FH, 10H → 3FH
RAM Y address: 00H → 0FH, 11H → 40H
RAM Y address: 00H → 0FH, 1AH → 49H
(b)
Number of scroll steps: 0 (R31: MSTn = 00H)
Number of scroll steps: 1 (R31: MSTn = 01H)
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 00H → 2FH, 30H → 3FH
RAM Y address: 00H → 2FH, 40H, 30H → 3FH
RAM Y address: 0AH → 2FH, 40H → 49H, 30H → 3FH
59
Data Sheet S15726EJ2V0DS
µPD161401
(2) Setting example 2
★
Duty: 1/64 duty
RAM read direction: reverse (R0: COMR = 1)
Scroll fixed area width: 16 lines (R27: FIXAW1,0 = 0,1)
(a) Scroll fixed position: upper (R23: FIXAHL = 1)
(b) Scroll fixed position: bottom (R23: FIXAHL = 0)
Y address
Y address
00H
COM64
00H
Fixed area
0FH
COM49
Display RAM
Display RAM
COM16
COM1
30H
3FH
Fixed area
3FH
4FH
4Fh
The relationships between the numbers of scroll steps and RAM Y address scan order in cases of (a) and (b) are as
follows.
(a)
Number of scroll steps: 0 (R31: MSTn = 00H)
Number of scroll steps: 1 (R31: MSTn = 01H)
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 3FH → 10h, 0FH → 00H
RAM Y address: 40H → 11h, 0FH → 00H
RAM Y address: 49H → 1Ah, 0FH → 00H
(b)
Number of scroll steps: 0 (R31: MSTn = 00H)
Number of scroll steps: 1 (R31: MSTn = 01H)
Number of scroll steps: 10 (R31: MSTn = 0AH)
RAM Y address: 3Fh → 30H, 2FH → 00H
RAM Y address: 3Fh → 30H, 40h, 2FH → 01H
RAM Y address: 3Fh → 30hH, 49H → 40H, 2FH → 0AH
60
Data Sheet S15726EJ2V0DS
µPD161401
5.9 Reset
When the reset command is input, the IC is initialized to the default status shown in the table below. Note that
initialization by using the /DISP pin should be used only to prevent malfunctioning due to noise.
Table 5−32. Default Values of Registers (1/2)
Register
Reset Command
/DISP
Control register 1
R0
R1
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
×
Ο (DISP, TRON flag only)
Control register 2
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
X address register
R4
Y address register
R5
MIN. X address register
MAX. X address register
MIN. Y address register
MIN. Y address register
Display memory access register
Main duty setting register
R7
R8
R9
R10
R12
R14
R15
R16
R17
R18
R19
R21
R22
R23
R27
R31
R37
R38
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
×
Main duty N-line inversion register
Main duty M-line shift register
Sub-duty setting register
Sub-duty N-line inversion register
Sub-duty M-line shift register
COM scanning address setting register
Sub-duty start address register
Scroll fixed area position register
Scroll fixed area width register
Scroll steps number register
Blinking/reverse setting register
Complementary color blink X address register
Complementary color blink start line address register
Complementary color blink end line address register
Complementary color blink data memory register
Specified color blink X address register
Specified color blink start line address register
Specified color blink end line address register
Specified color blink data memory register
Specified color setting register
Ο
Ο
Ο
×
Ο
Ο
Ο
Reverse X address register
Reverse start line address register
Remark O: Default value is input. X: Default value is not input.
Cautions 1. When initialization is made using the /DISP pin, the contents of memory are not guaranteed.
In this case, use the initialized RAM. When initialization is made via the reset command, the
contents of memory are retained.
2. If the device is initialized by the /DISP pin while the serial interface is being used, the serial clock
counter is initialized.
3. Always input the reset command as the first command after power application.
61
Data Sheet S15726EJ2V0DS
µPD161401
Table 5−32. Default Values of Registers (2/2)
Register Reset Command
Reverse end line address register
/DISP
R49
R50
Ο
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
Reversed data memory access register
Power system control register 1
Power system control register 2
Power system control register 3
Power system control register 4
Power system control register 5
Main electronic volume register
Sub-electronic volume register
×
R52
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
Ο
R53
R54
R55
R56
R57
R58
RAM test mode setting register
Driving mode select register
R61
R64
Main R grayscale data registers 1 to 8
Main G grayscale data registers 1 to 8
Main B grayscale data registers 1 to 4
Sub R grayscale data registers 1 to 8
Sub G grayscale data registers 1 to 8
Sub B grayscale data registers 1 to 8
R65 to R72
R73 to R80
R81 to R84
R85 to R92
R93 to R100
R101 to R104
Remark O: Default value is input. X: Default value is not input.
Cautions 1. When initialization is made using the /DISP pin, the contents of memory are not guaranteed.
In this case, use the initialized RAM. When initialization is made via the reset command, the
contents of memory are retained.
2. If the device is initialized by the /DISP pin while the serial interface is being used, the serial clock
counter is initialized.
3. Always input the reset command as the first command after power application.
62
Data Sheet S15726EJ2V0DS
µPD161401
6. COMMANDS
The µPD161401 identifies data bus signals by a combination of the RS, /RD (E), and /WR (R,/W) signals. It interprets
and executes commands only in accordance with the internal timing, without being dependent upon the external clock.
Therefore, the processing speed is extremely high and, usually, no busy check is necessary.
An i80 system CPU interface inputs a low pulse to the /RD pin when it reads data from the µPD161401 to issue a
command. It inputs a low pulse to the /WR pin when it writes data to the µPD161401.
Data can be read from an M68 system CPU interface if a high-pulse signal is input to the R,/W pin, and written if a
low-pulse signal is input to the R,/W pin. A command is executed if a high-pulse signal is input to the E pin in this status.
Therefore, in the explanation of the commands and display commands in 6.1 Control Register 1 (R0) and the sections
that follow, the M68 system CPU interface uses H, instead of /RD (E), when reading status or display data. This is how
it differs from the i80 system CPU interface.
The commands of the µPD161401 are explained below, taking an i80 system CPU interface as an example. When the
serial interface is used, sequentially input data to the µPD161401, starting from D7.
The data bus length to input commands is as follows:
• Commands other than those that manipulate the display memory access register (R12) are input in byte units,
regardless of the value of BMOD (control register 2 (R1), bus length setting).
• The commands that manipulate the display memory access register (R12) are input in 1-byte units when BMOD = 1,
or in 2-byte units when BMOD = 0.
A. Commands other than those that manipulate display memory access register (R12)
BMOD = 1 (8-bit data bus)
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Pin
DATA
BMOD = 0 (16-bit data bus)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Pin
Note
Note
Note
Note
Note
Note
Note
Note
DATA
Note 0 or 1
B. Display memory access register (R12)
BMOD = 1 (8-bit data bus)
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Pin
DATA
BMOD = 0 (16-bit data bus)
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Pin
DATA
63
Data Sheet S15726EJ2V0DS
µPD161401
6.1 Control Register 1 (R0)
This command specifies the general operation mode of the µPD161401.
RS
1
E /RD
1
R,/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
0
TRON
WAS
COMF
DISP
STBY
HALT
ADC
COMR
TRON
WAS
0: Normal mode (all values written to the test register are ignored)
1: Test register valid mode (values written to the test register are valid)
0: Normal data write mode
1: Window access mode (Refer to 5.2.7 Arbitrary address area access (window access mode (WAS)).)
0: Normal display operation
COMF
1: All output from common pins is OFF (all the common pins output a non-selected waveform. At this time, the
segment pins output OFF data (level 0)).
DISP
STBY
HALT
0: Display OFF (All the LCD output pins output a VSS level, and the oscillator and DC/DC converter operate.)
1: Display ON
0: Normal operation
1: Internal operation and oscillation stop. Display OFF
0: Internal operation starts.
1: Internal operation stops (all the LCD output pins output a VSS level, the oscillator operates, and the DC/DC
converter stops, and the reference voltage generator operates).
Column addresses correspond to SEG outputs that are used to display the display data RAM (refer to Table 6−1).
Selects the direction in which the lines of the graphic RAM are read (refer to Table 6−2).
ADC
COMR
Table 6−1. Relationship between Column Address of Display RAM and Segment Output
SEG Output
SEG1
000H
12EH
• • •
SEG303
12EH
000H
ADC
(D1)
0
1
→
←
Column address
Column address
→
←
Table 6−2. Relationship between Common Scan Circuit and Scan Direction
COMR
(D0)
0
1
00H
4FH
→
→
4FH
00H
Default (default value of reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
D1
0
D0
0
0
64
Data Sheet S15726EJ2V0DS
µPD161401
6.2 Control Register 2 (R1)
This command specifies the general operation mode of the µPD161401.
RS
1
E
R,/W
/WR
D7
D6
D5
D4
D3
D2
D1
D0
/RD
1
0
FDM
BMOD
DTY
INC
XDIR
YDIR
FDM
Sets all screen display modes.
0: Normal operation
1: All screen display (Turns ON all screens [outputs grayscale level 16 to all screens].)
Selects data length when parallel data is input.
0: 16-bit data bus
BMOD
1: 8-bit data bus
DTY
0: Main duty display mode
1: Sub-duty display mode
INC Note
XDIR Note
0: Increments/decrements X address each time it is accessed.
1: Increments/decrements Y address each time it is accessed.
Specifies the direction in which the X address is to be accessed.
0: Increment (+1)
1: Decrement (-1)
YDIR Note
Specifies the direction in which the Y address is to be accessed.
0: Increment (+1)
1: Decrement (-1)
Note If the access direction is changed by INC, XDIR, or YDIR, be sure to set the X address register (R4) and Y
address register (R5) before accessing the display RAM.
Table 6−3. Relationship between Functions of µPD161401 and Display Mode
Display Setting
Duty
Main Duty Display (DTY = 0)
Main duty setting register (R14)
Sub-duty Display (DTY = 1)
Sub-duty setting register (R17)
N-line inversion
M-line shift
Main duty N-line inversion register (R15)
Main duty M-line shift register (R16)
Power system control register 2 (R53)
VRR3 to VRR0
Sub-duty N-line inversion register (R18)
Sub-duty M-line shift register (R19)
Power system control register 2 (R53)
SVR3 to SVR0
VLCD adjustment
Bias value
Power system control register 3 (R54)
BIS2 to BIS0
Power system control register 3 (R54)
SBIS to SBIS0
Number of boosting
steps
Power system control register 4 (R55)
MBT2 to MBT0
Power system control register 4 (R55)
SBT2 to SBT0
Electronic volume
Grayscale data
setting
Main electronic volume register (R57)
Main R grayscale data register (R65 to R72)
Main G grayscale data register (R73 to R80)
Main B grayscale data register (R81 to R84)
Sub-electronic volume register (R58)
Sub R grayscale data register (R85 to R92)
Sub G grayscale data register (R93 to R100)
Sub B grayscale data register (R101 to R104)
Default (default value of reset command)
D7
0
D6
D5
0
D4
D3
0
D2
0
D1
0
D0
0
Note
Note
Note 0 or 1
65
Data Sheet S15726EJ2V0DS
µPD161401
6.3 Reset Command Register (R3)
When this command is input, the registers of the µPD161401 (R0 to R104) are set to the default values.
RS
1
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
1
Caution At power application, be sure to input the reset command as the first command.
6.4 X Address Register (R4)
The X address register specifies the X address of the display RAM the CPU accesses. This address is automatically
incremented or decremented each time the display RAM has been accessed (INC = 0).
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
XA6
XA5
XA4
XA3
XA2
XA1
XA0
Caution If the access direction is changed by control register 2 (R1: INC, XDIR, YDIR) or window access area
is changed or set by MIN. X address register (R7, R9) and MAX. X address register (R8, R10), be sure
to set the X address register (R4) and Y address register (R5) before accessing the display RAM.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.5 Y Address Register (R5)
The Y address register specifies the Y address of the display RAM the CPU accesses. This address is automatically
incremented or decremented each time the display RAM is accessed (INC = 1).
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
YA6
YA5
YA4
YA3
YA2
YA1
YA0
YA6 to YA0
Sets line address
Caution If the access direction is changed by control register 2 (R1: INC, XDIR, YDIR), be sure to set the X
address register (R4) and Y address register (R5) before accessing the display RAM.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
66
Data Sheet S15726EJ2V0DS
µPD161401
6.6 MIN.·X Address Register (R7)
This register specifies the X address of the start point of the display RAM the CPU accesses when the window
access mode is used.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
XMN6
XMN5
XMN4
XMN3
XMN2
XMN1
XMN0
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.7 MAX.·X Address Register (R8)
This register specifies the X address of the end point of the display RAM the CPU accesses when the window access
mode is used.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
XMX6
XMX5
XMX4
XMX3
XMX2
XMX1
XMX0
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.8 MIN.·Y Address Register (R9)
This register specifies the Y address of the start point of the display RAM the CPU accesses when the window access
mode is used.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
YMN6
YMN5
YMN4
YMN3
YMN2
YMN1
YMN0
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
67
Data Sheet S15726EJ2V0DS
µPD161401
6.9 MAX.·Y Address Register (R10)
This register specifies the Y address of the end point of the display RAM the CPU accesses when the window access
mode is used.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
YMX6
YMX5
YMX4
YMX3
YMX2
YMX1
YMX0
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.10 Display Memory Access Register (R12)
The display memory access register is used to access the display RAM. When data is written to this register, it is
directly written to the display RAM. In the µPD161401, the data of the display access memory register (R12) cannot be
read.
BMOD = 1 (8-bit data bus)
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
BMOD = 0 (16-bit data bus)
RS
1
D15
D15
D14
D14
D13
D13
D12
D12
D11
D11
D10
D10
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Default value (default value of reset command)
BMOD = 1 (8-bit data bus)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
BMOD = 0 (16-bit data bus)
D15
D14
D13
D12
D11
D10
D9
D8
Note
Note
Note
Note
Note
Note
Note
Note
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
68
Data Sheet S15726EJ2V0DS
µPD161401
6.11 Main Duty Setting Register (R14)
This register can set the display duty ratio in a range of 1/80, 1/72 and 1/64 duty as shown in Table 6−5 in the main
duty display mode.
Before changing the contents of this register, be sure to stop the internal operation by using the HALT command
(control register 1 (R0)).
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
MDT6
MDT5
MDT4
MDT3
MDT2
MDT1
MDT0
Table 6−5. Main Duty Setting Register (R14)
MDT6
MDT5
MDT4
MDT3
MDT2
MDT1
MDT0
Duty
1
1
0
0
0
1
0
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1/80
1/72
1/64
Default value (default value of reset command)
D7
D6
1
D5
0
D4
0
D3
1
D2
D1
D0
Note
1
1
1
Note 0 or 1
6.12 Main Duty N-line Inversion Register (R15)
This register can set the line position of AC driving in the main duty display mode as shown in Table 6−6.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
MID5
MID4
MID3
MID2
MID1
MID0
Table 6−6. Setting of Main Duty N-line Inversion Register (R15)
MID5
MID4
MID3
MID2
MID1
MID0
Line to be reversed
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
2
3
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
38
39
40
Default value (default value of reset command)
D7
D6
D5
1
D4
0
D3
0
D2
1
D1
D0
Note
Note
1
1
Note 0 or 1
69
Data Sheet S15726EJ2V0DS
µPD161401
6.13 Main Duty M-line Shift Register (R16)
This register shifts the reverse position of each frame in the main duty display mode by the shift amount shown in
Table 6−7.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
Table 6−7. Main Duty M-line Shift Register (R16)
Shift amount of position
to be reversed
MSD5
MSD4
MSD3
MSD2
MSD1
MSD0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
1
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
38
39
40
Make sure that the relationship between the display size, reverse cycle, and reverse position is established as follows.
Display size (Duty) ≥ reverse cycle ≥ reverse shift amount
Default value (default value of reset command)
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note 0 or1
70
Data Sheet S15726EJ2V0DS
µPD161401
6.14 Sub-duty Setting Register (R17)
This register can set the display duty ratio in a range of 1/48, 1/40, 1/32, 1/24 and 1/16 as shown in Table 6−8 in the
sub-duty display mode by setting SDT6 to SDT0.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
SDT6
SDT5
SDT4
SDT3
SDT2
SDT1
SDT0
Table 6−8. Main Duty Setting Register (R17)
SDT6
SDT5
SDT4
SDT3
SDT2
SDT1
SDT0
Duty
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/48
1/40
1/32
1/24
1/16
Default value (default value of reset command)
D7
D6
0
D5
1
D4
0
D3
1
D2
D1
D0
Note
1
1
1
Note 0 or 1
71
Data Sheet S15726EJ2V0DS
µPD161401
6.15 Sub-duty N-line Inversion Register (R18)
This register can set the line position of driving in the sub-duty display mode as shown in Table 6−9.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
SID5
SID4
SID3
SID2
SID1
SID0
Table 6−9. Sub-duty N-line Inversion Register (R18)
SID5
SID4
SID3
SID2
SID1
SID0
Line to be reversed
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
2
3
4
1
1
1
0
0
0
0
0
0
1
1
1
0
1
1
1
0
1
38
39
40
Caution Please protect the following relations.
Sub-duty display size (duty) ≥ sub-duty reversed line
If this relation is not protected, the operation is not guaranteed.
However, when the above-mentioned relation is not protected, inside µPD161401, processing which makes
reversed line equal to display size is carried out. In addition, the value of a register is not rewritten
automatically.
Default value (default value of reset command)
D7
D6
D5
1
D4
0
D3
0
D2
1
D1
1
D0
1
Note
Note
Note 0 or 1
72
Data Sheet S15726EJ2V0DS
µPD161401
6.16 Sub-duty M-line Shift Register (R19)
This register shifts the reverse position of each frame in the sub-duty display mode by the shift amount shown in
Table 6−10.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
Table 6−10. Sub-duty M-line Shift Register (R19)
SSD5
SSD4
SSD3
SSD2
SSD1
SSD0
Shift amount of position to be reversed
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
1
1
1
0
0
0
0
0
1
1
1
0
1
1
0
0
1
0
38
39
40
Make sure that the relationship between the display size, reverse cycle, and reverse position is established as follows.
Display size (duty) ≥ reverse cycle ≥ reverse shift amount
Default value (default value of reset command)
D7
D6
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note 0 or 1
73
Data Sheet S15726EJ2V0DS
µPD161401
6.17 COM Scanning Address Setting Register (R21)
This command specifies that scanning of the common outputs can be started from any of the On (n = 1 to 80) output
pins. Set the CSA4 to CSA0 bits as shown in Table 6−11 (1/2). The scan start pin can be specified by the value n
obtained from this table and the selected duty shown in Table 6−11 (2/2). The common wiring on the LCD panel can be
optimized according to the selected duty.
Tables 6−12, 6−13, and 6−14 indicate examples of the COM scan address settings for 1/64 duty, 1/72 duty, and 1/80
duty.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
CSA4
CSA3
CSA2
CSA1
CSA0
Table 6−11. COM Scanning Address Setting Register (1/2)
CSA4
CSA3
CSA2
CSA1
CSA0
n
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
2
3
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
0
1
15
16
17
Other settings prohibited
Table 6−11. COM Scanning Address Setting Register (2/2)
COMR = 0
COMR = 1
Scanning start
(COM1) pin
On
Scanning end
(COMa) Note pin
O(n+a−1) Note
Scanning start
(COM1) pin
O(82−a−n)
Scanning end
(COMa) Note pin
O(80−n+1) Note
→
→
→
→
Note a = 64: 1/64 duty
a = 72: 1/72 duty
a = 80: 1/80 duty
Caution Set the COM scan address setting register so that the scan start pin and scan end pin satisfy the
equation below. If a value that exceeds this condition is set, the µPD161401 operation is not
guaranteed.
O1 ≤ Scan start pin and scan end pin ≤ O80
74
Data Sheet S15726EJ2V0DS
µPD161401
Table 6−12. Example of COM Scanning Address Setting (1/64 duty)
COMR = 0
COMR = 1
Scanning start
(COM1) pin
→
Scanning end
(COMa) Note pin
Scanning start
(COM1) pin
→
Scanning end
(COMa) Note pin
CSA4
CSA3
CSA2
CSA1
CSA0
n
On
→
O(n+a−1) Note
O(82−a−n)
→
O(80−n+1) Note
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
O1
O2
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
O64
O65
O66
O67
O68
O69
O70
O71
O72
O73
O74
O75
O76
O77
O78
O79
O80
O17
O16
O15
O14
O13
O12
O11
O10
O9
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
→
O80
O79
O78
O77
O76
O75
O74
O73
O72
O71
O70
O69
O68
O67
O66
O65
O64
3
O3
4
O4
5
O5
6
O6
7
O7
8
O8
9
O9
10
11
12
13
14
15
16
17
O10
O11
O12
O13
O14
O15
O16
O17
O8
O7
O6
O5
O4
O3
O2
O1
Note a = 64 at 1/64 duty
75
Data Sheet S15726EJ2V0DS
µPD161401
Table 6−13. Example of COM Scanning Address Setting (1/72 duty)
COMR = 0
COMR = 1
Remark
Scanning start → Scanning end
Scanning start
(COM1) pin
→
Scanning end
(COMa) Note pin
CSA4
CSA3
CSA2
CSA1
CSA0
n
(COM1) pin
(COMa) Note pin
On
→
O(n+a−1) Note
O(82−a−n)
→
O(80−n+1) Note
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
1
2
O1
O2
O3
O4
O5
O6
O7
O8
O9
→
→
→
→
→
→
→
→
→
O72
O73
O74
O75
O76
O77
O78
O79
O80
O9
O8
O7
O6
O5
O4
O3
O2
O1
→
→
→
→
→
→
→
→
→
O80
O79
O78
O77
O76
O75
O74
O73
O72
3
4
5
6
7
8
9
10
Other settings
prohibited
Note a = 72 at 1/72 duty
Caution Set the COM scan address setting register (R21) so that O1 ≤ scan start pin and scan end pin ≤ O80. If a
value that exceeds this condition is set, the µPD161401 operation is not guaranteed
Table 6−14. Example of COM Scanning Address Setting (1/80 duty)
COMR = 0
COMR = 1
Remark
Scanning
start
→
Scanning end
(COMa) Note pin
Scanning start
→
Scanning end
(COMa) Note pin
CSA4 CSA3 CSA2 CSA1
CSA0
n
(COM1) pin
(COM1) pin
On
→
→
O(n+a−1) Note
O(82−a−n)
→
→
O(80−n+1) Note
0
0
0
0
0
0
0
0
0
1
1
2
O1
O80
O1
O80
Other settings
prohibited
Note a = 80 at 1/80 duty
Caution When the µPD161401 is used in 1/80 duty, set the COM scan address setting register (R21) to CSA4,
CSA3, CSA2, CSA1, CSA0 = 0, 0, 0, 0, 0. If any other settings are made, the µPD161401 operation is not
guaranteed.
Default value (default value of reset command)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note 0 or 1
76
Data Sheet S15726EJ2V0DS
µPD161401
6.18 Sub-duty Start Address Register (R22)
The sub-duty start address register specifies the start address of the display RAM the CPU accesses to use the sub-
duty display mode. The sub-duty display area starts from this start line address and consists of the number of lines
specified by the sub-duty setting register (R17).
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
Table 6−15. Sub-duty Start Address Register
SSA6
SSA5
SSA4
SSA3
SSA2
SSA1
SSA0
Common
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
COM1
COM2
COM3
COM4
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
0
1
COM78
COM79
COM80
Make sure that SSA (R22) and SDT (R17) have in the following relationship.
SSAn + SDTn ≤ MDT ≤ 4FH
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
77
Data Sheet S15726EJ2V0DS
µPD161401
6.19 Scroll Fixed Area Position Register (R23)
This command specifies the display position of the scroll fixed area to upper or bottom of side in LCD panel.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
FIXAHL
Table 6−16. Scroll Fixed Position Register (R23)
FIXAHL
Display Position
0
1
bottom
upper
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
Note
D0
Note
Note
Note
Note
Note
Note
1
Note 0 or 1
6.20 Scroll Fixed Area Width Register (R27)
This register selects the width of the area to be fixed from 0, 16, 24, and 32 lines.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
FIXAW1
FIXAW0
Table 4−16. Scroll Fixed Area Width Register (R27)
FIXAW1
FIXAW0
Fixed Area Width
0
0
1
1
0
1
0
1
0
16
24
32
Even if the screen display size is changed by the duty setting register (R14 and R17), FIXAW1 and FIXAW0 are not
overwritten.
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
D1
0
D0
0
Note
Note
Note
Note
Note
Note
Note 0 or 1
78
Data Sheet S15726EJ2V0DS
µPD161401
6.21 Scroll Step Number Register (R31)
This register sets the number of scroll steps when the scroll function is used.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
MST6
MST5
MST4
MST3
MST2
MST1
MST0
Table 6−18. Scroll Step Number Register (R31)
MST6
MST5
MST4
MST3
MST2
MST1
MST0
Number of Scroll Steps
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
1
2
3
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
77
78
79
Other settings prohibited
Caution The relationship between the number of scroll steps and scroll fixed area width should be as follows.
Number of scroll steps ≤ 79 − Scroll fixed area width
If values exceeding the above condition are set, the operation is not guaranteed.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
79
Data Sheet S15726EJ2V0DS
µPD161401
6.22 Blink/Reverse Setting Register (R37)
This register controls blink display or reverse display. Blink display is controlled by the BLD1 and BLD0 flags of this
register, and reverse display is controlled by the INV flag, as shown in the table below.
The condition of each of the blink and reverse display areas is individually set by R38 to R50.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
INV
BLD1
BLD0
Table 6−19. Blink/Reverse Display Control
INV
0
Display
Reverse display OFF
Reverse display ON
1
BLD1
Display
0
1
Specified-color blink display OFF
Specified-color blink display ON
BLD0
Display
0
1
Complementary-color blink display OFF
Complementary-color blink display ON
Default value (default value of reset command)
D7
D6
D5
D4
D3
0
D2
D1
0
D0
0
Note
Note
Note
Note
Note
Note 0 or 1
6.23 Complementary Color Blink X Address Register (R38)
The complementary color blink X address register specifies the X address of the complementary color blink RAM the
CPU accesses. This address is automatically incremented each time the complementary color blink data RAM is
accessed.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
CBX3
CBX2
CBX1
CBX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note
Note 0 or 1
80
Data Sheet S15726EJ2V0DS
µPD161401
6.24 Complementary Color Blink Start Line Address Register (R39)
The complementary color blink start line address register specifies the start line address the CPU accesses to use
complementary color blinking display. The range of the complementary color blink lines is determined by this register
and the complementary color blink end line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
CBS6
CBS5
CBS4
CBS3
CBS2
CBS1
CBS0
CBS6 to CBS0
Sets a start line address
Caution Make sure that CBS [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.25 Complementary Color Blink End Line Address Register (R40)
The complementary color blink end line address register specifies the end line address the CPU accesses to use
complementary color blink display. The range of the complementary color blink lines is determined by this register and
the complementary color blink start line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
CBE6
CBE5
CBE4
CBE3
CBE2
CBE1
CBE0
CBE6 to CBE0
Sets an end line address
Caution Make sure that CBE [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
81
Data Sheet S15726EJ2V0DS
µPD161401
6.26 Complementary Color Blink Data Memory Register (R41)
The complementary color blink data memory register is used to access the complementary color blink data RAM.
If this register is accessed for write, data is directly written to the complementary color blink data RAM.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Data
Status
0
1
Normal
Complementary color blinking
Default value (default value of reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
6.27 Specified Color Blink X Address Register (R42)
The specified color blink X address register specifies the X address of the specified color blinking RAM the CPU
accesses. This address is automatically incremented each time the specified color blink data RAM is accessed.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
SBX3
SBX2
SBX1
SBX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note
Note 0 or 1
82
Data Sheet S15726EJ2V0DS
µPD161401
6.28 Specified Color Blink Start Line Address Register (R43)
The specified color blink start line address register specifies the start line address the CPU accesses to use specified
color blinking display. The range of the specified color blink lines is determined by this register and the specified color
blinking end line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
SBS6
SBS5
SBS4
SBS3
SBS2
SBS1
SBS0
SBS6 to SBS0 Sets a start line address.
Caution Make sure that SBS [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.29 Specified Color Blink End Line Address Register (R44)
The specified color blink end line address register specifies the end line address the CPU accesses to use specified
color blink display. The range of the specified color blink lines is determined by this register and the specified color blink
start line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
SBE6
SBE5
SBE4
SBE3
SBE2
SBE1
SBE0
SBE6 to SBE0 Sets an end line address.
Caution Make sure that SBE [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
83
Data Sheet S15726EJ2V0DS
µPD161401
6.30 Specified Color Blink Data Memory Register (R45)
The specified color blink data memory register is used to access the specified color blink data RAM. If this register is
accessed for write, data is directly written to the specified color blink data RAM.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Data
Status
0
1
Normal
Specified color blinking
Default value (default value of reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
6.31 Specified Color Setting Register (R46)
This register sets specified color data when the specified color blink function is used. The data between this data and
the display RAM data blinks in a specified color.
RS
1
D7
D7
D6
D6
R
D5
D5
D4
D4
D3
D3
G
D2
D2
D1
D1
D0
D0
Remark
B
In 256-color mode
Default value (default value of reset command, all data)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
6.32 Reverse X Address Register (R47)
The reverse X address register specifies the X address of the reverse data RAM the CPU accesses. This address is
incremented each time the reverse RAM has been accessed.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
IVX3
IVX2
IVX1
IVX0
Default value (default value of reset command)
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note
Note 0 or 1
84
Data Sheet S15726EJ2V0DS
µPD161401
6.33 Reverse Start Line Address Register (R48)
The reverse start line address register specifies start line address of the display RAM the CPU accesses for reverse
display. The range of the reverse lines is determined by this register and the reverse end line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
IVS6
IVS5
IVS4
IVS3
IVS2
IVS1
IVS0
IVS6 to IVS0
Sets a start line address.
Caution Make sure that IVS [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.34 Reverse End Line Address Register (R49)
The reverse end line address register specifies the end line address of the display RAM the CPU accesses for reverse
display. The range of the reverse lines is determined by this register and the reverse start line address register.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
IVE6
IVE5
IVE4
IVE3
IVE2
IVE1
IVE0
IVE6 to IVE0
Sets an end line address.
Caution Make sure that IVE [6:0] ≤ 4FH. If 4FH is exceeded, operation is not guaranteed.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
85
Data Sheet S15726EJ2V0DS
µPD161401
6.35 Reverse Data Memory Access Register (R50)
The reverse data memory access register is used to access the reverse data RAM. When this register is accessed for
write, data is directly written to the reverse data RAM.
RS
1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
Setting
Data
Status
0
1
Normal
Reverse
Default value (default value of reset command, all data)
D7
D6
D5
D4
D3
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
86
Data Sheet S15726EJ2V0DS
µPD161401
6.36 Power System Control Register 1 (R52)
This command sets the power system mode of the µPD161401.
E
R,/W
/WR
RS
1
/RD
D7
D6
D5
D4
D3
D2
D1
D0
1
0
TCS2
TCS1
TCS0
OP3
OP2
OP1
OP0
TCS2 to TCS0 These bits set the value that selects the temperature curve of the VREG voltage to a value shown in Table 6−20.
OP3 to OP0
These bits turn ON/OFF the booster circuit, reference voltage generator, control the voltage regulator circuit (V
regulator circuit) and voltage follower circuit (V/F circuit). The functions controlled by these four-power control
set command controlled by these 4 bits are listed in Table 6−21.
Table 6−20. VREG Voltage Temperature Curve Value
TCS2
TCS1
TCS0
Status
Temperature Gradient (unit: %/°C)
VREG (TYP.) (unit: V)
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
–0.12
–0.13
–0.15
–0.17
−
1.77
1.69
1.63
1.59
−
Internal power supply
When external reference
power supply is used
Table 6−21. Details of Control by Each Bit of Power System Control Register
Status
Item
1
0
OP3
OP2
OP1
OP0
: Booster circuit control bit
ON
ON
ON
ON
OFF
OFF
OFF
OFF
: Reference voltage generator control bit
: Voltage regulator circuit (V regulator circuit) control bit
: Voltage follower circuit (V/F circuit) control bit
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
87
Data Sheet S15726EJ2V0DS
µPD161401
6.37 Power System Control Register 2 (R53)
This command sets the power system mode of the µPD161401.
E
R,/W
/WR
RS
1
/RD
D7
D6
D5
D4
D3
D2
D1
D0
Setting
1
0
VRR3
VRR2
VRR1
VRR0
SVR3
SVR2
SVR1
SVR0
VRR3 to VRR0
SVR3 to SVR0
When the main duty display mode is used, the resistance ratio can be changed in 16 steps by the VLCD internal
resistance ratio adjustment command. Four bits of the VLCD internal resistance ratio adjustment register set the
reference value of (1 + Rb/Ra) to the value shown in Table 6−22.
When the sub-duty display mode is used, the resistance ratio can be changed in 16 steps by the VLCD internal
resistance ratio adjustment command. Four bits of the VLCD internal resistance ratio adjustment register set the
reference value of (1 + Rb/Ra) to the value shown in Table 6−22.
Table 6-22. VLCD Internal Resistance Ratio Adjustment Register
Register
VRR3
SVR3
VRR2
SVR2
VRR1
SVR1
VRR0
SVR0
1 + Rb/Ra
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Default value (default value of reset command)
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
88
Data Sheet S15726EJ2V0DS
µPD161401
6.38 Power System Control Register 3 (R54)
This command sets the bias value for main duty display and sub-duty display by the µPD161401.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
BIS2
BIS1
BIS0
SBIS2
SBIS1
SBIS0
BIS2 to BIS0 Note
These flags select the bias ratio in the main duty display mode as follows:
BIS2
BIS1
BIS0
Bias Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/9 bias
1/8 bias
1/7 bias
1/6 bias
1/5 bias
Prohibited
Prohibited
Prohibited
SBIS2 to SBIS0Note
These flags select the bias ratio in the sub-duty display mode as follows:
SBIS2
SBIS1
SBIS0
Bias Ratio
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1/9 bias
1/8 bias
1/7 bias
1/6 bias
1/5 bias
Prohibited
Prohibited
Prohibited
Note Before changing these flags, execute the HALT command.
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
D2
0
D1
0
D0
0
Note
Note
Note 0 or 1
89
Data Sheet S15726EJ2V0DS
µPD161401
6.39 Power System Control Register 4 (R55)
This command sets the number of boosting steps for main duty display and sub-duty display of µPD161401 as shown
in Table 6−23.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
MBT2
MBT1
MBT0
SBT2
SBT1
SBT0
Table 6−23. Number of Boosting Steps for Main/Sub-duty Display of Booster Circuit
MBT2
MBT1
MBT0
Number of Boosting Steps (unit: fold)
SBT2
SBT1
SBT0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Two
Three
Four
Five
Six
Seven
Prohibited
Prohibited
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
D2
0
D1
0
D0
0
Note
Note
Note 0 or 1
90
Data Sheet S15726EJ2V0DS
µPD161401
6.40 Power System Control Register 5 (R56)
This command sets the status of the voltage follower circuit of the µPD161401 that drives the LCD, as follows:
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
LCS1
LCS0
LCC1
LCC0
HPM1
HPM0
PSM1
PSM0
Table 6−24. Setting of Segment Output Driving Capability (LCS1, LCS0 = 0, 0)
LCS1
LCS0
Segment Output Driving Capability
(unit: fold)
0
0
1
1
0
1
0
1
One
Two
Four
Eight
Table 6−25. Setting of Common Output Driving Capability (LCS1, LCS0 = 0, 0)
LCC1
LCC0
Common Output Driving Capability
(unit: fold)
0
0
1
1
0
1
0
1
Two
Four
Eight
Sixteen
Table 6−26. Setting of Operational Amplifier Operation Mode
HPM1
HPM0
Mode Setting
0
0
1
1
0
1
0
1
Normal mode
Power ON mode1
Power OFF mode
Power ON mode2
Table 6−27. Setting of Two-fold Supply Voltage (VLC3, VLC4 Level Voltage Follower Power Supply)
PSM1
Mode Setting
0
1
Not used
used
Table 6−28. Setting of Voltage Follower Bias Current
PSM0
Bias Current Setting
(unit: fold)
0
1
One
Two
Default value (default value of reset command)
D7
0
D6
0
D5
0
D4
1
D3
0
D2
0
D1
1
D0
0
91
Data Sheet S15726EJ2V0DS
µPD161401
6.41 Main Electronic Volume Register (R57)
The main electronic volume register specifies the electronic volume value for adjusting the contrast in the main duty
display mode, in 128 steps.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
MEV6
MEV5
MEV4
MEV3
MEV2
MEV1
MEV0
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
6.42 Sub-electronic Volume Register (R58)
The sub-electronic volume register specifies an electronic volume value for adjusting the contrast in the sub-duty
display mode, in 128 steps.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
SEV6
SEV5
SEV4
SEV3
SEV2
SEV1
SEV0
Default value (default value of reset command)
D7
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note 0 or 1
92
Data Sheet S15726EJ2V0DS
µPD161401
6.43 RAM Test Mode Setting Register (R61)
The RAM test mode setting register directly writes the data of each display status to the display RAM as shown in
Table 6−29.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
RTS2
RTS1
RTS0
Table 6−29. RAM Test Mode
RTS0 Write Data
RTS2
RTS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
Normal operation
1
0
1
0
1
0
1
all [00000000] / pixel display
all [11111111] / pixel display
Checker pattern display of [00000000] / [11111111]
Vertical grayscale bar display
Horizontal grayscale bar display
Each color grayscale display
256-color display
Default value (default value of reset command)
D7
D6
D5
D4
D3
D2
0
D1
0
D0
0
Note
Note
Note
Note
Note
Note 0 or 1
6.44 Driving Mode Select Register (R64)
The FXOR flag of the drive mode select register controls the reversal of the LCD drive waveform between frames as
shown in Table 6−30. Note that the reverse function is executed between frames regardless of the FXOR flag during
sub-duty display.
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
FXOR
Table 6−30. Driving Mode Select Register (R64)
FXOR
Reversing Between Frames
0
1
OFF
ON
Default value (default value of reset command)
D7
D6
D5
D4
D3
0
D2
D1
D0
Note
Note
Note
Note
Note
Note
Note
Note 0 or 1
93
Data Sheet S15726EJ2V0DS
µPD161401
6.45 Main R Grayscale Data Registers (R65 to R72)
The main R grayscale data registers specify the grayscale level of the R output in the main duty display mode. By
using these registers, grayscale display can be optimized.
Rx
Data
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
R65
R66
R67
R68
R69
R70
R71
R72
0, 0, 0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
MRG4
MRG4
MRG4
MRG4
MRG4
MRG4
MRG4
MRG4
MRG3
MRG3
MRG3
MRG3
MRG3
MRG3
MRG3
MRG3
MRG2
MRG2
MRG2
MRG2
MRG2
MRG2
MRG2
MRG2
MRG1
MRG1
MRG1
MRG1
MRG1
MRG1
MRG1
MRG1
MRG0
MRG0
MRG0
MRG0
MRG0
MRG0
MRG0
MRG0
1
1
1
1
1
1
1
D7
×
D6
×
D5
×
D4
0
D3
0
D2
0
D1
0
D0
0
Grayscale Level
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
×
×
×
0
1
1
0
1
0
1
0
1
0
Level 15
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note 0 or 1
94
Data Sheet S15726EJ2V0DS
µPD161401
6.46 Main G Grayscale Data Registers (R73 to R80)
The main G grayscale data registers specify the grayscale level of the G output in the main duty display mode. By
using these registers, grayscale display can be optimized.
Rx
Data
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
R73
R74
R75
R76
R77
R78
R79
R80
0, 0, 0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
MGG4
MGG4
MGG4
MGG4
MGG4
MGG4
MGG4
MGG4
MGG3
MGG3
MGG3
MGG3
MGG3
MGG3
MGG3
MGG3
MGG2
MGG2
MGG2
MGG2
MGG2
MGG2
MGG2
MGG2
MGG1
MGG1
MGG1
MGG1
MGG1
MGG1
MGG1
MGG1
MGG0
MGG0
MGG0
MGG0
MGG0
MGG0
MGG0
MGG0
1
1
1
1
1
1
1
D7
×
D6
×
D5
×
D4
0
D3
0
D2
0
D1
0
D0
0
Grayscale Level
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
×
×
×
0
1
1
0
1
0
1
0
1
0
Level 15
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note 0 or 1
95
Data Sheet S15726EJ2V0DS
µPD161401
6.47 Main B Grayscale Data Registers (R81 to R84)
The main B grayscale data registers specify the grayscale level of the B output in the main duty display mode. By
using these registers, grayscale display can be optimized.
Rx
Data
0, 0
0, 1
1, 0
1, 1
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
R81
R82
R83
R84
MBG4
MBG4
MBG4
MBG4
MBG3
MBG3
MBG3
MBG3
MBG2
MBG2
MBG2
MBG2
MBG1
MBG1
MBG1
MBG1
MBG0
MBG0
MBG0
MBG0
1
1
1
D7
×
D6
×
D5
×
D4
0
D3
0
D2
0
D1
0
D0
0
Grayscale Level
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
×
×
×
0
1
1
0
1
0
1
0
1
0
Level 15
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note 0 or 1
96
Data Sheet S15726EJ2V0DS
µPD161401
6.48 Sub R Grayscale Data Registers (R85 to R92)
The sub R grayscale data registers specify the grayscale level of the R output in the sub-duty display mode. By using
these registers, grayscale display can be optimized.
Rx
Data
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
R85
R86
R87
R88
R89
R90
R91
R92
0, 0, 0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
SRG4
SRG4
SRG4
SRG4
SRG4
SRG4
SRG4
SRG4
SRG3
SRG3
SRG3
SRG3
SRG3
SRG3
SRG3
SRG3
SRG2
SRG2
SRG2
SRG2
SRG2
SRG2
SRG2
SRG2
SRG1
SRG1
SRG1
SRG1
SRG1
SRG1
SRG1
SRG1
SRG0
SRG0
SRG0
SRG0
SRG0
SRG0
SRG0
SRG0
1
1
1
1
1
1
1
D7
×
D6
×
D5
×
D4
0
D3
0
D2
0
D1
0
D0
0
Grayscale Level
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
×
×
×
0
1
1
0
1
0
1
0
1
0
Level 15
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note 0 or 1
97
Data Sheet S15726EJ2V0DS
µPD161401
6.49 Sub G Grayscale Data Registers (R93 to R100)
The sub G grayscale data registers specify the grayscale level of the G output in the sub-duty display mode. By using
these registers, grayscale display can be optimized.
Rx
R93
R94
R95
R96
R97
R98
R99
R100
Data
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
0, 0, 0
0, 0, 1
0, 1, 0
0, 1, 1
1, 0, 0
1, 0, 1
1, 1, 0
1, 1, 1
SGG4
SGG4
SGG4
SGG4
SGG4
SGG4
SGG4
SGG4
SGG3
SGG3
SGG3
SGG3
SGG3
SGG3
SGG3
SGG3
SGG2
SGG2
SGG2
SGG2
SGG2
SGG2
SGG2
SGG2
SGG1
SGG1
SGG1
SGG1
SGG1
SGG1
SGG1
SGG1
SGG0
SGG0
SGG0
SGG0
SGG0
SGG0
SGG0
SGG0
1
1
1
1
1
1
1
D7
×
D6
×
D5
×
D4
0
D3
0
D2
0
D1
0
D0
0
Grayscale Level
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
×
×
×
0
1
1
0
1
0
1
0
1
0
Level 15
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note 0 or 1
98
Data Sheet S15726EJ2V0DS
µPD161401
6.50 Sub B Grayscale Data Registers (R101 to R104)
The sub B grayscale data registers specify the grayscale level of the B output in the sub-duty display mode. By using
these registers, grayscale display can be optimized.
Rx
Data
0, 0
0, 1
1, 0
1, 1
RS
1
D7
D6
D5
D4
D3
D2
D1
D0
Setting
R101
R102
R103
R104
SBG4
SBG4
SBG4
SBG4
SBG3
SBG3
SBG3
SBG3
SBG2
SBG2
SBG2
SBG2
SBG1
SBG1
SBG1
SBG1
SBG0
SBG0
SBG0
SBG0
1
1
1
D7
×
D6
×
D5
×
D4
0
D3
0
D2
0
D1
0
D0
0
Grayscale Level
Level 0
×
×
×
0
0
0
0
1
Level 1
×
×
×
0
0
0
1
0
Level 2
×
×
×
0
0
0
1
1
Level 3
×
×
×
×
×
×
0
1
1
0
1
0
1
0
1
0
Level 15
Level 16
Default value (default value of reset command, common to all grayscale data registers)
D7
D6
D5
D4
0
D3
0
D2
0
D1
0
D0
0
Note
Note
Note
Note 0 or 1
99
Data Sheet S15726EJ2V0DS
µPD161401
7. µPD161401 REGISTER LIST
(1/2)
Index Register
Data Bit
3
CS
RS
Register Name
R/W
W
6
5
4
3
2
1
0
7
6
5
4
2
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
IR
Index Register
IR6
IR5
IR4
IR3
IR2
IR1
IR0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
Control Register 1
Control Register 2
R/W TRON WAS COMF DISP STBY HALT
ADC COMR
R/W
FDM
BMOD
DTY
INC
XDIR
YDIR
Reset Command
W
RES
XA0
YA0
X Address Register
Y Address Register
R/W
R/W
XA6
YA6
XA5
YA5
XA4
YA4
XA3
YA3
XA2
YA2
XA1
YA1
MIN.·X Address Register
MAX. X Address Register
MIN. Y Address Register
R/W
R/W
R/W
R/W
XMN6 XMN5 XMN4 XMN3 XMN2 XMN1 XMN0
XMX6 XMX5 XMX4 XMX3 XMX2 XMX1 XMX0
YMN6 YMN5 YMN4 YMN3 YMN2 YMN1 YMN0
YMX6 YMX5 YMX4 YMX3 YMX2 YMX1 YMX0
R10 MAX. Y Address Register
R11
R12 Display Memory Access Register
D15
D7
D14
D6
D13
D5
D15
D4
D11
D3
D10
D2
D9
D1
D8
D0
W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R13
R14 Main Duty Setting Register
R/W
R/W
R/W
R/W
R/W
R/W
MDT6 MDT5 MDT4 MDT3 MDT2 MDT1 MDT0
MID5 MID4 MID3 MID2 MID1 MID0
MSD5 MSD4 MSD3 MSD2 MSD1 MSD0
R15 Main Duty N-line Inversion Register
R16 Main Duty M-line Shift Register
R17 Sub-duty Setting Register
SDT6 SDT5 SDT4 SDT3 SDT2 SDT1
SID5 SID4 SID3 SID2 SID1
SDT0
SID0
R18 Sub-duty N-line Inversion Register
R19 Sub-duty M-line Shift Register
SSD5 SSD4 SSD3 SSD2 SSD1 SSD0
R20
R21 COM Scanning Address Setting Register
R/W
R/W
R/W
CSA4 CSA3 CSA2 CSA1 CSA0
R22 Sub-duty Start Address Register
SSA6 SSA5 SSA4 SSA3 SSA2 SSA1
SSA0
R23 Scroll Fixed Area Position Register
FIXAHL
R24
R25
R26
R27 Scroll Fixed Area Width Register
R/W
R/W
FIXAW1 FIXAW0
R28
R29
R30
R31 Scroll Step Number Register
MST6 MST5 MST4 MST3 MST2 MST1 MST0
R32
R33
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R34
R35
R36
R37 Blink/Reverse Setting Register
R/W
INV
BLD1
BLD0
R38 Complementary Color Blink X Address Register R/W
CBX3 CBX2 CBX1 CBX0
CBS6 CBS5 CBS4 CBS3 CBS2 CBS1 CBS0
CBE6 CBE5 CBE4 CBE3 CBE2 CBE1 CBE0
R39 Complementary Color Blink Start Line Address Register
R40 Complementary Color Blink End Line Address Register
R41 Complementary Color Blink Data Memory Register
R42 Specified Color Blinking X Address Register
R43 Specified Color Blink Start Line Address Register
R44 Specified Color Blink End Line Address Register
R45 Specified Color Blink Data Memory Register
R46 Specified Color Setting Register
R47 Reverse X Address Register
R48 Reverse Start Line Address Register
R49 Reverse End Line Address Register
R50 Reverse Data Memory Access Register
R51
R/W
R/W
W
D7
D6
D5
D4
D3
D2
D1
D0
SBX0
SBS0
SBE0
D0
R/W
R/W
R/W
W
SBX3 SBX2 SBX1
SBS6 SBS5 SBS4 SBS3 SBS2 SBS1
SBE6 SBE5 SBE4 SBE3 SBE2 SBE1
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
R/W
R/W
R/W
R/W
W
D0
IVX3 IVX2
IVX1
IVS1
IVE1
D1
IVX0
IVS0
IVE0
D0
IVS6 IVS5 IVS4 IVS3 IVS2
IVE6 IVE5 IVE4 IVE3 IVE2
D7
D6
D5
D4
D3
D2
R52 Power System Control Register 1
R53 Power System Control Register 2
R54 Power System Control Register 3
R55 Power System Control Register 4
R56 Power System Control Register 5
R57 Main Electronic Volume Register
R58 Sub-electronic Volume Register
R59
R/W
TCS2 TCS1 TCS0 OP3
OP2
OP1
OP0
R/W VRR3 VRR2 VRR1 VRR0 SVR3 SVR2 SVR1 SVR0
R/W
R/W
BIS2 BIS1 BIS0
MBT2 MBT1 MBT0
SBIS2 SBIS1 SBIS0
SBT2 SBT1 SBT0
R/W LCS1 LCS0 LCC1 LCC0 HPM1 HPM0 PSM1 PSM0
R/W
R/W
MEV6 MEV5 MEV4 MEV3 MEV2 MEV1 MEV0
SEV6 SEV5 SEV4 SEV3 SEV2 SEV1
RTS2 RST1
SEV0
RST0
R60
R61 RAM Test Mode Setting Register
R62
R/W
R63
100
Data Sheet S15726EJ2V0DS
µPD161401
(2/2)
Index Register
Data Bit
CS
RS
Register Name
R/W
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IR
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R64
R65
R66
R67
R68
R69
R70
R71
R72
R73
R74
R75
R76
R77
R78
R79
R80
R81
R82
R83
R84
R85
R86
R87
R88
R89
R90
R91
R92
R93
R94
R95
R96
R97
R98
R99
Driving Mode Select Register
FXOR
Main R Grayscale Data Register 1 (0, 0, 0)
Main R Grayscale Data Register 2 (0, 0, 1)
Main R Grayscale Data Register 3 (0, 1, 0)
Main R Grayscale Data Register 4 (0, 1, 1)
Main R Grayscale Data Register 5 (1, 0, 0)
Main R Grayscale Data Register 6 (1, 0, 1)
Main R Grayscale Data Register 7 (1, 1, 0)
Main R Grayscale Data Register 8 (1, 1, 1)
Main G Grayscale Data Register 1 (0 ,0, 0)
Main G Grayscale Data Register 2 (0, 0, 1)
Main G Grayscale Data Register 3 (0, 1, 0)
Main G Grayscale Data Register 4 (0, 1, 1)
Main G Grayscale Data Register 5 (1, 0, 0)
Main G Grayscale Data Register 6 (1, 0, 1)
Main G Grayscale Data Register 7 (1, 1, 0)
Main G Grayscale Data Register 8 (1, 1, 1)
Main B Grayscale Data Register 1 (0, 0)
Main B Grayscale Data Register 2 (0, 1)
Main B Grayscale Data Register 3 (1, 0)
Main B Grayscale Data Register 4 (1, 1)
Sub R Grayscale Data Register 1 (0, 0, 0)
Sub R Grayscale Data Register 2 (0, 0, 1)
Sub R Grayscale Data Register 3 (0, 1, 0)
Sub R Grayscale Data Register 4 (0, 1, 1)
Sub R Grayscale Data Register 5 (1, 0, 0)
Sub R Grayscale Data Register 6 (1, 0, 1)
Sub R Grayscale Data Register 7 (1, 1, 0)
Sub R Grayscale Data Register 8 (1, 1, 1)
Sub G Grayscale Data Register 1 (0, 0, 0)
Sub G Grayscale Data Register 2 (0, 0, 1)
Sub G Grayscale Data Register 3 (0, 1, 0)
Sub G Grayscale Data Register 4 (0, 1, 1)
Sub G Grayscale Data Register 5 (1, 0, 0)
Sub G Grayscale Data Register 6 (1, 0, 1)
Sub G Grayscale Data Register 7 (1, 1, 0)
MRG4 MRG3 MRG2 MRG1 MRG0
MRG4 MRG3 MRG2 MRG1 MRG0
MRG4 MRG3 MRG2 MRG1 MRG0
MRG4 MRG3 MRG2 MRG1 MRG0
MRG4 MRG3 MRG2 MRG1 MRG0
MRG4 MRG3 MRG2 MRG1 MRG0
MRG4 MRG3 MRG2 MRG1 MRG0
MRG4 MRG3 MRG2 MRG1 MRG0
MGG4 MGG3 MGG2 MGG1 MGG0
MGG4 MGG3 MGG2 MGG1 MGG0
MGG4 MGG3 MGG2 MGG1 MGG0
MGG4 MGG3 MGG2 MGG1 MGG0
MGG4 MGG3 MGG2 MGG1 MGG0
MGG4 MGG3 MGG2 MGG1 MGG0
MGG4 MGG3 MGG2 MGG1 MGG0
MGG4 MGG3 MGG2 MGG1 MGG0
MBG4 MBG3 MBG2 MBG1 MBG0
MBG4 MBG3 MBG2 MBG1 MBG0
MBG4 MBG3 MBG2 MBG1 MBG0
MBG4 MBG3 MBG2 MBG1 MBG0
SRG4 SRG3 SRG2 SRG1 SRG0
SRG4 SRG3 SRG2 SRG1 SRG0
SRG4 SRG3 SRG2 SRG1 SRG0
SRG4 SRG3 SRG2 SRG1 SRG0
SRG4 SRG3 SRG2 SRG1 SRG0
SRG4 SRG3 SRG2 SRG1 SRG0
SRG4 SRG3 SRG2 SRG1 SRG0
SRG4 SRG3 SRG2 SRG1 SRG0
SGG4 SGG3 SGG2 SGG1 SGG0
SGG4 SGG3 SGG2 SGG1 SGG0
SGG4 SGG3 SGG2 SGG1 SGG0
SGG4 SGG3 SGG2 SGG1 SGG0
SGG4 SGG3 SGG2 SGG1 SGG0
SGG4 SGG3 SGG2 SGG1 SGG0
SGG4 SGG3 SGG2 SGG1 SGG0
SGG4 SGG3 SGG2 SGG1 SGG0
SBG4 SBG3 SBG2 SBG1 SBG0
SBG4 SBG3 SBG2 SBG1 SBG0
SBG4 SBG3 SBG2 SBG1 SBG0
SBG4 SBG3 SBG2 SBG1 SBG0
R100 Sub G Grayscale Data Register 8 (1, 1, 1)
R101 Sub B Grayscale Data Register 1 (0, 0)
R102 Sub B Grayscale Data Register 2 (0, 1)
R103 Sub B Grayscale Data Register 3 (1, 0)
R104 Sub B Grayscale Data Register 4 (1, 1)
R105
R106
R107
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
R108
R109
R110
R111
R112
R113
R114
R115
R116
R117
R118
R119
R120
R121
R122
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
R123
R124
R125
R126
R127
101
Data Sheet S15726EJ2V0DS
µPD161401
8. POWER SEQUENCE
The µPD161401 has on-chip power circuits such as a booster circuit and a voltage follower circuit. Resetting by the
/DISP pin should only be used to prevent malfunctioning due to noise.
If charge remains in the smoothing capacitor connected between the LCD drive pins (VLCD, VLC1 to VLC4) and VSS, the
display screen may momentarily blackout when power is turned ON or OFF. It is therefore recommended to turn
ON/OFF power in the following sequence to avoid any trouble.
102
Data Sheet S15726EJ2V0DS
µPD161401
8.1 Power ON Sequence (with Internal Power Supply, Power ON → Display ON)
Power ON when /DISP pin = L
↓
Power supply is stabilized.
↓
/DISP pin = H
↓
Wait for 50 µs or more.
Initialization of registers
Reset command
R3
R0
↓
Control register 1
DISP = 0, HALT = 1
Display OFF. Internal operation stops.
↓
IC function setting by command input 1
Control register 1
(DISP = 0, HALT = 1)
Control register 2
↓
IC function setting by command input 2
Power system control register 1
(OP3, OP2, OP1, OP0 = 1, 1, 1, 1)
Power system control registers 2, 3, and 4
Power system control register 5
(HPM1, HPM0 = 0, 1)
Specify power ON mode 1 (master IC only).
Main electronic volume register
Sub-electronic volume register
↓
User setting by command input
Setting of functions such as grayscale data
↓
Initialization complete
↓
Control register 1
(DIPS = 0, HALT = 0)
Display OFF. Internal operation starts.
R0
↓
LCD display screen setting
Display start line set
Writing of screen data
+ Wait time
Wait time 1
★
★
Wait for 120 to 150 ms or more from when the internal
operation starts until the LCD turns ON Note
.
↓
Power system control register 5
(HPM1, HPM0 = 0, 0)
(LCS1, LCS0 = 1,1)
(LCC1, LCC0 = 1,1)
(PSM = 1)
Change the operation mode of the operation amplifier to
“normal mode” (master IC only).
Segment output driving capability setting: x8
Common output driving capability setting: x16
Voltage follower bias current: x2
↓
<A> in the next page
Note The wait times1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
103
Data Sheet S15726EJ2V0DS
µPD161401
★
<A>
Wait time 2
Wait for at least 250 ms from when the output mode of the
operation amplifier is changed until the LCD turns ON Note
↓
.
Power system control register 5
(HPM1, HPM0 = 0, 0)
(LCS1, LCS0 = x,x)
(LCC1, LCC0 = x,x)
(PSM = x)
The operation mode of the operation amplifier: normal mode
Change the setting of the segment output driving capability,
common output driving capability, and voltage follower bias
current to the normal state.
R0
R0
↓
Control register 1
(DIPS = 1, HALT = 0)
Display ON. Internal operation starts.
x: 0 or 1
Note The wait times1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
104
Data Sheet S15726EJ2V0DS
µPD161401
8.2 Power OFF Sequence (with Internal Power Supply)
Operation status
↓
Control register 1
R0
Display OFF. Internal operation starts.
DISP = 0, HALT = 0
↓
Change the operation mode of the operational
amplifier to “power OFF mode”.
Power system control register 5
R56
(HPM1, HPM0 = 1, 0)
↓
[MEV6, MEV5, MEV4, MEV3, MEV2, MEV1, MEV0]
= [0, 0, 0, 0, 0, 0, 0]
Main electronic volume register setting
R57
R58
↓
[SEV6, SEV5, SEV4, SEV3, SEV2, SEV1, SEV0]
= [0, 0, 0, 0, 0, 0, 0]
Sub-electronic volume register setting
★
★
Wait time 1
↓
Wait for at least 120 ms Note
.
Control register 1
(DISP = 0, HALT = 1)
Display OFF. Internal operation stops.
R0
Wait time 2
↓
Wait for at least 380 ms before turning power OFF Note
.
Power OFF
Note The wait times 1, 2 vary depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
105
Data Sheet S15726EJ2V0DS
µPD161401
8.3 Power ON Sequence (with External Driving Power Supply, Power ON → Display ON)
This is an example of inputting a reference voltage to the VRS pin and a driving voltage to the VOUT pin from an
external power supply.
Logic power supply ON with /DISP pin = L
VDD1 and VDD2 ON, VOUT = Hi-Z
↓
Power supply stabilized.
↓
/DISP pin = H
↓
Wait for 50 µs or more.
Reset command
R3
R0
Initialization of registers
↓
Control register 1
DISP = 0, HALT = 1
↓
Display OFF. Internal operation stops.
IC function setting by command input 1
Control register 1
(DISP = 0, HALT = 1)
Control register 2
↓
IC function setting by command input 2
Power system control register 1
(OP3, OP2, OP1, OP0 = 1, 1, 1, 1)
Power system control registers 2, 3, and 4
Power system control register 5
(HPM1, HPM0 = 0, 1)
Specify power ON mode1 (master IC only).
Main electronic volume register
Sub-electronic volume register
↓
User setting by command input
Setting of functions such as grayscale data
↓
Initialization complete
↓
Control register 1
(DISP = 0, HALT = 0)
Display OFF. Internal operation starts.
R0
↓
Turn ON external driving power supply
Supply voltage to VOUT pin.
↓
LCD screen setting
Display start line setting
Writing of screen data
+ Wait time
Wait for at least 300 ms from when the internal operation
★
starts until the LCD turns ON Note
.
↓
Power system control register 5
Change the operation mode of the operation amplifier to
“normal mode” (master IC only).
(HPM1, HPM0 = 0, 0)
↓
Control register 1
(DIPS = 1, HALT = 0)
Display ON. Internal operation starts.
R0
Note The time of 300 ms varies depending on the characteristics of the LCD panel and the capacitance of the
smoothing capacitor. It is recommended to determine this value after thorough evaluation with the actual
system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
106
Data Sheet S15726EJ2V0DS
µPD161401
8.4 Power OFF Sequence (with External Driving Power Supply)
This is an example of inputting a reference voltage to the VRS pin and a driving voltage to the VOUT pin from an
external power supply.
Operation status
↓
Control register 1
DISP = 0, HALT = 0
Display OFF. Internal operation starts.
R0
↓
Change the operation mode of the operational
amplifier to “power OFF mode”.
Power system control register 5
(HPM1, HPM0 = 1, 0)
R56
Wait for at least 300 ms until power is OFF Note
.
★
↓
Turn OFF driving voltage VOUT after the levels of VLCD
and VLC1 to VLC4 have completely dropped.
Driving power supply OFF
↓
Power OFF
Power to VDD1 and VDD2 OFF
Note The time of 300 ms varies depending on the characteristics of the LCD panel and the capacitance of the
smoothing capacitor. It is recommended to determine this value after thorough evaluation with the actual
system (refer to 8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF).
107
Data Sheet S15726EJ2V0DS
µPD161401
8.5 Flow of VOUT and VLCD Voltages from Power ON to Power OFF
★
0 VDD
VOUT
/DISP pin = L
V
DD ON
/DISP pin = H
RES = 1
DISP = 0, HALT = 1
TCS = 0,1,1(M) OP = 1,1,1,1 (M)
LCS = 1,1 LCC = 1,1 HPM = 0,1 (M)
HALT = 0
120 to 150 ms
250 ms
LCS = 1,1 LCC = 1,1 HPM = 0,0 (M)
LCS = X,X LCC = X,X HPM = 0,0 (M)
DISP = 1
Main Duty Display
DISP = 0
HPM = 1,0(M)
DTY = 1
50 ms
HPM = 0,1(M)
HPM = 0,0(M)
DISP = 1
150 ms
Sub Duty Display
DISP = 0
HPM = 0,1(M)
DTY = 0
160 ms
HPM = 0,0(M)
DISP = 1
Normal Duty Display
DISP = 0
HPM = 1,0(M)
EV = 0 PEV = 0(M)
120 ms
380 ms
HALT = 1
V
DD OFF
Dotted line: VOUT
Solid line: VLCD
x: 1 or 0
Test conditions:
Supply voltage: VDD1 = VDD2 = 3.0 V
Number of boosting stages: x5 (in normal display mode), x3 (in partial display mode)
Capacitance: Between VLCn pin and Cn+/- pins = 1.0 µF
Caution Connect a capacitor of 0.1 µF or less to the AMPOUTM and AMPOUTS pins.
108
Data Sheet S15726EJ2V0DS
µPD161401
8.6 Flow of VOUT and VLCD Voltages in Display Output and HALT/Standby Modes
0 VDD
★
V
OUT
Main Duty Display
DISP = 0
HPM = 1,0(M)
EV = 0
300 ms
HALT = 1(STBY = 1)
HALT(STBY)
160 ms
HPM = 0,1(M)
EV = x,x(M)
HALT = 0(STBY = 0)
HPM = 0,0(M)
DISP = 1
Dotted line: VOUT
Solid line: VLCD
x: 1 or 0
Test conditions:
Supply voltage: VDD1 = VDD2 = 3.0 V.
Number of boosting stages: x5 (in normal display mode), x3 (in partial display mode)
Capacitance: Between VLCn pin and Cn+/- pins = 1.0 µF
Caution Connect a capacitor of 0.1 µF or less to the AMPOUTM and AMPOUTS pins.
109
Data Sheet S15726EJ2V0DS
µPD161401
9. USING RAM TEST MODE
The µPD161401 has a test mode in which seven types of screen data are written to the display RAM. When using this
test mode, be sure to execute the following sequence. If the RAM test mode is executed in any other sequence,
erroneous data may be displayed.
Operating status
↓
Control register 1
DISP = 0, STBY = 1
Display OFF. Standby setting
R0
↓
RAM test mode setting
R61
R0
Select data to be written to RAM.
↓
Control register 1
DISP = 0, STBY = 0
Display OFF. Standby cleared
↓
Wait for 200 ms or more from when the internal operation
Wait time
starts until the LCD turns OFF Note
.
↓
Control register 1
Display ON.
R0
DISP = 1
↓
Setting complete
Note The time of 200 ms varies depending on the characteristics of the LCD panel and the capacitance of the
boosting or smoothing capacitor. It is recommended to determine this value after thorough evaluation with
the actual system.
Remark The set display data is always written to the display RAM in the RAM test mode.
110
Data Sheet S15726EJ2V0DS
µPD161401
10. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, VSS = 0 V)
Parameter
Logic supply voltage
Symbol
Ratings
Unit
V
VDD1
VDD2
VOUT
−0.3 to +4.0
Booster circuit supply voltage
Driver supply voltage
−0.3 to +4.0
V
−0.3 to +20.0
V
Driver reference power input voltage VLCD,VLC1 to VLC4
−0.3 to VOUT + 0.3
−0.3 to VDD1 + 0.3
−0.3 to VDD1 + 0.3
−0.3 to VDD1 + 0.3
−0.3 to VOUT + 0.3
−0.3 to VOUT + 0.3
−40 to +85
V
Logic input voltage
VIN1
VO1
VI/O1
VIN2
VO2
TA
V
Logic output voltage
Logic I/O voltage
V
V
Driver input voltage
Driver output voltage
Operating ambient temperature
Storage temperature
V
V
°C
°C
Tstg
−55 to +125
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Range
Parameter
Logic supply voltage
Symbol
MIN.
1.8
2.4
5.5
0
TYP.
MAX.
3.6
Unit
V
VDD1
VDD2
VOUT
VIN
Note1
Note2
Booster circuit supply voltage
Driver supply voltage
Logic supply voltage
3.6
V
18.0
VDD1
VOUT
V
V
Driver supply voltage
VLCD,
0
V
Note2
VLC1 to VLC4
Note3
Maximum LCD voltage setting range VLCD
VOUT − 0.5
V
Notes 1. It is essential that VDD1 ≤ VDD2.
2. These conditions are recommended when the LCD is driven by an external power supply.
3. This condition is recommended when the LCD is driven by the internal power supply circuit.
Cautions 1. Make sure that the relationship of VSS < VLC4 < VLC3 < VLC2 <VLC1 < VLCD ≤ VOUT is satisfied when the
LCD is driven by an external power supply.
2. Make sure that the condition described in 8. POWER SEQUENCE are satisfied when turning
power ON or OFF.
3. Keep the voltage at the VR and VRS pins to between 1.0 V and VDD1 when an external resistor is
used (when the internal resistor is not used to adjust VLCD).
111
Data Sheet S15726EJ2V0DS
µPD161401
Electrical Specifications (Unless otherwise specified, TA = −40 to +85°C, VDD1 = 1.8 to 3.6 V, VDD2 = 2.4 to 3.6 V.)
Parameter
Input voltage, high
Symbol
VIH
Conditions
MIN.
TYP.Notes1
MAX.
Unit
V
0.8 VDD1
Input voltage, low
Input current, high
Input current, low
VIL
0.2 VDD1
V
IIH1
Other than D15 to D0
1
µA
µA
V
IIL1
Other than D15 to D0
−1
Output voltage, high
Output voltage, low
Leakage current, high
VOH
VOL
ILOH
IOUT = −1 mA. Other than OCSOUT
IOUT = 1 mA. Other than OCSOUT
D15 to D8, D7(SI), D6(SCL), D5 to D0,
VIN/OUT = VDD1
VDD1 −0.5
0.5
10
V
µA
Leakage current, low
ILOL
D15 to D8, D7(SI), D6(SCL), D5 to D0,
VIN/OUT = VSS
−10
4
µA
kΩ
kΩ
V
Common output ON resistance
Segment output ON resistance
RCOM
VLCn → COMn, VOUT = 15 V, VLCD = 13 V,
1/9 bias, |IO| = 50 µA
RSEG
VLCn → SEGn, VOUT = 15 V, VLCD = 13 V,
1/9 bias, |IO| = 50 µA
4
Driver voltage (booster voltage) VOUT
In 5-fold mode, VDD2 = 3.0 V,
diced display
13.8
16.6
In 6-fold mode, VDD2 = 3.0 V,
diced display
V
Regulated voltageNotes2
VREG
TA = 85°C.
1.430
1.485
1.540
50
V
(TCS2, TCS1, TCS0) = (0,1,0)
Temperature curve –0.15 %/°C
VLCn: VLCD, VLC1 to VLC4,
Output voltage deflection
∆VLCn
−50
mV
(OP3, OP2, OP1, OP0) = (0, 0, 0, 1)
VDD1 = 2.5 V, VOUT = 15 V,
AMPOUTM = 14 V, bias = 1/5 to 1/9,
IRS pin = L, display OFF, no load
∆AMPOUT IRS pin = H, 1+Rb/Ra = 10-fold
−100
100
97
mV
Oscillation frequency Notes3
Current consumption
fOSC
VDD1 = 3.0 V, TA = 25°C, 1/80 duty,
R = 360 kΩ (OSCIN1-OSCOUT)
VDD1 = 3.0 V, TA = 25°C, 1/38 duty,
R = 770 kΩ (OSCIN2-OSCOUT)
Frame frequency = 70 Hz, all PWM
display output, 1/80 duty,
72
85
40
kHz
33
46
kHz
IDD11
175
280
µA
VDD1 = VDD2 = 3.0 V, VLCD = 13 V,
in 5-fold mode, driving mode (segment x
1, common x 4)
Frame frequency = 70 Hz, all PWM
display output, 1/32 duty,
72
120
10
µA
µA
VDD1 = VDD2 = 3.0 V, VLCD = 7.0 V,
in 3-fold mode, driving mode (segment x
1, common x 4)
Current consumption
(standby mode)
IDD22
VDD1 = VDD2 = 3.0 V
Notes1 The TYP. values are reference values at TA = 25°C (except for regulated voltage (VREG)).
2
3
The TYP. values of Regulated voltage (VREG) at TA = 25°C are MIN. 1.580 V, TYP. 1.635 V, MAX. 1.690 V
Oscillation frequency is changed under the influence of the wiring capacity to the external resistor for
oscillation.
112
Data Sheet S15726EJ2V0DS
µPD161401
Timing Requirements (Unless otherwise specified, TA = −30 to +85°C.)
(1) i80 CPU interface
RS
t
AS8
t
AH8
t
f
tr
/CS1
(CS2 = H)
t
CYC8
t
CCLR, tCCLW
/WR, /RD
t
CCHR, tCCHW
t
DS8
t
DH8
D0
to D15(D
7)
(Write)
t
OH8
t
ACC8
D0
to
D7
(Read)
(VDD1 = 1.8 to 2.0 V)
Parameter
Address hold time
Symbol
tAH8
Conditions
MIN. TYP.Note MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
0
0
Address setup time
System cycle time
tAS8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
1000
160
430
160
160
160
0
Control L pulse width (/WR)
Control L pulse width (/RD)
Control H pulse width (/WR)
Control H pulse width (/RD)
Data setup time
/WR
/RD
/WR
/RD
D0 to D15 (D7)
D0 to D15 (D7)
Data hold time
tDH8
/RD access time
tACC8
tOH8
D0 to D7, CL = 100 pF
0
470
170
Output disable time
D0 to D7, CL = 5 pF, RL = 3 kΩ
0
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.0 to 2.5 V)
Parameter
Address hold time
Symbol
tAH8
Conditions
MIN. TYP.Note MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
0
Address setup time
tAS8
0
System cycle time
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
600
120
240
120
120
120
0
Control L pulse width (/WR)
Control L pulse width (/RD)
Control H pulse width (/WR)
Control H pulse width (/RD)
Data setup time
/WR
/RD
/WR
/RD
D0 to D15 (D7)
D0 to D15 (D7)
Data hold time
tDH8
/RD access time
tACC8
tOH8
D0 to D7, CL = 100 pF
0
0
280
170
Output disable time
D0 to D7 , CL = 5 pF, RL = 3 kΩ
Note The TYP. values are reference values at TA = 25°C.
113
Data Sheet S15726EJ2V0DS
µPD161401
(VDD1 = 2.5 to 3.6 V)
Parameter
Address hold time
Symbol
tAH8
Conditions
MIN. TYP.Note MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
0
0
Address setup time
System cycle time
tAS8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
100
40
40
40
40
40
0
Control L pulse width (/WR)
Control L pulse width (/RD)
Control H pulse width (/WR)
Control H pulse width (/RD)
Data setup time
/WR
/RD
/WR
/RD
D0 to D15 (D7)
D0 to D15 (D7)
Data hold time
tDH8
/RD access time
tACC8
tOH8
D0 to D7, CL = 100 pF
0
50
50
Output disable time
D0 to D7, CL = 5 pF, RL = 3 kΩ
0
Note The TYP. values are reference values at TA = 25°C.
Cautions 1. The rise and fall times (tr and tf) of an input signal are 10 ns or less.
2. All timing data is specified at 20% and 80% of VDD1.
114
Data Sheet S15726EJ2V0DS
µPD161401
(2) M68 CPU interface
RS
R,/W
t
AS6
t
AH6
t
f
tr
/CS1
(CS2 = H)
t
CYC6
t
EWHR, tEWHW
E
t
EWLR, tEWLW
t
DS6
t
DH6
D0
to D15 (D
7)
(Write)
t
OH6
t
ACC6
D0
to D
7
(Read)
(VDD1 = 1.8 to 2.0 V)
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Symbol
tAH6
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
tAS6
0
tCYC6
tDS6
1000
160
0
D0 to D15 (D7)
Data hold time
tDH6
D0 to D15 (D7)
Access time
tACC6
tOH6
D0 to D7, CL = 100 pF
0
470
170
Output disable time
Enable H pulse width
D0 to D7, CL = 5 pF, R = 3 kΩ
0
Read
Write
Read
Write
tEWHR
tEWHW
tEWLR
tEWLW
E
E
E
E
430
160
160
160
Enable L pulse width
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.0 to 2.5 V)
Parameter
Address hold time
Symbol
tAH6
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
Address setup time
System cycle time
Data setup time
Data hold time
tAS6
0
tCYC6
tDS6
600
120
0
D0 to D15 (D7)
tDH6
D0 to D15 (D7)
Access time
tACC6
tOH6
D0 to D7, CL = 100 pF
0
280
170
Output disable time
Enable H pulse width
D0 to D7, CL = 5 pF, R = 3 kΩ
0
Read
Write
Read
Write
tEWHR
tEWHW
tEWLR
tEWLW
E
E
E
E
240
120
120
120
Enable L pulse width
Note The TYP. values are reference values at TA = 25°C.
115
Data Sheet S15726EJ2V0DS
µPD161401
(VDD1 = 2.5 to 3.6 V)
Parameter
Address hold time
Address setup time
System cycle time
Data setup time
Symbol
tAH6
Conditions
MIN.
0
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RS
RS
tAS6
0
tCYC6
tDS6
100
50
0
D0 to D15 (D7)
Data hold time
tDH6
D0 to D15 (D7)
Access time
tACC6
tOH6
D0 to D7, CL = 100 pF
0
50
50
Output disable time
Enable H pulse width
D0 to D7, CL = 5 pF, R = 3 kΩ
0
Read
Write
Read
Write
tEWHR
tEWHW
tEWLR
tEWLW
E
E
E
E
40
40
40
40
Enable L pulse width
Note The TYP. values are reference values at TA = 25°C.
Cautions 1. The rise and fall times (tr and tf) of an input signal are 10 ns or less. If the system cycle time is
short, (tr + tf) ≤ (tCYC6 – tEWLW – tEWHW) or (tr + tf) ≤ (tCYC6 – tEWLR – tEWHR).
2. All timing data is specified at 20% and 80% of VDD1.
116
Data Sheet S15726EJ2V0DS
µPD161401
(3) Serial interface
t
CSS
t
CSH
/CS1
(CS2 = H)
t
SAS
t
SAH
RS
t
SCYC
t
SLW
SCL
t
f
tSHW
t
r
t
SDS
tSDH
SI
(VDD1 = 1.8 to 2.5 V)
Parameter
Serial clock cycle
Symbol
tSCYC
Condition
MIN.
250
100
100
150
150
100
100
150
150
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
SCL
SCL
RS
RS
SI
SCL high-level pulse width
SCL low-level pulse width
Address hold time
Address setup time
Data setup time
tSHW
tSLW
tSAH
tSAS
tSDS
tSDH
tCSS
tCSH
Data hold time
SI
CS - SCL time
/CS1 (CS2 = H)
/CS1 (CS2 = H)
Note TYP. values are reference values when TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
Serial clock cycle
Symbol
tSCYC
Condition
MIN.
150
60
TYP.Note
MAX.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCL
SCL
SCL
RS
RS
SI
SCL high-level pulse width
SCL low-level pulse width
Address hold time
Address setup time
Data setup time
tSHW
tSLW
tSAH
tSAS
tSDS
tSDH
tCSS
tCSH
60
90
90
60
Data hold time
SI
60
CS - SCL time
/CS1 (CS2 = H)
/CS1 (CS2 = H)
90
90
Note TYP. values are reference values when TA = 25°C.
Cautions 1. The rise and fall times of input signal (tr and tf) are rated as 15 ns or less.
2. All timing is rated based on 20% and 80% of VDD1.
117
Data Sheet S15726EJ2V0DS
µPD161401
(4) Common
Parameter
Symbol
fM
Conditions
MIN.
TYP.Note
85
MAX.
Unit
kHz
Clock input 1
OSCIN1. External clock is used in main
duty display mode,1/80 duty
Clock input 2
fS
OSCIN2. External clock is used in sub-duty
display mode, 1/40 duty
40
kHz
Note The TYP. values are reference value at a frame frequency = 70 Hz.
Cautions 1. The rise time and fall time (tr and tf) of an input signal is 15 ns or less.
2. All timing data is specified at 20% and 80% of VDD1.
(a) Timing of display control output
SYNC
OSC
(OUT)
t
DFR
FR
(VDD1 = 1.8 to 2.5 V)
Parameter
Symbol
tDFR
Conditions
MIN.
MIN.
TYP.Note
50
MAX.
200
Unit
ns
FR delay time
FR, CL = 50 pF
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
FR delay time
Symbol
tDFR
Conditions
TYP.Note
20
MAX.
80
Unit
ns
FR, CL = 50 pF
Note The TYP. values are reference values at TA = 25°C.
Caution All timing data is specified at 20% and 80% of VDD1.
118
Data Sheet S15726EJ2V0DS
µPD161401
(b) Reset timing
tRW
/DISP
tR
Reset
End of reset
Internal status
(VDD1 = 1.8 to 2.5 V)
Parameter
Symbol
Conditions
MIN.
50
TYP.Note
MAX.
Unit
µs
Reset time
Reset L pulse width
tR
tRW
50
/DISP
µs
Note The TYP. values are reference values at TA = 25°C.
(VDD1 = 2.5 to 3.6 V)
Parameter
Symbol
Conditions
MIN.
50
TYP.Note
MAX.
50
Unit
µs
Reset time
Reset L pulse width
tR
tRW
/DISP
µs
Note The TYP. values are reference values at TA = 25°C.
Caution All timing data is specified at 20% and 80% of VDD1.
119
Data Sheet S15726EJ2V0DS
µPD161401
11. CPU INTERFACE (Reference Example)
The µPD161401 can be connected to both an i80 system CPU and a M68 system CPU. In addition, the number of
signal lines can be reduced by using the serial interface.
The display area can be expanded by using two or more µPD161401 chips. In this case, each IC is selected and
accessed by a chip select signal.
(1) M68 series CPU
V
CC
V
DD1
A
0
RS
IFM0
IFM1
A
1
to A15
VIMA
Decoder
/CS1
CPU
D0
to D15
D0 to D15
E
E
µ
R,/W
/RES
R,/W
/DISP
GND
VSS
/RES
(2) i80 series CPU
V
CC
V
DD1
A
0
RS
IFM0
IFM1
A
1
to A
7
/CS1
Decoder
/IORQ
D to D15
0
CPU
D0
to D15
/RD
/RD
µ
/WR
/DISP
/WR
/RES
GND
V
SS
/RES
(3) Serial interface in used
V
CC
V
DD1
A
0
RS
IFM0
IFM1
A
1
to A
7
Decoder
/CS1
D
D
0
8
to D5,
Open
CPU
GND
to D15
Port1
SI(D7)
µ
SCL(D
6)
/Port2
/RES
/DISP
V
SS
/RES
120
Data Sheet S15726EJ2V0DS
µPD161401
[MEMO]
121
Data Sheet S15726EJ2V0DS
µPD161401
[MEMO]
122
Data Sheet S15726EJ2V0DS
µPD161401
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
123
Data Sheet S15726EJ2V0DS
µPD161401
•
The information in this document is current as of June, 2002. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
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