UPD16520A [NEC]
VERTICAL DRIVER FOR CCD SENSORS; 垂直驱动器，用于CCD传感器
| 型号： | UPD16520A |
| 厂家： | 
NEC |
| 描述： | VERTICAL DRIVER FOR CCD SENSORS |
| 文件： | 总19页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ PD16520,16520A
VERTICAL DRIVER FOR CCD SENSORS
DESCRIPTION
The µ PD16520 and µ PD16520A are vertical drivers for CCD image sensors that have a level conversion circuit and
a 3-level output function. Since it incorporates a CCD vertical register driver equivalent to the µ PD16510 (10
channels, consisting of six 3-level channels and four 2-level channels) and a VOD shutter driver (1 channel), it is ideal
as a vertical driver for multiple-electrode high-pixel CCD transfer type area image sensors employed in digital still
cameras.
The µ PD16520 and µ PD16520A use a CMOS process to achieve optimum transmission delay characteristics for
vertical driving of CCD image sensors, as well as output on-state resistance characteristics. The µ PD16520 and
µ PD16520A also support low-voltage logic (logic power supply voltage: 2.0 to 5.5 V).
FEATURES
• CCD vertical register driver: 10 channels (3-level: 6 channels, 2-level: 4 channels)
• VOD shutter driver: 1 channel
• High withstanding voltage: 33 V MAX.
• Low-output on-state resistance: 30 Ω TYP.
• Low-voltage input supported (Logic power supply voltage: 2.0 to 5.5 V)
• Latch-up free
• Same drive capacity as µ PD16510
• Small package: 38-pin plastic SSOP (7.62 mm (300) )
• Super small package: 42-pin wafer level CSP
APPLICATIONS
Digital still cameras, digital video cameras, etc.
ORDERING INFORMATION
Part Number
Package
µ PD16520GS-BGG
µ PD16520AFH-2Q1
38-pin plastic SSOP (7.62 mm (300) )
42-pin wafer level CSP
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. S14201EJ3V0DS00 (3rd edition)
Date Published February 2005 NS CP(K)
Printed in Japan
The mark
shows major revised points.
1999, 2003
µ PD16520,16520A
1. PIN CONFIGURATION
(1) 38-pin plastic SSOP (7.62 mm (300) )
µ PD16520GS-BGG (Top view)
GND
1
2
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
V
SS
VCC
VDD1
TO1
TI1
TI2
3
4
VDD2a
TO2
TI3
5
TI4
6
TO3
TI5
7
VDD2a
TO4
TI6
8
PG1
PG2
PG3
PG4
PG5
PG6
BI1
9
TO5
10
11
12
13
14
15
16
17
18
19
VDD2A
TO6
BO1
BO2
VDD2b
BO3
BI2
BO4
BI3
SUBO
Vsb
BI4
SUBI
V
SS
2
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
(2) 42-pin wafer level CSP
µ PD16520AFH-2Q1 (Bottom view)
13
12
11
10
9
14
33
32
31
30
29
28
27
4
15
34
42
16
35
36
37
38
39
40
25
2
17
18
19
20
21
22
23
24
1
8
7
41
26
3
6
5
Index Mark
Pin No.
Pin Name
BO4
Vsb
VSS
Pin No.
15
Pin Name
VSS
Pin No.
29
Pin Name
PG5
1
2
16
VDD1
VDD2a
TO2
30
PG2
3
17
31
TI6
4
BI4
18
32
TI4
5
BI2
19
TO3
33
TI2
6
BI1
20
TO4
34
GND
TO1
7
PG6
PG4
PG3
PG1
TI5
21
TO5
35
8
22
TO6
36
VDD2a
VDD2a
VDD2a
BO1
9
23
BO2
37
10
11
12
13
14
24
BO3
38
25
BO4
39
TI3
26
SUBO
BI3
40
VDD2b
SUBI
VCC
TI2
27
41
TI1
28
BI2
42
3
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
2. BLOCK DIAGRAM
(1) µ PD16520GS-BGG
38
V
SS
GND
1
2
37 VDD1
VCC
+
−
TI1
TI2
3
4
5
6
7
8
9
3-level
3-level
3-level
3-level
3-level
3-level
2-level
2-level
2-level
2-level
2-level
36 TO1
+
−
35 VDD2a
34 TO2
+
−
TI3
+
−
TI4
+
−
TI5
33 TO3
+
−
TI6
32 VDD2a
31 TO4
+
−
PG1
+
−
PG2 10
PG3 11
PG4 12
PG5 13
PG6 14
+
−
30 TO5
+
−
29 VDD2a
28 TO6
+
−
+
−
+
−
BI1 15
27 BO1
+
−
BI2 16
BI3 17
26 BO2
25 VDD2b
24 BO3
+
−
+
−
BI4 18
23 BO4
+
−
SUBI 19
22 SUBO
21 Vsb
20
V
SS
4
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
(2) µ PD16520AFH-2Q1
15
V
SS
GND 34
16 VDD1
V
CC 42
+
−
TI1 14
3-level
3-level
3-level
3-level
3-level
3-level
2-level
2-level
2-level
2-level
2-level
35 TO1
TI2 13
TI2 33
+
−
17 VDD2a
36 VDD2a
+
−
TI3 12
TI4 32
TI5 11
TI6 31
PG1 10
PG2 30
18 TO2
+
−
+
−
19 TO3
+
−
37 VDD2a
20 TO4
+
−
+
−
+
−
PG3
PG4
9
8
21 TO5
+
−
38 VDD2a
22 TO6
PG5 29
+
−
+
−
PG6
BI1
7
6
+
−
39 BO1
+
−
BI2
5
23 BO2
BI2 28
40 VDD2b
24 BO3
+
−
BI3 27
+
−
BI4
4
1
BO4
25 BO4
+
−
SUBI 41
26 SUBO
2
3
Vsb
V
SS
5
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
3. PIN FUNCTIONS
(1) µ PD16520GS-BGG
Pin No.
1
Pin Name
GND
I/O
−
Function
Ground
2
VCC
−
Logic power supply
3
TI1
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
−
3-level driver input (for charge transfer)
4
TI2
(Refer to 4. FUNCTION TABLES.)
5
TI3
6
TI4
7
TI5
8
TI6
9
PG1
PG2
PG3
PG4
PG5
PG6
BI1
3-level driver input (for charge read)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
(Refer to 4. FUNCTION TABLES.)
2-level driver input (for charge transfer)
BI2
(Refer to 4. FUNCTION TABLES.)
BI3
BI4
SUBI
VSS
VOD shutter drive pulse input
VL power supply
Vsb
−
VHH power supply (for SUB drive)
VOD shutter drive pulse output
2-level pulse output
SUBO
BO4
BO3
VDD2b
BO2
BO1
TO6
VDD2a
TO5
TO4
VDD2a
TO3
TO2
VDD2a
TO1
VDD1
VSS
Output
Output
Output
−
VMb power supply (for 2-level driver)
2-level pulse output
Output
Output
Output
−
3-level pulse output
VMa power supply (for 3-level driver)
3-level pulse output
Output
Output
−
VMa power supply (for 3-level driver)
3-level pulse output
Output
Output
−
VMa power supply (for 3-level driver)
3-level pulse output
Output
−
VH power supply
−
VL power supply
6
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
(2) µ PD16520AFH-2Q1
Pin No.
1
Pin Name
I/O
Output
−
Function
BO4
Vsb
VSS
2-level pulse output
2
VHH power supply (for SUB drive)
VL power supply
3
−
4
BI4
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
−
2-level driver input (for charge transfer)
(Refer to 4. FUNCTION TABLES.)
5
BI2
6
BI1
7
PG6
PG4
PG3
PG1
TI5
3-level driver input (for charge read)
8
(Refer to 4. FUNCTION TABLES.)
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
3-level driver input (for charge transfer)
TI3
(Refer to 4. FUNCTION TABLES.)
TI2
TI1
VSS
VL power supply
VDD1
VDD2a
TO2
−
VH power supply
−
VMa power supply (for 3-level driver)
3-level pulse output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
−
TO3
TO4
TO5
TO6
BO2
BO3
BO4
SUBO
BI3
2-level pulse output
VOD shutter drive pulse output
2-level driver input (for charge transfer)
(Refer to 4. FUNCTION TABLES.)
3-level driver input (for charge read)
(Refer to 4. FUNCTION TABLES.)
3-level driver input (for charge transfer)
(Refer to 4. FUNCTION TABLES.)
BI2
PG5
PG2
TI6
TI4
TI2
GND
TO1
Ground
Output
−
3-level pulse output
VMa power supply (for 3-level driver)
VDD2a
VDD2a
VDD2a
BO1
VDD2b
SUBI
VCC
−
−
Output
−
2-level pulse output
VMb power supply (for 2-level driver)
VOD shutter drive pulse input
Logic power supply
Input
−
7
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
4. FUNCTION TABLE (VL = VSS, VMa = VDD2a, VMb = VDD2b, VH = VDD1, VHH = Vsb)
Pins TO1 to TO6
Input
TI1 TI2 TI3 TI4 TI5 TI6 PG1 PG2
Output
Pin
PG3 PG4 PG5 PG6 TO1 TO2 TO3 TO4 TO5 TO6
Name
Pin
3
4
5
6
7
8
9
10
30
11
9
12
8
13
29
14
7
36
35
34
18
33
19
31
20
30
21
28
22
No.
14
13,
33
12
32
11
31
10
L
L
L
H
L
VH
VMa
VL
H
H
H
Remark Pin No. upper row: µ PD16520GS-BGG, lower row: µ PD16520AFH-2Q1
Pins BO1 to BO4
Input
Output
Pin
BI1
BI2
BI3
BI4
BO1
BO2
BO3
BO4
Name
Pin
15
6
16
5,
17
27
28
4
27
39
26
23
24
24
23
1,
No.
28
25
L
VMa
VL
H
Remark Pin No. upper row: µ PD16520GS-BGG, lower row: µ PD16520AFH-2Q1
Pin SUBO
Input
SUBI
Output
SUBO
Pin
Name
Pin
19
41
L
22
26
No.
VHH
VL
H
Remark Pin No. upper row: µ PD16520GS-BGG, lower row: µ PD16520AFH-2Q1
8
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
5. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C, GND = 0 V)
Parameter
Symbol
VSS
Condition
Rating
Unit
V
Power supply voltage
0 to −10
VSS − 0.3 to VSS + 20.0
VSS − 0.3 to VSS + 33.0
VSS − 0.3 to VSS + 33.0
VSS − 0.3 to VSS + 33.0
VSS − 0.3 to VCC + 0.3
−25 to +85
VCC
V
VDD1
VDD2
Vsb
VI
V
V
V
Input pin voltage
V
Operating ambient temperature
Storage temperature
Allowable dissipation
TA
°C
°C
mW
mW
Tstg
−40 to +125
Pd
µ PD16520GS-BGG
µ PD16520AFH-2Q1
500
600 Note
Note Mounted on 8-layer glass epoxy board of 30 mm x 30 mm x 1.6 mm
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions (TA = 25°C, GND = 0 V)
Parameter
Symbol
Condition
MIN.
2.0
TYP.
15.0
MAX.
5.5
Unit
V
Power supply voltage
VCC
VDD1
VDD1-VSS
VDD2a
VDD2b
VSS
Note
Note
10.5
16.5
−1.0
−1.0
−10.0
21.0
31.0
+4.0
+4.0
−6.0
31.0
VCC
V
V
V
V
V
Vsb-VSS
VIH
Note
V
High level input voltage
Low level input voltage
0.8 VCC
0
V
VIL
0.3 VCC
+70
V
Operating ambient temperature TA
Note Set VDD1 and VSS to values that satisfy VDD1-VSS rating.
−20
°C
9
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
Electrical Characteristics (Unless otherwise specified, TA = 25°C, VDD1 = +15 V, VDD2a = 0 V, VDD2b = +1.0 V,
Vsb = 21.5 V, VCC = +2.5 V, VSS = −7.0 V, GND = 0 V)
Parameter
Symbol
VH
Condition
MIN.
VDD1 − 0.1
VDD2a − 0.1
VDD2b
TYP.
MAX.
VDD1
VDD2a
VDD2b + 0.1
VSS + 0.1
Vsb
Unit
V
High level output voltage
Middle level output voltage
IO = −20 µA
IO = −20 µA
IO = 20 µA
IO = 20 µA
IO = −20 µA
IO = 20 µA
IO = 10 mA
IO = 10 mA
IO = −10 mA
VMa
V
VMb
V
Low level output voltage
VL
VSS
V
SUB high level output voltage VsubH
Vsb − 0.1
VSS
V
SUB low level output voltage
Output on-state resistance
VsubL
RL
VSS + 0.1
30
V
20
30
30
30
Ω
RM
45
Ω
RH
40
Ω
Rsub
TD1
TD2
TD3
TP1
TP2
TP3
40
Ω
Transmission delay time 1
Transmission delay time 2
Transmission delay time 3
Rise/fall time 1
No load,
200
ns
ns
ns
ns
ns
ns
Refer to Figure 5−2. Timing Chart.
200
200
Refer to Figure 5−1. Output Load
Equivalence Circuit and
500
Rise/fall time 2
500
Rise/fall time 3
Figure 5−2. Timing Chart.
200
10
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
Figure 5−1. Output Load Equivalence Circuit
(a) Between output pins
(b) Between output pin and GND
BO4
TO1
TO1
BO4
R1
R10
R1
TO1'
TO2
R10
BO4'
C10
C9
BO3
BO3
TO2
BO4'
TO1'
R2
TO2'
R2
BO3'
R9
TO2'
C1
R9
C2
BO3'
R3
TO3
C3 TO3' R3
BO2'
BO2
TO3
TO3'
R8
BO2
R8 BO2' C8
C7
C4
TO4'
BO1'
R7
R4
C5
BO1'
C6
R4
TO4'
TO5'
R7
TO6'
TO5'
TO6'
BO1
TO4
BO1
TO4
R5
R6
R5
R6
RGND
TO6
TO5
TO6
TO5
SUBO
C11
Output Load Capacitance Symbol
TO1'
−
TO2'
C_33
−
TO3'
C_33
C_33
−
TO4'
TO5'
C_33
C_33
C_33
C_33
−
TO6'
C_33
C_33
C_33
C_33
C_33
−
BO1'
BO2'
C_23
C_32
C_23
C_32
C_23
C_32
C_22
−
BO3'
C_32
C_23
C_32
C_23
C_32
C_23
C_22
C_22
−
BO4'
GND
TO1'
TO2'
TO3'
TO4'
TO5'
TO6'
BO1'
BO2'
BO3'
BO4'
SUBO
C_33
C_33
C_33
−
C_32
C_23
C_32
C_23
C_32
C_23
−
C_23
C_32
C_23
C_32
C_23
C_32
C_22
C_22
C_22
−
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C_33
C_33
C_33
C_33
C_33
C_32
C_23
C_32
C_23
−
C_33
C_33
C_33
C_33
C_23
C_32
C_23
C_32
−
C_33
C_33
C_33
C_32
C_23
C_32
C_23
−
C_33
C_33
C_23
C_32
C_23
C_32
−
C_33
C_32
C_23
C_32
C_23
−
C_23
C_32
C_23
C_32
−
C_22
C_22
C_22
−
C_22
C_22
−
C_22
−
−
11
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
Output Load Equivalence Circuit Constants
Parameter
Symbol
R1 to R10
PGND
Constant
0 Ω
Vertical register serial resistor
Vertical register ground resistor
0 Ω
Capacitance 1 between vertical register clocks (3-level - 3-level)
Capacitance 2 between vertical register clocks (2-level - 2-level)
Capacitance 3 between vertical register clocks (3-level - 2-level)
Capacitance 4 between vertical register clocks (2-level - 3-level)
Vertical register ground capacitance 1 (3-level)
Vertical register ground capacitance 2 (2-level)
Substrate ground capacitance
C_33
0 pF
C_22
0 pF
C_32
1000 pF
500 pF
3000 pF
1500 pF
1600 pF
C_23
C1 to C6
C7 to C10
C11
Figure 5−2. Timing Chart
BI1 to BI4
TI1 to TI6
TD1
TD1
V
V
Mb
Ma
BO1 to BO4
TO1 to TO6
V
L
TP1
TP1
PG1 to PG6
TO1 to TO6
TD2
TD2
V
V
H
Ma
TP2
TP2
SUBI
TD3
TD3
V
V
HH
SUBO
L
TP3
TP3
12
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
6. NOTE ON USE
6.1 Power ON/OFF Sequence
In the µ PD16520 and µ PD16520A, a PN junction (diode) exists between VDD2 → VDD1, input pin (TI1 to TI6, PG1
to PG6, BI1 to BI4, and SUBI) → VCC, so that in the case of voltage conditions: VDD2 > VDD1, input pin voltage (TI1
to TI6, PG1 to PG6, BI1 to BI4, and SUBI) > VCC, an abnormal current flows. Therefore, when turning the power
ON/OFF, make sure that the following voltage conditions are satisfied: VDD2 ≤ VDD1, input pin voltage (TI1 to TI6,
PG1 to PG6, BI1 to BI4, and SUBI) ≤ VCC. Also, to minimize the negative potential applied to the SUB pin of the CCD
image sensor, following the power ON/OFF sequence described below.
(1) Power ON
<1> Powering ON VCC
Make sure that input pin voltage (TI1 to TI6, PG1 to PG6, BI1 to BI4, and SUBI) ≤ VCC. Also, when Vsb = 2 V,
make sure that VCC reaches the rated voltage.
<2> Powering ON Vsb, VDD1, VDD2a, VDD2b and VSS
At this time, make SUBI high level (0.8VCC or higher) .
Vsb
VDD1
V
CC
2 V
VDD2a, VDD2b
0 V
<1> <2>
V
SS
Time
13
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
(2) Power OFF
<1> Powering OFF Vsb, VDD1, VDD2a, VDD2b and VSS
Until VCC power OFF, keep SUBI high level (0.8VCC or higher) .
<2> Powering OFF VCC
Power OFF VCC when Vsb becomes 2 V or lower. At this time, make sure that the input pin voltage (TI1 to TI6,
PG1 to PG6, BI1 to BI4, and SUBI) ≤ VCC.
<1>
Vsb
VDD1
<2>
V
CC
2 V
VDD2a, VDD2b
0 V
V
SS
Time
6.2 Recommended Connection of Unused Pins
Handle input pins and output pins that are not used as follows.
Input pin: High level (connect to VCC)
Output pin: Leave open
14
Data Sheet S14201EJ3V0DS
V
CC
V
SS
VDD1 Vsb
VDD2b
VSUB (Substrate voltage)
CCD
µ
PD16520GS-BGG
38
1
2
TG/SSG
V
SS
GND
37
36
VDD1
TO1
VCC
3
4
5
6
TI1
35
34
33
VDD2a
TO2
TI2
TI3
TO3
TI4
7
8
9
32
31
VDD2a
TO4
TI5
TI6
30
29
28
27
26
25
24
23
TO5
PG1
PG2
PG3
PG4
PG5
PG6
BI1
10
11
12
13
14
15
16
17
18
VDD2a
TO6
BO1
BO2
VDD2b
BO3
BO4
BI2
+
22
21
20
BI3
SUBO
Vsb
µ
1
F
BI4
19
SUBI
V
SS
µ
1 MΩ
µ
µ
µ
µ
µ
µ
0.1 F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
µ PD16520,16520A
8. PACKAGE DRAWINGS
38-PIN PLASTIC SSOP (7.62 mm (300))
38
20
detail of lead end
F
G
P
L
1
19
A
E
H
I
J
S
B
C
N
S
K
M
M
D
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.10 mm of
its true position (T.P.) at maximum material condition.
A
B
C
12.7 0.3
0.65 MAX.
0.65 (T.P.)
+0.05
0.37
D
−0.1
E
F
G
H
I
0.125 0.075
1.675 0.125
1.55
7.7 0.2
5.6 0.2
J
1.05 0.2
+0.1
0.2
K
−0.05
L
M
N
0.6 0.2
0.10
0.10
+7°
3°
P
−3°
P38GS-65-BGG-1
16
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
42-PIN WAFER LEVEL CSP (Unit: mm)
w S A
Pitch 0.5 x (5 − 1) = 2.0
D
ZD
9
8
7
6
5
4
3
2
1
φ
INDEX 0.25
Solder ball is not
loaded yet.
E
D
C
B
A
INDEX MARK
φ
42 −
b
t S A B
φ
x M S A B
C Block
Standard
Parameter MIN. TYP. MAX.
// y1 S
D
E
ZD
ZE
e
2.98
4.99
−
3.03
5.04
0.515
0.520
0.5
3.08
5.09
−
−
−
y S
t
A
A1
A2
b
y
x
w
y1
0.15
0.8
C Block Details
0.66
0.18
0.48
0.25
−
−
−
−
0.73
0.23
0.50
0.30
−
−
−
−
0.28
0.52
0.35
0.08
0.05
0.20
0.20
17
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
9. RECOMMENDED SOLDERING CONDITIONS
The µ PD16520 and µ PD16520A should be soldered and mounted under the following recommended conditions.
For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales
representative.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Surface Mount Device
µ PD16520GS-BGG: 38-pin plastic SSOP (7.62 mm (300) )
Process
Infrared reflow
Conditions
Symbol
Peak temperature: 235°C or below (package surface temperature) ,
Reflow time: 30 seconds or less (at 210°C or higher) ,
Maximum number of reflow processes: 3 times or less.
Peak temperature: 215°C or below (package surface temperature) ,
Reflow time: 40 seconds or less (at 200°C or higher) ,
Maximum number of reflow processes: 3 times or less.
Solder temperature: 260°C or below, Flow time: 10 seconds or less,
Maximum number of flow processes: 1 time,
IR35-00-3
Vapor phase soldering
Wave soldering
VP15-00-3
WS60-00-1
−
Pre-heating temperature: 120° or below (package surface temperature) .
Pin temperature: 300°C or below,
Partial heating method
Heat time: 3 seconds or less (per each side of the device) .
µ PD16520AFH-2Q1: 42-pin wafer level CSP
Process
Conditions
Symbol
Infrared reflow
Peak temperature: 260°C or below (package surface temperature) ,
Reflow time: 60 seconds or less (at 220°C or higher) ,
Maximum number of reflow processes: 3 times or less.
IR60-00-3
Caution Do not use different soldering methods together (except for partial heating) .
REFERENCE DOCUMENTS
NEC Semiconductor Device Reliability/Quality Control System (C10983E)
Quality Grades on NEC Semiconductor Devices (C11531E)
18
Data Sheet S14201EJ3V0DS
µ PD16520,16520A
NOTES FOR CMOS DEVICES
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
1
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
V
IH (MIN).
HANDLING OF UNUSED INPUT PINS
2
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
19
Data Sheet S14201EJ3V0DS
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