UPD16681_技术文档

DATA SHEET

MOS INTEGRATED CIRCUIT

µ

PD16681

LCD CONTROLLER/DRIVER FOR DOT MATRIX DISPLAY OF JIS LEVEL 1

AND JIS LEVEL 2 KANJI SETS

DESCRIPTION

The µPD16681 is a single-chip controller driver that can display Japanese text; including JIS Level 1 kanji, JIS Level

2 kanji, hiragana, and katakana. Each chip can display up to four lines containing up to eight full width characters (11

x 12 dots), or up to four lines containing up to 16 half width characters (5 x 12 dots), as well 96 pictographs.

FEATURES

• LCD controller/driver for dot matrix display of JIS Level 1 and JIS Level 2 kanji sets

• On-chip ROM for character generation

−JIS Level 1 + Level 2 kanji (11 x 12 dots) : 6,355 characters

−JIS non-kanji characters (11 x 12 dots) : 453 characters

−Other characters (symbols, etc.) (11 x 12 dots): 256 characters

−Half width alphanumeric characters (5 x 12 dots) : 192 characters

• On-chip RAM for character generation

−8 types (12 x 13 dots)

• On-chip boost circuit : switchable between 3x and 4x modes

• RAM for pictograph data displays : 96 bits

• Outputs : 96 segments, 52 commons

• Duty settings : 1/39 or 1/52

• Switchable data inputs : serial or 8-bit parallel

• On-chip divider resistor

• Selectable bias settings (1/8 bias, 1/7 bias, or 1/6 bias)

• On-chip oscillation circuit

ORDERING INFORMATION

Part number

Package

ROM code

µPD16681W-011

µPD16681P-011

Wafer

Standard

Chip (COG compliant)

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No.

S13104EJ5V0DS00(5th edition)

The mark ★ shows major revised points.

Date Published November 1999 NS CP(K)

Printed in Japan

1999

©

µPD16681

1. BLOCK DIAGRAM

OSCOUT

OSCIN

OSCBRI

/RESET

Oscillation Circuit

Timing Generator

SEGINV

COMINV

Index

Register

Control

Register

V

DD

LCD

V

SS

Common

Driver

COM

PCOM

1

to COM51

,PCOM

1

2

WS

STB

Display Data RAM

RAM Address

Counter

E/SCK

I/O

Buffer

D

0/DATA

8

96 bits

Shift

Register

96 bits

Latch

Circuit

Segment

Driver

SEG1 to SEG96

D

1

to D7

8

RAM Data

Register

TEST^OUT

Address Formation Circuit

12

8

3

7

4

8

Full-width

Character

Generator

ROM

Half-width

Character

Generator

ROM

Character

Generator

RAM

Pictograph

Data RAM

6

Display Attribute Control Circuit

D/A

Converter

DACHA

6

Cursor Control

Parallel/Serial Conversion Circuit

Smooth Scroll Control Circuit

Circuit

C ⁺

, C

C ⁺, C ⁻

1

, C ⁻

1

−

2

DC/DC

Converter

3

V

EXT

OP Amp.

LCD Voltage Generator

AMPIN(+)

AMPIN(−)

V

LCBS1

VLC5

V

LCBS3

AMPCHA

V

LC2

V

LC4

AMPOUT

V

LC3

VLCBS2

V

LC1

Remark /xxx indicates active low signals.

2

Data Sheet S13104EJ5V0DS00

µPD16681

2. PIN CONFIGURATION (Pad Layout)

Chip size : 2.80 x 10.48 mm²

241

219

1

218

Y

X

82

108

107

83

3

Data Sheet S13104EJ5V0DS00

µPD16681

Table 2-1. Pad Layout

PAD

No.

PAD

No.

PAD

No.

Pin Name X ( m) Y ( m)

µ µ

µ

No.

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

1

DUMMY1

V^LCBS1

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

4800

4680

4560

4440

4320

4200

4080

3960

3840

3720

3600

3480

3360

3240

3120

3000

2880

2760

2640

2520

2400

2280

2160

2040

1920

1800

1680

1560

1440

1320

1200

1080

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

DA^CHA

AMP^CHA

SEG^INV

COM^INV

OSC^IN

OSC^OUT

OSC^BRI

D⁰/DATA

D¹

1273

2400

SEG⁹⁰

SEG⁸⁹

SEG⁸⁸

SEG⁸⁷

SEG⁸⁶

SEG⁸⁵

SEG⁸⁴

SEG⁸³

SEG⁸²

SEG⁸¹

SEG⁸⁰

SEG⁷⁹

SEG⁷⁸

SEG⁷⁷

SEG⁷⁶

SEG⁷⁵

SEG⁷⁴

SEG⁷³

SEG⁷²

SEG⁷¹

SEG⁷⁰

SEG⁶⁹

SEG⁶⁸

SEG⁶⁷

SEG⁶⁶

SEG⁶⁵

SEG⁶⁴

SEG⁶³

SEG⁶²

SEG⁶¹

SEG⁶⁰

SEG⁵⁹

1273

3735

3645

3555

3465

3375

3285

3195

3105

3015

2925

2835

2745

2655

2565

2475

2385

2295

2205

2115

2025

1935

1845

1755

1665

1575

1485

1395

1305

1215

1125

1035

181

182

183

184

185

186

187

188

189

190

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

207

208

209

210

211

212

SEG³⁰

SEG²⁹

SEG²⁸

SEG²⁷

SEG²⁶

SEG²⁵

SEG²⁴

SEG²³

SEG²²

SEG²¹

SEG²⁰

SEG¹⁹

SEG¹⁸

SEG¹⁷

SEG¹⁶

SEG¹⁵

SEG¹⁴

SEG¹³

SEG¹²

SEG¹¹

SEG¹⁰

SEG⁹

1273

1665

−

2

1273

1120

1030

2520

2640

2760

2880

3000

3120

3240

3360

3480

3600

3720

3840

3960

4080

4200

4320

4440

4560

4680

4800

4920

5113

1273

1755

1845

1935

2025

2115

2205

2295

2385

2475

2565

2655

2745

2835

2925

3015

3105

3195

3285

3375

3465

3555

3645

3735

3825

3915

4005

4095

4185

4275

4365

4455

3

V^LCBS1

4

V^LCBS2

5

V^LCBS2

6

V^LCBS3

7

V^LCBS3

8

AMP^OUT

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

AMP^IN(

)

D²

−

)

−

D³

AMP^IN(+)

V^LC5

V^LC4

V^LC3

V^LC2

V^LC1

V^LCD

C1⁺

D⁴

D⁵

D⁶

D⁷

WS

STB

E/SCK

/RESET

TEST^OUT

DUMMY2

DUMMY3

DUMMY4

DUMMY5

COM²⁷

COM²⁸

COM²⁹

COM³⁰

COM³¹

COM³²

COM³³

COM³⁴

SEG⁸

SEG⁷

940

850

760

670

580

490

400

310

SEG⁶

−

SEG⁵

−

SEG⁴

SEG³

SEG²

SEG¹

COM²⁶

COM²⁵

945

855

765

−

C1⁺

33

34

1273

960

840

93

94

COM³⁵

COM³⁶

220

130

40

5113

153

154

SEG⁵⁸

SEG⁵⁷

1273

213

214

COM²⁴

COM²³

1273

4545

4635

−

C1⁺

C1⁻

C2⁺

1273

5113

−

35

36

37

38

1273

−

1273

−

1273

−

1273

−

720

600

480

360

95

96

97

98

COM³⁷

COM³⁸

COM³⁹

COM⁴⁰

5113

−

5113

−

5113

−

5113

−

155

156

157

158

SEG⁵⁶

SEG⁵⁵

SEG⁵⁴

SEG⁵³

1273

675

−

585

−

495

−

405

−

215

216

217

218

COM²²

1273

4725

4815

4905

4995

−

50

COM²¹

140

230

DUMMY10

DUMMY11

C2⁺

39

40

1273

240

120

0

99

COM⁴¹

COM⁴²

320

410

5113

159

160

SEG⁵²

SEG⁵¹

1273

315

219

220

DUMMY12

COM²⁰

950

860

5113

−

C2⁺

C2⁻

C3⁺

1273

100

5113

225

41

42

43

44

1273

−

1273

−

1273

−

1273

−

101

102

103

104

COM⁴³

COM⁴⁴

COM⁴⁵

COM⁴⁶

500

590

680

770

5113

−

5113

−

5113

−

5113

−

161

162

163

164

SEG⁵⁰

SEG⁴⁹

SEG⁴⁸

SEG⁴⁷

1273

135

45

221

222

223

224

COM¹⁹

COM¹⁸

COM¹⁷

COM¹⁶

770

680

590

500

5113

120

−

240

−

45

360

−

480

−

600

−

135

225

315

C3⁺

45

46

1273

105

106

COM⁴⁷

860

950

5113

165

166

SEG⁴⁶

SEG⁴⁵

1273

225

226

COM¹⁵

COM¹⁴

410

320

5113

−

C3⁺

C3⁻

V^DD1

V^DD2

V^SS

1273

DUMMY6

5113

47

48

49

50

51

52

53

54

55

56

57

58

59

60

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

1273

−

720

−

840

−

960

−

107

108

109

110

111

112

113

114

115

116

117

118

119

120

DUMMY7

DUMMY8

COM⁴⁸

COM⁴⁹

COM⁵⁰

COM⁵¹

DUMMY9

PCOM²

SEG⁹⁶

1040

1273

5113

−

4905

−

4815

−

4725

−

4635

−

4545

−

4455

−

4365

−

4275

−

4185

−

4095

−

4005

−

3915

−

3825

−

167

168

169

170

171

172

173

174

175

176

177

178

179

180

SEG⁴⁴

SEG⁴³

SEG⁴²

SEG⁴¹

SEG⁴⁰

SEG³⁹

SEG³⁸

SEG³⁷

SEG³⁶

SEG³⁵

SEG³⁴

SEG³³

SEG³²

SEG³¹

1273

405

495

227

228

229

230

231

232

233

234

235

236

237

238

239

240

241

COM¹³

COM¹²

COM¹¹

COM¹⁰

COM⁹

230

140

50

5113

585

1080

−

1200

−

1320

−

1440

−

1560

−

1680

−

1800

−

1920

−

2040

−

2160

−

2280

−

675

40

−

765

130

−

220

−

310

−

400

−

490

−

580

−

670

−

760

−

850

−

940

−

855

COM⁸

945

COM⁷

1035

1125

1215

1305

1395

1485

1575

COM⁶

COM⁵

V^SS

SEG⁹⁵

COM⁴

V^SS

SEG⁹⁴

COM³

V^SS

SEG⁹³

COM²

V^SS

SEG⁹²

COM¹

V^EXT

SEG⁹¹

PCOM¹

DUMMY13

1030

−

4

Data Sheet S13104EJ5V0DS00

µPD16681

3. PIN FUNCTIONS

3.1 Power Supply System Pins

Pin Symbol

V^DD

Pin Name

Pad No.

50-54

I/O

Description

Logic power supply pin

−

Power supply pins for logic and boost circuit

Boost circuit power supply

V^SS

Logic ground

55-59

29-31

−

Ground pins for logic and driver circuit

Driver ground

V^LCD

Driver power supply pins

Power supply pins for driver. Output pin for internal boost circuit.

Connect a 1-µF capacitor between these pins and the V^SSpins

for boosting.

If not using the internal boost circuit, a direct driver power supply

can be input.

V^LC1- V^LC5

Reference power supply

pins for driver

14-28

−

These are reference power supply pins for the LCD driver.

Leave these pins open if an internal bias has been selected.

Connect a capacitor to ground.

V^LCBS1- V^LCBS3Bias value setting pins

2-7

−

When selecting an internal bias, the bias value can be changed

connecting these pins outside of the IC.

+

-

C¹, C¹

Capacitor connection pins

32-49

These are capacitor connection pins for the boost circuit.

+

Connect a 1-µF capacitor.

C², C²

+

C³, C³

5

Data Sheet S13104EJ5V0DS00

µPD16681

3.2 Logic System Pins

Pin Symbol Pin Name

Pad No.

76

I/O

I

Description

WS

Select word length

Select D/A converter

Strobe

Use this pin to select the word length. An 8-bit parallel interface is used

for high level and a serial interface is used for low level. This setting

cannot be changed after the power has been switched on.

DA^CHA

STB

61

77

I

Use this pin to select whether or not to use the D/A converter for

regulating the LCD driver voltage. Select high level to use the D/A

converter or low level to not use it.

This is used for the device’s select signal and strobe signal for

communication. Communication is initialized at the rising edge or falling

edge of STB.

Command data receive standby status occurs at the falling edge of STB.

Communication is enabled when STB is low.

Also, enabled status or the shift clock is ignored when STB is high.

E/SCK

Enable/shift clock

78

I

This is an input enable pin for data when the parallel interface is used.

During the read-in operation, data is captured in the interface buffer at

the signal’s rising edge. During a read-out operation, data is read-out

from the interface buffer at the signal’s falling edge.

When using a serial interface, this pin is used for the data shift clock.

During the read-in operation, data is captured in the shift register at the

signal’s rising edge. During a read-out operation, data is read from the

shift register at the signal’s falling edge.

D⁰/DATA

D¹-D⁷

Data bus/data

Data bus

68

I/O

This pin is used for data bus bit D⁰when using the parallel interface.

When using the serial interface, it is an I/O pin (tri-state) for commands

and display data.

69-75

These pins are used for data bus bits D¹to D⁷when using the parallel

interface.

It should be fixed high or low when using the serial interface.

TEST^OUT

/RESET

AMP^CHA

Test output

Reset

80

79

62

O

I

This is a test output pin. Leave this pin open when using the device.

This pin is used for internal resets at low-level.

Op amp switch for

LCD driver’s power

supply level

I

This pin is used to control the op amp that works with the LCD driver’s

power supply level. High-power mode is set when at low level and

normal mode is set when at high level.

V^EXT

Reference power

supply switch

60

63

64

I

This pin is used to select the reference power supply circuit’s supply

mode. High level sets external mode and low level sets internal mode.

SEG^INV

COM^INV

Segment direction

switch

This pin is used to control the segment output direction. Low level sets

forward direction and high level sets reverse direction.

Common scan

direction switch

This pin is used to switch the common scan direction. Low level sets

forward direction and high level sets reverse direction.

•

OSC^IN

Oscillator pins

65

66

67

I

O

I

These pins are connected to a 100-kΩ resistance. When using an

OSC^OUT

OSC^BRI

external oscillator, input to OSC^INand leave OSC^OUTunconnected.

External clock for

blink function

This is an input pin for the 2-Hz external clock. Internally, it is divided by

half to generate a 1-Hz signal that is used as the synchronization signal

for the blink function.

6

Data Sheet S13104EJ5V0DS00

µPD16681

3.3 Driver System Pins

Pin Symbol

Pin Name

Pad No.

115-210

I/O

O

Description

SEG¹- SEG⁹⁶Segment

Segment output pins

Common output pins

COM¹-

COM⁵¹

Common

85-105

109-112

211-216

220-239

240

O

1/52 duty : Use COM¹to COM⁵¹.

1/39 duty : Use COM¹to COM¹⁹, COM²⁷to COM⁴⁵,

leave COM²⁰to COM²⁶, COM⁴⁶to COM⁵¹open.

Common output pins for pictographs

PCOM¹,

PCOM²

AMP^IN(+)

Pictograph common

Op amp inputs

O

I

114

The same signal is output from PCOM¹and PCOM².

10-13

These are input pins for the op amp that regulates the LCD driver

voltage.

Leave the AMP^IN(+)pin unconnected when using the on-chip D/A

converter. When not using the D/A converter, a reference voltage must

AMP^IN(⁻⁾

AMP^OUT

be input.

Connect the AMP^IN(⁻⁾pin to a resistor used to regulate the LCD voltage.

(See diagram below.)

Op amp outputs

8,9

O

These are output pins for the op amp that regulates the LCD driver

voltage. Normally, they are connected to resistors that are used to

regulate the LCD voltage. (See diagram below.)

Since the AMP^OUTpins are used to stabilize the on-chip amp’s output, we

recommend connecting them to a capacitor that is rated between 0.1 and

1.0 µF.

DUMMY

DUMMY pins

1,81-84,

106-108,

113,

−

DUMMY pins are not connected to the internal circuit. Leave open if they

are not used.

217-219,

241

Figure 3-1. Voltage Control Circuit

DACHA

D/A

converter

V

EXT

Reference power supply circuit

+

AMPIN(+)

−

V

LCBS1

AMP^IN(−)

AMPOUT

VLC1

V

LC2

V

LC3

V

LCBS3

V

LC4

V

LC5

V

SS

V

LCBS2

R2

R1

C1

7

Data Sheet S13104EJ5V0DS00

µPD16681

4. POWER SUPPLY CIRCUIT

A switchable (3x or 4x) boost circuit is included to generate a current for driving the LCD. A connection to a boost-

related capacitor is used to switch the boost circuit’s setting.

EXT

The V

pin (H: external, L: internal) is used to switch between using an external LCD driver power supply or the

on-chip boost circuit.

4.1 Boost Circuit

+

−

+

−

1

2

When using the internal power supply, connect the boost-related capacitor between C and C , C and C , and

+

−

3

C

3

LCD

SS

EXT

and C . Also, connect the capacitor for level stabilization between V

and V , and set V

low to boost the

DD

SS

potential between V and V from 3 to 4 times.

Since the boost circuit uses signals from the internal oscillation circuit, the oscillation circuit must be operating. The

relation between the boosted voltage and the potential is described below.

+

−

+

−

+

−

1

2

3

DD

The C , C , C , C , C , C and V pins all relate to the boost circuit, so the wire impedance should be

minimized.

Figure 4-1. 3x and 4x Boost Mode

V^LCD= 4VDD = 12 V

(During 4x boost mode)

V^LCD= 3VDD = 9 V

(During 3x boost mode^Note

)

VDD = 3 V

V^SS= 0 V

Note When set for 3x boost, connect boost-related capacitors between C²and C³and C¹and C¹.

−

+

−

8

Data Sheet S13104EJ5V0DS00

µPD16681

4.2 Regulation of LCD Driver Voltage

4.2.1 When not using internal power supply select or D/A converter (V^EXT= L, DA^CHA= L)

When using the internal power supply, the boosted voltage is used as the power supply for the op amp incorporated

in the IC for the LCD driver’s voltage. A common mode amplifier circuit can be configured by connecting external

REF

IN(+)

to AMP

resistors R1 and R2 and inputting the reference voltage V

, and this configuration can be used to

LC1

regulate the potential of the LCD driver voltage V . If using a thermistor to regulate the LCD driver voltage to suit

the liquid crystals’ temperature characteristics, we recommend connecting in parallel to R2.

LC1

The LCD driver voltage V

can be determined using the following formula.

R2′

R1

LC1

V

OUT

= AMP

REF

= 1+

V

R2 ‚ Rth

R2 + Rth

R2′ =

Figure 4-2. When Not Using Internal Power Supply Select or D/A Converter

DACHA

D/A

converter

VREF

To internal drive circuit

+

AMPIN(+)

−

AMP^IN(

−)

AMPOUT

VLC1

Rth

R2

R1

C1

4.2.2 When using internal power supply select and D/A converter (V^EXT= L, DA^CHA= H)

Using the D/A converter enables commands to be entered to control the reference voltage V

input of the op amp for the LCD driver voltage.

REF

that is input to the +

The D/A converter function sets 6-bit data to the D/A converter set register to set one of the 64 modes for the

REF

DD

reference voltage V

between V and 1/2 V .

LC1

The formula for V

is the same as in

4.2.1 When not using internal power supply select or D/A converter

(V^EXT= L, DA^CHA= L) above.

9

Data Sheet S13104EJ5V0DS00

µPD16681

Figure 4-3. Using Internal Power Supply Select and D/A Converter

V

DD

V

DD

D/A

converter

DACHA

To internal drive circuit

V

+

REF

AMPIN(+)

OPEN

−

AMP^IN(−)

AMPOUT

V

LC1

Rth

R2

R1

C1

4.2.3 When using an external power supply (V^EXT= H)

When an external power supply is used for the LCD driver voltage, the op amp incorporate in the µPD16681 (used

for the LCD driver voltage) is in OFF mode. Consequently, the LCD driver’s op amp and D/A converter function

cannot be used when using an external power supply. Instead, regulate the LCD driver voltage by inputting directly

LCD

LC1

and V

to the V

pins.

Cautions 1. Maintain the following relation for the voltage input to the V^LCDand V^LC1pins : V^LCD> V^LC1

2. Since the DA^CHA, AMP^IN(+), and AMP^IN(⁻⁾pins are CMOS inputs, they should be fixed either high or

low.

3. The AMP^OUTpin should be left unconnected.

4.3 Reference Voltage

4.3.1 When using internal power supply (V^EXT= L)

When using the internal power supply, the µPD16681’s on-chip divider resistor is used to create the six-level

LC1

LC2

LC3

LC4

LC5

SS

potential (V , V , V , V , V , and V ) required for the LCD driver.

4.3.2 When using an external power supply (V^EXT= H)

When use of an external power supply has been selected, the op amp incorporated in the µPD16681 for the LCD

LC1

LC2

LC3

LC4

driver level power supply is in OFF mode, so a reference potential must be directly input to V , V , V , V , and

LC5

V

.

Ordinarily, these levels are generated by dividing the resistance. Since large resistance values result in poorer LCD

display quality, be sure to select a resistance value that suits the type of LCD panel to be used.

The display quality can be improved by connecting capacitors between the level pins and ground pins. As with the

resistance values described above, the capacitance values of the capacitors should be selected to suit the divided

resistance values and the type of LCD panel to be used.

10

Data Sheet S13104EJ5V0DS00

µPD16681

4.4 Control of Op Amp for Level Power Supply

CHA

Input to the AMP

pin is used to control the op amp for the LCD driver level power supply.

CHA

• High power mode (AMP

= L)

This mode maximizes the LCD drive current supply capacity in the op amp for the LCD driver level power supply.

CHA

• Normal mode (AMP

= H)

This mode uses a lower LCD drive current supply capacity in the op amp for the LCD driver level power supply,

which is suitable for charging the capacitor used to stabilize the external level.

Caution For either mode, be sure to connect a level stabilization capacitor (rated from about 0.1 to 1.0 µF)

for the V^LC1to V^LC5pins. Poorer display quality results when these capacitors are not connected.

Figure 4-4. Reference Voltage Circuit

AMPOUT

VLC1

+

Output to SEG and COM

−

R

VLC2

+

−

VLC3

+

Output to SEG and COM

Op amp for level driver

−

VLCBS1

R

VLCBS2

V

LCBS3

2R

VLC4

+

Output to SEG and COM

−

R

V

LC5

+

Output to SEG and COM

−

V

SS

11

Data Sheet S13104EJ5V0DS00

µPD16681

4.5 Bias Value Settings

The bias value can be set as 1/6 bias, 1/7 bias, or 1/8 bias by selecting an internal bias for the (µPD16681 and by

LCBS1

LCBS2

, V

LCBS3

connecting externally from the IC among V

, and V

pins.

Bias Value

Connected Pin

1/8 bias

1/7 bias

V^LCBS1, V^LCBS2, and V^LCBS3leave open

Between V^LCBS1and V^LCBS2or between V^LCBS2and

V^LCBS3

1/6 bias

Between V^LCBS1and V^LCBS3and V^LCBS2leave open

4.6 Power Supply Circuit Use Example

Figure 4-5. Using Internal Power Supply and Normal Mode

A) 4x boost (D/A converter is not used.)

B) 3x boost

To VDD

V

DD

V

DD

AMP(+)

R2

Rth (thermistor)

AMP(−)

LCD

+

R

1

C

2

C

2

AMPOUT

+

C ⁺

1

V

LC1

C

1

+

1

+

C1

V

LC2

−

C

1

2

C

1

+

C

V

LC3

LC4

+

open

+

C

2

+

−

C2

−

C

2

3

+

C

C1

+

V

LC5

+

C

3

+

−

C ⁻

3

open

C3

V

DD

V

CHA

EXT

SS

AMPCHA

V

EXT

SS

Remarks 1. C¹= 1.0 µF,C²= 1.0 µF

+

−

2. Leave C²and C³pins open during 3x boost.

3. Leave AMP⁽⁺⁾open when using the D/A converter.

12

Data Sheet S13104EJ5V0DS00

µPD16681

Figure 4-6. Using External Power Supply Circuit

A) Use 1/8 bias

VDD

AMP(+)

AMP⁽⁻⁾

To external drive supply

AMPOUT

open

VLCD

C ⁺

1

VLC1

VLC2

VLC3

VLC4

VLC5

R

−

1

C

+

C2

open

C ⁻

2

+

C3

4R

R

C ⁻

3

VDD

V

EXT

SS

R

V

Remark Fix all open input pins high or low.

13

Data Sheet S13104EJ5V0DS00

µPD16681

5. LCD DISPLAY DRIVER

Either a 1/52 duty driver or a 1/39 duty driver can be selected for the µPD16681. Both drivers output a drive

waveform using the two-frame AC drive method.

5.1 1/52 Duty Driver

When the 1/52 duty driver is selected for the µPD16681, a select signal is output once per frame from the dot

1

51

block’s common outputs (COM to COM ) and from the pictograph block’s common outputs (same signal output

1

2

from PCOM and PCOM ).

Figure 5-1. 1/52 Duty Driver

1Frame

1

2

3

4

5

6

7

8

50 51 52 1

2

3

4

5

6

7

50 51 52

8

V

LC1

LC2

LC3

SEG

1

V

LC4

LC5

V

SS

V

LC1

LC2

LC3

COM

1

V

LC4

LC5

V

SS

V

LC1

LC2

LC3

COM

2

V

LC4

LC5

V

SS

V

LC1

LC2

LC3

PCOM

1

2

V

LC4

LC5

V

SS

14

Data Sheet S13104EJ5V0DS00

µPD16681

5.2 1/39 Duty Driver

When the 1/39 duty driver is selected for the µPD16681, a select signal is output once per frame from the dot

1

19

27

45

block’s common outputs (COM to COM , COM to COM ) and from the pictograph block’s common outputs (same

1

2

signal output from PCOM and PCOM ).

Figure 5-2 1/39 Duty Driver

1Frame

1

2

3

4

5

6

7

8

37 38 39 1

2

3

4

5

6

7

37 38 39

8

V

LC1

LC2

LC3

SEG

1

V

LC4

LC5

V

SS

V

LC1

LC2

LC3

COM

1

V

LC4

LC5

V

SS

V

LC1

LC2

LC3

COM

2

V

LC4

LC5

V

SS

V

LC1

LC2

LC3

PCOM

1

2

V

LC4

LC5

V

SS

15

Data Sheet S13104EJ5V0DS00

µPD16681

6. DESCRIPTION OF BLOCKS

6.1 Display Data RAM (DDRAM)

DDRAM is RAM that contains display data consisting of a 16-bit character code plus a character attribute code. The

RAM capacity is 16 x 72 bits, which means that up to 72 characters can be stored in RAM.

The following table shows correspondences between DDRAM addresses and LCD display positions. For further

description of these correspondences, see the section 7.1 LCD display and DDRAM addresses.

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

1st line

2nd line

3rd line

4th line

00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H

12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H

24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H

36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H

6.2 Full Width (11x12 dots) Character Generator ROM (FCGROM)

FCGROM generates a total of 7,064 full width character patterns, of which 6,355 are JIS Level 1 + Level 2 kanji, 453

are non-kanji characters and 256 other symbols. These character patterns are displayed in 11 x12 dot font patterns

based on 12-bit character codes. The section entitled 7.2.2 Full Width(11 x 12 dots) Character Code Setting

Examples describes the correspondence between the character codes set to DDRAM and this full width font pattern.

Also, see the section entitled 7.2 Character Codes for a description of the correspondence between the JIS code

and the character code set to DDRAM.

6.3 Half Width(5 x 12 dots) Character Generator ROM (HCGROM)

FCGROM generates a total of 192 half width (5 x 12 dots) character patterns, displayed in 5 x 12 dot font patterns.

The section entitled 7.2 Character Codes describes the correspondence between the character code set to DDRAM

and the half width font patterns.

16

Data Sheet S13104EJ5V0DS00

µPD16681

6.4 Character Generator RAM (CGRAM)

CGRAM is RAM to which the user can freely set character patterns. Eight types of 12 x 13 dot character patterns

can be defined. To display a character pattern that has been stored in CGRAM, the user specifies a value ranging

from “000H” to “007H”.

The relation between character codes and CGRAM addresses used to access CGRAM is shown below.

Figure 6-1. The Relation between Character Codes and CGRAM Addresses

Character code

CGRAM Data

CGRAM Address

C3 C2 C1 C0 A7 A6 A5 A4 A3 A2 A1 D

0 0 0 0 0 0 0

A0 ="0"

A0 ="1"

C12

to

7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A

0

0 0 0 0 0 0 0 1 0 0 1

·

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

A

17

Data Sheet S13104EJ5V0DS00

µPD16681

Remarks 1. CGRAM is selected when the high-order nine bits (C11 to C3) of a character code are all zeros. At that

time, the low-order three bits (C2 to C0) corresponds to CGRAM addresses 7 to 5 (A7 to A5). (Three

bits: eight types.)

2. Display ON is selected when the CGRAM data value is “1”. Display OFF is selected when this data

value is “0”.

3. The CGRAM address 0 (A0) corresponds to the left and right sides of the character pattern.

4. The high-order two bits of CGRAM are used to control the display attributes of the pattern

corresponding to the low-order six bits. In such cases, any display attribute specification made for

DDRAM is ignored. When the value of the high-order two bits is “00”, CGRAM’s pattern is displayed.

5. CGRAM addresses 4 to 1 (A4 to A1) corresponds to the line position of the character pattern. (Four

bits : 13 lines) The ORed result with the cursor is taken and displayed on the 12th line.

6.5 Pictograph Display RAM (PDRAM)

1

2

PDRAM is the RAM that contains pictograph display data that has been assigned to PCOM and PCOM . The data

display function is ON when the data value is “1” and OFF when the data value is “0”.

After data is written, the address counter is automatically incremented (by one), and the value after 0FH is 00H.

The correspondence between output from various segments and PDRAM addresses is shown below.

1

2

PCOM ,PCOM

Address

Segment Output No.

b7

X

b6

X

b5

6

b4

5

b3

4

b2

3

b1

2

b0

1

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

12

18

24

30

36

42

48

54

60

66

72

78

84

90

96

11

17

23

29

35

41

47

53

59

65

71

77

83

89

95

10

16

22

28

34

40

46

52

58

64

70

76

82

88

94

9

8

7

15

21

27

33

39

45

51

57

63

69

75

81

87

93

14

20

26

32

38

44

50

56

62

68

74

80

86

92

13

19

25

31

37

43

49

55

61

67

73

79

85

91

Remark X : Don’t care

18

Data Sheet S13104EJ5V0DS00

µPD16681

6.6 Pictograph Blink Data RAM (PBRAM)

1

2

PBRAM is the RAM that contains pictograph blink data that has been assigned to PCOM and PCOM . A data

value of “1” is written to the address of the pictograph to be set for a blink display.

After data is written, the address counter is automatically incremented (by one), and the value after 0FH is 00H.

The correspondence between output from various segments and PBRAM addresses is shown below.

1

2

PCOM ,PCOM

Address

Segment Output No.

b7

X

b6

X

b5

6

b4

5

b3

4

b2

3

b1

2

b0

1

00H

01H

02H

03H

04H

05H

06H

07H

08H

09H

0AH

0BH

0CH

0DH

0EH

0FH

12

18

24

30

36

42

48

54

60

66

72

78

84

90

96

11

17

23

29

35

41

47

53

59

65

71

77

83

89

95

10

16

22

28

34

40

46

52

58

64

70

76

82

88

94

9

8

7

15

21

27

33

39

45

51

57

63

69

75

81

87

93

14

20

26

32

38

44

50

56

62

68

74

80

86

92

13

19

25

31

37

43

49

55

61

67

73

79

85

91

Remark X : Don’t care

6.7 Relation between Addresses and Various ROM and RAM Devices

The µPD16681 assigned FCGROM addresses as shown below to HCGROM, CGRAM, and user-defined ROM.

Type

No. of Characters

Address Range

JIS kanji

6355

453

Same as kanji ROM IC

Non-JIS kanji

Half width alphanumeric

characters

192

Uses addresses 0080H to 039FH in the kanji ROM IC

User defined

CGRAM

256

8

Uses addresses 1000H to 101FH in the kanji ROM IC

Uses addresses 0000H to 0007H in the kanji ROM IC

19

Data Sheet S13104EJ5V0DS00

µPD16681

7. LCD DISPLAY

The µPD16681’s LCD display can display four lines containing up to 8 characters (11 x 12 dots) or 16 characters (5

x 12 dots) and 96 pictographs.

2

4

6

8

10

12

14

16

18

86

88

90

92

94

96

SEG

1

3

5

7

9

11

13

15

17

85

87

89

91

93

95

PCOM

1

COM

1

2

3

4

5

6

7

8

9

COM10

COM11

COM12

COM13

COM14

COM15

COM16

COM17

COM18

COM19

COM47

COM48

COM49

COM50

COM51

PCOM

2

Remark The same select signal is output from PCOM¹and PCOM².

20

Data Sheet S13104EJ5V0DS00

µPD16681

7.1 LCD Display and DDRAM Addresses

The character code used in the µPD16681 contains 16 bits (character code + character attribute code). When data

is stored to an address in DDRAM, a combination of full width (11 x 12 dots) and half width (5 x 12 dots) characters

can be displayed on the LCD.

The relation between the DDRAM’s character area and the actual LCD display when displaying a combination of full

width and half width characters is shown below.

Figure 7-1. The Relation between The DDRAM’s Character Area and The Actual LCD Display

LCD display:

"" : Half width(5 x 12 dots) space

DDRAM:

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

1st line

2nd line

3rd line

4th line

00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H

12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H

24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H

36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H

Remark Shaded areas indicate addresses.

Address characters that are not displayed are used as data for character scrolling.

7.2 Character Codes

The µPD16681 is able to combine full width characters (11 x 12 dots) and half width characters (5 x 12 dots) in the

same display. The character data that is stored in DDRAM is displayed starting from the top left corner of the LCD

screen. A one-dot character interval is added to the left of each character font.

Both full width (11 x 12 dots) and half width (5 x 12 dots) characters are handled using 16-bit code lengths and are

stored in DDRAM. The 16-bit code format uses the low-order 13 bits as the character code. The remaining 3 bits are

the high-order 3 bits, which specify the character width (full or half) and the display attribute. The MSB is the select

bit indicating full width or half width character code: “0” specifies full width characters and “1” specifies half width

characters. The character attribute code is assigned to the next two bits, and can specify attributes such as blinking

for individual characters. (See the section 7.3 Display Attributes.)

7.2.1 Code format

D13

A0

D12

C12

D11

C11

D10

C10

D8

C8

D15

F/H

D14

A1

D9

C9

D5

C5

D4

C4

D3

C3

D1

C1

D0

C0

D7

C7

D6

C6

D2

C2

High-order character code

Low-order character code

Display attribute codes

Full width(11 x 12 dots) character/

Half width(5 x 12 dots) character specification

21

Data Sheet S13104EJ5V0DS00

µPD16681

7.2.2 Full width (11 x 12 dots) character code setting examples

The following shows the correspondence between 16-bit JIS code and the µPD16681’s 13-bit character code. This

correspondence varies according to the values of the high-order 3 bits (b17, b16, and b15) in the first byte of the JIS

code.

Convert JIS code as shown below to generate character code for the µPD16681.

(1) JIS level 1 kanji and non-kanji characters

Table 7-1. When (b17, b16, b15) = (0, 1, 0)

JIS C 6226

First byte

b14

Second byte

b17

b16

b15

b13

C9

b12

C8

b11

C7

b27

C6

b26

C5

b25

C4

b24

C3

b23

C2

b22

C1

b21

C0

Character code

Remark C12 = C6 = C5 = 0

Table 7-2. When (b17, b16, b15) = (0, 1, 1) or (1, 0, 0)

JIS C 6226

First byte

Second byte

b17

C11

b16

b15

b14

C10

b13

C9

b12

C8

b11

C7

b27

C6

b26

C5

b25

C4

b24

C3

b23

C2

b22

C1

b21

C0

Character code

Remark C12 = 0

(2) JIS level 2 kanji and non-kanji characters

Table 7-3. When (b17, b16, b15) = (1, 1, 1)

JIS C 6226

First byte

Second byte

b17

b16

b15

b14

b13

C9

b12

C8

b11

C7

b27

C11

b26

C10

b25

C4

b24

C3

b23

C2

b22

C1

b21

C0

Character code

Remark C12 = 1, C6 = C5 = 0

Table 7-4. When (b17, b16, b15) = (1, 0, 1) or (1, 1, 0)

JIS C 6226

First byte

Second byte

b17

b16

C11

b15

b14

C10

b13

C9

b12

C8

b11

C7

b27

C6

b26

C5

b25

C4

b24

C3

b23

C2

b22

C1

b21

C0

Character code

Remark C12 = 1

(3) CGRAM

D15

0

D14

X

D13

X

D12

0

D11

0

D10

0

D9

0

D8

0

D7

0

D6

0

D5

0

D4

0

D3

0

D2

u2

D1

u1

D0

u0

Remark CGRAM addresses for user font: u2 to u0

22

Data Sheet S13104EJ5V0DS00

µPD16681

7.3 Display Attributes

In the µPD16681, the character code is assigned to 12 bits of the 16-bit data that is specified as full width (11 x 12

dots) characters or half width (5 x 12 dots) characters and the display attribute code is assigned to two of the

remaining four bits. Normal display or blink display mode can be specified for each character unit.

The blink cycle for blink display mode is 64 frames, so that display blinks on or off once every 32 frames.

7.3.1 Character code format

D13

A0

D12

C12

D11

C11

D10

C10

D8

C8

D15

F/H

D14

A1

D9

C9

D5

C5

D4

C4

D3

C3

D1

C1

D0

C0

D7

C7

D6

C6

D2

C2

High-order character code

Low-order character code

Display attribute codes

Full width(11 x 12 dots) character/

Half width(5 x 12 dots) character specification

7.3.2 Display attribute specifications

A1

0

A0

0

Display Mode

Normal display

0

1

Reverse display

Character blink

1

0

1

Reverse character blink

7.3.3 Display examples

(1) Normal display

(2) Reverse display

23

Data Sheet S13104EJ5V0DS00

µPD16681

(3) Blink display

Display alternates

once every 32 frames

(4) Reverse blink display

Display alternates

once every 32 frames

24

Data Sheet S13104EJ5V0DS00

µPD16681

8. COMMANDS

8.1 Basic format

Command register (CR)

+

Extended selection register (ESR)

+ RAM Address register (RAD)

+ · · ·

Address register (AR)

Command register (CR)^Note

+

DATA 1(DT1)

Note

The command (1 or 2 bytes) immediately follows the falling edge of the STB signal, and whatever is sent

after that is recognized as data.

Table 8-1. Command List

Command

Register Contents

Description

b7

0

1

b6

0

1

0

b5

1

0

1

0

1

b4

0

1

0

1

0

1

0

b3

0

b2

0

b1

1

b0

1

Reset

Display ON/OFF

Standby

1

b2

0

b1

0

b0

0

Duty setting

1

Cursor control

D/A converter setting

Scroll control

Blink setting

1

0

b3

0

b2

0

b1

b0

Address register

Data R/W mode

Test mode

1

0

b2

b3

25

Data Sheet S13104EJ5V0DS00

µPD16681

8.1.1 Reset

This command resets all of the commands in the µPD16681.

LSB

1

MSB

0

1

0

1

8.1.2 Display ON/OFF

This command controls the display’s ON/OFF status.

LSB

MSB

0

1

b2 b1 b0

Selection

000 : LCD OFF (SEG

001 : LCD OFF (SEG

111 : LCD ON

n

, COM

n

, PCOM

n

= VSS)

n, COM

n

= non-select waveform)

8.1.3 Standby

This command stops the DC/DC converter, which reduces the supply current. The display is set to OFF mode

n

SS

(SEG , COM = V ).

LSB

MSB

0

1

0

b2 b1 b0

Selection

000 : Normal operation

001 : Standby (stop DC/DC converter, fulll display off ^Note,stop OSC)

Note SEGⁿ, COMⁿ, PCOMⁿ= V^EE

8.1.4 Duty setting

This command specifies the duty setting.

LSB

MSB

0

1

0

b1 b0

Selection

00 : 1/52 duty

01 : 1/39 duty

Note

Note Use COM¹to COM¹⁹and COM²⁷to COM⁴⁵, leave COM²⁰to COM²⁶and COM⁴⁶to COM⁵¹open when setting

1/39 duty.

26

Data Sheet S13104EJ5V0DS00

µPD16681

8.1.5 Cursor control

This command controls the cursor’s ON/OFF status.

LSB

MSB

0

1

b1 b0

Selection

00 : Cursor OFF ^Note1

10 : Cursor ON (no blink)^Note2

11 : Cursor ON (blink)^Note3

Notes 1. 00 : Sets cursor to OFF mode.

2. 10 : Sets cursor to ON mode (cursor is displayed). The cursor is displayed at the character which

occupies the display position of the currently specified DDRAM address. The “address register” + “data

R/W command” combination is used to set data to DDRAM addresses. When accessing RAM, the

address counter in RAM is automatically incremented (+1) or decremented (−1), and the cursor is moved

accordingly.

3. 11 : This sets the cursor to ON mode and causes the cursor to blink. The blink cycle is 64 frames. The

correspondence between the cursor and the RAM address is the same as when the cursor is blinking.

Remark The cursor display function is valid only when the display attribute specifies “normal display”

(A0 = 0, A1 = 0).

8.1.6 D/A converter set 1

DD

.

The D/A converter’s output for the LCD driver is set in 64 steps from V to 1/2 V

LSB

0

MSB

0

LSB

MSB

0

+

0

1

0

1

0

b5 b4 b3 b2 b1 b0

Extended selection

D/A output selection

00H(MIN.) to 3FH(MAX.)

Remark This value is set to 20H after a reset.

27

Data Sheet S13104EJ5V0DS00

µPD16681

8.1.7 Scroll control

This controls scrolling of displayed characters.

The individual bits in the selection are allocated to their respective display lines. When the data value is “1”,

scrolling is enabled for that line. The distance of the dots’ leftward (horizontal) motion is selected via the extended

selection register that is input after the command. The dot move distance varies depending on the current LCD

display status and the contents of DDRAM. For details, see the section 8.4 Scrolling.

LSB

MSB

0

LSB

MSB

0

+

0

1

b3 b2 b1 b0

b6 b5 b4 b3 b2 b1 b0

Dot move distance selection

Selection

b0 : Scroll selection on fourth line

b1 : Scroll selection on third line

b2 : Scroll selection on second line

b3 : Scroll selection on first line

8.1.8 Pictograph blink setting

This command performs blink control for the pictograph at addresses where the blink (PBRAM) data value is “1”.

LSB

MSB

0

1

0

b1 b0

Selection

00 : Stop blink (blink frequency = f^OSC/319488)

01 : Stop blink (blink frequency = f^BR1^Note/2)

10 : Start blink (blink frequency = f^OSC/319488)

11 : Start blink (blink frequency = f^BR1^Note/2)

Note This refers to the frequency of the external clock that is input from the OSC^BR1pin.

28

Data Sheet S13104EJ5V0DS00

µPD16681

8.1.9 Data R/W command

This command performs data read/write operations.

LSB

MSB

1

LSB

MSB

+

· · ·

0

1

0

b2 b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

Selection 1

00 : Increments up from the current address^{Note 1}

01 : Retains current address

10 : Decrements down from the current address^{Note 1}

Selection 2

0 : Data write

1 : Data read^{Note 2}

Notes 1. During increment mode, when the current address is the last address the next address becomes 00H.

During decrement mode, when the current address is 00H, the next address becomes the last address.

2. Data read mode is cancelled at the rising edge of the STB signal (mode is switched to command/data write

mode).

Caution During a serial data transfer, write data in 8-bit or 16-bit segments. If the rising edge of STB occurs

during the data transfer operation, the operation is not guaranteed.

8.1.10 Test mode

This command sets the test mode. The test mode is only for confirming the IC’s operation. Regular or continuous

use while in test mode is not guaranteed.

LSB

MSB

1

0

1

0

b3 b2 b1 b0

Selection

0000 : Normal operation

0001 to 1111 : Test mode

29

Data Sheet S13104EJ5V0DS00

µPD16681

8.2 Address Register

This command selects the address type and specifies addresses.

LSB

MSB

0

LSB

MSB

+

1

0

1

0

b1 b0

b7 b6 b5 b4 b3 b2 b1 b0

Selection 1

Selection 2

00 : DDRAM address

01 : PDRAM address

10 : PBRAM address

11 : CGRAM address

DDRAM address : 00H to 47H

PDRAM address : 00H to 0FH

PBRAM address : 00H to 0FH

CGRAM address : 00H to F9H

Caution Operation is not guaranteed if an invalid address is set.

8.3 Reset

The contents of the various registers appear as shown below after a reset (command reset or hardware [pin] reset).

Command

Register Contents

Description

b7

0

b6

0

b5

0

b4

0

b3

1

b2

0

b1

0

b0

0

Display ON/OFF

LCD OFF

(SEGⁿ, COMⁿ, PCOMⁿ, = V^SS)

Normal operation

1/52 duty

Standby

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Duty setting

Cursor control

D/A converter setting

Scroll control

Blink setting

Cursor OFF

Set to 20H

No specified scroll line

Blink stop

Address register

Data R/W mode

Test mode

DDRAM is specified

Data write/increment (+1)

Normal operation

30

Data Sheet S13104EJ5V0DS00

µPD16681

8.4 Scrolling

Character scrolling is controlled by inputting scroll control commands (8 bits) plus scroll dot count data (8 bits). The

line to be scrolled is specified by the scroll control command and the scroll dot count data sets the number of dots to

be scrolled. When this command is input, the characters on the specified line are shifted leftward by the specified

number of dots.

The number of dots that can be scrolled differs according to the contents of the data stored in DDRAM (see 8.4.1

Scrollable number of dots and 8.4.2 Display and scroll amounts). Consequently, if scrolling is specified for an

amount of data that exceeds the scrollable data, the character data, only the scrollable data is shifted and

overwritten, and scrolling must be performed again.

Cautions 1. For character scrolling, be sure to input a scroll control command (8 bits) plus the amount of

scrolled data (8 bits).

2. If the characters on a scrolled line have various character attributes (normal/blink/reverse/

reverse/blink), the character display may become garbled after scrolling. This problem does not

occur when all of the characters on the line have the same character attribute.

8.4.1 Scrollable number of dots

Scroll amount = (12 dots x number of non-displayed full width characters that are stored in DDRAM)

+ (6 dots x number of non-displayed half width characters that are stored in DDRAM)

8.4.2 Display and scroll amounts

LCD display:

DDRAM status :

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

1st line

2nd line

3rd line

4th line

00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H

12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H

24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H

36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H

Remark Shaded areas indicate addresses.

Address characters that are not displayed are used as data for character scrolling.

31

Data Sheet S13104EJ5V0DS00

µPD16681

Character memory contents :

Remarks 1. Shaded areas indicate addresses.

2. First line :

(10 full width (11 x 12 dots) characters)

(6 full width (11 x 12 dots) characters),

Second line :

"484"†(4 half width (5 x 12 dots) characters)

Third line : "PB"(2 half width (5 x 12 dots) characters)

Fourth line :

(2 full width (5 x 12 dots) characters)

Scrollable dot counts;

First line : (12 dots x 10 characters) + (6 dots x 0 characters) = 120 dots

Second line : (12 dots x 6 characters) + (6 dots x 4 characters) = 96 dots

Third line : (12 dots x 0 characters) + (6 dots x 2 characters) = 12 dots

Fourth line : (12 dots x 2 characters) + (6 dots x 0 characters) = 24 dots

If scroll count data that exceeds the scrollable number of dots is entered using the scroll control

command, all dots that are in the area that goes beyond the DDRAM addresses are output as OFF

data.

32

Data Sheet S13104EJ5V0DS00

µPD16681

8.5 Serial Communication Format

(1) Reception 1 (command write, 1 byte)

STB

DATA

SCK

b7

b6

b5

b2

b1

b0

1

2

3

6

7

8

(2) Reception 2 (command/data write, 2 bytes or more)

STB

DATA

SCK

b7

b6

b5

b2

b1

b0

b7

b6

b5

b4

b3

1

2

3

6

7

8

1

2

3

4

5

Command 1

Command 1/Data

Wait time t^WAIT

(3) Transmission (command/data read)

STB

DATA

SCK

b7

b6

b5

b2

b1

b0

b7

2

b6

3

b5

4

b4

5

b3

6

1

2

3

6

7

8

1

Data read command setting

Data read

Wait time tWAIT

33

Data Sheet S13104EJ5V0DS00

µPD16681

8.6 Parallel Communication Format

(1) 8-bit parallel interface

STB

D0

- D7

E

34

Data Sheet S13104EJ5V0DS00

µPD16681

9. COMMAND EXAMPLES

Table 9-1. Initial Setting (1/39 duty) + Data Input

STB

D7

D6

D5

D4

D3

D2

D1

D0

Status

Hard Reset

H

L

X

0

X

0

X

0

X

1

X

0

X

0

X

1

X

0

X

1

X

1

X

0

X

0

X

0

X

0

X

1

X

0

Duty setting (1/39 duty)

H

L

Address register (DDRAM address

selection)

0

X

1

0

X

0

X

1

0

X

1

0

X

0

X

0

X

0

X

0

DDRAM address: 00H

H

L

Data write, address is incremented

starting from current address

Data for first character

D15

D7

D14

D6

D13

D5

D12

D4

D12

D4

:

D11

D3

D10

D2

D9

D1

D9

D1

D8

D0

D8

D0

D15

D7

D14

D6

D13

D5

D11

D3

D10

D2

Data for second character

Data for 54th character

D15

D7

X

D14

D6

X

D13

D5

X

D12

D4

X

D11

D3

X

D10

D2

X

D9

D1

X

D8

D0

X

H

L

0

1

0

1

0

1

Address register (PDRAM address

selection)

H

L

0

X

1

0

X

0

X

1

0

X

1

0

X

0

X

0

X

0

X

0

PDRAM address: 00H

Data write, address is incremented

starting from current address

PDRAM: data at 00H

X

D

:

D

PDRAM: data at 01H

X

0

X

1

D

X

0

D

X

0

D

X

1

D

X

0

D

X

1

D

X

0

PDRAM: data at 0FH

H

L

Address register (PBRAM address

selection)

0

X

1

0

X

0

X

1

0

X

1

0

X

0

X

0

X

0

X

0

PBRAM address : 00H

H

L

Data write, address is incremented

starting from current address

PBRAM: data at 00H

X

D

:

D

PBRAM: data at 01H

PBRAM: data at 0FH

Display ON

X

0

X

0

D

X

0

D

X

0

D

X

1

D

X

1

D

X

1

D

X

1

H

L

H

X

To next processing

Remark X : Don’t care

35

Data Sheet S13104EJ5V0DS00

µPD16681

Table 9-2. CGRAM Data Write

STB

D7

D6

D5

D4

Start

D3

D2

D1

D0

Status

H

L

X

0

X

1

X

0

X

0

X

1

X

0

X

1

X

1

Address register (CGRAM address

selection)

0

X

1

0

X

0

X

1

0

X

1

0

X

0

X

0

X

0

X

0

CGRAM address: 00H

H

L

Data write, address is incremented

starting from current address

A

D5

D4

:

D3

D2

D1

D0

Data for first character (at 000H)

Data in first line of pattern

Data for first character (at 000H)

Data in second line of pattern

A

X

A

X

D5

X

D4

X

D3

X

D2

X

D1

X

D0

X

Data for Xth character (at 00mH)

Data in nth line of pattern

H

To next processing

Remark X : Don’t care

36

Data Sheet S13104EJ5V0DS00

µPD16681

10. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T^A= 25 °C, V^SS= 0 V)

Parameter

Supply voltage (4x boost)

Supply voltage (3x boost)

Driver supply voltage

Symbol

V^DD

Rating

−0.3 to +3.75

Unit

V

V^DD

−0.3 to +5.0

V

V^LCD

V^LC1-V^LC5

V^IN1

−0.3 to +15.0, V^DD≤ V^LCD

−0.3 to V^LCD+0.3

−0.3 to V^DD+0.3

−0.3 to V^LCD+0.3

−40 to +85

V

Driver reference supply input voltage

Logic system input voltage

Logic system output voltage

Logic system input/output voltage

Driver system input voltage

Driver system output voltage

Operating ambient temperature

Storage temperature

V

V^OUT1

V^I/O1

V^IN2

V

V^OUT2

T^A

V

°C

T^stg

−55 to +150

Caution If the absolute maximum rating of even one of the above parameters is exceeded even

momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,

specify the values exceeding which the product may be physically damaged. Be sure to use the

product within the range of the absolute maximum ratings.

Recommended Operating Range

Parameter

Symbol

V^DD

MIN.

2.45

5.0

0

TYP.

10

MAX.

3.0

Unit

V

Supply voltage (4x boost)

Supply voltage (3x boost)

Driver supply voltage

V^DD

4.0

V

V^LCD

12

V

Logic system input voltage

Driver system input voltage

V^IN

V^DD

V^LCD

V

V^LC1-V^LC5

0

V

Remarks 1. When using an external power supply, be sure to maintain these relations:

SS

V

LC5

< V

LC4

< V

LC3

< V

LC2

< V

LC1

< V

LCD

≤ V

2. Maintain V^DD≤ V^LCDwhen turning the power on or off.

3. Keep voltage input to the AMP^IN(+)pin between 1.0 V and V^DDwhen using an internal power supply but

not using the D/A converter.

37

Data Sheet S13104EJ5V0DS00

µPD16681

Electrical characteristics (unless otherwise specified, T^A= −40 to +85 °C, V^DD= 2.45 to 3.0 V during 4x boost mode

or 2.45 to 4.0 V during 3x boost mode)

Parameter

Symbol

V^IH

Condition

MIN. TYP. MAX. Unit

High-level input voltage

0.8V^DD

V

Low-level input voltage

V^IL

0.2V^DD

High-level input current

I^IH1

Except for D⁰/DATA and D¹to D⁷

I^OUT= −1.5 mA, except OSC^OUT

I^OUT= 4 mA, except OSC^OUT

D⁰/DATA and D¹to D⁷, V^IN/OUT= V^DD

D⁰/DATA and D¹to D⁷, V^IN/OUT= V^SS

V^LCn→ COM^n,V^LCD≥ 3V^DD, I^LOL= 50 µA

V^LCn→ SEG^n,V^LCD≥ 3V^DD, I^LOL= 50 µA

During 3x boost

1

µA

V

Low-level input current

I^IL1

−1

High-level output voltage

Low-level output voltage

High-level leakage current

Low-level leakage current

Common output ON resistance

Segment output ON resistance

Driver voltage (boost voltage)

V^OH

V^OL

I^LOH

I^LOL

R^COM

R^SEG

V^LCD

V^DD0.5

−

0.5

10

V

µA

kΩ

V

−10

2

4

2.7V^DD

3.6V^DD

3.0V^DD

4.0V^DD

180

During 4x boost

V

Current consumption

(normal mode)

I^DD11

f^OSC= 375 kHz, all display OFF data output,

V^DD= 3.0 V during 3x boost mode

f^OSC= 375 kHz, all display OFF data output,

V^DD= 3.0 V during 4x boost mode

f^OSC= 375 kHz, all display OFF data output,

V^DD= 3.0 V during 3x boost mode

f^OSC= 375 kHz, all display OFF data output,

V^DD= 3.0 V during 4x boost mode

V^DD= 3.0 V

100

135

150

200

1

µA

210

280

340

10

µA

Current consumption

(high-power mode)

I^DD12

Driver system current consumption (V^DD) I^DD21

(Standby)

Remark The TYP. value is a reference value when T^A= 25 °C

Test Circuit

DA^CHA

D/A

Converter

VEXT

Reference supply circuit

VDD

+

AMPIN(+)

−

AMPIN(−)

AMPOUT

VLC1

VLC2

VLC3

VLC4

VLC5

VSS

38

Data Sheet S13104EJ5V0DS00

µPD16681

Switching characteristics (unless otherwise specified, T^A= −40 to +85 °C)

DD

V

= 2.45 to 2.7 V

Parameter

Symbol

f^OSC

Conditions

Self-oscillation,

MIN.

180

TYP.

MAX. Unit

•

Oscillation frequency

500

kHz

oscillation resistance R = 100 kΩ

SCK↓→DATA↓

Transfer delay time

t^PHL

t^PLH

60

ns

SCK↓→DATA↑

Remark The TYP. value is a reference value when T^A= 25 °C

DD

V

= 2.7 to 3.3 V

Parameter

Symbol

f^OSC

Conditions

Self-oscillation,

MIN.

240

TYP.

378

MAX. Unit

•

Oscillation frequency

560

kHz

oscillation resistance R = 100 kΩ

SCK↓→DATA↓

Transfer delay time

t^PHL

t^PLH

60

ns

SCK↓→DATA↑

Remark Use the following equation to determine the time per frame.

OSC

1 frame = 1/f

x 96 x number of duty

OSC

f

= 375 kHz, Given a 1/52 duty,

1 frame = 2.67 µs ( 96 x 52 = 13.1 ms 75 Hz)

39

Data Sheet S13104EJ5V0DS00

µPD16681

Required timing conditions (unless otherwise specified, T^A= −40 to +85 °C)

DD

Common (1) (V = 2.45 to 2.7 V)

Parameter

Clock frequency

Symbol

f^OSC

Conditions

OSC^INexternal clock

MIN.

180

600

400

TYP.

MAX. Unit

500

kHz

ns

µs

High-level clock pulse width

Low-level clock pulse width

High-level clock pulse width

Low-level clock pulse width

Rise/fall time

t^WHC1

t^WLC1

t^WHC2

t^WLC2

tr,tf

OSC^INexternal clock

OSC^BRIexternal clock

/RESET pin

100

Reset pulse width

t^WRE

t^RRE

50

Reset cancellation time

/RESET pin

Remark The TYP. value is a reference value when T^A= 25 °C.

DD

Common (2) (V = 2.7 to 3.3 V)

Parameter

Clock frequency

Symbol

f^OSC

Conditions

OSC^INexternal clock

MIN.

240

500

400

TYP.

375

MAX. Unit

560

kHz

ns

µs

High-level clock pulse width

Low-level clock pulse width

High-level clock pulse width

Low-level clock pulse width

Rise/fall time

t^WHC1

t^WLC1

t^WHC2

t^WLC2

t^r,t^f

OSC^INexternal clock

OSC^BRIexternal clock

/RESET pin

100

Reset pulse width

t^WRE

t^RRE

50

Reset cancellation time

/RESET pin

Remark The TYP. value is a reference value when T^A= 25 °C.

40

Data Sheet S13104EJ5V0DS00

µPD16681

DD

Serial interface (1) (V = 2.45 to 2.7 V)

Parameter

Symbol

Conditions

MIN.

600

300

210

260

40

TYP.

MAX. Unit

Shift clock cycle

t^CYK

SCK

ns

High-level shift clock pulse width

Low-level shift clock pulse width

Shift clock hold time

Data setup time

t^WHK

SCK

t^WLK

SCK

t^HSTBK

t^DS1

STB↓→SCK↓

DATA→SCK↑

SCK↑→DATA

SCK↑→STB↑

Data hold time

t^DH1

40

STB hold time

t^HKSTB

t^WSTB

t^WAIT

260

210

260

STB pulse width

Wait time

8th CLK↑→1st CLK↓

Remark The TYP. value is a reference value when T^A= 25 °C.

DD

Serial interface (2) (V = 2.7 to 3.3 V)

Parameter

Shift clock cycle

Symbol

Conditions

MIN.

500

260

210

260

40

TYP.

MAX. Unit

t^CYK

t^WHK

t^WLK

t^HSTBK

t^DS1

SCK

ns

High-level shift clock pulse width

Low-level shift clock pulse width

Shift clock hold time

Data setup time

SCK

STB↓→SCK↓

DATA→SCK↑

SCK↑→DATA

SCK↑→STB↑

Data hold time

t^DH1

40

STB hold time

t^HKSTB

t^WSTB

t^WAIT

260

210

260

STB pulse width

Wait time

8th CLK↑→1st CLK↓

Remarks 1. The TYP. value is a reference value when T^A= 25 °C.

2. For details, see 8.5 Serial Communication Format (3) Transmission (command/data read).

41

Data Sheet S13104EJ5V0DS00

µPD16681

DD

Parallel interface (1) (V = 2.45 to 2.7 V)

Parameter

Symbol

Conditions

MIN.

600

300

210

260

40

TYP.

MAX. Unit

Enable cycle time

High-level enable pulse width

Low-level enable pulse width

STB pulse width

t^CYCE

E↑→E↑

ns

t^WHE

E

t^WLE

t^WSTB

t^WKSTB

t^HSTBK

t^DS2

STB hold time

Enable hold time

Data setup time

D⁰to D⁷→E↑

D⁰to D⁷→E↓

Data hold time

t^DH2

40

Remark The TYP. value is a reference value when T^A= 25 °C.

DD

Parallel interface (2) (V = 2.7 to 3.3 V)

Parameter

Enable cycle time

Symbol

Conditions

MIN.

500

260

210

260

40

TYP.

MAX. Unit

t^CYCE

t^WHE

t^WLE

E↑→E↑

ns

High-level enable pulse width

Low-level enable pulse width

STB pulse width

E

t^WSTB

t^WKSTB

t^HSTBK

t^DS2

STB hold time

Enable hold time

Data setup time

D⁰to D⁷→E↑

D⁰to D⁷→E↓

Data hold time

t^DH2

40

Remark The TYP. value is a reference value when T^A= 25 °C.

42

Data Sheet S13104EJ5V0DS00

µPD16681

AC timing measurement voltages

VIH

Input

V

IL

VOH

Output

V

OL

AC characteristics waveforms

OSC

OSCIN

t

WHC1

t

WLC1

1/fOSC

t

f

t

r

OSCBRI

t

WHC2

t

WLC2

Serial interface (input)

STB

t

WSTB

t

CYK

t

HSTBK

t

HKSTB

t

WLK

t

WHK

SCK

t

DS1

t

DH1

DATA

Serial interface (output)

SCK

t

PHL

t

PLH

DATA

43

Data Sheet S13104EJ5V0DS00

µPD16681

8-bit parallel interface

STB

t

WSTB

t

WKSTB

t

CYCE

t

HSTBK

t

WLE

t

WHE

E

t

DS2

t

DH2

Dn

Reset

t

RRE

/RESET

t

WRE

Reset cancellation

time

Reset time

44

Data Sheet S13104EJ5V0DS00

µPD16681

11. CHARACTER CODE TABLES (standard ROM code, µPD16681W/P-011)

The following tables show the correspondences between character codes and characters. Character codes ranging

from 0000H to 0007H are assigned to CGRAM and those ranging from 1000H to 1380H are assigned to an area that

is defined by the user when establishing custom ROM codes.

•

Character allocation table (1)

C12 = 0

45

Data Sheet S13104EJ5V0DS00

µPD16681

Character allocation table (2)

C12 = 0

46

Data Sheet S13104EJ5V0DS00

µPD16681

Character allocation table (3)

C12 = 0

47

Data Sheet S13104EJ5V0DS00

µPD16681

Character allocation table (4)

C12 = 0

48

Data Sheet S13104EJ5V0DS00

µPD16681

Character allocation table (5)

C12 = 1

49

Data Sheet S13104EJ5V0DS00

µPD16681

Character allocation table (6)

C12 = 1

50

Data Sheet S13104EJ5V0DS00

µPD16681

Character allocation table (7)

C12 = 1

51

Data Sheet S13104EJ5V0DS00

µPD16681

Character allocation table (8)

C12 = 1

52

Data Sheet S13104EJ5V0DS00

µPD16681

[MEMO]

53

Data Sheet S13104EJ5V0DS00

µPD16681

[MEMO]

54

Data Sheet S13104EJ5V0DS00

µPD16681

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

55

Data Sheet S13104EJ5V0DS00

µPD16681

Reference Documents

NEC Semiconductor Device Reliability/Quality Control System (C10983E)

Semiconductor Device Mounting Technology (C10535E)

• The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

• No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

• Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,

software, and information in the design of the customer's equipment shall be done under the full responsibility

of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third

parties arising from the use of these circuits, software, and information.

• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

• NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated "quality assurance program" for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

M7 98. 8


型号：	UPD16681
厂家：	NEC
描述：	LCD CONTROLLER/DRIVER FOR DOT MATRIX DISPLAY OF JIS LEVEL 1 AND JIS LEVEL 2 KANJI SETS LCD控制器/驱动器的JIS等级1和JIS 2级汉字套点阵显示屏驱动器控制器 CD
文件：	总56页 (文件大小：900K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

UPD16681 [NEC]

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